DE3314973C1

DE3314973C1 - Circuit arrangement for generating a stable fixed frequency

Info

Publication number: DE3314973C1
Application number: DE19833314973
Authority: DE
Inventors: Antoine 7730 Villingen-Schwenningen Pery; Jean-Claude Rufray
Original assignee: Deutsche Thomson Brandt GmbH
Current assignee: Deutsche Thomson Brandt GmbH
Priority date: 1983-04-26
Filing date: 1983-04-26
Publication date: 1984-07-19
Also published as: JPH0754906B2; FR2545300B1; JPS59207746A; FR2545300A1; NL8401283A

Abstract

A circuit arrangement for generating a stable frequency, for example the reference frequency, for a demodulator circuit in a colour television receiver. A frequency within the range of the line frequency is transformed by division to form a gate signal which is used by a gate circuit for counting the pulses of an oscillator. The gate pulses are counted, compared with a nominal value and then the result is added to a result previously obtained until the value N no longer changes. The value for N is transformed into an analog voltage for controlling the voltage-controlled oscillator (VCO).

Description

mißt bzw. aufsummiert. Das Zählergebnis M wird an den einen Eingang einer Vergleichsstufe 10 geschaltet, die den eingegebenen Wert M mit einem Sollwert P vergleicht. Der Sollwert Pergibt sich aus dem Produkt von D und R, wobei R das Verhältnis von F₁ der Sollfrequenz des Oszillators 1 und Fo, der dem Teiler 4 zugeführten Frequenz, darstellt, im Beispiel ist R gleich F/Fo gleich 4430/62,5 gleich 70,92 und somit P=Dx/? = 32 χ 70,92 = 2270.measures or adds up. The counting result M is switched to one input of a comparison stage 10 which compares the entered value M with a nominal value P. The nominal value Per results from the product of D and R, where R represents the ratio of F _{1 of} the nominal frequency of the oscillator 1 and Fo, the frequency fed to the divider 4, in the example R is equal to F / Fo equal to 4430 / 62.5 equal to 70.92 and thus P = Dx /? = 32 χ 70.92 = 2270.

Das Vergleichsergebnis Μ—Ρ wird in einer weiteren Addierstufe It zu dem zuvor errechneten Wert N addiert und das Ergebnis auf ein erstes Register (Latch) geschaltet. Dieses Register 12 wird mit Hilfe eines Impulses P1 durchgeschaltet, so daß an seinem Ausgang der digitale Wert N erscheint, der an den Digital-Analog-Wandler 13 gelangt, der diesen Wert in eine analoge Steuerspannung Vo umwandelt, wodurch der Oszillator 1 nachgestellt wird und eine geänderte Frequenz F erzeugt. Der Wert N gelangt gleichzeitig an den Eingang eines zweiten Registers (Latch) 14, dessen Inhalt durch den Impulse P 2 freigegeben und an den zweiten Eingang der Addierschaltung 11 gelegt wird. Die Entstehung und die zeitliche Lage der beiden Steuerimpulse Pl und P2 sind mit Hilfe der Fi g. 2 dargestellt. Durch den P2-Impuls wird der Zähler wieder zurückgestellt, und es kann nach öffnen des Tores 8 ein erneuter Zählvorgang beginnen. Die neu ermittelte Frequenz F des Oszillators 1 gelangt nach Zählung wiederum auf die Vergleichsstufe 10. Das Zählergebnis F wird mit dem Sollwert P verglichen und das Ergebnis der Addierstufe zugeführt. Dieser Vergleichswert wird über das Register 12 wieder auf den Digital-Analog-Wandler 13 gegeben, aus dem eine geänderte Spannung Vo resultiert. Es wird der Fall eintreten, bei dem aus der Vergleichsstufe 10 der Wert 0 abgegeben wird, der zu dem vorhergehenden über das Register 14 eingegebenen Wert hinzuaddiert wird. Das ist der Punkt, an welchem das System die Frequenz Fdes Oszillators 1 nicht mehr ändert und der Regelvorgang abgeschlossen ist.The comparison result Μ-Ρ is added to the previously calculated value N in a further adding stage It and the result is switched to a first register (latch). This register 12 is switched through with the aid of a pulse P1, so that the digital value N appears at its output, which is sent to the digital-to-analog converter 13, which converts this value into an analog control voltage Vo , whereby the oscillator 1 is readjusted and a changed frequency F is generated. At the same time, the value N arrives at the input of a second register (latch) 14, the content of which is released by the pulse P 2 and applied to the second input of the adder circuit 11. The emergence and the timing of the two control pulses Pl and P2 are shown with the help of Fi g. 2 shown. The counter is reset by the P2 pulse and a new counting process can begin after gate 8 is opened. After counting, the newly determined frequency F of the oscillator 1 again reaches the comparison stage 10. The count result F is compared with the nominal value P and the result is fed to the adder stage. This comparison value is returned to the digital-to-analog converter 13 via the register 12, from which a changed voltage Vo results. The case will arise in which the value 0 is output from the comparison stage 10, which is added to the previous value entered via the register 14. This is the point at which the system no longer changes the frequency F of the oscillator 1 and the control process is completed.

Da es wegen der Digitalisierung bei der Frequenzerzeugung vorkommen kann, daß bei einer exakten Frequenz F das aus der Vergleichsstufe kommende Ergebnis den digitalen Wert 1 besitzt, bei welchem das System sofort die Frequenz nachregeln würde, muß verhindert werden, daß Ergebnisse, die nur um einen digitalen Schritt von dem Sollwert abweichen, weitergeleitet werden, damit keine Frequenzänderung erfolgt. Hierzu ist hinter der Vergleichsstufe 10 ein Detektor 15 eingefügt, der bei einem Ergebnis des digitalen Wertes 1 den Pl-Impuls über das NAND-Glied 16 und das UND-Glied 17 sperrt. Auf diese Weise wird verhindert, daß das Register 12 durchgeschaltet werden kann. Die Gatter 18 und 19 dienen zur Erzeugung der in_F i g. 2 dargestellten Impulse P1 = ABC und P2 = ABC.Because of the digitization when generating the frequency, it can happen that at an exact frequency F the result coming from the comparison stage has the digital value 1, at which the system If the frequency were to be readjusted immediately, it must be prevented that results that only relate to a digital Step deviate from the setpoint value, so that no frequency change occurs. For this a detector 15 is inserted behind the comparison stage 10, which in a result of the digital value 1 den PI pulse through the NAND gate 16 and the AND gate 17 blocks. In this way it is prevented that the register 12 can be switched through. The gates 18 and 19 are used to generate the in_F i g. 2 pulses shown P1 = ABC and P2 = ABC.

Mit Hilfe der Fig. 3 soll abschließend die Wirkungsweise der Schaltung an einem einfachen Beispiel erläutert werden. Aufgetragen ist die Funktion M = f(N), d. h. das sich ergebende Zählergebnis M in Abhängigkeit von der dem Digital-Analog-Wandler 13 zugeleiteten digitalen Informationen N und damit in Abhängig- eo keit von der Steuerspannung Vo, von der die Frequenz F des Oszillators 1 abhängt. Es sei angenommen, der Punkt für N = 5, d. h. M = 2270, der Sollwert sei. Das System sei zunächst mit seiner Frequenz Fderart eingestellt, daß M = 2263 ist. Bei einem fest vorgegebenen Wert von P = 2270 ergibt sich nach der Vergleichsstufe 10 ein Wert von —7, der, zu dem Wert von π = 15 in der Additionsstufe 11 hinzuaddiert, den Wert 8 ergibt. Dieses neue N erzeugt eine höhere Frequenz F, die als Zählergebnis den Wert M = 2268 liefert. Das Vergleichsergebnis liefert den Wert —2. Dieses zum vorhergehenden addiert ergibt ein neues N = 6, welches wiederum ein M — 2269 liefert. Nach dem Rücksetzen des Zählers 9 und nochmaliger Messung liefert die Vergleichsstufe 10 den Wert —1, woraus der neue Wert N = 5 entsteht. Bei diesem Wert stellt sich der Oszillator 1 auf die Sollfrequenz ein, so daß der Zähler 9 ein M = 2270 liefert, so daß die Differenz 0 entsteht und das System eingeregelt ist.Finally, with the aid of FIG. 3, the mode of operation of the circuit will be explained using a simple example. The function M = f (N) is plotted, ie the resulting counting result M as a function of the digital information N supplied to the digital-to-analog converter 13 and thus as a function of the control voltage Vo, on which the frequency F des Oscillator 1 depends. Assume that the point for N = 5, ie M = 2270, is the setpoint. Let the system first be set with its frequency Fderart so that M = 2263. With a fixed predetermined value of P = 2270, a value of −7 results after the comparison stage 10, which, when added to the value of π = 15 in the addition stage 11, results in the value 8. This new N generates a higher frequency F, which supplies the value M = 2268 as a counting result. The comparison result supplies the value —2. Adding this to the previous one results in a new N = 6, which in turn yields an M - 2269. After resetting the counter 9 and repeated measurement, the comparison stage 10 supplies the value -1, which results in the new value N = 5. At this value, the oscillator 1 sets itself to the setpoint frequency, so that the counter 9 supplies an M = 2270, so that the difference is 0 and the system is adjusted.

Aus Gründen der Stabilität muß die Neigung dM/dN der Funktion M = f(N) negativ und der Betrag der Neigung kleiner als 1 sein, um Schwingungen zu vermeiden.For reasons of stability, the inclination dM / dN of the function M = f (N) must be negative and the amount of the inclination must be less than 1 in order to avoid oscillations.

Der Wert für den Vergleichwert P ist abhängig von der Frequenz, die der Oszillator 1 abgeben soll. So ist dieser Wert verschieden groß, je nachdem, ob der Oszillator eine Frequenz zur Demodulation eines PAL-Signals, SECAM-Signals oder NTSC-Signals erzeugen soll. Bei einem angenommenen fest eingestellten Vergleichswert P und einem festen Teilungsfaktor D sollen sich die beiden Frequenzen Fo/F wie D/P verhalten, so daß die anzulegende Referenzfrequenz Fo aus den gegebenen Werten leicht ermittelt werden kann.The value for the comparison value P depends on the frequency that the oscillator 1 is to emit. This value is different depending on whether the oscillator is to generate a frequency for demodulating a PAL signal, SECAM signal or NTSC signal. Assuming a fixed reference value P and a fixed division factor D, the two frequencies Fo / F to as D / P restrained, so that the reference frequency Fo to be applied can readily be determined from the given values.

Die in F i g. 1 gezeigte Datenverarbeitung, die dort parallel erfolgt, kann gegebenenfalls auch seriell vorgenommen werden.The in F i g. 1, which takes place in parallel there, can optionally also be carried out serially will.

Hierzu 3 Blatt ZeichnungenFor this purpose 3 sheets of drawings

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Claims

1 21 2

A circuit arrangement built according to the preamble of the claim is known (FR

22 94 587). It is used to control an oscillator

1. Circuit arrangement for generating a stable frequency which is a multiple of the frequency of a fixed frequency F with the aid of a reference frequency of a periodic binary signal. Here, the frequency F _0, the one that occurs in relation to the generated frequency number of binary transitions that low in a bestimmquenz F frequency with a Torschal- th period known. The oscillations of the oscillator to be controlled are counted while the gate signal is opened by dividing the low reference of a duration of several periods of the binary signal reference frequency F _{0, as well as with a gate signal at the input of the gate switch} is stored in a memory. In the switched-on voltage-controlled oscillator, depending on the memory content, an analog retor (VCO) is generated, the gate circuit generating a counter signal for the oscillator. Then the one that is connected is the one that reads the counters output by the oscillator as a function of the memory content and the passage time of the gate. The pulse must count so that the control loop can work, characterized in that the counting result is continuously recalculated at a comparison stage (10) for the presetting of the counter. This requires some effort, which is a fixed, predetermined comparison. The object of the invention is to supply this value (P) to avoid the effort at the output. This problem is solved by the comparison stage (10), an adder stage (11) connected in the characterizing part of claim 1, to which a first register (12) for intermediate storage is achieved.

assurance of the calculated value is switched that the claimed circuit arrangement has the

this first register (12) to a digital-analog advantage that a fixed setpoint value a

Converter (13) is connected to which the control-a certain frequency can be generated so that through

The output of the oscillator (1) to adjust it. Change the specified setpoint setting

is switched that the output of the first register 25 generated frequency can be varied in a simple manner

(12) to a second. Register (14) is switched, wel- can. This is important in case when using the same

ches with a further input of the adder circuit arrangement for several stable frequencies

(11) is connected, and that the two registers (12, different operating modes are to be generated, such as

14) alternately switched through as a latch register z. B. for the various reference frequencies at

will. 30 Receiving color television signals from the various

2. Circuit arrangement according to claim 1, there standards.

characterized in that the gate signal (C) starts with HiI- Below is based on an exemplary embodiment

fe of series-connected divider stages (4, 5, 6, 7) the essence of the invention with the help of the drawing

is formed, the divider stage (4) being the reference explained. The example refers to the

frequency (F ₀ ) by the factor 2 and the subsequent generation of a control voltage for a reference oscilloscope

Lowing divider stages (5,6,7) the divided reference relator in a color television receiver.

Divide the sequence by a factor D , where D is a measure. Fig. 1 shows the essential assemblies in one

for the resolution AF of the generated frequency F is the block diagram.

and has the value AFJAF , F is the generated Fre- F i g. 2 shows the derivation of some control pulses for

sequence, F ₀ the reference frequency and D a the reference 40 the arrangement according to FIG. 1.

dividing the reference frequency, the resolving power F i g. 3 shows a diagram to explain the effects

the generated frequency F is the determining factor. k manner of the circuit according to FIG. 1.

In Fig. 1, an oscillator 1 is used to generate a

fixed frequency F, which is applied to a multiplier 2

45, at the other input of which is the color signal FR, FB to be demodulated. At the output of the multiplier

The invention is based on a circuit arrangement stage, the demodulated color signal R or B can be

tion to generate a stable fixed frequency can be taken. The demodulated signal arrives

Using a reference frequency according to the generic term also to an input of a stage 3, at the other

of claim 1. 50 rem input the control described in more detail later

It is known that there is a fixed, precise and stable equilibrium voltage for the oscillator. This from one

quenz required for demodulation of color signals in digital-to-analog converter 13 supplied voltage is

a color television receiver. The generated is obtained in the following way:

Fixed frequency applied to a multiplier, at whose first input the modulated color signal is applied in the vicinity of the line frequency. The demodulating chain and 7 existing divider chain can then be divided down at the frequency Fo at 55 via an output of the multiplier consisting of stages 4, 5, 6. In the gete color signal can be taken. The demodulation example shown is a frequency Fo product and its accuracy or quality depends on 62,500 hearts, which with the help of the divider 4 initially depends on the fixed frequency generated. This frequency is divided by two and by subsequent stages by one today, mostly with the help of a voltage-controlled 60 factor D. In the example shown, D is equal to the oscillator (VCO) in a phase-locked loop circuit 32. The factor D is generated which determines the resolution (PLL). For this purpose, this PLL circuit needs some of the oscillator frequency generated. With the Frene as constant a reference frequency as possible, with the frequency division a gate pulse is obtained, which has a length of 512 \ is with the exactness of the loop from the height of this reference selected example. This frequency depends. A crystal is usually used to deliver a gate pulse is applied to a gate circuit 8 and this reference frequency is used. This is each open for the specified period of time in order to allow the pulses generated by a switching oscillator 1 to pass through, which is expensive and therefore increases the costs, the device of the type described above considerably. be given to a counter 9, which the pulses