DE3119161A1 - Self-clocked full-bridge circuit as a four-quadrant controller for electric motors - Google Patents

Abstract

A method is specified by means of which a full bridge in accordance with Fig. 1 is used for four-quadrant control (regulation) of electric motors, which full bridge controls the intensity and direction of the currents flowing through the motor inductance (14) via controllable switches (3, 4, 7, 8), especially semiconductor one-way switches, in a self-clocking manner. Only one of the controllable switches (3, 4, 7, 8) of a selected circuit is always pulsed by the bridge, especially in order to reduce the switching losses, while the other switches are merely switched on or off in accordance with the required current direction. When the switches are driven in a suitable manner, this results in a lower switching frequency of the pulsed switches.

Description

Self-clocked full bridge circuit as a four-quadrant controller for

Electric motors The invention relates to a method for operating a self-clocked full bridge circuit according to the preamble of claim 1.

In the case of such four-quadrant controllers, the corresponding Switch once the direction of current through the motor inductance and second through pulsing of these switches when an upper setpoint limit is exceeded or when falling below a lower setpoint limit, an average current value is achieved that largely corresponds to the setpoint. (See reference book "Power Electronics" volume 1 by Robert Jötten, pages 236 to 262.) As controllable switches are thyristors or transistors are most often used, as they provide a sufficiently high clock frequency of e.g. 1 kHz and more can be achieved.

However, in particular with electric motors of greater power difficulties with increasing switching frequency. For example, mainly join a use of semiconductor one-way switches when switching on and / or off Power loss peaks, the semiconductor switch with higher power or a Make parallel connection of further semiconductor switches necessary and additional Require measures for heat dissipation.

To avoid this, it is known (e.g. DE-OS 26 50 673 and DE-OS 26 51 492), this loss of power due to complex additional circuit arrangements largely to be avoided.

The object of the invention is the disadvantages caused by high switching frequency arise, in particular how to reduce the switching losses without great effort, whereby the advantages of a self-timed switching regulator such as the high efficiency should be preserved.

The invention as characterized in the claims solves this task and causes a significant reduction in the switching frequency una reduces the number of switches to be clocked. For example, the switching losses with much less effort - than when using the known circuit arrangements is required to avoid high switching losses - reduced to about a third will.

If this reduction is not sufficient, the known ones can also be used Circuit arrangements used to avoid the high power dissipation stress but then only for the smaller number of clocks to be clocked Switch will be required.

In the following the invention is illustrated with reference to the drawings Embodiments explained in more detail. 1 shows the known principle circuit diagram a full bridge circuit as a four-quadrant controller, FIG. 2 shows a diagram with current changes in the self-clocking in motorized operation Fig. 3 resulting in a clocking Circuits with motor operation, Fig. 4 with a clocking resulting circuits in generator mode Fig. 5 Current and switching curves in generator mode, 6 shows a basic circuit diagram for the control and FIG. 7 shows a three-phase bridge circuit.

In a known circuit according to FIG. 1, there is a connection 1 the operating voltage source 2 each have a connection of two controllable switches 3 and 4, each of which has a freewheeling diode 5, 6 connected in parallel. The second Connection of the two controllable switches is in each case on one connection of two further controllable switches 7, 8, the other terminal on the second terminal 9 of the operating voltage source. These switches 7 and 8 are also freewheeling diodes lo and 11 connected in parallel. At the connection points 12, 13 of the switches 3 and 7 as well as 4 and 8, a motor inductance 14 is connected, in the running Electric motor E a counter voltage 15 is released. The individual switches 3, 4, 7 and 8 with the free-wheeling diodes 5, 6, lo and 11 connected in parallel form the four bridge arms a full bridge circuit in whose shunt arm the motor inductance 14 is located.

This bridge circuit is used in a known manner as a DC chopper used, in motorized operation in clockwise rotation (1st quadrant) the switches 3 and 8 switched on when the setpoint falls below a lower limit value and are switched off when the setpoint exceeds an upper limit value, i.e. the two switches 3 and 8 located in the diagonal branches of the bridge become keyed at the same time.

When switches 3 and 8 are closed, a current flows out of the Operating voltage source via the switch 3 ', the inductance 14 and the switch 8, while with the switches open a freewheeling current in the same direction from the Inductance 14 further, via the free-wheeling diodes located in the diagonal bridge branches 6 and loain the operating voltage source flows back. In motor operation at Counter-clockwise rotation, the diagonal branches of the bridge swap their roles, i.e. switches 4 and 7 are clocked while switches 3 and 8 remain open.

In the method according to the invention, only one of the switches is ever used clocked, while the other closed or in the diagonally lying bridge branch stays open. If, for example, switch 3 is clocked with a clockwise start, it remains the switch 8 in this quadrant is constantly closed.

The clocking causes the same when switch 3 is closed As in the known method, however, the current rise when the switch 3 is open the decrease in the current to the same value, e.g. a lower setpoint limit value, a much longer time is required, since here the freewheeling current from the inductance can flow through the closed switch 8 and the diode lo.

For the dimensioning and construction of these circuits are the Switching losses of the controllable switches 3, 4, 7 and 8 are of essential importance, The switching losses increase almost linearly with the switching frequency. Conditional Due to the self-clocking, the switching frequency of the counter voltage is 15 (EMK) therefore dependent on the speed of the electric motor.

In FIG. 2, curve 17 shows the current through the motor inductance 14 during the start-up of the electric motor if there is no clocking.

When clocking in the lower speed range 18 with a small counter voltage 15 in the current limits 19 there is a rapid current increase in the known method, since only a small counter voltage 15 is effective and an approximately equally rapid current drop, since this too is essentially only determined by the operating voltage UB. In the middle speed range 20 the current rise is somewhat flatter, since here the effective difference value UB-Uls has become smaller, on the other hand takes place Power consumption is much faster because UB + U15 is now effective. In the upper speed range 21 there is only a slow current increase for the same reasons, however very rapid power drop. During the switching frequency in the lower speed ranges is relatively large, it decreases somewhat in the upper speed ranges. This can be seen from the clocked current curves 22, 23 and 24 shown in expanded form.

In the method according to the invention, the increase in current is in the single cycle phase largely the same, but the current does not flow into the operating voltage source in the clock-out phase 2 back, but there is a circuit across the closed switch 8 and the Free-wheeling diode lo closed. This results in the lower speed range Clock ranges with slowly falling current values according to curve 25.

In the middle speed range in which the counter voltage 15 is about half is as large as the operating voltage UB, the current rise and current fall times according to the curve 26 approximately the same size. In the current curve 27 for the upper speed ranges are the current drop times are shorter since the counter voltage 15 is large here. The shortest Cycle time results in the middle speed ranges and is around 50 there »Longer than the shortest cycle time with the known method. Since the Clocking at the constantly closed switch 8 no switching losses occur, reduce the total switching losses are around a third.

The same conditions apply when the motor is operated in counter-clockwise rotation e.g. by pressing switch 4 when switch 7 is closed. The circuit for the cycle time is shown in Fig. 3a and for the cycle time in Fig. 3b.

In order to achieve the same mode of operation with generator operation To be able to do so, the switch must be in the diagonally opposite bridge branch Switches that are lying down remain open. The circuits and current changes that act here are shown in Figs. In generator mode, a current setpoint should be used 30 the kinetic energy of the electric motor is consumed. For this purpose, the Control of the bridge, as explained later, a corresponding current value Setpoint voltage, which is in the polarity of a setpoint voltage for the opposite Corresponds to the direction of rotation and as a result, as provided for this direction of rotation, the Switch 3 clocks and the switch 8 closes (Fig 4a). In this time range a the upper current limit value 31 is reached very quickly without any clocking he follows. As with motorized operation, when the upper limit value is reached 31 the switch 3 is open. The resulting circuit according to FIG. 4b however, the freewheeling diode lo no longer causes a current reduction, but one further increase in current 32. With an appropriate circuit structure of the control can this current increase when a further limit value 33 is exceeded is used for this purpose are to open the switch 8 (Fig 4c). During the following time period c a current flows in the opposite direction into the operating voltage source via the freewheeling diodes 6 and lo back. Since the operating voltage is greater than the counter voltage 15 sinks the current is now off. If the current has decayed to the lower current limit value 34, it closes as in the motorized operation of the switch 3 again, and there is a circuit according to FIG. 4 d. During the following time period d, the current increases again as with time range b, but now there is a circuit in the bridge over the Switch 3 and the freewheeling diode 6 is formed until the upper current limit value again is achieved. If the kinetic energy of the motor is used up, the current increases in switch position Fig. 3 d no longer on, but falls below the lower current limit value from, where - in the same way as when the upper limit value is exceeded 33 am End of time range b - when falling below a further lower limit value 35 the switch 8 is rescnicssen and motor operation is initiated.

6 shows a circuit structure for controlling a full bridge 40 shown, whereby as usual, instead of the current setpoint and actual values accordingly Target and actual voltages can be used for control. The setpoint voltage is present at one input each of a comparator 41 with a small hysteresis and a comparator 42 with a slightly larger hysteresis.

At aen second entrances and at a window discriminator 43 is located the value voltage. If the actual value voltage exceeds the setpoint voltage an upper limit value 31, the output of the comparator 41 goes high, increases If the actual value continues, the comparator 42 also follows at a second limit value 33. If the actual value voltage falls below a lower first compared to the setpoint voltage Limit value 34, sc, the comparator 41 goes to low and after falling below a second Limit value 35 gent the comparator 42 to low. The window discriminator 43 its second input is at zero potential and only then gives a high signal at the Q output to two AND gates 44 and 45 when the actual value is in a zero range comes. The second inputs of these AND gates are at the output of the comparator 41 where the AND gate 44 is controlled directly and the AND gate 45 is controlled via an inverter 46 will.

The outputs of AND gates 44 and 45 are each at the R or S input of a flip-flop 47 and set this when the actual voltage is through the nuil range is about.

The Q output of the flip-flop 47 is connected to an input of two NOR gates 48 and 49 and two two AND gates 50 and 51.

At the second input of the NOR gate 48 and the AND gate So is the output of the comparator 41.

With positive setpoint and actual values - with locked flip-flopp 47 with Q output low - the switch controlled via the output of NOR gate 48 3 off when the upper limit value (31) is reached and when the lower limit value is reached (34) switched on.

In the case of negative setpoint and actual values, the comparator 41 and the locked flip flopp 47 with Q output high, switch 4 via the AND gate (vice versa) when a lower limit value that is insufficiently negative compared to the setpoint is reached switched on and switched off if the limit value is too negative. At the second entrances of the NOR gate 49 and the AND gate 51 is the output of the comparator 42, which as long as the actual value is in the ranges of the comparator 41, in the case of pcsitivem Setpoint -Low and, if the setpoint is negative, High. This will make the over the output of the NOR gate 49 controlled switch 8 closed with a positive setpoint held while the controlled via the output of the AND gate switch 7 is open remain. If the setpoint is negative, switch 8 is opened via NOR gate 49 held, while the controlled by the AND gate 51 switch 7, locked Flipp-Flopp 47 with Q output high, remains closed.

If the setpoint changes its polarity, e.g. from negative to positive and the Q output of the flip-flop is set to low and the current rises in positive direction until it exceeds the hysteresis of the comparator 41 (Fig 5, time range a). This output voltage U41 (FIG. 5) of the comparator 41 goes here to high and opens switch 3. The current continues to rise in freewheeling mode (time range b) and exceeds the hysteresis of the comparator 42, whose output voltage U42 then also jumps to high, whereby the switch 8 is opened. Through this the current decreases (time range c) until it reaches the lower limit of the hysteresis of the comparator 41 is reached and its output voltage U41 is low, whereby the switch 3 again is closed. Since the hysteresis limit of the comparator 42 is no longer thereafter is exceeded, this continuously delivers a high signal and holds the switch 8 opened via the NOR gate 49.

If the kinetic energy of the electric motor is used up, it decreases Current despite closed switch 3 up to the lower limit of the hysteresis of the comparator 42 from, the output of which then goes high, the switch 8 also closes and hereby initiates motor operation.

If the setpoint is zero, the output voltage of the comparator is also zero 41 and 42 on low. If the actual value is equal to zero, the output voltage of the window discriminator goes to high and the output voltage of the inverter 46 via the comparator 41 as well on high. As a result, the flip-flop 47 is reset via the AND gate 45. In order to achieve a secure initial state, the output of the AND gate is located 45 via an RC element at an R input of the comparator 42, which if necessary resets (output voltage low). Here the output voltages are the NOR gates 48 and 49 at high and the output voltages of AND gates 50 and 51 at low. This causes switches 3 and 8 to be switched on and a current through the motor inductance 14 until the upper limit of the hysteresis of the comparator 41 is reached and its Output voltage high via NOR gate 48, switch 3 opens. This sounds like the current decreases again until the output voltage of the window discriminator 48 is high goes. Since the output voltage of the comparator remains high, the flip-flop becomes 47 is set, whereby the Q output voltage jumps to high.

Via a further RC element 53 with a capacitor between the output of AND gate 44 and an S input of comparator 42 is also its output voltage set to high. As a result, the AND gates 50 and 51 are now the switches 7 and 4 are closed and switches 3 and 8 are opened via the NOR gates 48 and 49 will or will remain. Now a current increases in the opposite direction until the lower limit of the hysteresis of the comparator is reached and its output voltage drops back to low and switch 4 opens via AND gate 50. Through this the current dies down again until the window discriminator responds again.

The bridge circuit or the control can be arranged or differently being constructed. So switches 3 and 7 can be clocked and switches 4 and 8 toggled or switches 7 and 8 clocked and 3 and 7 toggled and the structure of the control depends very much on the application.

The application is not limited to DC motors, but can be used to control AC or three-phase motors in a correspondingly modified manner Find use. For example, three motor inductances can be achieved via three separate bridge circuits a three-phase machine, or these are as shown in Fig. 7, summarized in a star point 57, which is also at the zero point of an operating voltage source can lie. In such a three-phase bridge there are three controllable ones Switches 58, 59 and 60, 61 and 62, 63 in series between the connections 64, 65 the operating voltage source switched. At the connection points that are in series the three motor inductances 66, 67 and 68 are located. Allen controllable switches 58 to 63 is a freewheeling diode 69 to 74 in parallel switched.

The control takes place via three each at 120 degrees in the phase shifted setpoint alternating voltage, the upper switches 58, 60, 62 clocked and the lower switches 59, 61 and 63 toggled or vice versa.

At the connection points of the switches in series, instead of of the separate connections of the inductors 66, 67 and 68 also the corresponding these inductances are connected in a delta connection.

With a little more switching effort, the switching losses can be increased reduce if only the switch that is the only one energized is clocked one of the inductances 66, 67 or 68 with one of the connections 64, 65 of the operating voltage source has to connect, while two other of the controllable switches have the other inductors to the other connection of the operating voltage source. This is then done alternately always one of the upper ones after zero crossing of the setpoint alternating voltages lower switch and so on clocked, after a full AC voltage period has elapsed all switches are clocked once.

With very high outputs and / or separate heat dissipation for the individual switches it can also be useful to choose which of the switches is clocked should be, e.g. to make it dependent on a heat measurement at the individual switch. Single or parallel-connected power transistors are suitable as switches, as well as thyristors such as e.g.

GTO thyristors (gate turn-off thyristors) are particularly good.

Leadership

Claims (10)

Claims 1. A method for operating a self-clocked full bridge circuit as a four-quadrant controller for electric motors, with controllable switches in the individual Bridge branches, each of which has free-wheeling diodes connected in parallel, and with one motor inductance lying in the cross arm of the bridge, depending on the quadrant Self-clocked via two diagonal bridge arms to an operating voltage source can be connected, characterized in that each one in motorized operation the controllable one with a connection to one pole (9) of the operating voltage source (2) lying switch (7; 8) of a bridge branch closed during the clocking and remains open during generator operation, while a second of the controllable, with one connection at the other pole (1) of the operating voltage source (2) Switch (3; 4) is clocked in the diagonal bridge branch. 2. The method according to claim 1, characterized in that two of the controllable switches (7; 8) of the quadrant switching located in the bridge branches serve and from the controllable switches located in the two remaining bridge branches (3; 4) one at a time takes over the timing. 3. The method according to claim 1 for a three-phase bridge, characterized in that that three of the controllable ones located at one pole (64) of the operating voltage source Switches (58; 60; 62) are used for phase and quadrant switching and three of the am other pole (65) of the operating voltage source lying controllable switch (59; 61; 63) take over the timing. 4. The method according to claim 1 or 2 for a four-quadrant DC converter characterized in that in one quadrant during motor operation one of the controllable switches (7) is constantly closed and when changing to the generator operation remains open until the kinetic energy the engine is dismantled. 5. The method according to claim 1 or 2 for a four-quadrant AC power controller with a predetermined alternating current setpoint, characterized in that in the motorized Operation with positive instantaneous values of the setpoint a first controllable switch permanently closed and constantly open in the case of negative instantaneous setpoints, here a second controllable one, located at the other connection of the motor inductance Switch closes, which was open with positive instantaneous values and that depends a third or a fourth controllable switch of the respectively closed switch clocked wi: ti, de here one circuit via the motor inductance to the other T ol oer operating voltage source closes. 6. The method according to any one of claims 1 to 3 for a four-quadrant three-phase current controller with three phase-shifted AC current setpoints and three in the disturbance point or Motor inauctivities interconnected to form a triangle, with their three connections each at a cross-branch connection of a three-phase bridge with three times two in series lying bridge branches are connected, characterized in that three of the common to the one connection (65) of the operating voltage source lying controllable Switches (70; 72; 74) at the zero crossing of the respective AC current setpoint and can be switched over when changing from motor to generator operation and the three together at the other terminal (64) of the operating voltage source lying controllable switch (58; 60; 62) depending on the polarity of the corresponding, momentary AC current setpoint take over the timing. 7. The method according to the preamble of claim 6, characterized in that that only one of the six switches in the three-phase bridge branches (58 to 63) is clocked. 8. Self-clocked full bridge circuit for carrying out a method according to one of claims 1 to 7, characterized in that the controllable switches (3; 4; 7; 8) are semiconductor one-way switches, the switches (3; 4) to be clocked in per se known way about tax levels when exceeding or falling below a switch-on or switch-off signal from setpoint limits (31; 34) of a predetermined setpoint (30) received and the controllable switches (7; 8) of the other bridge branches via control stages can be switched, depending on the polarity of the specified setpoint (30) receive a control voltage for switching through or blocking at zero crossing. 9. Self-clocked full bridge circuit according to claim 8, characterized in that that for the detection of the overshooting and undershooting of setpoint limits (31; 33; 34; 35), Comparators (41; 42) and a window discriminator for detecting the zero crossings (43) is provided, the outputs of which are connected to a control logic, which control signals for the individual controllable switches (3; 4; 7; 8) supplies. 10. Self-clocked full bridge circuit according to one of the preceding Claims characterized in that the switches (3; 4) to be clocked have an additional Circuit arrangement known per se for reducing power dissipation stress when switching on and / or off.