DE3017960C2 - Circuit for generating an interrogation voltage for double gate transistors - Google Patents

Description

The invention relates to a circuit for generating an interrogation voltage for double gate sensors in an EPROM memory circuit with subsiral bias.

Virtually all LSI n-channel MOS circuits operate with substrate bias. Efforts have recently been made to integrate the bias generator on the circuit board and to make the bias variable and dependent on certain factors, e.g. B. the threshold voltages of the various transistors, the applied voltage (V " ) of the power supply, the temperature and the aging. A well designed substrate bias generator can produce an output voltage on the order of -1.0 to -7.0 volts with a power supply voltage Vc of 5.0 volts.

A disadvantage is that transistors of erasable programmable Nuriesespeiche. η (EPROMs) must have a threshold voltage of the size «? · 'r-rg from + 2.0 to +5.0 volts. Jair't en. : ute programmability is achieved. When connected to an EPROM transistor with normal Srhwellewertxvoltage between 1.5 and 25 volts t. . ^ Substraivorspannung is applied se- ^may: e rSchwellcnspannung up; to about 7VoIl rise and / ar · of the "specific resistance of the substrate material and the substrate voltage when the voltage (V _a) of the power supply is dependent on 5.0 volts. , therefore, it is impossible to set any transistors with a threshold voltage above 5.0 volts in the on-state. Incidentally, if the total threshold voltage of an EPROM transistor subjected to a substrate bias is lower than the 5.0 volts of the V _n - If the level would be, for example 4 volts, it can be switched to the on-state, but it can take an extremely long time for this, for example hours or days.

Because of these difficulties, the design of modern circuits, for example single-chip microprocessors, so far a choice has to be made whether to use either erasable programmable read-only memory on the Circuit dies should be used, losing all advantages of the substrate biasing technique, or to work with substrate bias and then memory of another type, i.e. no EPROMs, to use.

The invention is therefore based on the object of a To create circuitry for generating an interrogation voltage for Poppelgate transistors, which allows to obtain the advantages of the substrate bias technique using an EPROM memory circuit.

This object is achieved with a circuit of the type indicated at the outset, which is indicated by a reference voltage generator circuit for measuring the threshold voltage of an unprogrammed EPROM pattern transistor in the generator circuit when the substrate bias is applied, and for generating a reference output voltage which is equal to the threshold voltage,

a high-voltage tractor. which with the reference voltage generator circuit is coupled and responsive to the reference output voltage to produce an output signal equal to the threshold voltage plus a predetermined constant additional voltage, and

a gate transistor which is coupled between the output of the high-voltage generator and in each case one of several EPROM transistor gate conductors, the gate electrode of the gate transistor being coupled to the output of an x-selection circuit that works together with the memory.
The reference voltage generator circuit is of essential importance. which constantly measures the threshold voltage of an unprogrammed EPROW control transistor on the same semiconductor chip, and which of the same substrate bias voltage. Temperature. Aging and other other factors. which can influence the properties of the memory transistors. The output of this reference voltage generator circuit is a voltage, which is exactly equal to the threshold voltage of! 0 EPROM transistors, and it is applied to a high-voltage generator circuit, which adds a predetermined fixed voltage level to the reference voltage in order to obtain the desired access time of the memory.

Preferred embodiments of the invention are described below with reference to the drawings. F i g. I is a circuit diagram of a small portion of a conventional style EPROM circuit, and it shows that Connection to the reference generator and the high-voltage generator according to the invention;

F i g. 2 shows a simplified circuit diagram of the reference generator and the high-voltage generator, which is shown in FIG Fig. I are included in a block diagram;

F i g. 3A to 3D show various in the schematic representation of FIG. 2 symbols used and the associated equivalent circuits;

F i g. 4 shows voltage-time diagrams of signals at various in FIG. 2 designated points.

F i g. 1 shows a simplified circuit diagram of a small portion of an EPROM matrix 10 together with an associated one X selection circuit 12 and a Y selection circuit 14. The X selection circuit 12 can be a decoder circuit of the usual type, which, when appropriate Control one of the horizontal EPROM gate conductors, e.g. B. Head 16, 18 or 20, selects and one EPROM query voltage applies to all memory cells, which work together with the respective X line. The Y selection circuit receives in a corresponding manner 14 receives an input signal from a suitable Y-division decoder and causes a pre-charge at one of several vertical lines, for example lines 22,24,26 or 28. The one at the intersection the selected X-line division and the selected Y-line arranged memory / part is then interrogated by the interrogation signal, and a state of the line or the non-conduction, which represents a binary on / off state, can be achieved by an output buffer amplifier, for example amplifier JO. to be established.

EPROM cells arranged on integrated circuit chips are usually double-gate transistors formed, for example transistor 38 at the intersection of the Y line 22 and the X line 16. The double gate transistor is a silicon MOS transistor, such a floating gate, which is arranged between the η-channel and the Steuereate and is isolated from them. This floating gate affects the conductivity of the transistor only in to a small extent, unless it is ensured that it contains a charge of electrons. To therefore one To program EPROM transistor, a voltage becomes which is higher than the normal operating voltage is applied to the gate and drain electrodes, so that the floating gate absorbs and has a small electron charge. This charge of the floating Gates increases the conduction threshold of the double gate transistor from a low level of about 2 volts to a level of 10 volts or higher

on the amount of charge absorbed, είπα EPROM matrix, which contains several charged and uncharged double gate transistors, can therefore read that a read voltage is applied, which is at least equal to the threshold voltage of an unprogrammed or uncharged transistor is, however, still definitely below the threshold level of a loaded or programmed transistor

As already described, it was previously impossible to use EPROMs, for example the double-gate transistor cell matrix described. to be arranged on shading plates in which there is a negative substrate bias. The reason for this is. that the bias would significantly increase the threshold voltage of the EPROM transistor by varying amounts depending on the varying level of the substrate bias. The circuit shown in FIG. I now contains a reference generator 40 which, in the manner described, measures the threshold voltage of an unprogrammed EPROM test transistor which is located on the same substrate and is subjected to the same substrate bias. The reference generator 40 therefore generates a DC output reference voltage. which is equal to the threshold voltage of the unprogrammed EPROM transistor and, accordingly, of all other unprogrammed EPROM transistors which are located on the same semiconductor die and are subjected to the same substrate bias. The high-voltage generator 42 receives this reference voltage and it increases this voltage by a fixed level of z. B. 25 volts to increase the access speed of the memory to a level of about 200 nanoseconds. The conductor 44 at the output of the high-voltage generator 42 is connected to the drain electrodes of several gate transistors, for. 46, 48 and 50., and the gates of these transistors are connected to the horizontal X-lines of the matrix 10 via light-depletion transistors, which will be described below. The source electrodes of these transistors are connected directly to the control gates of the EPROM transistors in the line assigned to them, and the control gates of transistors 46, 48 and 50 are connected to the corresponding X lines at the output of the X selection circuit 12.

Fig. 2 schematically shows details of the reference generator 40 and the high-voltage generator 4Z soft in FIG. 1 are included in a block diagram. The drawing according to FIG. 2 includes transistors and various inverter circuits. which are depicted with different symbols. These different circuits are shown in Fig. 1 for ease of illustration and explanation. 3 reproduced.

3A to 3D show the various in Fig.2 obtained inverter circuits. In Fig. 3A, the symbol for an inverter includes a small triangle. The equivalent The schematic representation is located directly below the inverter symbol. and it contains one Light depletion stress transistor 52. which between Kv and the output terminal. The gate element of transistor 52 is coupled to the output terminal and drain of a transistor 53 thereof Source is at ground reference potential and whose gate forms the input of the circuit

F i g. 3B shows an illustration of how the circuit in FIG. 3A, with the difference that the fully drawn triangle within the inverter symbol represents a severe depletion load, so that depletion transistor 54 is always in the on-state; According to this illustration, there is no voltage drop between V _n - and the output terminal.

3C shows an inverter symbol in which the letter "E" is located. This shows an enhancement transistor 56 which is located between V _K and the output, the gate of transistor 56 being coupled to the current source Kr. Transistor 56 is located

ίο is therefore always in the on state, but it introduces a threshold voltage factor between V _n and the output.

F i g. 3D shows the symbol for a gate whose high or low output is controlled by inputs a and b , as the associated schematic drawing shows. Transistor 58 as shown in FIG. 3D may be an enhancement circuit with the letter "E", a light depletion stress transistor with the open triangle or a heavy depletion trinsistor with the solid triangle.

The description of the schematic time 'g according to FIG. 2 continued The reference generator within the dashed line 40 contains one or more unprogrammed or uncharged EPROM transistors 60, 62, which are located between circuit point 64 and ground reference potential. Since a reference voltage control transistor 88 to be described below requires a gate voltage which is significantly higher than the voltage V _n supplied to the circuit, a voltage pump circuit is provided. A potential Kr of preferably 5 volts is applied to terminal 66 and then it is brought to a higher voltage of about 7.5 volts through the voltage pump circuit with series-connected transistors 68, 70 and 72. Gate and drain of transistor 68 are connected to one another, and the source electrode is connected to the gate and drain of the transistor «; The transistor 70 is also capacitively coupled to a phase of the associated two-phase computer clock circuit. The source of the transistor 70 is coupled to the gate and drain of the transistor 72, the gate element of which is capacitively coupled to the second phase of the two-phase clock circuit. The pumping effect achieved by the two clock phases generates a high-frequency half-wave direct current signal above the Kr base potential, and this half-wave signal is filtered by a capacitor 74, which lies between the ground reference potential and the source element of transistor 72. The voltage now occurring at the source of transistor 72 is considerably higher than the voltage V _1x . and it is preferably 7.5 volts
In order to ensure that faster power is available when the circuit is started up, the reference generator preferably contains a start-up circuit with transistor 76, which is located between the Kv terminal and conductor 78. The gate of transistor 76 is coupled to the output of an inverter 80 thereof Input comes from node 64 so that. when the potential at node 64 is at zero level, inverter 80 applies a positive signal to the gate of transistor 76; the potential Kr is therefore at the beginning on conductor 78. Subsequently, when node 64 assumes a potential, inverter 80 will switch transistor 76 into the off state.

The source of transistor 72 in the voltage pumping circuit carries the higher voltage over

Conductor 82 to a heavy depletion stress transistor 84 sandwiched between conductors 82 and 78. The gate terminal of transistor 84 is coupled to conductor 78, so that transistor 84 has a variable resistance depending on the voltage level on conductor 78. Conductor 78 is coupled to circuit point 64 via an enrichment transistor 86, the gallery element of which is coupled to conductor 78, transistor 86 is n \ dr * la forth constantly in liin "/. ustnnd, and it leads a small voltage drop which is equal to its Sehwcllenspannüng. the voltage between node 64 and ground reference potential is determined by the threshold voltage of the EPROM transistors 60 or 62. There is therefore a voltage divider circuit between the high-voltage conductor 82 and ground potential, which contains a series resistance of transistor 84, the threshold value of enhancement transistor 86 and the threshold value of EPRGM transistor 60 or 62, and node 64 will always be at a level which is the same the threshold value of an unprogrammed EPROM transistor rs is.

Conductor 78 will be at a level which is equal to the threshold of the EPROM transistor plus the threshold of the enhancement transistor 86. Conductor 78 connects to the gate electrode of an enhancement transistor 88 connected, the source element of which is connected to the V ^ terminal 66.

The voltage appearing on the drain electrode of the transistor 88 becomes equal to that on its gate applied voltage minus the threshold voltage of transistor 88. Since conductor 78 is at a potential equal to the threshold value of the EPROM transistor 60 or 62 plus the threshold voltage of transistor 86, the voltage at the output of the Transistor 88 may be a voltage threshold lower than the voltage appearing on conductor 78 or it becomes exactly equal to the voltage threshold of the unprogrammed EPROM transistor 60 or 62.

In the schematic drawing of the reference generator 40 there is a pair of series-connected transistors 90 and 92, which are connected in parallel with EPROM transistors 60 or 62 and lie between circuit point 64 and ground potential. These transistors are double gate transistors like EPROM transistors 60 and 62: however, they are designed so that the two gates within each transistor are interconnected so that their respective threshold voltages are about half that of EPROM transistors 60 and 62 with floating gate. The purpose of series transistors 90 and 92 is to provide essentially the same voltage threshold at node 64 should the two EPROM transistors 60 and 62 be programmed in any way and not the desired EPROM threshold voltage at node 64 provide. The transistors 90 and 92 are therefore not required for the actual operation of the circuit, but according to a preferred embodiment they are provided with an auxiliary function as a safety group.

The output of the reference generator 40 carries a voltage which is exactly equal to the threshold voltage of an unprogrammed EPROM transistor as described above.

If this voltage level were applied to the EPROM transistors in the matrix 10 of FIG. 1, the unprogrammed storage transistors would one Output, but the memory access time would be on the order of hours.

<; In order to set this / ugriffszoit to a technically usable value, it is necessary to set the read or KPROM transistor voltage over the threshold level licr iinprogramniierlen IiPUOM transistors; iny.uhcbcn. If (lic Lcscspaniuing were unnecessarily high,

κι the programmed EPROM transistors can deliver a false output, and even if the reading voltage is appropriately reduced in order to avoid such an erroneous output / u, reading the matrix would only result in a higher voltage. than it is necessary. over time the program destroy. Therefore, a more precise, predetermined voltage level must be above the unprogrammed Schwcllensspannung are generated. As already described, This higher reading voltage controls the gas speed of the storage, and it was found that a read voltage of 2.5 volts plus the EPROM threshold voltage is required to achieve a Get access time of around 200 nanoseconds. If access times are required for slower access the mentioned higher voltage values can be reduced somewhat.

The EPROM transistor threshold reference voltage generated in the reference generator 40 is applied to the high-voltage generator 42, and it is switched here by a gate transistor 96, the drain electrode of which is connected to the output conductor 44. which with the source electrodes of all X-choice gate transistors is in connection, for example transistor 46. which is described in connection with FIG became. The drain of transistor 96 is also grounded through a gate transistor 98 connected, and the control gate of transistor 98 is coupled to input terminal 100 to which an active low read phase signal is applied by the associated computer circuit. Until the earth-pointing read signal is applied to input terminal ICO, transistor 98 is therefore "on" to earth conductor 44. and when applied of the read phase signal, transistor 98 is switched "off" so that conductor 44 is from ground is separated.

For a better understanding of the circuit of the high-performance generator 42 according to FIG. 2, time-voltage curves are shown in FIG. 4, which show signals occurring at various points in the circuit, which are denoted by the corresponding letters. Curve A in FIG. FIG. 4 shows the read phase signal falling to ground potential, which is applied to terminal 100 in accordance with the illustration in FIG. 2 lies. The signal is applied to the gate of transistor 98 to render it non-conductive, and it is also applied to one input terminal of a NOR gate 102 which produced a low output prior to the application of the signal falling to ground, which was applied to the gate of transistor 96 via transistor 104. The gate of transistor 104 is directly coupled to the Kt 'source so that a high voltage is applied and transistor 96 is placed fully in the on state.

The read phase signal at terminal 100 is also sent through a delay circuit, soft contains a heavy depletion inverter 106 in series with a βC circuit in which transistor 108, the gate of which is returned to its entrance

ίο

10

is coupled to be a resistor; the AC circuit also includes a grounded capacitor 110. The output from this RC delay line is represented by curve B in FIG. 4 represents which is normally at a low level; it is raised to its high level approximately 250 nanoseconds after the low-to-ground signal is applied to terminal 100. The delay line also contains an enhancement inverter 112, the output voltage level of which is controlled by the signal output of the transistor 108 according to curve B in FIG. The output of transistor 112 is therefore given by the same signal β of FIG. 4 reproduced. and this signal is applied to the second input terminal of NOR gate 102 so that a signal is generated at its output which is represented by curve C of FIG. 4 is reproduced. The transistor 96 in the high-voltage generator circuit 42 is therefore only switched to the on state for a period of approximately 250 nanoseconds in accordance with the curve Cin.

The output of inverter 112 is applied to the input of a light stress depletion inverter 114, which receives its second input from terminal 100. When the B input to inverter 114 is high its output is grounded and when the input transitions low the inverter is enabled to receive the A signal at terminal 100. The result is a signal which is indicated by curve D in FIG. 4 is shown; it will be interrupted at the entrance of 98 to earth.

The EPROM gate or read voltage applied to conductor 44 is now conducted through gate transistor 46 to the control gate of the selected EPROM transistor. When the X selection circuit 12 has selected the X _{o line} 16. For example, the 5 volt signal V _n .- from circuit 12 (curve CJ in FIG. 4) is applied to the gate of transistor 46 through light depletion transistor 126. The gate of transistor 126 is _{coupled to V n} - and the gate of transistor 46 will accept _{the full voltage V tc.} When the high-voltage generator 42 then provides an output to the conductor 44, a portion of this higher voltage is capacitively coupled to the gate of the transistor 46, as shown by the capacitor 128 shown in dashed lines, which represents the capacitance present within the circuit. This will raise the gate voltage of transistor 46 an additional amount above its normal. Level V ₁₁ - corresponding to the representation of curve H in FIG. 4 increased. This additional amount is proportional to the ratio of the capacitance of 128 to the sum of capacitances 128 and 130 (between the gate of transistor 46 and ground). The transistor 46, which now has a high gate voltage, is fully switched to the "on" state and will apply the required high read voltage to the gates of those EPROM transistors which are connected to the X line 16; this is also shown by curve ] in FIG. 4th

The invention allows in an advantageous manner

20th

Inverter 116 applied. Shunted to inverter 116 jo representation of a circuit on the semiconductor plate is a circuit which contains an inverter 118 and an integrated MOS circuit with a Zennen transistor 120; the gate element of the transit unit and an EPROM, the correct stors 120 being _{coupled to the current source V n} - so that EPROM read voltage independent of the substrate in the output drain a full V _n signal is generated at control voltage of the central unit. This is applied to 116, which generates an output signal which is achieved in that the circuit generates a voltage through the curve in FIG. 4 is reproduced. ZugEgenerator contains, which continuously a

Double gate EPROM transistor measures and supplies a reference voltage which is exactly the same as its threshold voltage is, and a controlled high-voltage generator, which the reference voltage by a fixed Value increased in order to achieve optimal access time and gate-

40

The output from inverter 116 is applied to one side of a capacitor 112, the other terminal of which is connected to conductor 44 and the drain electrode of gate transistor 96. As already described, by applying the read phase signal to terminal 100, transistor 96 is put into the on-state, while transistor? * S is put into the off-state. About 250 nanoseconds later, transistor S6 is turned off while transistor 98 remains off. Like curve F in FIG. 4 shows, the output of inverter 116 is applied to capacitor 122 at the instant transistor 96 is turned off. This has the consequence that the voltage on conductor 44 increases by a value which depends on the ratio of the capacitance of the capacitor 122 to the total circuit capacitance 124 in a selected X line of the EPROM matrix 10 Welding voltage of the EPROM transistor to the drain terminal of transistor 96 to raise a voltage which is equal to half the value of V _n . is. Capacitor 122 is therefore carefully selected so that its capacitance is equal to the total X-line circuit capacitance 124. The signal appearing at point Fin of the circuit is therefore represented by curve F in FIG. 4; its first step shows the threshold voltage of the EPROM transistor, while the second, rounded step _{speaks half the value of V ir} en ' . It can be seen that the voltage drops back to its low level when the read signal a' at terminal 100 and accordingly the line through To get transistor voltage of EPROM.

For this purpose 2 sheets of drawings

Claims (13)

30 17 9 * 0 claims: 1. Circuit for generating an interrogation voltage for double gate transistors in an EPROM memory circuit marked with substrate bias by a reference voltage generator circuit (40) for measuring the threshold voltage of an unprogrammed double gate transistor in the generator circuit with applied substrate bias, and for generating a reference output voltage, which is equal to the threshold voltage is a high-voltage generator (42), which is connected to the reference voltage generator circuit (40) is coupled and responds to the reference output voltage in such a way that that he is an exit signal! generated, which is equal to the threshold voltage plus a predetermined one constant boost voltage is, and fine gate transistor (46,48,50), which between zj the output of the high-voltage generator (42) and one of several EPROM transistor gate ::} is coupled to festering, the gate electrode of the JGate transistor (46,48,50) with the output of a - is coupled to the X selection circuit (12) which cooperates with the memory. 2. Circuit according to claim 1, characterized in that that the total output voltage generated by the high-voltage generator (42) "is higher than that Threshold voltage of an unprogrammed EPROM transistor and lower than the threshold voltage of the programmed EPROM transistor. 3. A circuit according to Ansp »xh 2, characterized in that the high voltage generator (42) is controlled by an external read pulse with einvi 'first pulse duration (A) and has a delay circuit (106,108,112) that picks up the read pulse and that of the Reference voltage generator circuit (40) converts the reference voltage received into a voltage pulse of a second duration (C) which is shorter than the duration of the first pulse 4. Circuit according to claim 3, characterized in that that the high-voltage generator (42) contains a capacitor (122) which between the Output conductor of the generator (42) and the output of the delay circuit (106,108,110,112) and is charged to a first level by the reference voltage pulse of a second duration. wherein the delay circuit (106, 108, 110, 112) upon termination of the reference voltage pulse second duration provides the capacitor (122) with an additional charge. 5. A circuit according to claim characterized thereby-7firhnpt Haß dip 7ii ": ät7lirhp! .Adunp reaches a total amplitude _{which is proportional to the supply voltage V 1x} times the ratio of the capacitance of the capacitor (122) to the output capacitance of the output conductor of the high-voltage generator (42). 6. Circuit according to one of claims f-5, characterized characterized in that the voltage reference generator circuit (40) has at least one unprogrammed Contains double-gate EPROM transistor (60 or 60, 62). 7. Circuit according to claim 6, characterized by at least two series-connected non-programmable, double gate transistors (90, 92) with connected gates giving essentially the same threshold voltage measurement as the EPROM transistor (60 or 60,62) deliver. 8. A circuit according to claim 6, characterized in that the output reference voltage of the reference voltage generator circuit (40) is controlled by a control transistor (88) which lies between the supply voltage V _n - and the output conductor of the reference generator (40), the voltage control electrode of the control transistor ( 88) is coupled to the EPROM transistor (60 or 60,62) and is responsive to the threshold voltage of the EPROM transistor (60 or 60,62) in such a way that it adjusts the output level of the reference voltage generator circuit (40) to the voltage level of its Voltage control electrode minus the threshold voltage of the control transistor (88) controls 9. A circuit according to claim 8, characterized in that the EPROM transistor (60 or 60, 62) connected in series with a first transistor (86) whose threshold voltage is equal to the threshold voltage of the control transistor (88) is around the measured EPROM transistor threshold voltage by an amount equal to the threshold voltage drop through the control transistor (88) is, so that the control transistor (88) provides an output voltage exactly equal to that of the soft Threshold voltage of the EPROM transistor (60 or 60,62) 10. A circuit according to claim 9, characterized in that the reference voltage generator sound (40) a voltage pump circuit (68,70,72) contains the amplitude of the voltage across the Raise level V.v of the circuit, with the raised Level applied through the first transistor (86) and the EPROM transistor (60 and 60, 62, respectively) and is applied to the control electrode of the control transistor (88) 11. A circuit according to claim 10, characterized in that the reference voltage generator circuit (40) contains a start-up circuit (cf. 76) which responds to a low output of the voltage pump circuit (68, 70, 72) in such a way that it has a voltage level V _1x . directly applied to the control electrode of the control transistor (88) 12. A circuit according to claim 6, characterized in that the control gate of the gate transistor (46, 48, 50) is coupled to the output of the X- \ Va! I! Scha ', device (12) via a transistor whose gate is coupled to voltage level V. ₁₁ - lies 13. A circuit according to claim 12, characterized in that the voltage level on the control gate of the gate transistor (46,48,50) above the level V ₁₁ . is increased by an amount which is proportional to the output level of the high-voltage generator circuit (42) and the source-to-gate capacitance of the gate transistor (46, 48, 50). and inversely proportional to the sum of the source-to-gate capacitance and the gate-to-ground capacitance.