DE3008443A1 - DIGITAL DATA PROCESSING ARRANGEMENT - Google Patents

Description

- 19 patent attorneys 3 QO 84 4

Dipl.-Ing. Dipl.-Chem. Dipl.-Ing.

E. Prince - Dr. G. Hauser - G. Leiser

Ernsbergerstrasse 19

8 Munich 60
Our sign; T 3305 February 29, 1980

TEXAS INSTRUMENTS INCORPORATED 13500 North Central Expressway-Dallas, Texas, V.St.A.

Digital data processing order

The invention relates to a digital data processing arrangement and more particularly to one having an image display device and a memory controller equipped digital data processing arrangement.

Digital data processing systems with image reproduction devices are known. Examples of known video systems that use relatively rigid image patterns one or more moveable patterns are disclosed in U.S. Patent No. 4,107,664 and U.S. Patent No. 4,129 described. Systems for the digital generation of image blanking sync signals are also known; these systems however, generally produce only monochrome image reproductions, or they produce their own chrominance and luminance signals for application to conventional color saturation and video modulators. Examples of this can be found in

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U.S. Patents 4,107,665, 4,116,444, and 4,129,858. Digital Data processing systems typically contain one or more storage systems that can be addressed by a processing device. Using a Inexpensive PMOS read-only memory can significantly reduce the cost of the storage devices; however, the slow operating speed of such memories is due to the increased processor latency to a considerable reduction in effectiveness.

The problems occurring with known digital data processing arrangements are eliminated with the aid of the invention solved. An important feature of the invention is an image display processor that provides an image blanking sync signal for application to an image display unit in an image display system supplies and reproduces a first video image superimposed on this signal.

Another important feature of the invention is a video generator that incorporates a monolithic image display processor is combined and contains a single voltage divider circuit, all for generating an image blanking sync signal supplies the necessary reference voltage values.

Another important feature of the invention is a memory controller with an auto-incrementing Address counter.

The invention will now be explained by way of example with reference to the drawing. Show it:

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1 shows a schematic representation of a digital data processing arrangement with the preferred one Embodiment of the invention,

Fig. 2 is a block diagram of the image rendering processor of Fig. 1,

Fig. 3 is a block diagram showing the overlay control section of the image rendering processor illustrates

Figure 4 is a schematic representation of the control register section the image rendering processor,

FIG. 5 is a flow chart which, together with FIG. 3, shows the mode of operation of the overlay control part of the image rendering processor generally indicates

6 shows another embodiment of a section of the Flow chart of Fig.5 »

7 shows another embodiment of a further section of the flow chart of Figure 5,

Fig. 8 is a flow chart for explaining the operation of the Read / write memory control section of the image reproduction processor,

Fig. 9 is a schematic representation of the priority selection section the image rendering processor,

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10 is a schematic representation of the FarbphaseAgeneratorabschnitts Bildwiederg _a beprozessors,

Fig.1i a schematic representation of the color decoding and Video mixing sections of the image rendering processor,

12 shows a diagram containing several signals for the purpose of explanation the operation of the video generator portion of the image. Playback processor,

Fig. 13 shows a block diagram of the slow read-only memory (ROM) contained in Fig. 1 and <

14 shows a flow chart for explaining the mode of operation of the slow read-only memory shown in FIG.

FIG. 1 shows a digital data processing arrangement which is the preferred embodiment of the invention contains. The digital data processing arrangement 10 generally consists of a central processing unit 12, a memory subsystem 14, an input / output subsystem 16 and an image display subsystem 18. The central processing unit 12, which can be formed by a monolithic microprocessor of the type TI 9985, works in a conventional manner of control by digital control programs stored in memory subsystem 14, with the working usually in response to processing requests initiated via the input / output sub-system 16 are working in the input / output sub-system 16 an I / O control unit 20, which can be formed by a monolithic, integrated circuit of the type TI 9901,

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conventionally so that a central processing unit transfer bus 22 is coupled to an I / O bus 24 which is connected to one or more I / O control units 20 connected is. The I / O input control units 26 can for example, the following conventional devices: input devices including a keyboard 28, multiple handheld devices 30 and various types of remote sensors 32; Output devices including a speech synthesis unit 34 and ßines printer 36 for the production permanent copies; Dual-directional input and output devices including one Magnetic disk unit 38, a magnetic tape unit 40 and a transmission modem 42.

In the memory subsystem 14, it is often desirable to have some fixed storage capacity (ROM) with some Combine read / write storage capacity (RAM). With such a structure, support programs For example, a suitable operating system and an assembler or compiler, stored in permanent memory, while user programs and volatile data are stored in read / write memory. Be that way the relatively static programs are held in the relatively inexpensive permanent memory, so that only the relatively short-term existing programs and data must be stored in the generally more expensive read / write memory.

In the preferred embodiment shown in Figure 1, the storage subsystem 14 is also constructed so that the inexpensive and relatively slow read-only memory and the dynamic read / write memory are advantageous

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are used that no significant impairment of the performance of the central unit 12 occurs. In the read-only memory section of the storage subsystem 14, a relatively limited portion of a fast read-only memory 44 _f, preferably of an N-channel MOS type such as the TI 4732, is directly connected to the central unit 12 via a memory bus 36, while a larger proportion is a relatively slow read-only memory 48 , preferably of a P-channel MOS type such as the TI 0430, is connected to the central unit 12 via a bus buffer 50, for example the TI 74LS245, which is inserted between the memory bus 46 and an auxiliary bus 52. In that each device forming the slow read-only memory 48 is provided with an internal, self-incrementing address counter, the central unit's organizational header associated with the sequential access to the slow read-only memory 48 is greatly reduced. Also, if, as in the TI 0430 device, each of the devices making up the low-speed read only memory 48 is assigned its own ROM address page number, another group of such devices can be added to form a ROM library module. 54 for connection to the auxiliary bus 52 is created via a suitable plug connection. The ROM library module 54 therefore forms a plug-in module.

In the read / write memory section of the memory subsystem 14 is a block from a dynamic read / write memory 56, preferably of the N-channel MOS type such as the TI 4027, connected to the central processing unit memory bus 46 via a RAM bus 58 and via an image display processor 60. The image reproduction processor 60 is constructed so

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that it is in addition to those to be described below further functions has the ability of a self-incrementing address counter, as it is in the slower Read only memory 48 forming devices is included. In addition, the image rendering processor 60 provides a periodic refreshing of the contents of the various devices forming the read / write memory 56. The central unit 12 is thus freed from the task of each access in a sequence of sequentials Accesses to the read / write memory 56 to provide addresses, and it is also of the considerable Organizational intent, normally the periodic refreshing of the dynamic read / write memory assigned.

In the image display sub-system 18, the image display processor 60 are activated by the central unit 12 via the memory bus 46 so that all video control and generate synchronization signals necessary on a raster scan television to reproduce a group of playback data previously generated by the central unit 12 and stored in the Read / write memory 56 have been stored. The resulting image blanking synchronous signal (BAS signal) is provided on signal path 62 and can either be a dedicated monitor device or a conventional RF modulator 64 prior to application to a conventional television receiver. In the preferred embodiment, a tone generator 66, for example of the type TI 9919, is connected to the central unit 12, connected via the auxiliary bus 52; this tone generator delivers

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an audio signal controlled by the central unit, which is sent to an auxiliary loudspeaker 68 via a signal path 70 or the RF modulator 64 via a signal path 72 for mixing with the BAS signal generated by the image display processor 60 are fed.

The image display processor responds to facilitate initialization and synchronization of the system preferably to a manual reset or to an external synchronization signal on one Signal path 74 such that its various control sections are placed in a known state. It is also believed desirable that the image display processor 60 have an externally generated BAS signal received via a signal path 76 and with the internally generated BAS signal for output via the signal path 62 can mix. For example, under certain circumstances it may be desirable to have the image display processor 60 generated BAS signal with a BAS signal generated by an auxiliary television camera or from a broadcast television signal is derived. In this embodiment, the image reproduction processor can expediently be synchronized with the external BAS signal source by conventionally suitable Synchronization sections separated from the external BAS signal on signal path 76 and the image display processor 60 are supplied via the signal path 74. As is readily apparent to those skilled in the art, this is facilitated the ability of the image rendering processor to input and external video signals Synchronization, the merging of two or more image reproduction processors 60, which increases the data reproduction

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and animation capabilities of the digital data processing device 10 are greatly improved.

In Fig.2 is the block diagram of the image rendering processor 60 of Figure 1. The image display processor 60 is constructed to be in both a RAM control mode as well as in a video control mode, with between there is considerable simultaneous operation of these two modes of operation. Much of the circuit to achieve the RAM control functions can also expediently be achieved together with additional circuit parts the video control functions. In this way there are considerable savings in terms of time and circuit complexity.

In general, a central processing unit interface 78 responds to requests for access made over the memory bus 46 come from the central unit 12. When a central unit access request is initially received, transmit the interface 78 transfers the selected RAM address via a register bus 82 to a register control unit 80 so that it is stored in a specific control register in a control register group 84. In the event of a write request, the interface 78 inputs the write data from the memory bus 46 a central processing unit data register 86 via an address and data bus 80 and it resolves a central processing unit write access request for operation by a RAM control unit 90. In response to the write request the RAM control unit 90 takes the RAM address through the register control unit 80 from the control registers

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and forwards the RAM address via the RAM bus 58 to the read / write memory 56 (RAM). In addition to it The RAM control unit 90 transfers the write data from the central processing unit data register 86 via the RAM bus 58 into read / write memory 56. In the event of a read request, interface 78 merely resolves a central unit read access request for operation by the RAM control unit 90. As in the case of a write request, the RAM controller 90 transmits then the RAM address from the control registers 84 into the read / write memory 56. Then work on it the RAM control unit 90 with the read / write memory together so that from the read / write memory 56 over read data supplied to the RAM bus 58 are input to the central processing unit data register 56. When the central unit 12 calls up the data, the interface 78 transmits the data from the data register 86 at the address and Data bus 88 supplied read data via the memory bus to the central unit 12.

As soon as a write request has been serviced, the RAM control unit 90 causes an automatic advance the RAM address contained in control registers 84 so that a subsequent CPU write access request can be carried out in the next address space in the read / write memory 56 by simply transfer the write data from the central processing unit 12 to the data register 86 via the interface 78 will. In the same way, the RAM control unit 90 also switches those contained in the control registers 84 RAM address continues automatically after a read request has been operated so that a subsequent central processing unit

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Read access request from the next address space can be carried out in the read / write memory 56 as soon as the interface 78 has transferred the previous read data to the central unit 12 has ended. The central unit 12 spends in this way a minimal amount of time waiting for one. Data transfer, ^ after an access request has been delivered.

When a register access request is received from the image display processor, the interface transmits 78 the address of a particular register from the group of control registers 84 via the register bus 82 to register control unit 80. In the event of a register write request, interface 78 transmits the Write data from memory bus 46 to register bus 82 for subsequent transmission via the register control unit entered into the selected control register 84. In the event of a register read request, the register control unit connects 80 the selected control register 84 with the register bus 82, the interface 78 in connection »On it connects the register bus 82 to the memory bus 46.

When the image reproduction processor 60 is only operating in the RAM control mode, the RAM control unit 90 operates conventionally so that an access to each of the refresh segments in the write / Read memory 86 is performed. The content of the read / write memory is protected in this way in the event that that the central unit 12 the refresh segments during

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does not perform normal RAM access operations.

In the video control mode, the image display processor generates a BAS signal corresponding to a group of control parameters contained in control registers 84 using a group of display data fields stored in read / write memory 56. When reproduced on a suitable picture display device, the BAS signal generates a video picture made up of M columns and N rows of individual picture elements that are separated from one another. For information display convenience, the (MxN) picture elements can be viewed as being grouped into smaller, contiguous groups or blocks that can be shaped or defined to form distinguishable characters or patterns as in conventional character generators. In addition, the preferred embodiment of the image ^{rendering processor 60 enables multiple moveable blocks or M} gnomes "to be freely moved with respect to the fixed rendering image by specifying or selecting a particular column U in row V at which the upper left corner of the gnome to be rendered is located The image display processor 60 thus generates the BAS signal synchronously with the currently present column and row positions X and Y of the fast scan, so that either the fixed patterns or the movable gnomes are displayed.

In the preferred embodiment, the image rendering processor 60 operates in one of three ways certain image display modes selected by the control center, namely in a graphic pattern mode, in a multicolor operation or a text operation. In the graphic pattern mode, the image rendering processor 60 generates a 32-column, 24-row one Image made up of patterns (8x8 picture elements), which consist of a

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Pattern generator table (256 pattern definition blocks) corresponding to a pattern name table (768 pattern names) to be selected; it also superimposes up to 32 movable patterns or "gnomes" (8x8 picture elements), from a gnome generator table (256 gnome definition blocks) corresponding to a gnome name table (32 gnome description blocks) can be selected, which also includes the displacement of each gnome relative to the image pattern define. The image rendering processor generates in multicolor operation 60 a 32-column and 6-row picture from color samples (2x8 blocks of 4x4 picture elements each), from a sample color table (1536 elements) corresponding to a sample name table (192 pattern names) can be selected, where up to 32 gnomes can be created in essentially the same way as in the graphic pattern mode. In text mode the image rendering processor 60 generates a 40-column and 24-row image from patterns (6x8 Picture elements) obtained from a pattern generator table (256 pattern definition blocks) according to a pattern name table (960 pattern names) is selected. The image reproduction processor selects each of the three image reproduction modes 60 out of 16 individual colors including white, gray and black as well a special transparent state to be described in more detail later. Since the image rendering processor 60 in the multi-color mode and in the text mode, apart from the differences indicated above, essentially just as works in the graphic pattern mode, the discussion below deals primarily with the precise working method in the graphic sample operation.

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During system initialization and, if necessary, thereafter, the image display processor 60 operates in the memory control mode with the central unit 12 so that in the read / write memory 56 the various playback data fields can be created for one of the three picture reproduction modes. So that the image rendering processor 60 can work in the graphic pattern mode, the central unit 12 should, for example, be in the read / write memory 56 store the various pattern and gnome tables that the image rendering processor 60 requires. The pattern generator table consists of several consecutive ones Pattern definition blocks of eight 8-bit bytes each, which form the bit pattern for the individual Define patterns as in conventional character generators. In contrast to this, the pattern name table consists of a field arranged in rows and columns Pattern names that organize the pattern definition blocks into each of the 32 columns of 24 pattern rows, which represent a video sample image covering the full screen. It also provides a color swatch table wells for each of the 32 contiguous groups eight pattern definition blocks of the pattern generator table together two video color code groups, each of the Video color code groups of one of the 16 available colors is equivalent to. The pattern name table, the pattern generator table and the pattern color table thus represent an ordered field, whereby the individual bits that form a pattern deletion block, which by means of the Video color code groups associated with the sample color table in each of the M columns of N rows of picture elements which form a full screen video sample image. Consists in the same way the gnome generator table from several consecutive gnome definition blocks, each consisting of three 8-bit bytes consist of certain bit patterns for each of the as

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Define Gnome Patterns to Use. The gnome name table, on the other hand, consists of thirty-two 4-byte gnome description blocks, the a certain column shift U and a certain row shift V for the reproduction of the particular Define gnomes in terms of the video sample image, where 1 = U ^ M and 1 = V ^ N. Also includes each of the gnome description blocks in the gnome name table has a gnome name referring to a specific Gnome definition block in the Gnome Generator tab, as well as a video color code group that consists of Specifies a specific color for the 16 available colors that the active section of the gnome should adopt. The gnome name table and the gnome generator table therefore represent an ordered field, whereby the individual Bits that form a gnome definition block, the video color code group assigned via the gnome description block arrange into S columns out of T rows of picture elements that make up a particular video gnome image form, where 1 ^ S ^ M and 1 H T ^ N. To The dimensions of the pattern and gnome images as well as the displacement of the Gnome image with respect to the model image expressed by individual picture elements, since the format of the different Tables in read / write memory 56 are generally discrete to the specific number of rows and columns Symbols or characters is related, which are characteristic of the selected picture display mode.

A sequence control unit 92 operates in a conventional manner So that a cyclic column count X and a cyclic row count Y are maintained which indicate the chronologically successive position of the raster scan of the image display unit.

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As will be apparent to those skilled in the art, part of the entire raster scanning period used for the active reproduction of patterns on the image display device, since a section of each horizontal scan row is assigned to horizontal return, while a number complete rows or horizontal scans for performing vertical return and the related synchronization is required. At least during the active playback period however, the sequencer 92 does the column count X and the row count Y via the address and data bus 88 available. The sequence control unit also provides a color reference signal via a signal path 94 at a frequency related to the 3.5 MHz NTSC carrier; she also delivers to one Synchronization bus 96 is a group of synchronization signals which is generally conventional in shape. In response to the reset signal or the external synchronization signal on signal path 74, the sequence control unit clears the column and row numbers, and it synchronizes the color reference signal and the synchronization signals with the external source. In the preferred embodiment, there is sequencer 92 from a conventional clock circuit and from two programmable control fields (PLA) for generation various control signals on a control bus 98 depending on the current column and row numbers.

An overlay control unit 100 operating as a function of the column and row numbers requests this RAM control unit 90 periodically to retrieve selected sections of the pattern and gnome table from the write / Read memory to be taken. When the playback data is supplied from the read / write memory 56 via the RAM bus 58 the overlay control unit 100 receives the pattern data and delivers on a pattern bus a first pattern signal that is the bit in the pattern generation 030038/0766

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gate-table, which the picture element in the column X the row Y of the video gnome image, where: I = X = M and 1 "= Y ^ N. The overlay control unit 100 also receives the gnome data, and it delivers a second pattern signal via the pattern bus 102, which the Contains bit in the gnome generator table which the picture element in the column (X - U + 1) of the row (Y-V + 1) of the video gnome image if rU ^ X ^ CU + applies and V ^ Y ^ (V + T). Also receives the overlay control unit 100 the video color code groups that spring Patterns and assigned to each gnome during their rendering. In other words, the overlay control unit processes 100 the pattern data fields so that the correct bit patterns for each of the selected Patterns can be supplied throughout the period of time that playback is active, but while they are the Gnomdatenfeider processed so that the correct Bit patterns for each selected gnome are only provided during the portion of the active playback period, specified for reproduction.

The two sample signals and the associated video color code groups are applied to a priority voting unit 104 over the pattern bus 102. In response, that only the first pattern signal is received, the priority selection unit 104 selects an associated video color code group associated with the first pattern signal, and with the selection from the current digital value of the first pattern signal is dependent. On the other hand, the priority selection unit dials 104 in response the reception of the second sample signal, the video color code group assigned to it, whether the first sample signal is now also received or not.

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If neither the first pattern signal nor the second mistake signal is received, the priority selection unit 104 generally selects an error video color code group, which is provided by one of the control registers 84 via an error color bus 106. Vfean in a preferred embodiment the overlay controller 100 provides a second pattern signal for each of a plurality of active gnomes the priority selection unit 104 selects the second Pattern signal corresponding to the gnome image, which is generated according to a predetermined priority order of the available Gnome images has the highest priority. For example, if it is assumed that the overlay control unit 100 can simultaneously provide a second pattern signal for each of four different gnomes, who represent four gnomes out of a priority group of 32 gnomes, chooses the Priority selecting unit 104 selects the second pattern signal corresponding to the gnome from among the four gnomes that the has the highest priority. In any case, the video color code group is transmitted via a color bus 108 as a video control signal which corresponds to the current, selected pattern signal.

A color phase generator 110 which is part of a BAS video generator 1-12 receives this from the sequencer 92 supplied color reference signal via signal path 94, and it generates the six NTSC color phase signals, each phase shifted by a predetermined amount with respect to the color reference signal are. In a color decoder 114, the video color code groups are decoded which are that of the priority selection unit 104 form video control signals supplied over the color bus 108, and after decoding they become

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a video mixer 116 is supplied together with the color phase signals supplied by the color phase generator 110. In the video mixer 116, each couples from the color decoder 114 decoded video color code groups in a selected manner a complementary color phase signal pair to a subsequent one yet to be described switching unit on, so that the information part of a BAS signal for output is generated via the 'signal path 62. The video mixer 116 also receives the data from the scheduler 92 synchronization signals supplied via the synchronization bus 96, and it creates the usual horizontal, vertical and color sync sections in dependence thereon of the BAS signal. In the preferred embodiment, the video mixer 116 can be switched to external video mode in which an external video signal received over signal path 76 is selected in a selected manner is combined with the internally generated BAS signal for output via signal path 62.

In Figure 3 is a block diagram is shown that generally the operation of the overlay control unit 100 (FIG. 2) according to the flowchart shown in FIG illustrated, the stored by the central unit 12 in the control register 84 shown in FIG Information is used. The overlay controller 100 is generally responsive to the Column and row numbers that are provided by the sequence control unit 92 will be delivered. When the column number X and the row number Y indicate that the raster scan is on At the beginning of one of the horizontal rows of the active display area, the overlay control unit enters 100 enters a sample processing procedure 118 (decision block 120) and requests the RAM

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Control unit 90 to load the pattern name associated with the current column and row numbers from the pattern name table of a name holding circuit 122 (processing block 124). In response to this access request from the image reproduction processor, the RAM control unit 90 concatenates a pattern name table base address stored in a pattern name table base register 126 (FIG. 4) with the current row number Y and the current column count X, thus a RAM address for output to the read / write memory 56 is derived. For example, in graphic pattern mode, the upper five bits of row number Y and the upper five bits of column number X provide access to any of the 788 pattern names.

After the pattern name is input to the name holding circuit 122, the overlay control unit 100 requests the RAM control unit 90 to make two Video color code groups from the sample color table in two sample color registers 128 (processing block 130) to load. In response to this access request from the image display processor, the RAM control unit chains 90, a pattern color table base address stored in a pattern color table base register 132 (Fig. 4) with an appropriate high order portion of the pattern name to derive a RAM address for output to read / write memory 56. In the preferred embodiment, for example the upper five bits of the pattern name provide access to one of 32 video color code group pairs for the consecutive group of eight pattern names in the pattern name table. In a preferred Execution defines one of the video color code groups,

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which is assigned to a particular pattern, the color of the foreground or information section of the pattern « image, while the other video color code group is the color of the background or constant portion of the Defined sample image.

After the video color code groups have been loaded into sample color registers 128, the overlay controller requests 100 instructs the RAM controller 90 to insert a specific byte out of the eight bytes or pattern lines from the pattern generator table Pattern Shift Register 134 (processing block 136) to load. In response to this access request from the image display processor, the RAM control unit chains 90, a pattern generator table base address stored in a pattern generator table base register 138 (Fig. 4) with the pattern name stored in the name holding circuit 122 and with an appropriate one Lower order section of the running number Y, so that a RAM address for output to read / write memory 56 is derived. In the preferred Execution, for example, the lower three bits of the row number Y give access to a specific byte the 8-bit sample bytes that are assigned to the sample name selected pattern definition block.

After loading, the pattern shift register 134 outputs one by one Each successive bit of the pattern line in response to a column control signal, which it receives from the sequence control unit 92 via the signal path 98a synchronously with the column-wise! Move the raster scan is guided within the active display area ±. The second pattern signal on In this way, signal path 1O2a forms a chronologically consecutive digital representation of the den full screen pattern image when the

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Raster scan scans the active display area.

After the pattern line has been loaded into the pattern shift register, the overlay control unit switches 100 an internal central unit access index (processing block 14O) in modulo-four operation. If the resultant value of the central processing unit's access index is not equal to 3 (decision block 142) and if so If a stop flag has not been set in a manner to be described hereinafter (decision block 144), the overlay controller occurs enters a gnome preprocessing procedure 146 and advances a running gnome number included in a Gnome counter 148 (processing block 150) is included. Subsequently, the overlay control unit 100 requests the RAM control unit 90 to perform the row shift Get V for the current gnome number from the gnome name table (processing block 152). In response to this access request from the image display processor, the RAM control unit chains a gnomname table base address stored in a gnomname table base register (Fig. 4) with the current gnome number and an additional number, which is the special byte in the gnome description block that defines the row shift V, so that a RAM address for output for write / Read memory 56 is derived. In the preferred embodiment, the row shift is V, for example in the first byte of the gnome description block

for each gnome included in the gnome name table. (

The overlay control unit 100 compares in a subtraction and comparison unit 156 the found row shift V with a

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predetermined stop code group (decision block 158), which then, if it is present, indicates that all subsequent entries in the gnomname table ignored or otherwise not processed. Although essentially any value can be used outside the active row number range makes the preferred embodiment of the Stop code value 208 uses which is outside the active playback range from 0 to 192, however is within the entire number of rows range from 0 to 255. Doing this can be a considerable Number of RAM access cycles for use can be made available by the central processing unit 12, if so desired, less than the 32 available gnomes.

If the row shift V does not equal the stop code group, the subtract and determine Comparison unit 156 as to whether the running number Y is within the desired display range the current gnome number (decision block 160). If the running row number Y is within the display range for the running gnome number (see 6), the overlay control unit 100 the current gnome number into a FIFO gnome stack 162 (first-in-first-out stack) (processing block 164).

If the row shift V equals the stop code group (decision block 158) or if the Gnome stack 162 is full (decision block 166) upon entry (processing block 164) of the current gnome number, the above-mentioned .stop flag is set set (processing block 168). After this, or if the Gnome stack 162 is not full, (Ent-

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divorce block 166) after the current gnome number has been entered (processing block 164), or if the current row number Y is not within of the display area of the current gnome number (decision block 160), the overlay controller 100 examines the current column and row numbers again (decision block 120).

If, on the other hand, the central unit access index is 3 (decision block 142) or the stop flag has been set (decision block 144), the overlay controller sets a central processing unit access identifier (processing block 170) indicating that a RAM access cycle has been allocated for use by the central processing unit 12 that this has been needed. Subsequently, the overlay control unit 100 checks the current column and row numbers again (decision block 120).

If the number of columns X and the number of rows Y indicate that the raster scan. Between the end of a horizontal Row and the beginning of the next horizontal row is in the active playback area, the Overlay control unit 100 in a Gnom post-processing procedure 172 (decision block 120). If the gnome stack 162 is not empty (decision block 174), the overlay controller picks up 100 is the first entered gnome number (processing block 176). The overlay controller requests then the RAM controller 90 to determine the column shift U for the particular gnome number from the Gnome name table in a gnome down counter 178 to load (processing block 180). In response to this access request from the image rendering processor

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the RAM control unit 90 concatenates those in the gnomname table base register 154 (Fig. 4) stored gnomname table base address with the particular gnome number and an additional number indicating the particular byte in the gnome description block that the column shift U is defined to derive a RAM address for output to read / write memory 56. In the preferred embodiment, the column shift U is, for example, in the second byte of the Contains gnome description blocks for each of the gnomes defined in the gnome name table.

After the column shift U is loaded into the gnome down counter 178, the overlay controller 100 prompts the RAM controller 90 to the video color code group for the particular gnome number from the gnome name table into a gnome color register 182 (processing block 184). In response to this image rendering processor access request the RAM control unit 90 concatenates the gnomname table base register 154 (FIG. 4) saved gnome name table base address with the determined gnome number and an additional number, the specifies the specific byte in the gnome description block that defines the video color code group for a RAM address for output to read / write memory 56 is derived. In the preferred For example, the video color code group is in the fourth byte of the gnome description block included for each gnome defined in the gnome name table. After the gnome video color code group has been loaded into the gnome color register 182,

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the overlay controller 100 requests the RAM controller 90, the row shift V for the specific gnome number can be found in the gnome name table (Processing block 180). In response to this access request from the image reproduction processor, the RAM control unit 90 stores the gnomname table base address stored in the gnomname table base register 154 (FIG. 4) with the specific gnome number and an additional number for the specific byte in the gnome description block, which indicates the row shift V so a RAM address for output to read / write memory 56 is derived.

Calculated in the subtraction and comparison unit 156 the overlay control unit 100 an offset value, by subtracting the detected row shift V from the current row number Y (processing block 188). Overlay controller 100 then prompts RAM controller 90 for the gnome name for the particular Load gnome number from the gnome name table into name hold circuit 122 (processing block 190). as The RAM control unit 90 concatenates the response to this access request from the image reproduction processor those stored in the gnomname table base register 154 (FIG. 4) Gnome name table base address with the specified gnome number and an additional number that specifies that Byte in the gnome description block, which defines the gnome name, so a RAM address for the output to the read / write memory 56 is derived. In the preferred embodiment, the gnome name is for example in the third byte of the gnome description block for each

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of the gnomes defined in the gnome name table.

After the gnome name in the name holding circuit has been loaded, the overlay controller requests 100 the RAM control unit 90 on, one or more bytes or gnome lines (see Fig.7) from the Load the gnome generator table into a gnome shift register (processing block 194). As answer to this access request of the image rendering processor, the RAM control unit 90 concatenates those in a gnome generator table base register 196 (Fig. 4) stored gnome generator table base address with that in the name holding circuit 122 stored gnome name and with the calculated offset value (processing block 188), so that a RAM address for output to read / write memory 156 is derived.

After the gnome line in the gnome shift register has been loaded, the overlay controller 100 sets the central processing unit access flag (Processing block 198) indicating that a RAM access cycle for an application by the central processing unit 12 has been assigned, if necessary. The overlay control unit then checks 100 again the contents of the gnome stack 162 (decision block 174).

If the gnome deck 162 is empty (decision block 174) the step flag is reset by the overlay control unit 100 (processing block 200), thereby enabling the gnome preprocessing procedure 146

030 0 38 / 076S

becomes (decision block 144). The overlay control unit 100 also clears the ones contained in the gnome counter 148 Gnome number (processing block 202) for subsequent use by the gnome preprocessing procedure 146. The overlay controller 100 then rechecks the current column and row numbers (decision block 120).

After the raster scan back into the active display area has occurred, the gnome down counter 178 continuously decrements the column shift it contains as a function of the column control signal which the sequence control unit 200 via the signal path 134 supplies. After the reduction to the counter reading 0, the Gnom down counter 178 carries the column control signal to the gnome shift register 192. In response to the column control signal, the gnome shift register provides consecutively the successive bits of the gnome line. The first sample signal exists on signal path 102b So from a chronologically consecutive, digital representation of the particular gnome image only during the Section of the raster scan selected for rendering the gnome.

In the preferred embodiment, the group of gnomes defined in the gnome name table can be one of four certain sizes selected size can be displayed. For example, the central unit 12 can be a MAG bit reset in a control register 204 (Fig <> 4),

€ 30038/0766

so that the overlay control inhe ifc1 OO is requested, classify each bit in a gnome definition block into a single picture element, or it can set the MAG bit, so that the overlay controller 100 is prompted to to organize each bit in the gnome definition block into a 2x2 block of picture elements. In the same way, the Central unit 12 reset a SIZE bit in control register 204 so that overlay control unit 100 prompts each gnome as an 8x8 pattern of bit elements using eight consecutive ones Build up 8-bit bytes as a gnome description block. The central unit 12 can also set the SIZE bit so that the overlay controller 100 is prompted to subdivide each gnome as a 16xi6 pattern of picture elements Use of 32 consecutive 8-bit bytes as Build gnome description block. If the central unit 12 sets both the MAG bit and the SIZE bit, The overlay control unit 100 builds each gnome as a 16x1 (? pattern from 2x2 blocks of picture elements using of thirty-two 8-bit bytes as a gnome description block. Compared to the standard or Error bit, the SIZE bit alone causes a quadrupling of the gnome image area without loss of detail resolution, while the MAG bit alone quadruples the gnome image area, but with a quadruple loss the detail resolution causes. The actual display area for each gnome thus generally depends on the selected dimensional parameters (decision block 16O of Figure 5).

030038/0766

In the gnome preprocessing procedure 146, the Overlay control unit 100, whether the current row number Y is within the display range for each in the gnome defined in the gnome name table (decision block 160). In making this determination, the overlay control unit calculates 100 get an offset value by taking the row offset V for a given gnome number subtracted from the current row number Y (processing block 206 of Figure 6). If the calculated The offset value is less than 0 (decision block 208), the row number Y is not yet the specified Row shift V is reached and the overlay controller 100 can restore the current column and check row numbers (decision block 120 of Figure 5). However, if the calculated offset value is greater than 0 (decision block 208), however is not greater than 7 (decision block 210), the current row number Y is clearly within the Display area for the specific gnome number, and the overlay control unit 100 outputs the specific Gnom number in the stack 162 (processing block of Figure 5).

If the calculated offset value is greater than 7 (decision block 210) and neither is the SIZE bit the MAG bit is still set (decision block 212), then the current row number Y lies outside the display range of the specific gnome number, and the Overlay control unit 100 can again check the current column and row numbers (decision block 120 of Figure 5). However, if the SIZE bit or the MAG bit

030038/0 7 66

is set (decision block 2i2) and if the calculated The offset value is no greater than 15 1st (decision block 214) then the running row number Y is within of the extended display range of the current gnome number, and the overlay control unit 100 gives the current gnome number in the gnome stack 162 (decision block 164 of Figure 5). If on the other hand the calculated Offset value is greater than 15 (decision block 214) and if the SIZE and MAG bits are not set (decision block 216) then the current row number Y is outside the expanded range of the certain gnomes, and the overlay controller 100 can again check the current column and row numbers (decision block 120 of FIG. 5). If the SIZE and MAG bits are set (decision block 216), however, the calculated offset value is greater than 31 (decision block 218), then if the current row number Y is outside the maximum display range of the particular gnome, and the overlay control unit 100 can again check the current column and row numbers (decision block 120 of FIG. 5). If the SIZE and MAG bits are set (decision block 216), but the computed offset value is no greater than 31 (decision block 218), then the running number Y is of course within the maximum playback range for the particular gnome, and the overlay control unit 100 inputs the particular gnome number into the Gnome stack 162 (processing block 164 of Figure 5).

Ö300 38/0 76B

In the Gnom post-processing procedure 172, if the MAG bit is to be set (decision block 220 7) when the gnome shift register 192 is loaded is to be (decision block 194 of Figure 5) the overlay control unit 100 the calculated Offset value (processing block 188 of Figure 5), through 2 (processing block 222 of Figure 7), before the RAM control unit 90 is requested to select one of the bytes or one of the gnome lines from the Load gnome generator table into gnome shift register 192 (processing block 194 of FIGS Fig. 7). In this way, each byte of a particular gnome definition block is referred to for each of two consecutive rows of the gnome image exercised an access. If on the other hand the SIZE bit is set (decision block 224 of FIG. 7), the overlay control unit 100 adds to the calculated Offset value is 16 (processing block 226) and requests RAM controller 90 to a second byte or gnome pattern line from the top half of the 32-byte gnome definition block to load (processing block 228). If the MAG bit is also set (decision block 220), then of course the calculated offset value has already been set (processing block 222) that two consecutive accesses to each of the bytes in the upper half of the extended gnome definition block be allowed. The gnome shift register (Fig.3) is of course constructed in such a way that it can contain up to 16 bits

03003 ^ / 0766

or two gnome lines from a gnome definition block. The gnome shift register 192 should only be on every second Respond column control signal supplied to it from Gnom down counter 178 so that each bit in of the gnome line during the movement of the raster scan across two column locations as the first pattern signal is delivered.

In summary, it can be stated that the overlay control unit 100 consecutive sections of the pattern fields processed during the Perlode, in the the raster scan passes through each row within the active display area so that the pattern data for the particular row are available for immediate playback o essentially simultaneously performs the Overlay control unit 100 preprocessing the gnome fields so that those gnomes are selected which are to be reproduced in the following series. During the intermediate horizontal retrace interval the overlay control unit 100 processes only those Sections of the gnome fields assigned to the selected gnomes so that the gnome data is available when the raster scan reaches the corresponding column parts in the next row. In this way the overlay control unit 100 can do all the necessary Perform pattern and gnome processing functions, while the central unit 12 still has the option of periodically accessing the read / write memory 56 exercise.

Referring to Figure 8, there is shown a flow chart showing the general Operation of the RAM controller 90 of Figure 2

030038/0766

3Q08443

illustrated. The RAM control unit 90 operates generally depending on the number of rows Y received from the sequence control unit 92 is supplied via the address and data bus 88. For example, if the number of rows shows Y, that the raster scan is in the active display area (decision block 230 of Figure 8), and if so Central processing unit access identifier (processing block 170) of Figure 5 is set (decision block 232 of Figure 8), the RAM controller 90 effects the reset the central processing unit access identifier (processing block 234). When a central processing unit access request has been triggered over the central processing unit interface 78 (decision block 236), the RAM controller executes 90 performs a central processing unit access procedure 238. Otherwise, the RAM control unit 90 reverses to examine the running row number Y (decision block 230).

In the central processing unit access procedure 238 transmits the RAM control unit 90 which is initially stored in an address register 240 (FIG. 4) via the interface 78 RAM address via RAM bus 58 to read / write memory 56 (processing block 244), the RAM control unit 90 puts the read / write memory 56 into the read state and supplies corresponding control signals, the input from the read / write memory 56 supplied Effect data into data register 86 (processing block 246). If on the other hand the central unit s-access is a write request, the RAM controller 90 relocates the read / write memory 56 into a write state, and it transfers the data contained in the data register 86 to the RAM bus 58,

030038/0766

so that they are stored in read / write memory 56 (processing block 248). In any case, the RAM control unit 90 automatic switching the RAM address contained in the address register 240 (processing block 250). Then examined the RAM controller 90 returns the current row number Y (decision block 230).

If the row number Y indicates that the raster scan is within the active display area (decision block 230) and the CPU * access flag is not set (decision block 232) but an image rendering processor access request is pending (Decision block 252), the RAM controller 90 builds a corresponding RAM address in the manner outlined above and it outputs this RAM address along with corresponding RAM control signals to the RAM bus 38 (processing block 254). Then the RAM control unit delivers suitable control signals for entering the data supplied by the read / write memory 56 into the corresponding register (Processing block 256). If there is then no access request from the image reproduction processor floats (decision block 252), the RAM controller 90 again checks the running row number Y (T decision block 230).

When the running number Y indicates that the raster scan is outside the active display area (Decision block 230) but has not yet reached the end of a picture or screen (decision block 258), the RAM controller 90 enters a refresh procedure 260 a. In the refresh procedure 260, the RAM control unit 90 performs the RAM accesses,

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which are necessary so that the content of the read / write memory 56 is periodically refreshed with certainty. In particular, the RAM control unit 90 gives with each Perform refresh procedure 260 using an internal refresh counter, a refresh address (processing block 262). Following this, the RAM control unit 90 switches increments the refresh counter (processing block 264) corresponding to the sequential Addressing Each of the refresh segments of the read / write memory 56 is selected. The RAM control unit 90 determines whether a central processing unit access request floats (decision block 236).

When the running number Y indicates that the raster scan is outside the active display area (Decision block 230) and just the end of a picture or has reached screen (decision block 258) the RAM control unit 90 works together with the interface 78 so that the central unit 12 in corresponding Mode is interrupted (processing block 266). The RAM controller 90 then performs the refresh procedure 260 through.

The circuit diagram of the priority selector 104 from FIG. 2 is shown schematically in FIG. The priority selector consists primarily of a gnome selection section 268, a pattern foreground selection section 270, a pattern background selection section 272 and an error selection section 274. In the gnome selection section 268, an AND receives

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Element 276 the second pattern signal supplied by the gnome shift register 192 via the signal path 102a. The AND gate 276 also receives an active playback control signal from the sequence controller 92 via the signal 98a, when the column and cell counts indicating that the raster scanning is within the active display area. As can be recognized by those skilled in the art, the AND gate 276 provides a gnome selection signal with a high signal value for application to a gnome color switching element 2/8 via a signal path only when the second pattern signal and the active playback control signal have a high signal value. For example, the gnome selection signal has a low signal value when the active display control signal on signal path 98a has a low signal value, which indicates that the raster scan is outside the active display area. In the same way, the gnome selection signal has an o-low signal value when the second pattern signal on signal path 102a has the digital value "0", which indicates an inactive pixel in the corresponding section of the video gnome image. In response to receiving the high level gnome select signal, the gnome color switch 278 transmits the video color code group provided by the gnome color register 182 via the signal path 102b to the color decoder 114 via the color bus 108.

In the preferred embodiment, the gnome selection section also includes an OR gate 282 which is input via a signal path 284 provides an output signal which can be applied to AND gate 276 and which indicates the state of the video color code group obtained from the gnome color register 182 has been provided over signal path 102b. In particular, OR gate 282 provides an output signal

030038/0766

with a high signal ^{value on} signal path 284 when the video color code group received from gnome color register 182 via signal path 102b has a digital value other than zero. On the other hand, the OR gate 282 provides a low level output signal when the video color code group received via the signal path 102b has the digital value "0". In the latter case, the AND gate 276 outputs the gnome selection signal with a low signal value, and the gnome color switching element 278 does not transmit the video color code group from the signal path 102b to the color bus 108. A video color code group with the digital value "0" thus leads to a specific one Image element of the gnome image to a transparent state.

In the pattern foreground selecting section 270, an AND gate 286 receives the first pattern signal transmitted through the signal path 102c is supplied from the pattern shift register 134. AND gate 286 also receives from the sequencer 92 active playback control signal provided on signal path 98a. Furthermore, the AND gate 286 receives the complement of the AND gate 276 via an inverter 288 between the complement of the gnome selection signal supplied to the signal path 280 and a signal path 290. As for the professional can be seen, the AND gate 286 provides a foreground selection signal with a high signal level for application to a Foreground color switching element 292 via a signal path 294 only when the first pattern signal and the active reproduction control signal have a high signal value and the gnome selection signal has a low signal value. For example, the foreground selection signal is low Signal level when the active playback control signal on path 98a is low, indicating that

030038 / 078S

the raster scan is outside the active display area. In the same way, the pattern selection signal has a low value when the first pattern signal on signal path 102c has the digital value "0", the indicates an inactive pixel in the corresponding portion of the video sample image. The foreground dial signal however, is also low when the gnome dial signal on path 280 is high, which indicates that the gnome is active on the particular pixel. In other words, it means that the pattern foreground selecting section 270 is overridden or blocked when the gnome selection section 268 is active, so that the Gnome image is actually superimposed on the sample image. On the other hand, when the gnome selecting section 268 is inactive while the pattern foreground selecting section 270 is active is, the foreground color gate 292 is responsive to the high level foreground selection signal in such a way that it is received from the foreground portion of the swatch color register 128 via the signal path 102d video color code group provided over the color bus 108 to the color decoder 114 transmits.

As with the gnome selection section 268, the preferred embodiment includes the pattern foreground selection section 270 also an OR gate 296 which has an output signal for application to the AND gate 286 via a signal path 298 that outputs the state of the foreground portion of sample color register 128 via signal path 102d supplied video color code group. In particular

330033/0766

30Q8443

the OR gate 296 outputs a high signal value on the signal path 298 when the video color code group received from the foreground portion of the sample color register 128 via the signal path 102d has a digital value other than νοη'Ό ". On the other hand, the output signal of the OR gate 296 has a low signal value if the video color code group received via signal path iO2d has the digital value "O." In the latter case, AND gate 286 provides a foreground selection signal with a low signal value, and foreground color switch element 292 does not transmit the video color code group from signal path 102d to color bus 108 Sample foreground video color code group with the digital value ¹¹ O "thus leads to a transparent state after classification in a specific picture element of the sample image.

In the pattern background selection section 272, an AND gate 300 receives the logical inversion of the first pattern signal auä the pattern shift registers 102c via an inverter 302 which is connected between the signal path 102c and a signal path 304 is inserted. The AND gate 300 also receives that from the sequence control unit 92 active playback control signal provided over signal path 98a. As with the pattern foreground selection section 270, the AND gate 300 receives the logical inversion of the gnome selection signal, which is transmitted from the negator 288 via the signal path 290 is delivered. In addition, AND gate 300 receives the logical inverse of the pattern foreground select signal via an inverter 306 which is inserted between the signal path 294 and a signal path 308.

As can be recognized by a person skilled in the art, the AND element 300 supplies a background selection signal with a high signal value for application to a background color switching element 310 via a signal path 312 only when (1) the active playback control signal has a high signal value, (2 ) the first pattern signal has a low signal level, (3) the gnome selection signal has a low signal level, and (4) the foreground selection signal has a low signal level. For example, when the background selection signal is low, the active display control signal on path 98a is low, indicating that the raster scan is outside the active display area. In the same way, the background selection signal has the low signal value when the first pattern signal on the signal path 102c has the digital value "1 ^H , which indicates an active picture element in the corresponding section of the video image pattern. Furthermore, the background selection signal has the low signal value when either the gnome selection signal is on the signal path 280 or the foreground selection signal on path 294 has the high signal level. In other words, the background selection signal has the high signal level only when the gnome selection section 268 and the pattern foreground selection section 270 are inactive, but the raster scan is within the display area In response to receipt of the high level background select signal, background color switch 310 transmits the orbcode group provided by the background portion of sample color register 128 via signal path 102d to color decoder 114 via color bus 108.

030038/0766

In the preferred embodiment, the pattern includes background selection section 272 also has an OR gate 314 which has an output signal for application to the AND gate 300 via signal path 316 that indicates the state of the from the background of sample color register 128 via signal path 102d. In particular, the OR gate 314 provides an output signal high on path 316 when that from the background portion of sample color register 138 is through path iO2d delivered color code group one different from "0" Has digital value. On the other hand, the OR gate 314 outputs an output signal with a low signal value, if the video color code group received on signal path 1021 has the digital value "0". In the latter case, the AND gate 300 outputs the background selection signal with a low level And the background color switch transmits the video color code group received from signal path 102eb not to color bus 108. A sample background video color code group with the digital value "0" leads therefore to a transparent state when classifying in a certain picture element of the sample image.

In the error selection section 274, an AND gate 380 receives this from the sequence control unit 92 via the signal path 98a provided active playback control signal. As with the pattern background selecting section 272, the AND gate receives 318 is the logical inversion of the gnome selection signal supplied by the inverter 288 via the signal path 290 and the logical inversion of the foreground selection signal supplied by inverter 306 via signal path 308.

030038/0761

30Q8443

In addition, the AND gate 318 receives the logic inversion of the background selection signal via an inverter 320 which is inserted between the signal path 312 and a signal path 322. As can be recognized by those skilled in the art, the AND gate 318 provides an error selection signal with a high signal path for application to an error color switching element 324 via a signal path 326 only when (1) the active playback control signal has the high signal value, (2) the gnome selection signal has the low signal level, (3) the foreground selection signal has the low signal level, and (4) the background selection signal has the low signal level. The error selection signal thus has the low signal value when the active playback control signal on the signal path 98a the. has a low signal value indicating that the raster scan is outside ^{1 of} the active display area. In the same way, the error selection signal has the low signal value when the gnome selection signal on signal path 280, the foreground selection signal on signal path 294 or the background selection signal on signal path 312 has the digital value "0", which is inactive in each of the corresponding sections of the gnome or pattern images Displays image elements. In other words, the error selection signal is high only when the gnome selection section 268, the pattern foreground selection section 270 and the pattern background selection section 272 are inactive, but the raster scan is within the active display area. Depending on the receipt of the error selection signal with a high signal value, the error color switching element 324 transmits the video color code group stored in an error color register 328 (FIG. 4) and supplied via the error color bus IO6 via the

030038 / O766

Color bus 108 to color decoder 114.

In summary, it can be stated that the priority selector 104 is dependent on the first and second pattern signals from the overlay control unit 100 operates, when the active display control signal provided by the sequencer 92 indicates that the raster scan is within the active playback area. In particular the priority selector 104 transmits a non-transparent Gnome video color group from the gnome color register 182 to the Color decoder 114, when the second pattern signal indicates that the gnome is active on the current picture element. On the other hand, if the second pattern signal indicates that the gnome is inactive while the first pattern signal indicates that the pattern is active on the current picture element, transmits the priority selector 104 is a non-transparent foreground video color code group from the foreground portion of sample color register 128 to color decoder 114. Wemd the first pattern signal and the second pattern signal indicates that both the gnome and the pattern are active on the current pel, priority selector 104 transmits a non-transparent background video color code group from the background portion of sample color register 128 to color decoder 114. If none further non-transparent video color code group is selected for playback, such as in a border area, transmits the priority selector 104 is an error video color code group from the error color register 328 to the color decoder 114 "

In Fig. 10 is the circuit diagram of the color phase generator 110 of Fig. 2. The color phase generator 110 operates generally dependent on the color reference signal, which is determined by the

030038/0766

Control unit 92 is supplied via signal path 94 (see Fig. 2). In a preferred embodiment, the sequence control unit 92 supplies the color reference signal in the form of two complementary clock signals 01 and 02 with the Frequency 10.738635 MHz, i.e. three times the value of the 3.57MHz NTSC color carrier (see Fig. 12). As reaction The color phase generator 110 supplies six color phase signals with the 3.57 MHz NTCS color carrier frequency to the color reference signal, however, these signals are out of phase with it by a predetermined number of degrees the six NTSC standard color reference signals for the colors yellow, red, magenta, blue, cyan and green can be approximated.

In the preferred embodiment, the color phase generator 110 consists of a three-stage ring counter, wherein each stage provides interleaved complementary output signals. In particular, the color phase generator contains 110 a first stage 330, a second stage 332, a third stage 334 and a feedback circuit 336. In the first stage 330, the input of a negator 338 is connected to the output of the feedback circuit 336 via a gate transistor 340, which is controlled by means of the clock signal 01 supplied to its gate electrode via the signal path 94a. The exit of the inverter 338 is connected to the input of an inverter 3 # 2 through a gate transistor 344 which is applied to its gate electrode via signal path 94b Clock signal 03 is controlled. In the second stage 332 the input of an inverter 346 is connected to the output of the Inverter 342 of the first stage 330 is connected via a gate transistor 348, which is connected by the via the signal path 94a

030038/0766

clock signal 01 supplied to its gate electrode is controlled. The output of the inverter 346 is connected to the input of an inverter 350 via a gate transistor 352 which is controlled by means of the clock signal 03 fed to its gate electrode via the signal path 94b. In the third stage 334, the input of an inverter 354 is connected to the output of the negator 350 of the second stage 332 via a gate transistor 356 which is controlled by means of the clock signal 01 supplied to its gate electrode via the signal path 94a. The output of the inverter 354 is connected to the input of an inverter 358 via a gate transistor 360 which is controlled by means of the clock signal 03 supplied to its gate electrode via the signal path 94b. In the feedback circuit 336, one input of a NOR gate 362 is connected to the output of the inverter 342 of the first stage 330, and a further input of the NOR gate is connected to the output of the inverter 350 of the second stage 332; the output of the NOR ^{gate 362 is connected to the N} input of the inverter 338 of the first stage 330 via the gate transistor 340.

As will be appreciated by those skilled in the art, the color phase generator 110 is constructed so that one and only one negator 338, 346, or 354 provides a low level output during each cycle of the clock signal 01. In in the same way, one and only one inverter 342, 350 or 358 provides a high level output signal during each cycle of clock signal 03. By negating the outputs of inverters 342, 350 and 358 by means of the inverters 364, 366 and 368, respectively, become a group of six

030038/0766

Obtain color reference signals in which two and only two during each half cycle of the clock signals 01 and 03 have the low signal value. The simple because reference are the output signals of the inverters 338, 364, 346, .366, was 35 ^ and 368 indicated in the figures 10 and 11, each with a respective one of six NTSC-standard colors, ie, yellow, ^R ot, Miagenta, Blue , Cyan and five-green.

In Fig.11 is the circuit diagram of the color decoder 114 and of the video mixer 116 of FIG. To explain the operation of the color decoder 114 and the video mixer 116, appropriate reference is made to the signals shown in FIG.

The color decoder 114 receives a color selection portion of the video color code group supplied from the priority selector 104 via the color bus 108. In the preferred embodiment, the color selection section of the video color code group consists of three color selection bits.Depending on each unique combination of the three color selection bits, the color decoder 114 provides a high signal value output on a particular color selection line 370. For example, the color decoder 114 provides as in a conventional 3-to-4 8-line decoder provides a high level output on color selection line 370a in response to receipt of a color selection bit group "011". In the same way, the color decoder 11.4 provides a high level output on the color selection line 370b in response to receiving a color selection bit group "111". In response to the receipt of a color ^{selection bit group 11} OOO ", the color decoder delivers

Q30038 / 076g

at the color selection line 37Oc with an output signal high signal value.

The video mixer 116 operates in a color generating operation, a synchronous generation operation or a External video operation, as determined by the status of the sequence control unit 92 via the signal path 96 delivered synchronization signals depends. In the paint production plant A switching network 172 selectively applies reference voltages from a voltage divider 374 the gate electrode of a mixer transistor 376 is generally in phase with a complementary one Pair of color reference signals from color phase generator 110. Represented in a preferred embodiment the digital value "011" in the color selection section of the video color code group the colors cyan or red, which is the digital value of an intensity section of the video color code group depends. Depending on the receipt of a signal with a high signal value on the color selection line 370a, for example an AND gate 378 at the same time an upper cyan reference voltage at a tap point 380 of the voltage divider 374 to a high intensity corresponding transistor 382 via a gate transistor 384 and a lower cyan reference voltage at a tap 386 of the voltage divider 374 to a low one Intensity corresponding transistor 388 via a gate transistor 390, which is in phase with the cyan color reference signal which is supplied by the inverter 354 of this color phase generator 110. In the same An AND gate 392 applies an upper red reference voltage to a tap point 394 of the voltage divider 374 transistor 388 via a gate transistor 396 and a lower red reference voltage at a tap 398 of the voltage divider 374 to the transistor 382 via a gate transistor is tor. 400, which in this case, however

030038/0766

takes place in phase with the red color reference signal that supplied by the inverter 364 of the color phase generator "HO will.

In the preferred embodiment, the high intensity corresponding transistor 382 is a Intensity bit portion of the video color code group supplied by priority selector 104 over color bus 108 controlled. The transistor 388 corresponding to the low intensity, on the other hand, is switched from the logic inversion of the intensity bit is controlled via an inverter 402. The cyan upper reference voltage and the lower red reference voltage are thus connected to the gate electrode of the mixer transistor 376 alternately in phase with the cyan and red reference signals when the intensity bit the video color code group on color bus 108 is high. In contrast, the lower Cyan reference voltage and the upper red reference voltage to the gate electrode of mixer transistor 376 alternately in phase with the cyan or red reference signals when the intensity bit is the Video color code group on color bus 108 has the low signal level.

In the preferred embodiment, the upper reference voltage becomes cyan and the lower reference voltage becomes red chosen so that they have a potential difference 404 which is characteristic of the color cyan Chrominance value is proportional, and which have a medium potential that is a medium luminance value is proportional, so that that is applied to the gate electrode of mixer transistor 376 via transistor 382 applied signal is a BAS signal on signal path 62 which is a digital approximation of the standard video signal for the color cyan, as in 4o6 is indicated in Fig.12. In the same way

030038/0766

are the lower cyan reference voltage and the upper one Red reference voltage chosen so that they have a potential difference 408 which is that for the color red characteristic chrominance value, and have an average potential that corresponds to a relatively low luminance value is proportional to that of the gate electrode of the mixer transistor 376 generates a BAS signal on signal path 62 which is a digital Represents approximation of the standard video signal for the color dark red, ie indicated at 410 in FIG is. For each of the color selection lines 370 that use the Video color code groups having a color selection section other than "000" and "111" are assigned, Similar arrangements of NAND elements and gate translstoren are provided.

Those skilled in the art will recognize that the video signals corresponding to the colors white and gray have a fixed luminance value and have no chrominance value. In the preferred embodiment, the digital value represents "111" in the color selection section of the video color code group, the colors white or gray, depending on the digital value of the intensity section depends on the video color code group. The one from the color decoder 114 on the color selection line 370b is used to simultaneously provide a white reference voltage At the tap point 412 of the voltage divider 374, the transistor 382 via a gate transistor 414 and a gray reference voltage at tap point 416 of voltage divider 374 to transistor 388 via a gate transistor 418 feed. When the white reference voltage is selected to match the luminance value of the color White is proportional to that applied to the gate electrode of mixer transistor 376 through transistor 382 Signal on signal path 62 a BAS signal, the one

030038/0768

If the gray reference voltage is selected to be proportional to the luminance value of the gray color, the gate M-efetrode of mixer transistor 346 will produce this supplied through the transistor 388 signal is a composite video signal on signal path ϋΖ illustrating a digital approximation of the video signal>'for the color gray, which is expressed in l miefit.

As with the d & n colors white and gray, the color black has a fixed Luiainance value, but no Chroraainance value. In the preferred embodiment, the digital value ⁿ OÖ0 ⁿ in the FariwShl section of the video color code group represents the color black or the transparent state - which depends on the digital value of the intensity bit section of the video color code group. The output signal supplied by the color decoder 114 to the color selection line 376 c is used to transmit a black reference voltage at a tap point 422 of the voltage divider 374 to the transistor 382 via a gate transistor 424. When the intensity bit is high, the signal applied to the gate electrode of mixer transistor 376 via transistor 382 produces a BAS signal on signal path 62 which is a digital approximation of the video signal for the color black, as at 426 in Figure 12 is specified. If the intensity bit has the low signal value, an AND gate 428 applies the black reference voltage switched through by the gate transistor 324 via a gate transistor 430 to the gate electrode of the mixer transistor 376, and the BAS appearing on the signal path 62 -Signal then represents a digital approximation of the video signal for the color black, as in

030038/0766

432 is indicated in Fig.12.

In the synchronous generation mode, the switching network sets 372 in a selected manner from the voltage divider reference voltages supplied to the gate electrode of the Mixer transistor 376 on, which is generally dependent of syncnronization signals that are sent by the sequential control unit 92 supplied via signal path 96 are »In response to the receipt of a syncron- sizing signal with a high signal value on signal path 96a For example, an AND gate 434 sets a synchronization reference voltage at the tap point 436 of the voltage divider 374 via a gate transistor 438 to the Gate electrode of mixer transistor 376 “If the Synchronization reference voltage is chosen so that it is proportional to the standard sync value, that is generated at the gate electrode of the mixer transistor 376 applied signal on signal path 62 is a BAS signal, which represents a digital approximation of the video signal for a horizontal sync pulse, as indicated at 440 in F ± g * .12.

In response to the receipt of a burst color signal With a high signal value on the signal path 96b, an AND gate 442 applies an upper color synchronous reference voltage at the tap point 444 of the voltage divider 374 via a gate transistor 446 to the gate electrode of mixer transistor 37-6., which takes place in phase with the yellow color reference signal that is sent from the inverter 338 ^ ies colored gas generator 110 is supplied. In in the same way, an AND gate 448 applies a lower color sync reference voltage at the tap point 450 of the voltage divider 374 via a gate transistor 452 to the gate electrode of the mixer transistor 376,

Q30038 / 076S

which in this case, however, is in phase with that supplied by the negator 366 of the color phase generator 110 Blue color reference signal occurs. The upper color sync reference voltage and the lower color sync reference voltage become the gate electrode of the mixer transistor 376 in this way alternately in phase with the yellow and blue reference signals fed. By having the upper and lower color sync reference voltages so selected be that they have a potential difference 454 have that are proportional to the peak-to-peak value that is characteristic of the NTSC burst signal is, and have an average potential proportional to the standard blanking value, generates the on The signal applied to the gate electrode of mixer transistor 376 on signal path 62 is a BAS signal which is a digital Figure 12 approximates the standard video signal for the burst signal as indicated at 456 in FIG.

In response to receiving a high level blanking signal on path 96c, an inverter 458 generates a low level output which is applied to a NOR gate 460. The NOR gate 460 also receives the synchronization signals and the color sync signals from the sequence control unit 92 via the signal paths 96a and 96b, respectively. As can be recognized by a person skilled in the art, the NOR element 460 emits an output signal with a high signal value only when the blanking signal has the high signal value and the synchronization and color sync signals simultaneously have the low signal value. The NOR element 460 thus applies the black reference voltage at the tapping point 422 of the voltage divider via a gate transistor 462 to the gate electrode of the

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Mixer transistor 376 only turns on during those portions of the normal exchange interval other than the Horizontal sync pulse and the burst signal are assigned. Because the black reference voltage has been selected to have a value proportional to the standard blanking level has generated that applied to the gate electrode of mixer transistor 376 through transistor 462 Signal on path 62 is a BAS signal that is a digital approximation of the standard video signal for the blanking interval, as indicated at 464 in Fig. 12. The blanking signal on Signal path 96c is also fed to color decoder 114 so that the output signal is sent to each of the Color select lines 370 has a low signal level during the blanking interval.

In external video mode, an inverter delivers depending on the reception of an external video release signal a low output from sequencer 92 on path 96d Signal value that is fed to AND gates 434, 442 and 448. The external video enable signal on signal path 96d, NOR gate 460 is also applied. As a result, the Outputs of AND gates 434, 442 and 448 and NOR gate 460 throughout Blanking interval at the low signal value, which causes the generation of the BAS signal in this Time interval is prevented. An AND gate 468, which is dependent on the external video enable signal on

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Signal path 96d and from the blanking signal switched through via an OR gate 470 on signal path 96c operates, applies an external video signal received via signal path 76 via a gate transistor 472 to the gate electrode of mixer transistor 376. Assuming that the sequence control unit 92 synchronized in a conventional manner with the external source of the external video signal the resulting BAS signal contains am Signal path 62 blanking signal, synchronizing signaluinI i ^ rbsynci ^ on ^ ignalpegel, the 4th levels in the External video signal proportional, are.

In addition to that the synchronizing sections of the external video signal are used instead of the internally generated values, the preferred one switches Execution of the video mixer 116 also through the information portion of the external video signal when the from Priority selector 104. Supplied video color code group corresponds to the transparency status. In particular becomes the output signal provided by the inverter 466 is applied to the AND gate 428 so that the output signal from this maintains the low signal level when the external video enable signal on path 96d has the high signal level. The common connection of the black reference voltage via the gate transistors 424 and 430 are suppressed in this way. For this, a delivers depending on the Farbwänlleitung 37Oc and the logic inversion of the intensity bit supplied by the inverter 402 AND gate 474 has an output signal with a high signal level through OR gate 470 to enable AND gate 468 when the external video enable signal is also enabled has the high signal value. As a result, xlas sets the AND gate

03 ^ 038/0766

468 receives the external video signal on path 76 through the gate transistor 472 to the gate electrode of miser transistor 376. In other words, this means that a video color code group, which corresponds to the transparent state, to a BAS signal on signal path 62 with a digital signal profile approximated to the color black supplies (see at 426 inELg. 12) when the video mixer 116 does not work in external video mode, but does Provides a BAS signal that is substantially the same as the external video signal on signal path 76 when the video mixer 116 works in external video mode

In Fig. 13 is a block diagram of each, the slow read-only memory 48 of FIG shown .; Using this block diagram, the operation of these components should correspond to that in Fig.i4 illustrated flowchart will be explained-The Read only memory 48 (ROM) operates in response to ROM access requests from the central processing unit are supplied via the memory bus 46, and via the Bus buffer 50 are fed to the auxiliary bus 52. In particular the central unit 12 can write a new address in an address counter 476 in the plague memory 48, the address currently in the address counter 476 or in a read-only memory matrix 478 at the address contained in the address counter 476 Read data. In the preferred embodiment, the read-only memory matrix contains the processing information in 6144 bytes of eight bits each, each sequentially or optionally via the lower 13 bits of a 16-bit address are addressable. The upper three bits of the 16-bit address form a page designation, the indicates one of the eight individual components that make up the read-only memory 48, as will be explained.

In response to receiving a ROM access request of the central processing unit 12 over the auxiliary bus 52 which rub the Sc (decision block 480) of an address (decision block 482), a sequence control unit 484 prepares the. Receipt of the first eight bits of the 16 bits before that form the new address by adding the ones in the internal eight bit positions of the address counter 476 contained Address bits are shifted into the top eight bit positions (processing block 486). When the first eight Address bits of the new address become available on auxiliary bus 52, the sequence control unit 484 provides an input buffer 488 is free and loads the first eight address bits into the lower eight bit positions via an input bus 490 of address counter 476 (processing block 492). As a reminder that the first eight If the new address has already been loaded, the flow control unit 484 sets an internal flag (Processing block 494). As a result, if the flag is set (decision block 496), the sequence control unit 484 generates a ready signal (processing block 498), which the central processing unit 12 is supplied via the auxiliary bus 52 to indicate that the read-only memory 48 is ready for the second receive eight bits of the address.

Upon receipt of a second ROM access request requiring the writing (decision block 480) of an address (Decision block 482), the sequencer shifts 484 the first eight bits of the new address from the lower eight bit positions of the address counter 476 in its upper eight bit positions (processing block 486). If the second eight bits of the new address

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supplied by the central processing unit 12 via the auxiliary bus 52 the sequencer 484 outputs the input buffer 488 free and loads the second eight bits of the new address via input bus 490 (processing block 492) in the lower eight bit positions of the address counter 476. If after the second switch of the flag (processing block 494) the flag is reset (decision block 496), the sequence control unit 484 carries out a self-advancing procedure 500.

In the self-advancing procedure 500, the sequence control unit 484 loads the information currently in the address counter 476 into an address hold circuit 502 (decision block 504). The sequencer 484 then advances the address contained in address counter 476 (processing block 506). Using the in of the address holding circuit 502, the sequence control unit 484 then transmits the address processing information contained in the particular address location in the read-only memory matrix 478 a data hold circuit 508 (processing block 510). After completion of the self-advancing procedure 500 represents the sequence control unit 484 ensures that the flag is reset (processing block 512), and then generates a ready signal (processing block 498) so that the central processing unit 12 is indicated that the read-only memory 48 is ready to receive the next ROM access request from the central processing unit 12.

When the next ROM access request is a data read command (decision block 480 decision block 514), the flow control unit 484 transmits that stored in the data holding circuit 508

030038/0766

3Q08443

Processing information into an output hold circuit 516 (processing block 518). If the page label section the address contained in the address counter 476 of the specific address assigned to the component during manufacture Page number (decision block 520), a page selector 522 provides an output buffer 524 free via signal path 526 (processing block 528) to allow the output hold circuit 516, processing information supplied via an output bus 530 is transmitted to the auxiliary bus 52. In connection on that, or even if the page number does not match (decision block 520), the sequencer performs 484 the above-described self-switching procedure 500 through which it is ensured that the flag is reset (processing block 512) and generates a ready signal (processing block 498) to indicate that the requested Data are available on the auxiliary bus 52.

In response to receiving a ROM access request, which requires reading (decision block 480) an address (decision block 540) is transmitted by the state machine 484 the eight address bits contained in the upper eight bit positions of the address counter 476 to output hold circuit 516 (processing block 532). The sequencer 484 then issues the output buffer 524 free (processing block 534) to have the output hold circuit 516 via the Upper address byte supplied to output bus 530 is transferred to auxiliary bus 52. The sequence control unit then shifts the eight address bits contained in the lower eight bit positions of address counter 476 in its upper eight bit positions (processing block 536). Following this, the sequence control

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unit 484 ensures that the flag is reset (processing block 512) and generates that Ready signal (processing block 498) to indicate to the central processing unit 12 that the upper Byte of the address on auxiliary bus 52 is available.

Upon receipt of a subsequent address read command (decision block 480, decision block 514) The sequence control unit 484 transfers the lower byte of the address, which is now in the upper eight Bit positions of the address counter 476 are located to the output hold circuit 516 (processing block 532), and it enables output buffer 524 (processing block 534) to place the lower address byte on the auxiliary bus 52 is transmitted. As before, the sequencer 484 then shifts the ones to the bottom eight Bit positions of the address counter 476 contain eight bits in its upper eight bit positions (processing block 536), ensuring that the indicator is reset (processing block 512), and generates the ready signal (processing block 498) to indicate to the central processing unit 12 that the lower address byte is available on auxiliary bus 52.

In response to receiving a RO'M access request, requiring the writing (decision block 480) of data (decision block 482) the sequencer 484 simply goes through the self-advancing procedure 500 before the flag is reset (processing block 512) and the ready signal to indicate the completion of the command

030038/0766

is generated (processing block 498). The data write command is therefore a convenient way to reset the flag during a self-advancing operation is carried out.

In the preferred mode of operation, the central unit initially issues a data write command to reset the License plate. The central unit 12 then supplies a selected start address with the aid of two consecutive ones Address writing commands. Thereafter, the read-only memory 48 automatically supplies the in the following processing information contained in higher address spaces in response to each subsequent data read command from the central unit 12. As part of the self-advancing procedure 500, which is carried out in response to every data read command, loads the read-only memory 48 the data holding circuit 508 with the next byte, so that this for a fast transfer to the central unit 12 is available. The central unit 12 therefore only spends one minimal amount of time waiting for the data after a data read command has been issued.

The invention has been described here in connection with a specific embodiment, but it is apparent to those skilled in the art that within the scope of the invention, modifications of the structure and the Operation of the embodiment described can be carried out.

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Claims (1)

Claims Digital data processing arrangement with a storage device for storing program steps and data, a processor device that is equipped with a Storage device is connected and works in a selectable manner with the program steps and data, and a video device connected to the processor device and in a selectable manner Output signals of the processor device for a Operator of the arrangement visible reproduces, characterized in that the video device a raster scanning image display unit and an image display processor including a Image blanking synchronous signal (BAS signal) for application to the image display unit, this image blanking synchronous signal containing a first video image, which is superimposed on a second video image. 030038/0766 2. Arrangement according to claim 1, characterized in that the image reproduction processor is a sequence control unit which carries out a cyclic column count and a cyclic row count to display the position of the raster scan in succession in time. 3. Arrangement according to claim 2, characterized in that the image reproduction processor also has a signal generator device for generating a video control signal from video color code groups 4. Arrangement according to claim 3, characterized in that the image reproduction processor also includes a device for generating the BAS signal according to the video color code groups of the video control signal. 5. Image display processor in a for use with raster scan image display device certain image display system, which contains a random access memory, in which a first ordered field Digital code elements are stored which represent a set of video color code groups in the M columns out of N rows classify from image display elements that a first Display video image in which a second ordered field of digital code elements is stored, which arrange the set of video color code groups in the S columns of T series image display elements, which represent a second video image and in which a third field is stored, which is a column shift U and a row shift V for the display of the second video image with respect to the first 030038/0766 - ³ - 30Q8A43 Contains video image, where the following applies: 1 "= S%, 1 * = T = N, 1" = ■ υ "= M and 1" = V ^ N, and where the image display processor provides an image lock synchronous signal (iBAS signal) to be applied to the Image reproducing device generated so that the first video image can be reproduced on which the second video image with the column and row shifts is superimposed, characterized by a sequence control device which carries out a cyclic column counting and a cyclic row counting for displaying the chronologically successive position of the raster scan, a memory control device for selectively extracting parts of the first, second and third fields from the read / write memory, an overlay control device which cooperates with the memory control device in synchronism with the column and row counts for outputting a first pattern signal which forms the digital code element in the first field which the image display element in column X of row Y of the first video image it classifies if: 1 ^ X * = N and 1 "= Y = N, and which supplies a second pattern signal which forms the digital code element in the second field, which the image display element in the column (X - U + 1) the series (Y - V + 1) of the second video image, if the following applies: U = X = (U + S) and V * = Y ^- = (V + T), a priority selection device connected to the overlay control device, the first and receives the second pattern signal, selects the second pattern signal in response to the receipt of this second pattern signal, selects the first pattern signal if the second pattern signal is not selected, and supplies a video control signal from video color code groups which are classified by the digital code elements which form the second pattern signal , and a 030038/0766 BAS signal generating device operating with the priority selector in synchronization with the column and row numbers cooperates and the BAS signal according to the video color code groups of the video control signal generated. 6. image playback processor according to claim 5, characterized in that that the overlay control device contains the following assemblies: A preprocessing unit, which at I = X = M and 1 ^ (Y + 1) Hn cooperates with the memory controller and the row shift V takes and determines whether the number of rows (Y + 1) is within of a predetermined reproduction range of the row shift V, a processing unit attached to 1 * = X "= M and I = Y = N with the memory controller cooperates and extracts the digital code element in the first field as the first pattern signal, and sequentially supplies the bit display element in column X and row Y of the first video image classifies a post-processing unit, which at 1 "= X = · M and 1 * = (Y + 1) = N with the memory control device cooperates and dependent on the preprocessing device determining that the Row number Y + 1 is within the predetermined display range of the row shift V that Column shift U and the digital code elements in the second field, which extracts the S image display elements in the row (Y-V +1) of the second video image, and one with the post-processing unit cooperating unit operating in sequential 030038/0766 As the second pattern signal, that from the post-processing unit extracted digital code element supplies in the second field, which the image display element in the Column (X - U + 1) of the row (Y - V + 1) of the second video image, if the following applies: U la X < (u + S) and V ^ Y ^ (V + T). 7. Image reproduction processor according to claim 5 or 6, characterized in that at least one first video color code group an image display element having a predetermined color corresponds to that at least one second video color code group corresponds to an image display element having no predetermined color, and that the priority selection unit corresponds to the selected second pattern signal only if the digital code element forming the extracted second pattern signal classifies a different video color code group as the second video color code group. 8. Image reproduction processor according to claim 5 or 6, characterized in that several in the read / write memory Second ordered fields of digital code elements are stored which make up the set of video color code groups arrange in the S columns of T rows of the image display elements, each of which represents second video images, that the third field has a column shift U and a row shift V for the display of each of the second video images relative to the first video image that the overlay control device contains a plurality of supplies second pattern signals which each form the digital code element in a respective second field which the image display element in the column (X - U + 1) of the 030038/0766 30Q8443 Row (Y - V + 1) of the respective second video image classifies if: U ^ X = (U + S) and V = Y = (V + T), and in that the priority selection device corresponds to a certain pattern signal from the received second pattern signals selects a predetermined order of priority of the second video images. 9. Method for the simultaneous display of a first video image from M columns from N rows of image display elements and a second video image made up of S columns out of T rows of image display elements, the first Video image is superimposed so that it is at a predetermined column shift U and at a predetermined row shift V begins, where I = S ^ M, I = T ^ N, 1 Is u Is M and 1 ^ V ^ N, on one with the raster scan working image display device, characterized in that that a first ordered field of digital code elements is stored which comprise a set of video color code groups arrange into the M columns of N rows of picture display elements which represent the first video picture, that a second ordered field of digital code elements is stored, which the set of video color code groups arrange in the S columns of T rows of image display elements that represent the second video image, that a third ordered field is stored, which the column shift U and the row shift V contains, 030038/0766 3Q08443 that a cyclic column counting X and a cyclic row counting Y are carried out, the time indicate the successive position of the raster scan, that at 1 ^ X ^ M and 1 ^ Y ^ N a first pattern signal which forms the digital code element in the first field which the image display element in assigns column X to row Y of the first video image, that at U ^ X = U + S and V = Y ^ (V + T) a second Pattern signal is supplied which forms the digital code element in the second field which is the image display element into the column (X - U + 1) of the row (Y - V + 1) of the second video image, that the second pattern signal is selected when the second pattern signal is supplied, that the first pattern signal is selected when the second pattern signal is not selected, that a video control signal is provided which consists of the video color code groups derived from the digital Code elements of the selected pattern signal are classified, and that the BAS signal corresponds to the video color code groups of the video control signal is generated. 030038/0766 3Q08443 10. The method according to claim 9, characterized in that when the second pattern signal is supplied, the procedure is such that when 1 = X ^ M and 1 1 (Y + 1) = N, the row shift V is extracted and it is determined whether the number of rows Y + 1 is within a predetermined display range the row shift V is that with I = X = M and 1 = Y = N depending on whether the number of rows (Y + 1) is within the predetermined display range of the row shift V, the column shift U and the digital code elements in the second field are taken, which are the S image display elements place in the row (Y - V + 1) of the second video image, and that with U = X = (U + S) and 1 ^ Y ^ N the extracted image display element in the second field is supplied as a second pattern signal in a sequential manner that the image display element is in the column (X - U + 1) of the row (Y - V + 1) of the second video image classifies. 11. The method according to claim 9 or 10, characterized in that at least one of the video color code groups is an image display element having a predetermined color corresponds to that at least one second video color code group corresponds to an image display element without a predetermined color, and that upon selection of the second pattern signal the extracted second pattern signal is only selected if the digital code element, which forms the extracted second pattern signal, a video color different from the second video color code group beodegruppe. 030038/0766 12. The method according to claim 9 or 10, characterized in that that a plurality of second video images from each S columns from T rows of image display elements on the first video image are superimposed, each with a predetermined column shift U and a predetermined Row shift V is started that when storing the second ordered field several second ordered fields are stored that when storing the third ordered field such third ordered field is stored as each of the column shifts U and the row shifts V contains that when the second pattern signal is supplied, a plurality of second pattern signals are supplied, each consisting of a digital code element in one of the respective second fields consists that the image display element in the column (X - U + 1) of the row (Y - V + 1) of the respective classifies second video image, and that in the selection of the second sample signal a certain second Pattern signal upon delivery of at least one of the second pattern signals a specific second Pattern signal is selected in accordance with a priority order of the plurality of second video images. 13. Digital data processing arrangement with a storage device for storing program steps and data, a processor device that is equipped with a Storage device is connected and works in a selectable manner with the program steps and data, and a video device connected to the processor device and in a selectable manner Output signals of the processor device for a 030038/0766 Operator of the arrangement shows visible, characterized by a color phase generator, the depending on a phase reference signal, first and second color phase signals with a predetermined phase and a predetermined one Frequency generated with respect to the color reference signal. 14. Arrangement according to claim 13, characterized in that in that the video device also includes a voltage regulator device, the first and second Supplies reference voltage values whose potential difference is proportional to a predetermined chrominance value and the mean value of which is proportional to a predetermined luminance value is. 15 · Arrangement according to claim 14, characterized in that the video device also includes a switching device which is selected depending on the color phase signals in Way the first reference voltage is in phase with the first color phase signal and the second reference voltage is in phase with the second color phase signal switches through. 16. The arrangement according to claim 15, characterized in that the video device also includes a mixer which, depending on the gating device, generates a BAS signal generated with the predetermined chrominance and luminance values. 17. Image display processor in an image display system for use in a raster scanning image display device, characterized by a 030038/0766 Sequence control device for outputting a color reference signal at a predetermined frequency, a video generating device for outputting an image scanning synchronous signal (BAS signal) for application to the image display device, a color phase generator in the video generating device, which depends on the color reference signal first and second color phase signals with a predetermined Phase and predetermined frequency generated with respect to the color reference signal, a voltage divider in the Video generating device generating first and second reference voltages whose potential difference corresponds to one predetermined chrominance value and its mean value is proportional to a predetermined luminance value is proportional, a switching device in the video generating device which is dependent on the color phase signals selectively the first reference voltage in phase with the first color phase signal and the second reference voltage in phase with switches through the second color phase signal and a mixer device in the video generator device, which depends on the connected reference voltages the RAS signal with predetermined chrominance and luminance values generated. 18. Image rendering processor according to claim 17 »characterized in that that the first and second reference voltages are chosen so that their potential difference corresponds to the chrominance value of a predetermined color and their mean value to the Luminance value are proportional to that color. 030038/0766 3Q08443 19. Image rendering processor according to claim 17, characterized in that that the voltage divider device supplies a third reference voltage, the word of which corresponds to a predetermined Luminance value is proportional, and that the switching device switches through the third reference voltage in a selected manner, so that the mixer device provides the BAS signal in the predetermined luminance value. 20. Image reproduction processor according to claim 19, characterized in that that the third reference voltage is chosen so that its value is proportional to the luminance value of a predetermined one of the colors white, gray and black. 21. Image reproduction processor according to claim 19, characterized in that that the third reference voltage has a value which is proportional to the luminance value of the blanking signal or the synchronizing signal. 22. Image display processor according to claim 17 or 18, characterized in that the first and the second reference voltage are chosen so that their potential difference is proportional to the value of the burst signal from peak to peak and its mean value is proportional to the blanking value. 23. Image rendering processor according to claim 22, characterized in that that the switching device switches through an external video signal in selected Welse, so that the Mixing device supplies the BAS signal with the value of the external video signal. 030038/0766 3QQ8443 24. Image reproduction processor according to claim 23, characterized in that the sequence control device is a composite synchronization signal having a predetermined shape and duration with respect to the color reference signal supplies and that the switching device in a selected manner the switching accordingly the composite sync signal. 25. Image reproduction processor according to claim 18 or 20, characterized by a selection device for outputting a color selection signal which is one of the predetermined colors indicates and that the switching device carries out the switching in dependence on the color selection signal. 26. Image rendering processor according to claim 25 »thereby characterized in that the selection device provides a color selection signal having a transparent state indicates, and that the switching device in a selected manner an external video signal in dependence of the color selection signal indicating the transparent state, so that the mixer device the BAS signal generated with the value of the external video signal. 27. Image reproduction processor according to claim 17, characterized in that the switching device in selectively switches through an external video signal so that the mixer device receives the BAS signal generated with the value of the external video signal. 030038/0766 28. Image rendering processor according to claim 27, characterized in that that the sequencer is a composite Synchronization signal with a predetermined shape and provides duration with respect to the color reference signal, and that the switching device in a selected manner the switching process depending on the composite Performs synchronization signal. 29.Digital data processing arrangement with a storage device, which contains processing information at successive address locations, and which at one Adreseenplatz sends stored processing information depending on the receipt of its address, and a central unit which works in dependence on the processing information and an address of one of the sequential ones Addresses places supplies, characterized by an address counter device between the central unit and the storage device receiving the address provided by the central processing unit and the storage device feeds, and a control device cooperating with the address counter device for incrementing the address in the address counter device for addressing the next address block in the storage device in response to the fact that the central unit receives the processing information, the memory device in response to the address supplied to it by the address counter device supplies, whereby the processing information stored at the next address location from the Storage device is dispensed in response to it, 030038/0766 that the processing information located at this address is received by the central unit. 30. Arrangement according to claim 29, characterized in that between the storage device and the central unit a holding device is inserted which operates depending on the control device and which is dependent on the storage device receives output processing information and the central unit in dependence thereon supplies the control device to increment the address counter device. 31 · Arrangement according to claim 30, characterized in that the storage device is a permanent storage device is. 32. Arrangement according to claim 30, characterized by a page selection device which is dependent on a predetermined Page number the holding device in response to a page number corresponding to the page designation portion of the Releases address in the address counter device. 33 · Arrangement according to claim 30, characterized in that the storage device is a random access memory device. 3 * u arrangement according to claim 33, characterized in that the storage device is a dynamic random access memory device and that the control device cooperates with the address counter device to periodically refresh the memory device. 030038/0766 35.- arrangement as claimed in claim 33, "that the holding device also receives the processing information supplied from the central processing unit and the storage device supplies and that the Steuervorrich- ^N processing with the storage device so co-t, that the processing information is stored at the address location, the indicates the address provided by the address counter device. 36. Arrangement according to claim 30, characterized in that the holding device cooperates with the control device in such a way that that it receives the address supplied by the address counter device and supplies it to the central unit. 37. Arrangement according to claim 29, characterized in that the storage device is a read-only storage device. 38. Arrangement according to claim 29, characterized in that the storage device is a random access memory device. 39. Arrangement according to claim 38, characterized in that the storage device is a dynamic random access memory storage device and that the control device with the address counter device for periodic Refresh of the storage device cooperates. 40. Plug-in library module for use in a digital data processing arrangement with a Q30038 / 0766 Central unit, which is the address of one of several consecutive Address locations selected address location supplies and dependent on processing information works supplied to it in response to the address with an interface device a plug connector for temporarily accommodating the library module and for achieving a transmission between the central unit and the library module, characterized in that the library module has the following Structural units contains: a memory device in which processing information is contained at successive address locations and which is provided with the springs Address counts available processing information in response to the receipt of its address, an address counter device that receives the information provided by the Central unit receives delivered address and sends the address to the storage device, a connection device, which can be connected to the connector of the interface device and the address supplied by the central unit to the Address counter device and the processing information supplied from the storage device the central unit applies, and one to the address counter connected control device which changes the address in the address counter device to the address of the next address location in the memory device advances depending on the fact that the Central processing unit received from the storage device in response to that received from the address counter device supplied address supplied processing information 030038/0766 receives, whereby the next address space stored processing information of the storage device is supplied in response to the processing information from that address is received by the central unit. Library module according to claim 40 for use in a central processing unit operating at relatively high speed, characterized in that the memory device is a relatively slow operating P-channel MOS component _{or the like} 030038/0766