DE2952349A1 - PRIORITY RESOLUTION DEVICE - Google Patents

Description

The present invention relates generally to data processing systems and, more particularly, to prioritization solution device according to the preamble of the claim This facility will display the device that has the highest priority for a given set of device requests having. A device with a higher priority is able to intercept a channel program that corresponds to a predetermined Time is effective with regard to a device with lower priority. The present invention also addresses one Addressing device for interrupting a computer program using an interrupt vector containing the addresses can provide a large number of unique function codes to direct the processing of any of these number of interrupt routines.

Computer systems generally include a processor and multiple input / output devices. As a number of devices request cooperation with the processor at the same time A priority system must be established so that the processor can be in an ordered order with the I / O devices can work together. Known systems have this priority problem solved in many ways, using sophisticated hardware, hardware / firmware and software techniques became. In this connection, U.S. Patents 3,993,981, 4,001,783 and 4,028,684 are mentioned.

These systems are designed for large scale computer systems and are expensive and relatively demanding in terms of hardware plenty of time to select the appropriate I / O device. Furthermore, the known priority systems are according to their Realization no longer easily changeable. This problem becomes more important when the I / O devices are dialog lines » each of which has the ability to process data in different modes, e.g. synchronous and asynchronous and with different Receive and send bit rates.

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In a computer system that works with multiple I / O devices, the subsystem controlling the data flow can be operated by means of channel programs and a microprocessor and have multiple I / O devices. The I / O devices can be universal, both synchronously and asynchronously Have receiver / transmitter (USART = Universal Synchronous Asynchronous Receiver Transmitter) for each dialog line to be operated. The microprocessor can, for example, control a receiver / transmitter USART, which operates by means of a channel program is. If another dialog line with a higher priority requests treatment, the microprocessor must program the channel, which is effective, interrupt and switch the channel program, so that it takes effect in connection with the requesting dialogue line. In the prior art, the microprocessor interrupts the channel program, the information being stored in memory. This information stored in the memory allows the continuation of the Kana! program on this interrupted one Dialogue management. The information consists of the contents of various registers in the system that must be unloaded when a dialog line with a higher priority requires an interruption and must be reloaded when the dialog line with a higher priority has ended the data transmission and the system returns to the original dialog line. This known system has the disadvantage that a large amount of information must be loaded and unloaded, whereby the Operating speed is decreased. Furthermore, it is difficult to prevent the interruption when required by the system and finally there is no identification of the line of dialogue that interrupted the system.

In a running computer program there are generally two phases which normally occur alternately. First commands and / or operands are called up to the central processor and then processed. During the retrieval phase the processor calls the next instruction to be processed from the main memory and transfers it to an or several control registers in which further modifications,

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such as indexing, indirect addressing, and base addition can be performed if necessary. During the processing phase of an instruction, the processor decodes the instruction and the operation specified by the instruction is running.

Most digital computers with a stored program have facilities for interrupting the running program, with this can be done on request based on an external or internal signal. There are a variety of reasons that cause the May require interruption of a computer program, for example when inputting or outputting information or when Calling a routine for executing a standard routine, such as a maintenance, diagnosis, square root routine etc.

The simplest form of an interrupt is to use an instruction that causes a halt or a branch. Such commands are specified by the following subroutines, for example: HALT or GO TO and RETURN. Because of of such subroutines, the central processing unit advances to another memory location in main memory to move to the next one to receive the processing command instead of the next one Command of the program to continue. Before the new program or the new routine can be executed, however, the content any indirectly addressable registers, such as program counters, accumulator registers or the like Registers are saved so that control can return to the interrupted program at the point where it Program was interrupted. This requires additional time to unload and reload the program counter.

There are many variations on this basic interrupt function, such as conditional interrupts, priority interrupts and nested breaks. In this context, reference is made to U.S. Patents 3,226,694, 3,408,630,

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3,221,309 and 3,693,162.

In general, both instructions and data operands are used for the processing is stored in different addressable memory locations of the same main memory. In addition, you can the commands can still be grouped in groups that form subroutines. This requires address storage locations to be allocated in advance when determining the program of a subroutine for a specific problem. In addition, the programmer must if the subroutine is later modified, not only the original memory allocation but also the later modifications consider. In order to allow the programming to be independent of the actual address storage locations in the main memory indirect addressing can be used. With the help of index registers groups of data or programs are used without having specific address locations for each word in the group at the time the program is created must be assigned. Although the absolute address is later put in the memory location on the is referenced by the instruction, it can be different for each program flow, depending on where the group is passing through the machining program is stored in the main memory. Because the group is addressed indirectly through a number of instructions the address of the instructions remains unchanged and only the absolute address of the group is changed if the group's storage space is modified. This technique generally requires special words to act as descriptors are known and which take the place of operand words or command words in the memory. When a command is reading out of an operand word from the memory, it can find a data descriptor word which is a base address of a Group of words and which further includes information defining it as a descriptor word instead of an operand word. The descriptor word can also contain information relating to the length of the command group or data group and a Have information that indicates whether indexing is required is or not. In this context, the US

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See patents 3,938,096 and 3,222,649.

While in an interrupt operation it is desirable to arrange operands or instructions in groups that are somewhere in the Main memory can be stored, on the other hand, it is just desirable that the addresses of the descriptors or the indirect Address words of a different type are fixed. This can be done through a central storage location, such as a segment or a table for storing such words. Both processes are relatively slow, with one being requires different accesses to the main memory by means of indirect addressing of the descriptors, while the other method requires the comparison of the instruction or the function code word with the words stored in the table. About that in addition, these methods require a considerable amount of memory. If a microprocessor is used, it must Storage space and speed are bought with expensive money. It is therefore a hardware technique for the interruption required by indirect addressing of some predetermined memory location that is fast and economical when using the processor and main memory space.

It is the object of the present invention to provide an improved means for resolving the priority order of a number of devices or dialog channels that request access to a processor. Here channel programs should be from one Device with a higher priority can be intercepted. This object is achieved in accordance with what is characterized in the claims Invention.

The hardware device for interrupting a machining program uses an indirect addressing method. In the preferred embodiment, predetermined storage locations store the high and low byte of an interrupt vector in main memory. If the storage space in the main memory,

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which stores the high value byte of the interrupt vector is addressed by the microprocessor, the high value The position of the program counter of the microprocessor is provided with the high value byte of the interrupt vector. if however, the low byte of the interrupt vector is addressed, the bits of the address become various hardware devices in the central processing unit CPU, whereby the normal addressing mechanism of the central processing unit is blocked and an indirect addressing mechanism is enabled. Indirect addressing provides a selected address for one of 64 memory locations in the read-only memory ROM or PROM of the microprocessor. The content of this selected address supplies a second address, which is stored in the low-order byte position of the program counter of the microprocessor, whereby an absolute address of a searched memory location in main memory is specified, at which the interrupt subroutine is stored. Thus, any of 64 interrupt subroutines can be executed with a minimum of memory footprint can be called up quickly.

Based on one shown in the figures of the accompanying drawing Exemplary embodiment is described in more detail below, the invention. Show it:

Figure 1A is a schematic block diagram of the preferred Embodiment of the invention.

Figure 1B is a schematic diagram of the typical addressing format of the invention.

1C shows a division of the read-only memory PROM

Figure 2A is a schematic diagram of the typical organization of real memory in accordance with the invention.

Figure 2B is a schematic diagram of the typical organization of the virtual memory according to the invention.

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Figures 3, 4, 4A, 4B, 4C, 4D, 5A, 5B and 7 are diagrams of the

preferred embodiment of the invention.

Figure 6A is a flow chart description of portions of the invention.

Figure 6B is a timing diagram. to explain the invention.

The drawings show means for prioritizing a number of I / O devices in accordance with one Number of mandatory rules.

A programmable read only memory PROM-384 (Fig. 4D) in Integrated circuit technology allows for simplified high-speed priority resolution. The different Input / output devices 6 20 (FIG. 5A) participate via channel programs the microprocessor together. Each I / O device has its own request signal line which is connected to the address input terminal of the read-only memory PROM.

For example, the receiver / transmitter has USART-116 for the Line 0, a reception request signal line and a Send request signal line to the input address connections 1 and 2 of the read-only memory PROM-384 accordingly are connected. The receiver / transmitter ÜSART-117 for the Line 1 has receive and send request signal lines, which are connected to the input address connections 3 and 4 of the read-only memory PROM-384. A microprocessor request line is connected to the input address connection 0 of the read-only memory PROM-384. Furthermore, the input address connections of the read-only memory are supplied with signals that indicate the channel number of the currently active channel program. The output signals of the read-only memory PROM include the channel number of the intercepting I / O device and a signal to indicate that a higher priority I / O device is requesting access to the program.

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It is obvious to a person skilled in the art that a number of devices can request the channel program at any particular point in time, with a particular device cooperating with the channel program. Each of these states at this point in time is represented by a PROM address signal which selects a particular PROM memory location. A bit configuration is permanently stored in this memory location, which indicates the device with higher priority and which indicates whether this device should intercept the channel program when the current device has completed its channel program subroutine.

Some typical situations with regard to the USART receivers / transmitters are solved as follows:

If both receivers / transmitters USART 116 and 117 are operated synchronously priority is given to the receive operation.

If both lines are not synchronous, the receiver / transmitter USART 116 has priority over the receiver / transmitter USART 117.

The background program running on the microprocessor 101 has priority over the two receivers / transmitters USART 116 and 117.

If the receiver / transmitter USART 116 was in transmit mode and the receiver / transmitter USART 117 requested the channel program for a receive operation , the channel program switches over to the ^{USART 117 after the L 1} SART 116 has been operated.

The facility forms a means for intercepting the sewer program when processing a different line of dialogue at a time in the channel program where very little Information is to be stored. The termination of a microprogram subroutine of the microprocessor is just such a point in time.

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The microprocessor subroutine ends with a jump to address BD40 _1g (7E BD40). The address signal BD40 _1g contains a command which is interpreted by the microprocessor as a "reset interrupt mask" microword, by means of which the microprocessor interrupt line is released. If there is no pending interrupt request, the program then advances to address BD41 ... The BD41 signals on the address bus enable a command register and block the normal memory read data path 110. If another dialog line requests the interception of the channel program, the microword NO OP 01, stored in the command register, appears.

id

on the U-bus, which leads to the fact that the microprocessor sends out the address BD42, which starts the handling routine for the Interception pretends. If there is no interception, the "return from subroutine" microword 39 .. is stored on the U-bus, whereby the microprocessor returns normally to processing the current channel program.

Referring to Fig. 1A, there is shown a block diagram of a preferred embodiment of the invention which also illustrates the flow of information and shows the modification of the information for improved addressing. A microprocessor 101 implemented by the im Commercially available type 6800 from Motorola Inc. may be specified, uses an address bus 102 with 16 bits for addressing of the main memory 108. This results in an addressing option for 64K bytes of the main memory 108. The formats of the command are shown in Figure 1B. There are primarily two formats, one of which is an 8-bit opcode and one byte a having 8 bits, while the other has an operation code of 8 bits, a byte a having 8 bits and a byte b having 8 bits. In order to save storage space and cycle time, it is more advantageous to only use byte b. Accordingly In the schematic representation according to FIG. 1A, the register 103 uses the first 5 high-value bits 8, 9, 10, 11 and 12, to address the page division signal generator 105. This generator 105 is an integrated circuit, which under type number 5610 is commercially available and manufactured by Motorola Inc. The side divider signal

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generator 105 stores 32 words that can be addressed by bits 8-12 of byte b. Since 5 bits are used, to address the page division signal generator, any of the 32 words can be addressed. The internal circuit of the generator 105 is such that when addressing the first 8 words, i. H. up to address 07 the signal CPGLIN is activated, d. H. takes the low level. When the next 4 words of the signal generator 105 are addressed, d. H. addresses 8-11, both signals CPGLIN and CPGDIR are activated. If the next word is 13 at address 12 is addressed, all of the following signals are activated: CPGLIN, CPGDIR, CPGCCB and CPGAD4. The page division signal generator 105 is enabled when a low level output signal from the microprocessor 101 is at its input terminal E is present. A low level input signal is supplied to the input terminal E from the output of the NOR gate 104 of the page division signal generator 105 is applied when all input bits 1-8 of byte a are low or the Have the value "0". These bits 1-8 of byte a have the value "0" if a modification of the one formed by byte a and b 16 bit address is required. If all bits of byte a have the value "0", a corresponding signal results with a low level at the output of the NOR gate 104, which is the input terminal E of the signal generator 105 to enable it is fed. When the page subdivision signal generator is enabled, one of the control signal storage locations becomes 105a enabled by bits 9-13 of byte b. When one of these control signals 105a is active, i. H. the low one Level, then the virtual 16-bit address 106 is modified to the real address 107, which then the main memory 108 addressed. If none of the control signals 105a is effective, then the 16-bit address 106 is identical to that 16 bit address 107 and there is no modification in the addressing of memory 108. The mechanism for execution this modification will be explained in more detail later in connection with FIG. Therefore, if one assumes that the control signal CPGCCB is effective, bit 11 becomes the

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ORIGINAL INSPECTED

virtual address by the bit at positionOC of the CCB register 115 is replaced and bit 12 is replaced by the bit on the Replaced position / S in CCB register 115 to form the real address. If the control signal CPGDIR is effective, bit 10 of the virtual address is replaced by bit D of channel register 114. If the control signal CPGLIN is effective, so bit 9 of the virtual address is replaced by bit M of CH register 114 and bit 8 of the virtual address becomes replaced by bit H of CH register 114. When the control signal CPGAD8 is active, bit 7 becomes the virtual Address replaced by the value "1". Finally, when control signal CPGAD4 is asserted, bits 4, 5 and 6 of the virtual address is replaced by the value "1".

The signal CE $ U2ü is used to address the line number of a selected receiver / transmitter USART116 or 117. Such receivers / transmitters are sold by the company Texas Instrument under the type now 74LS24 5 in the trade. The control signal CEI02U enables the I-bus 113 via the bidirectional bus driver 111. These bidirectional bus drivers are also commercially available from Texas Instruments under type number 74LS245. The signal CE102U allows a dialogue between the I-bus 113 and the u-bus 112, while the signal CEU2I0 allows a dialogue between the U-bus 112 and the I-bus 113. Various registers can be connected to the I-bus in order to store dialog information. Some typical such registers are, for example, the high order data register 120, the low order data register 121, the channel number register and the status register 123. These registers are connected to the microprocessor via the I-bus 113 and the U-bus 112 and with the main memory 108 via the I-bus 113 and the M-bus 109 in communication. For the different connection to the I-bus 113 for a dialog with the main memory 108 and with the microprocessor 101, it is necessary to allocate memory space in the main memory for different lines and channels which are assigned to each dialog connection. According to Fig. 2A it can be seen that part of the storage space area of the real memory 200 for

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lines 0-3 is reserved. Each line comprises 64 bytes and the total of 4 lines 0-3 contains the storage space for the logic table LCT. Each line 0-3 is further divided into two channels of 32 bytes each. Accordingly there there are 8 channels with 32 bytes, which comprise the 4 lines with 64 bytes of the logic table LCT. The next 256 bytes are for Channel instruction programs CCP reserved. There are also 3 to 4 K bytes that go along with the unused space are reserved for channel instruction programs CCP. Below this space there is an additional 256 bytes that are used for the channel control block CCB are reserved. As with the storage space for the logic table LCT, each line 0-3 is a control block CCB of 64 bytes each allocated, which is divided into two channels of 32 bytes each. Below this storage space space is reserved for the firmware main memory. Accordingly, it can be seen that each line 0-3 has a memory space the logic table LCT and the control block CCB is assigned, each of which is divided into two channels. A part the addressing mechanism described in connection with FIG. 1A addresses all of these storage locations. To do this, however, the two address bytes a and b must be taken because an address byte comprises 8 bits and only 256 memory locations can be addressed with 8 bits. As can be seen in FIG. 2A However, 768 memory locations (3 χ 256) are provided, whereby the 3K / 4K memory locations are not yet taken into account. These 256 memory locations are the most frequently addressed memory locations, as lines 0-3 maintain a constant dialog with the logic tables LCD, the control blocks CCB and the firmware. To address the 768 memory locations is it is very ineffective to use the 16-bit address, which can normally address over 64,000 memory locations. By However, an 8-bit address can only address 25t memory locations. The present invention allows addressing of the 768 memory locations by the first 5 bits 8-12 of the b-byte 103 by modifying the virtual address of Fig. 2B is made possible in the manner explained above. With this short form of addressing, cycle time and Saved storage space.

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Referring to Figure 1C, the logic diagram of the page division signal generator is 105, d. H. of the page divider PROM300 shown. The scheme is self-explanatory. The address memory locations are in different number systems is shown in the first three columns, while the last column is the one actually saved at this address memory location Contains information. The fourth column defines the hexadecimal storage locations that have the same content.

According to FIG. 2B, 256 memory locations are shown in the memory 201, which is reserved as virtual memory. The first 64 memory locations or bytes are decimal from 0 to 63 and hexadecimal numbered from 0 to 3F and they comprise the logic table LCT of the current line used by the instruction program CCP. The next 32 memory locations or bytes in the decimal memory locations 64-95 and the hexadecimal memory locations 40-5F are for the logic table LCD of the current firmware used channel reserved. The next 8 memory locations or bytes correspond to the decimal memory locations 96-102 or the Hexadecimal storage locations 60-67 are for the active control block CCB of the current channel reserved. This is followed by an unused memory space and then three memory spaces for each 8 bytes, which for the receiver / sender USART of the current line, the covered receiver / sender USART of the current line and the extension of the logic table LCT of the current channel are reserved.

A typical example illustrates how the improved addressing scheme of the invention works. It is therefore assumed that memory location 5 of row 0 of virtual memory 201 is to be addressed. Accordingly, all bits 0 to 7 of byte a of the register 103 have the value "0", whereby the NOR gate 104 and the page division signal generator 105 are enabled. The next 5 bits 8 to 12 also have the value "0", while bit 13 has the value "1 ^M , bit 14 denotes

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Value "O" and bit 15 has the value "1", which results in binary address 101 and decimal address 5. The virtual address 106 furthermore has the value “0” in the bits 0 to 12, the bit 13 having the value “1”, the bit 14 having the value “0” and the bit 15 having the value “1”. The control signal CPGLIN is also active, however, since bits 8 to 12 of byte b in register 103 have the value "0". It has previously been shown that when bits 8-12 are used to address the first 8 words in the page division signal generator 105, the CPGLIN signal is active or low. When the CPGLIN signal is active, bits 8 and 9 of the virtual address are correspondingly replaced by bits H and M of channel register 114. With the initial assumption that memory location 5 of line 0 is addressed, bits H and M of channel register 114 have the value "0" and accordingly bits 8 and 9 of real address 107 also have the value "0". The final real address therefore has bits 0-12 with the value ¹¹ O ", bit 13 has the value" 1 ", bit 14 has the value" 0 "and bit 15 has the value" 1 ", whereby the fifth Memory location of line 0 of the real memory is addressed.

In order to develop the problem one step further, it is now assumed that the fifth memory location in row 1 is too address is. The bit content of the register 103 and the virtual address 106 will differ from the previous one Example have not changed. However, since line 1 is to be addressed now, the channel register 114 has the value "0" in its high-value bit H and a value "1" in the bit M. If the signal CPGLIN is activated again accordingly, since bits 8-12 of byte b of register 103 all have the value "0", bit 8 of virtual address 106 becomes through the bit H of the channel register 114 which has the value "0" is replaced and the bit 9 of the virtual address 106 is replaced by replaces the middle bit M of the channel register 114, which in this example has the value "1", since line 1 is being addressed. The real address 107 is thus the value "0" in the bit potentials 0 to 8, the bit 9 becomes the Have the value "1", bits 10-12 remain at the value "0",

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bit 13 still has the value "1", bit 14 still has the value "0" and bit 15 still has the value "1". Correspondingly, the hexadecimal memory location 45 in the real memory, which is the fifth memory location in line 1, is now addressed. From this consideration it is easy to see that the same addressing can take place at memory location 5 of line 2 or line 3 by merely replacing bits H and M of channel register 114 with bits 8 and 9 of virtual address 106 to obtain the to get real address 107.

3 shows the detailed logical block diagram of the page subdivision device for the improved allocation of virtual addresses to real addresses. First, a structural description will be given, the various structures of Fig. 3 being identified by elements in Fig. 1A wherever possible. Thereafter, the operation of the structure of FIG. 3 will be described to show the various functions performed. Referring to Figure 1A previously described, the page dividing mechanism is designed to modify bits 4 through 12 of virtual address format 106 to form the final real address 107, bits 4 through 12 either in accordance with the presented signals be modified or not. Referring to Figure 3, it should be noted that multiplexers (MUX) 302, 303 and 304 and driver 305 provide the output signals on lines 302A, 303A, 304A, 305A and 305B, these lines being modified bits 8 through 12 of the real address 107 represent. Multiplexer 301 and driver 308 form the output signals on lines 301A, 308A, 308B and 308C, which represent bits 4 through 7 of the modified real address 107. Register 309 corresponds to register 114 in Figure 1A and it stores bits H, M and D and provides these bits as output signals on lines 309A, 309B and 309C. Register 310 corresponds to CCB register 115 in FIG. 1A and it stores and provides the OC and β> bits as signal outputs on lines 310A and 310B.

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The read-only memory PROM 300 corresponds to the page division ■ signal generator 105. As previously described, it provides the various signals for the transmission of the virtual address 106 into the real address 107. The division of the read-only memory PROM 300 corresponds to that in FIG. 1C. The drivers 305 and 306 are connected to AND gate 311A to provide the real memory address bits 11 and 12 to form. Register 311 is used to store various signals.

Each of these devices is commercially available from manufacturers such as Texas Instrument, Motorola, Intel and other semiconductor manufacturers are available, using the table below I the type numbers of the various components are given:

Table I.

Component with
Reference number

MÜX301, 302, 303 and 304 drivers 305, 306, 307 and 308

Register 114, 115, 120, 121, 122, 122, 123A, 309, 310, 311, 360, 361, 370, 371, 372 and

AND gates 311A, 354, 358A, and 372

PROM 300 and 384

Decoders 351, 352, 353, 355, 356, 357 and 380

Comparators 358 and 35fcB USART 116 and 117
Bus drivers 110 and 111

Customary identification number

74LS253 74LS241 74LS374

74LS08

5610
74LS139

74LS08

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Referring again to FIG. 3, the mode of operation and function of the page subdivision device for the improved allocation of virtual addresses to real addresses will be described in more detail. As previously described in connection with FIG. 1A in more detail, the CPGLIN-side sub-division line signal dialog takes the active state by it assumes the low level when the addresses are addresses 0 through 7 of the PROM chip 300. This is illustrated in the page subdivision PROM list in FIG. 1C, in which the contents of the list have the value 01111111 in the first 8 positions. Bit position 7 has the value "0", which activates the CPGLIN signal. This signal is then fed to input terminals 2ag and 2ah of multiplexers 302 and 303, respectively. The other input control signal at the input terminals was 1ah and the multiplexers 302 and 303 is given by the logic signal "1" (LOGIC 1), which is switched so that it always has the high level. When the signal CPGLIN is active, ie has the low level, it addresses the input connections lag and 1ah of the multiplexers 302 and 303, which means that the signals at the input connections 1g and 1h are passed through and appear as output signals 302A and 303A accordingly. By tracing the CPGCNH signal on input terminal 1g of multiplexer 302 back to its source, it will be determined that it is from the high order bit on line 309A of channel register 309. In the same way , by tracing back the input signal CPGCNL at the input connection 1h of the multiplexer 303, it can be determined that it is coming from the output line 309B with medium significance. This corresponds to bits H and M of channel register 114 in Figure 1A. Correspondingly, when the signal CPGLIN is activated, the bits H and M of the registers 114 and 309 for the virtual address bits 8 and 9 on the output lines 302A and 303A are used accordingly. Conversely, if the signal CPG-LIN is not activated, the address bits 8 and 9 of the virtual address are not modified and these are passed on as they are to the output lines 302A and 303A of the multiplexers 302 and 303 . This is due to the fact that

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when the level is high for the signal CPGLIN and for the signal LOGIC1 the address 3g and 3h is addressed decimally (binary 11) to the multiplexers 302 and 303. The input address 3g of the multiplexer 302 is specified by signal CADU08, which is interpreted as the dialog address of microprocessor bit 8. the Input address 3h of multiplexer 303 is specified by signal CADU09, which is used as dialog address microprocessor bit 9 is interpreted. If the input connections 3g and 3h are addressed, these connections are activated and it can the addresses at these connections are passed on to the output lines 302A and 303A of the multiplexers 302 and 303.

The next control bit for the modification of the virtual address 106 taken from the PROM chip 300 is the directional bit CPGDIR. The directional bit is the low order bit D in the channel register 114 or the bit on the line 309C at the output of the channel register 309. The directional bit is activated, if the addresses 8, 9, 10 and 11 (decimal) of the read-only memory PROM 300 are addressed (see Fig. 1C). if If these bits 8-11 are addressed, the output signal CPGLIN is also active. Accordingly, in addition to that Signal CPGLIN applied to multiplexers 302 and 303, signal CPGDIR to input terminals 1d and 1ai of the multiplexers 301 and 304 supplied. If the CPGDIR signal at input terminal 1 of multiplexer 304 is inactive, it does not matter whether the input signal CPGAD8 at the input terminal 2ai of the multiplexer 304 is high or low, since both States either the input connection Ob or 2b (binary addresses 0 or 11) is activated and the signal CPGCND this is supplied to both addresses. The signal CPGCND comes from the output line 309C of the channel register 309, which is the bit D of the channel register 114 and 309 corresponds. If the directional bit CPGDIR is activated accordingly, the 10th bit (decimal) of the virtual address 106 is modified in accordance with the content of the bit D of the channel register 114 or 309. It results does not affect the signal CPGDIR at the input terminal 1d of the multiplexer 301, unless the signal CPGAD8

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is also activated. This is due to the fact that when the signal CPGAD8 (high level) is inactive, only addresses 2e or 3e (binary 10 or 11) · of the multiplexer 301 are addressed and these are both equal to each other and represent bit 7 of the dialog address of the microprocessor. But when the signal CPGAD8 from the read only memory PROM300 also is activated (low level), only the addresses Oe or 1e (binary 00 or 01) of the multiplexer 301 are addressed and active. Both addresses are supplied with the logic signal LOGIC 1 with the value "1" and this signal becomes the output line 301A of the multiplexer 301 passed on if both signals CPGAD8 and CPGDIR are active or if only the signal CPGAD8 is active.

When the CPGAD8 signal is active, bit 7 of the virtual address is modified and set to the value "1".

As previously described with reference to FIG. 1A, bits 11 and 12 of virtual address 106 are replaced by channel bits OC and β of register 115 when channel register bit CPGCCB is active, ie has the low level. Since register 310 in FIG. 3 corresponds to channel register 115 and bit CPGCCH on output line 310A corresponds to bit <* - of channel register 115 and bit CPGCCL on output line 310B corresponds to bit β of register 115, these bits replace bits 11 and 12 of the virtual address when the signal CPGCCB is active, ie has the low level. Let us now see what happens. When the signal CPGCCB is asserted, it is applied to the input terminal 11 of the driver 306 and one input terminal of the AND gate 31IA. Accordingly, driver 306 is enabled and channel control bit signals CPGCCH and CPGCCL on output lines 310A and 310B are applied to terminals 1h and Oh of driver 306, respectively, and passed to output lines 306A and 306B of driver 306 for bits 11 and 12 of the virtual memory address. It should be noted that when the signal CPGCCB at the input terminal 1 of the driver 306 is low, the driver 306 is enabled, but the same is applied to the input terminal 19 of the

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The signal supplied to driver 305 blocks this driver. Thus, the signals CADU at the input terminals 24 and 25 of driver 305 is not passed to output terminals 305A and 305B, but through the bits of channel register 310 in replaced in the manner previously described. It can thus be seen that either driver 306 or driver 305, but not both, is enabled and that either the channel register bits via driver 306 or the microprocessor address bits via the Driver 305 to be passed to the output.

Finally, with regard to the virtual address modification the modification of bits 4, 5 and 6 is explained. As previously stated with reference to FIG. 1A, this is done via the signal CPGAD4. If the address 12 (decimal) of the page division signal generator is addressed, all of the following signals become active: CPGLIN, CPGDIR, CPGCCB and CPGAD4. this can be seen from Fig. 1C, in which the address 12 (decimal) has the following bit combination 00001111. Thus, the Bit positions 4, 5, 6 and 7 are low and active, so that the signal generator 105 in FIG. 1A generates the signals Outputs CPGAD4, CPGCCB, CPGDIR and CPGLIN. It has already been shown how the first 3 signals create the virtual address in their active state and it will now be shown how the signal CPGAD4 modifies the virtual address and inserts the value "1" into bits 4, 5 and 6 of the virtual address. The signal CPGAD4 is applied to the enable terminal 19 of the driver 308 supplied. When driver 308 is enabled, the binary value "1" in bits 4, 5 and 6 becomes correspondingly set. If it is not released, the CADU microprocessor address for bits 4, 5 and 6 is passed through accordingly. This is because driver 308 is a commercially available tri-state circuit of the type LS241, the Has pull-up resistors for the applied signal. Accordingly, when a low level signal such as the CPGAD4 signal is asserted, this signal does not enable the driver 308 and the output signals are asserted + 5V pulled up, resulting in a logic "1" level. On the other hand, when the CPGAD4 signal is inactive, i. H. the high

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Level, the driver 308 is enabled and allows the address signals to be passed on to the input terminals 1k, 2k and 3k of driver 308.

The page division signal generator 105 in FIGS. 1A and 1B Generate equivalent in the form of the read-only memory PROM-300 in Fig. 3 not only signals by which the memory 109 can be addressed more efficiently, but they also generate signals, that a more efficient addressing and a more efficient dialogue between the main memory 108, the microprocessor 101 and the different registers and peripheral devices on the I-bus and the U-bus. This dialogue between the different Devices such as between the registers and memory and registers using the U-bus and the I-bus is triggered by activating the CEU2I0 signal. The signal CEU2I0 has the low level and is activated / when the assigned bit in the memory map of FIG. 1C has the value "0". It should be noted that the signal CEU2I0 corresponds to bit position 1 of the page division signal generator 105. Referring to Fig. 1C, which shows the memory usage of the page division signal generator 105 and its corresponding read-only memory PROM-300 shows, it can be seen that there are 3 addresses at which a "0" is stored in bit position 1. These addresses correspond to the decimal memory locations 18, 21 and 22 or the virtual hexadecimal storage locations 90, A8 and BO. Therefore, if any of these memory locations of the page division signal generator 105 or the read-only memory PROM-300 is addressed by the microprocessor 101, then the signal CEU2I0 is active and has the low level. The signal CEU2I0 triggers the dialog process and controls the release bus driver 111 in Fig. 1A and bus driver 711A, respectively in Fig. 7. The signal is also provided as an input to AND gate 354 in Fig. 4 and ensures pulse delivery thereafter the data on the bus has become valid.

030028/0822

Referring to Figures 3 and 4, a signal CEU2I0 becomes in the bit position 1 of the memory PROM-300 is generated when the I-bus driver is enabled 711A is desired to transfer data from the U-bus to the I-bus to be transferred and this either in the channel register 114, the CCB register 115 or S register 123A. 4 it can be seen that the signal CEU2I0 has an input terminal of the AND gate 354 is supplied and an AND operation with a key signal CTPHZD is subjected to the signal CEU2I0-10 at the output of AND gate 354 to be generated. This signal is then fed to the enable input of the decoder 355. Furthermore, the input terminals 2OA and 10A of the Decoder 355 bits 10 and 11 of address 103 of the dialog address unit fed. These bits are then decoded to one of 4 signals at the output terminals of the decoder 355 to activate. When bits 10 and 11 on input terminals 2OA and 10A of decoder 355 are 10 or have the binary decimal value 3, the output signal CEU2I0-A2 is released and sent to the release input of the decoder 357 created. In addition, bits 13 and 14 of the dialog address unit, i.e. H. the signals CADU13 and CADU14 to the input connections 2PA and 1PA of decoder 357 are applied. If both bits 13 and 14 have the word "0", the output of the decoder 357 activates and uses the signal CEI2CN, to write into the channel register 114 in Fig. 1A and 309 in Fig. 3, respectively. On the other hand, when bits J3 and 14 are "0" and "1" and are supplied as signals CADU13 and CADU14 to the input terminals 2PA and 1PA of the decoder 357, so the signal CEI2CB is active at the output of the decoder 357 and is used to set the CCB register 115 in FIG. 1A or 310 in FIG to address. Finally, when bits 13 and 14, which are fed as signals CADU13 and CADU14 to input terminals 2PA and 1PA of the decoder 357 have the values "1" and "0" or the decimal value 2, then at the output of the decoder 357 asserts the CEI2SR signal and uses it to address the S register 123A. The signal CEU2I0 is thus used to enable bus driver 111 and address registers 114, 115 and 322A. Accordingly, when the microprocessor 101 has a

030028/0822

ORIGINAL INSPECTED

Write command processed, which writes the accumulator contents of the microprocessor in the hexadecimal memory location A8, the microprocessor puts the contents of the accumulator to the U-bus and enables the bus driver 111 in the write direction, whereupon the bus information in the appropriate register address is keyed in.

When a write command is processed and information in any the register on the I-bus is written, the bus driver 110 according to FIG. 1A also enables the M-bus 109 and the same information written into the address register is also stored in an addressed section of the memory 108 enrolled. In this context, reference is also made to FIGS. 2A and 2B. The bus driver 110 is missing a Signal CEMB2U released and it switches the M-Bus through in the direction of memory 108. Thus the in the register written information is also written into a "shadow memory" which stores the information for diagnostic purposes or kept for the test and which forms a storage space for storing data when external maintenance is carried out will.

When reading data from the I-bus to the U-bus, it is necessary to to block data transmission from the M-Bus to the U-Bus. This allows the I-bus to control the data on the U-bus. This function is carried out by generating the signal CEI02U in the page division signal generator 105. This signal is then applied to the enable terminal of decoder 351 in FIG. 4 and at the same time bits 9 and 10 become the Address 103 is applied to input connections 2K and 1K as signals CADU09 and CADU10. These signals are a first Subjected to decoding level to produce an output signal CEI02U-A1 at the output terminal 01 of the decoder 351 when the Input bits 9 and 10 have the values "0" and "1", respectively. The CEI02U-A1 signal is then applied to the enable terminal of decoder 352 along with bits 14 and 15 on the input terminals 2LA and 1LA created. Depending on the

030028/0822

Binary value of bits 14 and 15 becomes one of 4 sub-instruction signals is generated at the output terminals of the decoder 352. If the bits 14 and 15 have the value "0", what the addressing of the hexadecimal memory location A8 in the virtual memory, a sub-instruction CEDH2I-00 is generated at the output connection 00 of the decoder 352 is generated. This signal is then applied to the enable terminal of register 360. The registry 360 corresponds to high order data register 120 in FIG. 1A. The signal CEI02U represents a means accordingly for reading out data from the high-quality data register 120 on the I-bus and on the u-bus. However, since the bus driver has been blocked by the presence of the signal CEMB2U, the memory location addressed by address 103 is not read and only the high order data register 120 is read. Similarly, the low order data register 121 becomes read when bits 14 and 15 are 01, thereby addressing output terminal 01 of decoder 352. Consequently the signal CEDL2I-00 is generated, which is sent to the release connection of register 361 in Fig. 4A is applied. It can thus be seen that the registers 360 and 361 of FIG. 4A Corresponds to registers 120 and 121 in Fig. 1A.

Bus driver 110 in Figure 1A corresponds to driver 370 in Figure 4B. This is a bidirectional driver and it can either drive data from the memory bus 109 to the O-Ba s 112 or vice versa. The direction of the data transmission is controlled by the signal CEMB2U. If the signal is present, data flow is permitted from the memory bus 109 to the microprocessor bus 112, and if the signal is not present, data transfer in the reverse direction is permitted. The signal CEMB2U is generated via AND gates 371 and 372 in FIG. These AND gates perform a simple AND operation of various signals, these signals being specified by the microprocessor read signal CUREAD, the key signal CIPHZ2 and the dialog enable signals CESR2U and CEIN2U. The signal CEMB2U is generated from these signals, which is then sent to the

030028/0822

an input terminal of the AND gate 371 is supplied . It should be noted that in a transfer operation from the I-bus to the U-bus, ie in other words in a read operation from a register on the I-bus to the U-bus, this signal at the input of the AND gate 371 has the high level and that the signal CEMB2U has the high level when the remaining signals also have the high level. When this high signal is applied to the input terminal of driver 370 in Figure 4B, it blocks information passage through bus driver 110 from the I-bus to the M-bus.

The addressing of the receiver / transmitter USART 116 and 117 will now be described with reference to FIGS. 1A, 1C and 4. The signal which triggers this addressing is given by the signal CE $ U2U , which occurs as bit 3 at the page division signal generator 105 in FIG. 1A. It can be seen from Fig. 1C that the only address which has the value "0" in bit position 3 is the hexadecimal address 88. Therefore, when this memory location is addressed, bits 0, 3, 4 and 7 become active. As previously mentioned, bit 3 specifies the signal CE $ U2ü , which is fed to the enable connection of the decoder 350A in FIG. 4 and which takes part in the decoding of the middle bit of the channel number CPGCNL. Depending on the value of this bit, one of two output signals CE0U2U and CE1U2U at the output terminals 0 and 1 of the decoder 350 A becomes effective. If the signal CE0U2U is active, the receiver / transmitter USART 116 is enabled, while if the signal CE1U2U is active, the receiver / transmitter L ¹ SART 1 17 is enabled . When information is written into the enabled receiver / transmitter USART, it is also written into the part of the memory which is addressed by the address 103 . This type of dual addressing uses two virtual addresses that are converted into the same physical address in order to create a duplicate address or a shadow image of the physical device actually addressed. For example, it was shown how the hexadecimal

030028/0822

Address 88 addresses the receiver / transmitter USART by forming a release signal for the correct receiver / transmitter USART will. 1C it can be seen that the hexadecimal address C8 has the same binary value as the hexadecimal address 88, with one exception, which is that the bit number 3 of the hexadecimal address 88 has the value "O", while bit number 3 of hexadecimal address C8 has the value "1". Accordingly, it can be seen that with the exception of the third bits, the hexadecimal address 88 supplies the same signals as the hexadecimal address C8, so that the address C8 regarded as the shadow of the addressed recipient / sender USART if the signal CESU2U is supplied by the hexadecimal address 88. It can thus be seen that the hexadecimal address 88 or decimal address 17 addresses the actual USART data, while the hexadecimal address C8 or the decimal address 25 whose shadow is addressed. If accordingly written under the hexadecimal address 88 , USART is written to the receiver / transmitter and the appropriate memory location is addressed, which is defined by the hexadecimal address C8 is specified, which is done in accordance with the principles explained above. This is explained using a typical example. First, let the page division signal generator 105 addressed with respect to the decimal memory location 17. Using the address format 103 results in the address as follows: 0000000010001000. Es it should be noted that bits 8 through 12 which effect the actual addressing contain the decimal number 17 in binary format. According to FIG. 1C it can be seen that the decimal memory location 17 has active bits in positions 0, 3, 4 and 7. That Bit 0 generates signal CPGAD8 in the page division signal generator 105 and this signal sets bit 7 to the value "1" in the active state. Bit 3 forms the signal which addresses the receiver / sender USART and which does not take part in the change from the virtual address to a real address. Bit 4 of the page division signal generator specifies the signal CPGAD4, which in its active state the

030028/0822

Sets bits 4, 5 and 6 to the value "1". Finally, the bit 7 of the signal generator 105 delivers the in the active state Signal CPGLIN and sets the high-order bit and the medium-order bit of the channel register to bit positions 8 and 9 the real address. Assuming in the present example that those bit positions have the value "0", the result is Bits 8 and 9 with the value "0" and the final real address has the value: 000011110000000. If now the decimal address 25 is addressed, the address format 103 takes the following form: 0000000011001000. Again, Fig. 1C can be seen, that the following signals are active: CPGAD8, CPGAD4 and CPGLIN. Since the signal CE $ U2U, which in the previous example was also present, does not participate in the change of the address, the final real address is the same as the one before specified address and has the following form: 00001111 0000000. It can thus be seen that the same address is in the Memory is addressed. Accordingly, when external maintenance or diagnostic operations are required, only the Shadow memories are addressed and addressing the actual recipient / sender USART is not required In principle, the same applies to other peripheral devices or registers that are also connected to the I-bus.

This shading technique when addressing a hardware component such as the receiver / transmitter USART, the channel register or the channel control block register, etc. is special useful and saves cycle time when an interrupt occurs in which the contents of a register, for example of the CCB register must be replaced. In the conventional design, the content of the register is read out and stored in a stored in temporary memory and the new information is written into the register. If the original content of the register is to be written back, the register must first be read out again and the content in a temporary one Memory can be stored and then the original content can be written back. With the invention In the case of an interruption mode, the shading concept only has to write the new information into the register.

030028/0822

there is a shadow or an image of the original information in the register in a predetermined memory location in the main memory is stored. The old information is retained in the shadow memory location and when it is in the register is to be written back, it can be read directly from the shadow memory location. Since about 3 με for one read operation and 4 με are required for a write operation, a total of 4 με can be saved during each complete cycle.

With reference to FIGS. 5 and 6, the preferred embodiment is described below a vectorial interruption. Fig. 6B shows the timing diagram of the interrupt sequence. That Signal PTIME3 is a mass effective TTL signal that is sent every 500 ns is generated by the central processing unit CPU 600 and has a pulse width of 100 ns. This signal is being used extensively used by system 600A peripheral controls to set and reset states on buses 620, 621 and 622 and to act as a data key pulse. The BINTR signal is the interrupt request signal which is on an open collector driver line is present on the buses and is connected to ground by some peripheral control of the system, when this controller attempts an interrupt. The PIOCT signal is also a grounding TTL signal that is generated by the Central processing unit CPU 600 is used to indicate to a selected controller that there are coded states on the bus, which transmit the bus dialog control information to the controller. The data bus valid signal indicates that the data are stabilized on the bus. When activated by the central processing unit CPU 600, the signal PBYTE supplies the low-order signal Byte, d. H. bits 8-15 of the addressed word to a controller such as microprocessor 601. Finally, the signals PBBUSY or PROCED indicate in the active state that either a controller is occupied and the instruction rejects or that it accepted the last interrupt that existed on the bus.

030028/0822

The microprocessor interrupt mechanism described here is activated when the central processing unit CPU-600 initiates an I / O command which is directed to one of the I / O devices 620 or 601 via the I / O bus via the channel number. Should the command be directed to this microprocessor 601, a decoder recognizes the channel number and sets the microprocessor interrupt request. The 16 bits of information on the system bus during instruction initiation (see Fig. 6B, signal PIOCT) include the 10 bit channel number and the function code a and b. At the point in time when the channel number is compared and when it is determined that it is the channel number of the microprocessor, this information is stored in register 362 (channel number) and register 311 (FCN) and an interrupt request to the microprocessor is displayed in a flip- Flop saved. Since the microprocessor treats this request as a masked interrupt, its action can be postponed. The time sequence of these measures is shown in FIG. 6B .

Typically, when the microprocessor 601 receives an interrupt command, it sequentially addresses hexadecimal storage locations FFF8 and FFF9 in main memory 108 in which the high order byte and the low order byte of the interrupt vector are stored. It can be seen that the hexadecimal address FFF8 with binary notation in the address format 103 has the following bit combination: 1111111111111000. In the same way, the hexadecimal address FFF9 results as follows with binary notation: 1111111111111001. If the address FFF9 is addressed accordingly after the high-value byte of the interrupt register has been called up, the bits with the value "1" of address FFF9 take effect. These bit signals are supplied to the various hardware circuit elements in FIG. 3 in various combinations or individually. In other words, these address bits are used instead of the hexadecimal address FFF9 in the main memory 608A and 608B to a) disable the page division addressing mechanism and b) the decoder 380 in the central processing unit CPU

030028/0822

which in turn c) enables the register 311 to transfer a predetermined base address to the PROM / RAM-601B and which e) in turn contains the address of a selected function code within 64 function codes. This happens when bits 0, 1, 2, 13, 14 and 15 of the aforementioned address are input terminals of decoder 380 are supplied according to Fig. 4C. As mentioned before, when addressing the hexadecimal address FFF9, bits 13 and 14 has the value "0" and bit 15 has the value "1", these bits being supplied to the enable terminals of the decoder 380 will. In addition, bits 0, 1 and 2 of the address, all of which have the value "1", are assigned to connections 1, 2 and 4 of decoder 380 in Fig. 4C. Since the connections to which bits 13 and 14 are in the form of signals CADU13 and CADU14 are supplied, have an inversion and the information at the terminals 1, 2 and 4 of the decoder 380, respectively has the value "1", there is an active signal CADUH7 at the output terminal 7 of the decoder 380. This is the case, because the binary value 111 is decoded as a decimal value 7. The signal CADUH7 is then the release terminal F of the register 311 in Fig. 3 and it is also simultaneously to the enable / disable input connection of the multiplexers 301, 302 and 303 and applied to AND gate 311A, whereby the page division addressing mechanism is blocked. Instead of accessing the hexadecimal memory location FFF9 the register 311 is enabled and it provides the low-order bits 10 to 15 at its output terminals. These Bits form an address for addressing the RAM or PROM-601B memory. The content at the address of the Memory 601B is stored in the low-order byte position of program counter 601D. The information in the register 311 represents the function code information shown in FIG. 5B which has been delivered by the central processing unit CPU when a Interruption was triggered (see signal PBYTE in Fig. 6B). Since the page division addressing mechanism has been disabled and since the signal CADUH7 again directs the addressing of the hexadecimal memory location FFF9 to the register 311 and

030028/0822

since the CADUH7 signal also enables register 311, the lower-order bits 10 to 15 of register 311 are used, in order to access information in the memory 601B which is stored in the low-order byte position of the program counter 601D will. Since there are 6 bits in the low-order byte of the function code, up to 64 memory locations can be saved in the RAM or PROM 601B can be addressed. Each of these storage locations contains the low-order byte of the interrupt vector, the its function code is assigned, which includes the interrupt address when supplemented.

Depending on the information content of the function code, an interrupt is accordingly achieved which can start at any one of 64 different storage locations in the memory PROM 601B and can accordingly carry out up to 64 different interrupt operations. In addition, the program counter 601D or other registers receive their information from a shadow memory location and accordingly it is not necessary to first unload and then save the old information and then load the new information and repeat the same process again when the interrupt loop is left. It should also be noted that the normal interrupt procedure of the microprocessor, which refers the microprocessor to the address FFF9, bypassed wild iiinl «Min '/ Vii er .. ·; ο ViM) (> I ο i iiilrul l <jch / Vh eri- en .iu { om.il i ri \\ is supplied by the function code, whereby an effective restriction to 64 different vectors or routines is achieved.

With reference to FIGS. 4 and 6B, it should be noted that when activated of the signal CADUH7 this is fed to the AND gate 358A together with a phase signal CTPHZD, whereby the Signal CEI2CN is triggered. In addition, the CADUH7 signal is ORed with the CECN2I signal in gate 358B subjected to trigger the CECN2I signal. The CEI2CN signal is applied to terminal C of channel register 309 in FIG. which as previously explained, the channel register 115A in

030028/0822

COPY

Fig. 1A corresponds. Likewise, the CECN2I signal is used to store the contents of the channel new register 122 in FIG. 1A to clock on the I-bus or vice versa.

Accordingly, the vector interrupt does two things: First, it automatically addresses any of 64 memory locations according to a unique function code and then it loads the hardware channel number register with the channel number that is required for handling the interruption. The channel control block register CCB-115 can also be used in a Interruption can be changed, which depends on the function code.

There is also another type of interrupt, which is the establishment of priorities within a number of competing input / output devices. This type of interruption is implemented by means of a read-only memory PROM which has a number of predetermined memory locations which store the information for setting the priorities. For example, in Fig. 1A either the receiver / Transmitter USART 116 or the receiver / transmitter USART 117 with the Microprocessor 101 under the control of a channel program. The priorities are formed in a read-only memory PROM 384 in FIG. 4D and the signal input CPBACK + 00 of the read-only memory PROM 384 is activated when microprocessor 101 is processing a background program. The request signals CORRQT (reception) and COTRQT (transmission) of the receiver / sender USART 116 are fed to the address connections 1a and 2a of the PROM 384, respectively. In the same way, the request signals C1RRQT and ClTRQT of the receiver / transmitter USART 117 are den Address connections 3a and 4 of the memory PROM 384 are supplied. The signals CPGCNH, CPGCNL and CPGCND identify the channel number of the currently active channel program and they are fed to the address connections 5a, 6a and 7a. The read-only memory PROM 384 is internally encoded to provide one output signal within 256 output signals. The codes are by compliance formed a number of rules.

030028/082?

COPY

When a channel is processing, its counterpart cannot be intercepted. This means in the event that the receiver / transmitter USART 116 receives and receives the receive request signal CORRQT + 00 at the input of PROM 384 has the high level, the send / request signal COTRQT + 00 of USART 116 just as the transmit signal CITRQT + 00 of the USART 117 is set to the high level and the USART 116 remains in the receive mode until the channel program completes the receiving operation, whereupon the channel program performs a sending operation regarding the USART 116 can start.

If both receivers / transmitters USART 116 and 117 are operated synchronously the receive operation is given priority over the send operation. When the USART 116 receiver / transmitter is in transmission mode and the receiver / transmitter USART 117 requested the channel program for a receive operation, the channel program switches to the treatment of the receiver / sender USART 117, after the receiver / transmitter USART 116 has completed its transmit operation.

If both lines are not operated synchronously, the receiver / transmitter USART 116 has priority over the receiver / Transmitter USART 117. The one running on the microprocessor 101 The background program has priority over both the USART 116 and the USART 117. The one in the read-only memory PROM permanently stored logic configurations define the priorities.

If the channel program is to be intercepted, the output signal of the PROM 384 selects the channel number of the device operated with the intercepted channel program, this being done via the output signals CICHNH + 00, ClCHNL + 00 and CICHND + 00 of the PROM 384 . In addition, the signal CITCTR at the output of the PROM 384 is applied to the inputs of a register 382. When the channel program reaches the end of a subroutine, a jump microinstruction is issued from the microprocessor 101 and has the hexadecimal code 7EBD40. The hexadecimal bits encoded with 7E

030028/0822

define a jump microinstruction, the bits coded hexadecimally with BD40 define the address to which the channel program has to jump. The BD40., Address signals are processed by the microprocessor 101 is interpreted as a microword "set interrupt mask", whereby the interrupt line of the microprocessor 101 is blocked.

The next address BD41 i (1011 1101 0100 0001) is applied to the address bus 102 and the input decoder 380 as shown in FIG. 4C. The bit positions 0, 1, 2, 13, 14 and 15 are applied to the input of the decoder 380 in FIG. AC or the decoder 128 in FIG. 1A as address bus signals CADUOO + 00, CADU01 + 00, CADU02 + 00, CADU13 + 00, CADU14 +00 and CADU15 + 00 supplied. The output signal CADUHT-OO of the decoder 380 is set to the low level, thereby enabling the I register 382 in FIG. 4D and the I register 130 in FIG. 1A, respectively.

If a request is not issued to intercept the channel program, the CITCTR-OO signal is at the logic level "1" and the output of register 382 occurs on U-bus 112 in FIG. 1A by means of signals CDBUOO-07 + 00 hexadecimal than 39, thereby returning to the start of the microinstruction. If there is a request for interception, so the signal CITCTR-OO is at the logic level "0" and the output signal of the register 382 occurs on the U-bus 112 in 1A in hexadecimal as 01, which specifies an NO OP microprogram.

The hexadecimal value 01 on the U-Bus 112 is generated by the microprocessor 101 added in order to start a handling routine which begins at the hexadecimal address memory location BD42 and which Channel program intercepts.

In Fig. 4, input signal CADUH5-00 at the input of AND gate 372 prevents the flow of information therefrom when the level is high U-bus 112 to the M-bus 109 in FIG. 1A via the driver 110, by adding the signal CEMB2U + 00 at the output of the AND gate 371 in FIG. 4

030028/0822

is set to the high level.

According to FIG. 3, the signal CPBACK + 00 is at the output of the CCB register 310 takes effect when the signal CDBIO2 + 00 of the I-bus in FIG. 1A has the logic level "1", whereby the PROM 384 4D indicates that the microprocessor 101 is operating in a background mode.

030028/0822

Claims (14)

HONEYWELL INFORMATION SYSTEMS INC. December 21, 1979 Smith Street 5101647 Ge Waltham, Massachusetts, USA Priority resolver Patent claims: Priority resolution device for a computer system with multiple input / output devices to one. I / O bus, a system bus connected to the I / O bus, with a central unit and a microprocessor on the system bus, with a memory bus connected to the central processing unit, leading to a main memory leads and several to the microprocessor connected dialog lines, marked by a. a first device connected to the microprocessor and having a first predetermined number of memory locations for storing on the main memory, the central processing unit, the microprocessor, the I / O devices and the dialog lines related priority information; b. a second device connected to the first device, which respond to signals from the main memory, from the central processing unit, from the microprocessor, from the I / O devices and is responsive to the dialog lines and addresses any of the first predetermined memory locations; and c. a third device connected to the first device for deriving signals that indicate the priority information at the memory location address. 030028/0822 ORIGINAL INSPECTED 2. Device according to claim 1, characterized by one connected to the third device interrupt device for assigning an interrupt priority to the main memory, the central unit, the microprocessor, the I / O devices and the dialog lines. 3. Priority resolver for a computer system nit multiple I / O devices on one I / O bus, at least one system bus connected to the I / O bus, with at least one Central unit and a microprocessor on the system bus, with at least one connected to the central unit Memory bus that leads to at least one main memory and with several dialog lines connected to the microprocessor, marked by a. a first device connected to the microprocessor with a first predetermined number of storage locations for the storage of information related to certain devices, the priority information in any Storage space of the first predetermined number is dependent on a predetermined combination of states; b. a second facility connected to the first facility, to resolve the priority of signals corresponding to a first selected combination of states is responsive to address a first selected memory location within the predetermined number; and c. a third device connected to the first device for deriving signals indicating the priority information stored at the memory location address. 4. Device according to claim 3, characterized in that that the dialog lines are in competition with regard to the control of the microprocessor, that At least one dialog line is operated synchronously and the remaining dialog lines are operated asynchronously that a fourth facility is arranged to receive signals corresponding to the first 030028/0822 .Combination within the predetermined combinations of states to form, wherein the predetermined combinations of states include a warning priority to the synchronously operated dialog line. 5. Device according to claim 4, characterized in that there are at least two dialog lines (a) and (b) are in competition in controlling the microprocessor and both dialog lines are operated asynchronously that a fifth device is arranged to generate signals corresponding to the first combination of the predetermined combinations of states to form, wherein the predetermined combinations of states include a warning priority to the dialogue line (a). 6. Vector multipath interrupt device for a computer system with a virtual '; and a real memory, a page subdivision device for addressing this memory, with a central unit connected to the virtual and real memory and with one connected to the central unit, the virtual and the real memory connected microprocessor, which has a read-only memory PROM and a program counter having, the read-only memory having a plurality of base addresses for addressing a predetermined number of memory locations in the real memory and some base address of the search for a memory location in the real Memory is used in which a predetermined number of interrupt routines are stored, marked by a. one to the virtual and the real memory, the central processing unit and first device connected to the microprocessor for disabling the page dividing device, when addressing a predetermined storage location in the real memory; b. one connected to the program counter and the microprocessor second device for addressing the read-only memory if the first device is the page subdivision device locks; and 030028/0822 c. one connected to the second device and responsive to the read-only memory and the program counter Means for addressing a selected memory location in the real memory, whereby a selected one Interrupt routine becomes available for use by the central processing unit. 7. Device according to claim 6, characterized in that the program counter has a high quality and has a low order address range and that a fourth device connected to the third device is arranged to in the high-quality address area the content of the predetermined memory location of the real To save memory. 8. Device according to claim 7, characterized by a fourth device for storing the content of a selected read-only memory storage location in the low-order address area of the programming counter. 9. Vector multipath interrupt device for a computer system with a virtual and a real memory, the real memory being a high-order byte and a low-order byte Byte corresponding to an interrupt vector stores in a first and second predetermined memory location, with a page divider for addressing the virtual and the real memory, one to the virtual one and real memory and a central unit connected to the central unit and the virtual and real memory connected microprocessor, which has a read-only memory and a program counter, the read-only memory several base addresses for addressing a specific one Number of storage locations in the real memory and the program counter has a high value and a low value Has address range, identified by 030028/0822 a. a first device for issuing an interrupt command to interrupt the central unit; b. a second device connected to the first device and responsive to the interrupt command for Addressing the first predetermined memory location of the real memory; c. one connected to the real memory and the program counter and third means, responsive to the second means, for retrieving the high-order byte of the Interrupt vector from the first predetermined memory location of the real memory in the high-value address area the program counter; and d. a fourth device connected to the second device for addressing the second predetermined memory location of the real memory. 10. Intercepting device for channel programs in a computer system with a main memory on a memory bus, a bus driver connected to the memory bus for enabling and Blocking the flow of information to the main memory, a U-3us connected to the bus driver, with a microprocessor processing channel programs and a command register on the U-bus are connected and the command register of the trip an interception operation and several dialog devices also connected to the U-bus, characterized by a. first means connected to the microprocessor for interrupting the same; b. a second device for addressing a first predetermined memory location in the main memory, wherein this first memory location stores first signals for enabling the device; c. a third device for addressing a second predetermined memory location in the main memory, wherein this second predetermined memory location is the next memory location following the first memory location and is addressed when there is no interrupt request for 030028/0822 the microprocessor takes place, and wherein the second predetermined memory location second signals for enabling the command register stores; d. a device connected to the bus driver and responding to the second signals for blocking the bus driver, the normal memory read data path is disabled; and e. one connected to the command register and the dialog devices and responsive to an interception request from one of the dialog devices fifth device for triggering an interception operation. 11. Device according to claim 10, characterized in that the second device has a read-only memory, comprises a virtual and a real memory. 12. Device according to claim 11, characterized in that the bus driver is a bidirectional Has tristate circuit. 13. Interception device for intercepting a microprocessor control requesting channel program in a computer system, with a main memory on a memory bus, a bus driver connected to the memory bus for enabling and disabling the Information flow to the main memory, one to the bus driver connected U-bus, whereby a channel program processing microprocessor and a command register on the U-bus are connected and the command register of the resolution of an interception operation and several also connected to the U-bus Dialog devices is used and with a connected to the memory bus Central unit, characterized by a. first means connected to the microprocessor for forming an intercept request to the microprocessor; and b. a second device connected to the first device to intercept the interception request. 030028/0622 14. Device according to claim 13, characterized by one connected to the second device
third means for intercepting the interrupt request when the central processing unit has a minimum of information to process. 030028/0822