DE2949490C2 - Method for monitoring the supply voltage of a storage system - Google Patents

Description

30th

The invention relates to a method for monitoring the supply voltage of a memory the preamble of claim 1.

Solid-state memory with volatile information storage, z. B. built up from semiconductor elements memory, lose their memory content if a The supply voltage is interrupted. The content of the individual memory locations is removed when the power is switched on again the supply voltage in a bit pattern that characterizes the individual memory locations, of the failure bit pattern, over. To prevent this undesired loss of memory content, the In most cases, backup batteries are used, which in the event of a failure of the supply voltage from a first Voltage source take over the further supply of the solid-state memory and thereby the failure of the Prevent supply voltage.

In various applications, however, the use of backup batteries to prevent a. Failure of the supply voltage is not possible. Sc is z. B. in some applications the use of backup batteries in telephone subscriber sets equipped with solid-state memories with volatile information storage or the like is not permitted. In such applications, the failure of the supply voltage must be reported to the user
reliably appear to him the loss
The memory contents are brought to the attention, and 1
rewriting of the memory contents erfc ^. before the solid-state memory is operated in readout mode

A variety of devices are known for the presence or absence of a supply voltage to monitor and display. These facilities are constantly and actively switched on because they are relatively complex to build up, they consume considerable energy.

The object of the invention is to provide a method indicate that allows a previous failure of the supply voltage that has been remedied in the meantime in a particularly simple and energy-saving way to indicate the loss to the user of the memory content of the solid-state memory.

This object is achieved by the characterizing features of claim 1.

According to the invention, the failure of the supply voltage are indirect via the change in the content at least one predetermined memory location is monitored in its failure bit pattern, in which a predetermined Bit pattern, the so-called test bit pattern, is stored, this being different from the failure bit pattern is what the memory location concerned will assume if the supply voltage fails. Once the failure bit pattern which is different from the previously stored test bit pattern is read out the previous failure of the supply voltage is displayed. Sufficient to carry out this procedure the circuit units available for reading in and reading out the solid-state memory, additional ones Circuits for monitoring the analog supply voltages can be dispensed with.

Preference is given to monitoring the test bit specified in the test memory location (s) this memory location is read out periodically and its content is checked.

According to a particularly preferred embodiment of the invention, the check bit pattern is equal to Negation of the failure bit pattern selected. This causes a voltage fluctuation or the like Caused change of the memory content of the volatile 1-est body memory with the largest possible Probability recorded per test memory location. A test memory location is then essentially sufficient, in order to detect undesired random changes to the memory content with the required reliability.

The inventive method has the decisive advantage that the failure that has occurred Supply voltage can be identified safely and reliably indirectly via the content of a test memory location is.

Claims (3)

Patent claims: 1. Method for monitoring the supply voltage of a memory with volatile information onsaving, with several storage locations, the content of which when switched on again after a previous failure of the supply voltage assumes certain failure bit patterns, with a Parameter is monitored and, if the parameter changes, the failure of the supply voltage is displayed, characterized in that as a parameter in at least one predetermined Storage space is a predetermined one that differs from the relevant failure bit pattern Test bit pattern is stored and monitored, and that when the content is changed de ;; the previous failure of the supply voltage is displayed in the monitored memory location. 2. The method according to claim 1, characterized in that the test bit pattern is equal to the negation of the failure bit pattern. 3. The method according to claim 1 or 2, characterized in that the memory locations in which the test bit patterns were stored, read out periodically and given the relevant ones Check bit patterns are compared.