DE2938567C2 - Housing for highly integrated circuits - Google Patents

Housing for highly integrated circuits

Info

Publication number
DE2938567C2
DE2938567C2 DE19792938567 DE2938567A DE2938567C2 DE 2938567 C2 DE2938567 C2 DE 2938567C2 DE 19792938567 DE19792938567 DE 19792938567 DE 2938567 A DE2938567 A DE 2938567A DE 2938567 C2 DE2938567 C2 DE 2938567C2
Authority
DE
Germany
Prior art keywords
housing
highly integrated
contact points
conductor tracks
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19792938567
Other languages
German (de)
Other versions
DE2938567A1 (en
Inventor
Peter Dipl.-Ing. 8000 München Fuchs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19792938567 priority Critical patent/DE2938567C2/en
Publication of DE2938567A1 publication Critical patent/DE2938567A1/en
Application granted granted Critical
Publication of DE2938567C2 publication Critical patent/DE2938567C2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

Die Erfindung betrifft ein Gehäuse, insbesondere Dual-in-line-Gehäuse, für hochintegrierte Schaltkreise mit einem in einem Anschlußstifte tragenden Gehäuseunterteil angeordneten Halbleiterplättchen und einem Gehäuseoberteil zu dessen Abdeckung.The invention relates to a housing, in particular a dual-in-line housing, for highly integrated circuits with a semiconductor chip arranged in a housing lower part carrying connection pins and one Upper part of the housing to cover it.

Komplexe Bausteine und Systeme, welche aus vielen LSI- (Large Scale Integration) und VLSI (Very Large Scale Integration) Schaltungen aufgebaut sind, lassen sich durch ihre Komplexität schwer testen. Mit der Entwicklung immer umfangreicherer Schaltungen auf einer Flachbaugruppe wächst das Testproblem überproportional. Es kann bis jetzt nur durch teure und komplizierte Testeinrichtungen, welchen nur die Benutzerschnittstellen der Bauteile zugänglich sind, gelöst werden.Complex modules and systems, which consist of many LSI (Large Scale Integration) and VLSI (Very Large Scale integration) circuits are built up, are difficult to test due to their complexity. With the With the development of ever more extensive circuits on a flat module, the test problem grows disproportionately. Up to now it can only be done through expensive and complicated test facilities, which only the user interfaces the components are accessible.

Aus der US-Patentschrift 32 92 241 ist ein Dual-inline-Gehäuse nach dem Oberbegriff des Hauptanspruchs bekannt.From US Pat. No. 3,292,241, a dual-in-line housing according to the preamble of the main claim is disclosed known.

In der OS 23 60 801 ist außerdem eine Prüfeinrichtung zum Prüfen, von Halbleiterchips beschrieben, wobei mit der Prüfeinrichtung in elektrischer Verbindung stehende, in einem Träger eingelassene Prüfspitzen mit dem jeweiligen Prüfling in Kontakt versetzbar sind. Aus der DE-OS 23 59 152 ist außerdem eine integrierte Schaltung mit unkonventioneller Anordnung von Anschlüssen zu entnehmen.OS 23 60 801 also describes a test device for testing semiconductor chips, with the test device in electrical connection, embedded in a carrier test probes with the respective test object can be brought into contact. From DE-OS 23 59 152 there is also an integrated circuit with unconventional arrangement of connections.

Aufgabe der vorliegenden Erfindung ist es, die Funktionsprüfung von komplexen integrierten Schallbausteinen zu vereinfachen.The object of the present invention is to test the functionality of complex integrated sound modules to simplify.

Zur Lösung dieser Aufgabe wird dabei das Gehäuse für hochintegrierte Schaltkreise derart ausgebildet, daß auf der Leiterbahnen zu den Anschlußstiften führenden Oberseite des Unterteils zusätzliche Kontnktpunkte vorgesehen sind, die über weitere Leiterbahnen unmittelbar mit ausgesuchten Anschlüssen des Halbleiterplättchens verbunden sind und daß im Gehäuseoberteil Durchbrüche über den Kontaktpunkten vorgesehen sind, durch die Prüfspitzen zu Meßzwecken einführbar sind.To solve this problem, the housing for highly integrated circuits is designed in such a way that Additional contact points on the upper side of the lower part leading to the connecting pins are provided, which are directly connected to selected connections of the semiconductor wafer via further conductor tracks are connected and that openings are provided above the contact points in the upper part of the housing through which test probes can be inserted for measurement purposes.

Durch die Schaffung von zusätzlichen Meßpunkten welche in Betrieb nicht zugänglich sind und welche keine Einschränkungen hinsichtlich der Schaltungsauflösung mit sich bringen, ist eine wesentliche Vereinfachung der Anzahl der Meßausgänge und von gleichzeitig zu überwachenden Signalen erreichbar.
Anhand der Figur wird die Erfindung näher erläutert.By creating additional measuring points which are not accessible during operation and which do not entail any restrictions with regard to the circuit resolution, a significant simplification of the number of measuring outputs and of signals to be monitored at the same time can be achieved.
The invention is explained in more detail with the aid of the figure.

(Die Figur zeigt einen Baustein mit z. B. einem |Halbleiterplättchen hoher Integration. Auf dem Unterseil 3, das die Anschlußstifte 2 trägt, ist eine Mulde vorgesehen, in der das Halbleiterplättchen 7 liegt. Das Plättchen ist mit den rund um die Mulde liegenden Anschlüssen durch dünne Drähte mit den Halbleiterplättchenanschlüssen verbunden. Die Anschlußstifte 2 wiederum sind dann mit Leiterbahnen mit den sich um die Mulde herum befindlichen Anschlüssen verbunden. Zusätzlich zu diesen Leiterbahnen 1 sind weitere Leiterbahnen 5 vorgesehen, die in sogenannten Kontaktpunkten 4 enden. Diese Kontaktpunkte stellen Meßpunkte für bestimmte ausgesuchte Schaltungspunkte des hochintegrierten Halbleiterplättchens 7 dar.
Die Meßpunkte werden bei der Gehäuseherstellung gleichzeitig mit der »Verdrahtung« für die Anschlußstifte gestanzt. Nach dem Bonden und Verschließen bleiben nur mehr die Endpunkte 4 dieser Leiterbahnen 5 durch Durchbrüche 9 im Gehäuseoberteil 8 zugänglich und ermöglichen damit ein Abtasten von Meßpunkten, welche bei Layout bzw. Schaltungsentwurf vorgesehen worden sind. Es können je nach Gehäusegröße eine unterschiedliche Anzahl von Meßpunkten vorgesehen werden, wobei im Sinne einer Standardisierung möglichst viele Meßpunkte vorgesehen werden sollten. (The figure shows a module with, for example, a semiconductor chip with high integration. On the lower part 3, which carries the connecting pins 2, a trough is provided in which the semiconductor chip 7 lies The connection pins 2 are in turn connected with conductor tracks to the connections located around the trough. In addition to these conductor tracks 1, further conductor tracks 5 are provided which end in so-called contact points 4. These contact points represent measuring points for certain selected circuit points of the highly integrated semiconductor chip 7.
During the manufacture of the housing, the measuring points are punched at the same time as the "wiring" for the connecting pins. After bonding and sealing, only the end points 4 of these conductor tracks 5 remain accessible through openings 9 in the upper housing part 8 and thus enable the scanning of measuring points which have been provided in the layout or circuit design. Depending on the size of the housing, a different number of measuring points can be provided, whereby as many measuring points as possible should be provided in the interests of standardization.

Es müssen im Einzelfall nicht immer alle benutzt werden. Bei einer Normung ist es möglich, Mehrfachiprüfspitzen zu verwenden, welche es auf einfache Art und Weise ermöglichen, alle in Frage kommenden Signale ohne umständliche Anschlußarbeiten an einem Prüfautomaten o. ä. weiterzuleiten.Not all of them have to be used in individual cases. With a standardization it is possible to have multiple test probes to use which make it easy to identify all of the Passing on signals to a test machine or the like without cumbersome connection work.

Hierzu 1 Blatt/ZeichnungenFor this 1 sheet / drawings

Claims (2)

Patentansprüche:Patent claims: 1. Gehäuse, insbesondere Dual-in-line-Gehäuse, für hochintegrierte Schallkreise mit einem in einem Anschlußstifte tragenden Gehäuseunterteil angeordneten Halbleiterplättchen und einem Gehäuseoberteil zu dessen Abdeckung, dadurch gekennzeichnet, daß auf der Leiterbahnen (J) zu den Anschlußstiften (2) führenden Oberseite des Unterteils (3) zusätzliche Kontaktpunkte (4) vorgesehen sind, die über weitere Leiterbahnen unmittelbar mit ausgesuchten Anschlüssen (6) des Halbleiterplättchens (7) verbunden sind und daß im Gehäuseoberteil (8) Durchbrüche (9) über den Kontaktpunkten (4) vorgesehen sind, durch die Prüfspitzen zu Meßzwecken einführbar sind.1. Housing, especially dual-in-line housing, for highly integrated sound circuits with a lower housing part that carries connection pins Semiconductor wafer and an upper part of the housing to cover it, characterized in that that on the conductor tracks (J) to the connecting pins (2) leading top of the lower part (3) additional contact points (4) are provided are connected directly to selected connections (6) of the semiconductor wafer via further conductor tracks (7) are connected and that in the upper part of the housing (8) openings (9) above the contact points (4) are provided through which test probes can be inserted for measuring purposes. 2. Gehäuse nach Anspruch 1, dadurch gekennzeichnet, daß die Kontaktpunkte (4) so angeordnet sind, daß Mehrfachprüfspitzen verwendbar sind.2. Housing according to claim 1, characterized in that the contact points (4) are arranged are that multiple probes can be used.
DE19792938567 1979-09-24 1979-09-24 Housing for highly integrated circuits Expired DE2938567C2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19792938567 DE2938567C2 (en) 1979-09-24 1979-09-24 Housing for highly integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19792938567 DE2938567C2 (en) 1979-09-24 1979-09-24 Housing for highly integrated circuits

Publications (2)

Publication Number Publication Date
DE2938567A1 DE2938567A1 (en) 1981-04-02
DE2938567C2 true DE2938567C2 (en) 1982-04-29

Family

ID=6081681

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792938567 Expired DE2938567C2 (en) 1979-09-24 1979-09-24 Housing for highly integrated circuits

Country Status (1)

Country Link
DE (1) DE2938567C2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923548A (en) * 1982-07-30 1984-02-07 Fujitsu Ltd Semiconductor device
FR2603739B1 (en) * 1986-09-05 1988-12-09 Cimsa Sintra ELECTRONIC COMPONENT PACKAGE PROVIDED WITH CONNECTION PINS COMPRISING A REMOVABLE MICROPACKAGE
FR2614134B1 (en) * 1987-04-17 1990-01-26 Cimsa Sintra METHOD FOR CONNECTING AN ELECTRONIC COMPONENT FOR TESTING AND MOUNTING IT, AND DEVICE FOR CARRYING OUT SAID METHOD
EP0346061A3 (en) * 1988-06-08 1991-04-03 Fujitsu Limited Integrated circuit device having an improved package structure
EP0351581A1 (en) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG High-density integrated circuit and method for its production
WO1990015438A1 (en) * 1989-06-08 1990-12-13 Unistructure, Inc. Beam lead and semiconductor device structure and method for fabricating integrated structure
JP3138539B2 (en) * 1992-06-30 2001-02-26 三菱電機株式会社 Semiconductor device and COB substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3292241A (en) * 1964-05-20 1966-12-20 Motorola Inc Method for connecting semiconductor devices
US3795845A (en) * 1972-12-26 1974-03-05 Ibm Semiconductor chip having connecting pads arranged in a non-orthogonal array
US3806800A (en) * 1972-12-26 1974-04-23 Ibm Method and apparatus for determining the location of electrically conductive members on a structure

Also Published As

Publication number Publication date
DE2938567A1 (en) 1981-04-02

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OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8339 Ceased/non-payment of the annual fee