DE2928618A1 - Dynamic channel distribution and data input circuit - includes computer assembly with stacking unit for instruction codes, from input line and recycle processor - Google Patents

Abstract

The circuit arrangement is for the independent a synchronous data transfer between an input/output unit and a central computer installation, several peripheral units and several other input/output and control units. The main control unit (40) is connected through an input-output channel to an integrator (41). Recycled signals are supplied to a channel writing stick unit (43). The latter is connected to a converter (44), with several parallel line outputs to several terminals (47 to 50). The input data line (43) is passed to a distributor (46) which feeds data through the input data reader in parallel with feedback signals from the terminals.

Description

Dynamic sub-channel assignment

The invention relates to a method and an arrangement for dynamic Assignment of subchannels to assign the input / output subchannels to the input / output channels can easily be changed by fields z To transfer information to and from the peripheral. Devices have the conventional Rechemamtomat medium and large One or more input / output units with a fixed number of input / output openings or channels. In addition, multiple peripheral devices can be connected to a single one Fin / output channel to be connected to the computer. One can say that that each pariphare device transmits messages via an input / output sub-kenal. From the designation of a given input / output sub-channel are in logical Way the switching means are prescribed in the divided input / output channel, dedicated to message transmission with one of the peripheral devices In the WSA Patent No. 3,251,040 by R. L. Rurkholder et al.

is an overview of the sequence of asynchronous data transfers given using a buffer for input / output, with several bit combinations and words asynchronous to the currently executed programs of the calculator without a fault in the latter can be input or output.

Although there are numerous methods of messaging several peripheral devices on a single input / output channel, this is included here an externally prescribed indexing applied via the DSA-Tatentschrift No. 3,243,783 of C. W. Ehiarrn et al. gives an overview. Allows, when using multiple peripheral devices through a single input / output channel asynchronous, buffered transfers while maintaining multiple buffer control words to undertake. Each of these peripheral devices has such a buffer control word dedicated to maintaining the transmission state and control on this one device . To identify it, the peripheral device in question transmits an indene, so that the calculator uses the appropriate buffer star word for correct control the data transfer can choose. These buffer control words are in main memory of the computer. There is therefore a room for each input / output channel intended to store as many buffer control words as needed will.

The placement of the buffer control words in main memory has the Disadvantage that a rather slow cycle is required to access such a word is. Therefore, this method has already been improved in such a way that the buffer control words in a fairly small semiconductor memory with fast, random access, namely stored in the general registers of an input / output unit. Each individual addressed location within this general register is used for Storage of the buffer control word for the one peripheral device, which the corresponding, it transmits identifying index. Under the term of an input / output sub-channel should therefore combine the individual addressable space in the general registers with the rest of the circuitry that is used for messaging with a single peripheral device is provided. With regard to the cost of the switching means one seeks to limit the total number of input / output sub-channels. Thus the Number of peripheral devices that work with an externally prescribed index, so limited that sufficient adaptability to the economic Opportunities is given.

When using this working method with an externally prescribed The index in the known systems is a fixed number Input / output sub-channels easily assigned to each input / output channel. A maximum of Aup @@ arkeit is not achieved, however, since both the total bandwidth of the transmission and the number of input / output sub-channels are also limited. The result is bai Vial notes indicate that some input / output channels have a limited range E @@@@@ en, without all available input / output. Partial sales rooms from @@@@, @@@@ and others In- / output-channels add to the @@@@ l of the available input / output-tail channels are limited, while ais within the ge @@ th bandwidth of on / off @@@@@ kenals lead. Because of this situation, the number of @@@ barable inputs / outputs can @@ Teilkandie be smaller than that actually in the arrangement of the Ansahl.

According to the invention, for the assignment of the input / output subchannels to an input / output channel. a second memory with random access, namely a so-called Konalbeschreibungsatapal applied, the for each input / output sub-channel contains an addressable place that records the information that is required for Identification of the input / output channel to which the corresponding input / output sub-channel is required is assigned. This channel writing batch will be shared in such a way that it communicates with corresponds to the desired input / output arrangement.

The Preferred Embodiment is the Channel Description Stack loaded from the system support that a general purpose computer with a stored program programmed to operate the Syatem is set and he the monitoring and control functions, as well as new settings which are normally carried out on the patient's control panel. With the mentioned loading, each input / output sub-channel is allocated to the desired input / output channel and is part of the commissioning of the system each new setting of the input / output sub-channels in the wänschten way To @@ chen.

To determine which input / output channel is to be used when a buffered transmission through a given input / output subchannel in action is to be set, the channel description stack is accessed. The operation the individual data requests from a peripheral device takes place via the circuit means of the input / output channel to which the corresponding input / output sub-channel is assigned is. Therefore, the individual data requirements do not need to be serviced Channel description stack to be accessed, but an access only needs to Start of a buffered input / output. In the preferred embodiment belongs to the channel description stack after a status display of the input / output sub-channel.

Embodiments of the invention are shown in the drawing and are explained in more detail below. FIG. 1 shows the general structure of a computer with an ESn-ZAusgabee: .rthei t; 12 and several peripheral Devices, Figure 2 the ailgematds organization of the input / output unit 12, Figure 3 a detailed circuit diagram of a channel control module 30 from the input / output unit 12, Figure 4a in detail the work; a decomposer 46 from the channel 1.e: sermodul 30, FIG. 4v shows the work of an integrator 11 from the channel control module 30, FIG Figure 4c details the functionality of a batch address selector 42 from the channel star module 30, FIG. 5 shows the detailed mode of operation of a channel description stack 40 the channel control module 30 and Figures 6a to 60 the temporal Sequence of switching processes in the canister control module 30 during start-up of the system, the input / output buffering or during a change in the MODE field of the channel description stack 43.

In the computer of FIG. 1, a central processing unit 11 leads numerous calculations aut; and attacks; storage units on cables 20a and 20b 18 and 19. The input / output unit is located between the computer and external devices 12 switched on. with the central processing unit 11 via a cable 22 control and status information exchanges and connections with via cables 21a and 21b the storage units 18 and 19 produces a system support system 17 as digital Calculator for general purposes with a stored program before and is programmed to perform the control and monitoring functions that fall to the system control and the involvement of a sedentary. This is according to the invention connected to the input / output unit 12 by a cable 27. Further cables (not shown) run between the system support system 17 and others Share the calculator. With the start-up of the system, the systematic system leads 17 a program kept within its internal memory in order to retrieve the information Via the assignment of the corresponding input / output sub-channel through the cable 27 to submit. The format and timing of this information will be later explained.

The input / output unit 12 is connected to devices via one or more cables outside of the reohening machine in connection. Such a cable together with his associated circuit within the input / output unit 12, from which the transmissions are maintained during input / output 9 is designated as input / output channel beo For the sake of clarity, only one input / output channel is considered here, although most calculators do larger number usually to the power of 2. The input / output channel corresponds to FIG. 1 a cable 23 carrying one or two sets of bits (words) in one or two able to transmit in both directions.

External devices 14 to 16 transmit to the input / output unit 12 the messages through the one-eye channel and a peripheral subsystem 13. the nested or de-nested at the transition from cable 23 to cable 24, 25 or 28 will. An externally prescribed indexing is applied to the input / output corner used the independent, asynchronous and buffered transfers between the Input / output unit 12 and the external devices 14 and 16 through the individual input / output channels with the cable 23 allows. This indexing is in U.S. Patent No. 3,243,781 by C. W. Khrmann et al. explained, but with a memory utit randomly distributed Access to the storage of individual buffer control words according to the independent, asynchronous, buffered transmissions between the input / output unit 12 and the external devices 14 to 16 is applied. As already explained, relates the term of the input / output tail channel on or

the addressable locations within this memory that contains the

the buffer control words for the transfer between the input / output unit 12 and a given external device 14, 15 or 16, as well as the others Circuit means within the input / output unit 12, which this function dedicate. It can thus be said that the external device 14 via the one input / output sub-channel, the external device 15 via a further input / output sub-channel and the external device 16 Messages with the input / output unit via a third input / output subchannel 12 exchanges, and that these three sub-channels are the only input / output kenal share with the cable 23.

The entire control and timing for the input / output unit 12 causes the channel control module 30 of Figure 2, which the input / output unit 12 in detail reproduces. He too is an element of in- / The cables 35, 36, 37 and 39 are from the relevant channel modules 31 to 34 (Figure 2) to connections 47 to 50 led to lines 63 to 60, of which the control and status information are transmitted between the control unit 40 and the causal modules 31 to 34, Ven Control lines 64 to 67 and status lines also go to connections 47 to 50 68 to 71, which according to the invention are associated with the @ analm @@ will.

The control device 40 can therefore independent, asynchronous, buffered transmissions on four input / output channels on each of the eight channel modules and a maximum of Create 32 input / output channels, albeit for reasons of clarity only one input / output channel is illustrated. Furthermore, the control unit 40 has the Possibility of externally prescribed indexing on one or more of apply to the 32 input / output channels. Have the preferred embodiment General input / output registers the ability to serve a maximum of 1,023 sub-channels; they are designed to contain buffer control words for 1,023 external devices of the transmission on the 1,023 subchannels, the 32 possible Input / output channels can be assigned.

This allocation of the filing channel concerned to the corresponding input / output channel Together with certain status information, it is contained in the channel description @@@@ gsstapeis 43, which in this case has an addressable space for each of the 1,023 Has part of channels. In this channel description stack 43, a number of the Subchannel is used as an address to access one of the 1,022 places to use the input / output channel to iment @ fify the @ar subchannel is assigned. For this erosion one of the 1,023 sub-channels, i.e. the corresponding space in the channel set page starel 43 10 bits are required, which are treated as Ausesseablts and from the stack address @ ahler 42 but a line @@ @@@@@@@ naltesen @ ei @@@@ sstapel 43 will be requested.

The cables 35, 36, 37 and 39 are from the respective channel modules 31 to 34 (Figure 2) led to connections 47 to 50 on lines 63 to 60, from which the control and status information between the control unit 40 and the Channel modules 31 to 34 are transmitted. From the connection on 47 to 50 also go Control lines 64 to 67 and status lines 68 to 71, which according to FIG Invention can be associated with the vanal modules.

The control unit 46 can therefore carry out unrelated, asynchronous, buffered transmissions on four input / output channels of the eight channel modules and consequently a maximum of Introduce 32 input / output channels, albeit for reasons or clarity only one input / output channel is illustrated. Furthermore, the control unit 40 has the Possibility of externally prescribed indexing on one or more of the 32 input / output channels. In the preferred embodiment, have general input / output registers the ability to serve a maximum of 1,023 sub-channels; So they are designed so that they have buffer control workforces for 1 03 external devices of the transmission on the 1,023 subchannels, the 32 possible Input / output channels can be assigned.

This allocation of the relevant Telkanais to the corresponding input / output channel is contained in the channel description @@ gestapeis together with certain status information 43, which in this case has an addressable space for each of the 1,023 Instructs part of channels. In this channel description stack 43, a number of the Subchannel is used as an address to access one of the 1,023 places to enable the input / output @@ enal to identify to which the @@@@ subchannel is assigned. For this addressing one of the 1,023 sub-channels, i.e. the corresponding flat in the channel coverage day 43 10 bits are required, which are as A @@@@@ ats batracatet and from the address @@ les 42 @@@@ a line @@ @@@@ @@@@ naltes @@@@ eib @@@@ stapel 43 can be transferred.

Each addressable location in the channel description stack 43 has 13 Bit positions that, together with the selenium address bits, form an assignment word can be compiled from 23 bits, the fields of which are shown in the following table are listed: Bit positions Functions O = 9 Address bits identify one of the 1,023 subchannels 10 - 12 operating status bits indicate the current status of the Subchannel on; Zeros mean idle 13 - 13 channel module number indicates one of the eight channel modules at 16-17 These bits indicate the type of Hodub, namely the Bits 100 an indexing prescribed from within, bits Ol an from the outside mandatory indexing, bits 10 a block interleaving and the bits 11 an unassigned sub-channel 18-19 These bits indicate one of the four input / output channels within a channel module at 20 This bit indicates the transmission in the case of zero of one word and, in the case of one, the transmission of two words to 21 parity bits shows odd parity of bits 13 to 22 at 22 parity bits shows odd Parity of bits 10-12 in this table, address bits 0 to 9 indicate a of the 1,023 subchannels, while bits 10, 11 and 12 specify an operating state, z. B. idling when the calculator is started. Bits 13 to 15 designate the number of one of the eight channel modules and bits 18 and 19 designate one of the four input / output channels within a channel module. So combined they give one of the 32 possible input / output channels. Bits 16 and 17 define the type of the module, which is therefore suitable for a

externally prescribed indexing or for a transfer of Blocks with nesting is designed, with the indexing in the USA patent No. 9,243,781 to Ehman @.

a, is explained in detail in the case of the inside provided indexing the transmissions take place in each input / output channel for only one sub-channel. the Interleaved block transfer is based on an industrial standard without the use of buffer control words. Therefore, the invention applies to input / output channels used in which the transmissions on input / output with an external prescribed index can be made, Bit 20 determines whether a or two words are used when the identified sub-channel with an outside prescribed index is working. Bits 21 and 22 are parity bits for an inner one Error control. The collective term module descriptor can be used for bits 13 to 22 be taken.

The key description stack 43, which is reproduced in detail in FIG receives ten address bits on line 55 for addressing. The operating status bits 10-12 enter on line 58, and the module descriptor (bits 13-22) is transmitted as a word of ten bits through a line 59.

The channel module number read from the key description stack 43 (Bits 13 to 15) is provided on a line 57. Bits 18 and 19 (of the table) run over a line 53. The operating status bits 10 to 12, which indicate the type of Module specifying bits 16 and 17, the word length specifying bit 20 and the Parity bits 21 and 22 reach a structure circuit via one line 83, 82 and 81, respectively 80, which contain these three fields from the channel description table as a word of 8 bits a line 73 to the control unit 40 transmits.

As already mentioned, according to FIG. 3, there is no channel description stack 43 over the line 55 ten address bits from the stack address selector 42. the Operating status bits 10-12 come on line 58 from a channel description selector 45, while the decomposer 46 controls the module descriptor, i.e. bits 13 to 22 via the Line 59 brings up the channel description stack 43. The the input / output channels bits 18 and 19 indicating that are from the channel description stack 43 on the line 53 fed to the integrator 41. The key module number, i.e. bits 13 to 15, arrive in the line 57 to a converter 44, while the operating status bits 10 to 12, bits 16, indicating the type of module, and 17, which indicate the length of the word Bit 20 and the parity bits 21 and 22, as already mentioned, after passing through the Aufbaauschal device 80 and the line 73 in the control unit 40 enter.

With the help of the ten address bits from the stack address selector 42, one of the 1,023 locations in the channel hash stack 43 is accessed, the Stack address selector 42 simply sifts out which inputs the address bits Should deliver. Namely, it receives input signals from the control unit 40 via a Line 54 ond from the Systemstätzanlage 17 via lines 27 and 56 with participation of the decomposer 46 provided, there are 12 wires in the line @ 4, ten of which transmit the 10 address bits, while the two remaining control wires are, via which the stack address selector 42, which is shown in detail in Figure 4c is caused, the input signals from one or the other line 54 or 56 on @@ take. From a dismantler 101, the 12 wires of the line 54 are correspondingly the address bits and control signals and on lines 104 and 103 one Selector 102 executed, which also take address bits from line 56 tooth can. This selector 102 puts the tooth address bits from the line 164 or 56 on the line 68 or suppresses the address bits if they are all ones. Depending on the control signals in line 103, one of these three becomes Choices set.

The channel description stack is used to perform three basic functions 43 accessed. The first is the activation of the system, that is, all addressable ones Places of the channel description stack 43 with the information about the assignment of the Sub-channel for input / output can be occupied by the system payment days 17. The second Function includes reading out the module descriptor from the channel descriptor stack 43, so that the control device 40 sine independent, asynchronous data transmission Use of a sub-channel can initiate, The Gritten function includes registered mail @@@ Read out the operating mode in the or from the channel description stack 43, which indicates the operating status of the sub-channel. In this preferred embodiment he follows. thus a specification of the operating state type in the channel description tag.

The system facility 17 overlies with the input / output information from 23 bits about the allocation of a sub-channel to the decomposer 46, which they in the Line 27 receives and converts a word of three bits and two words of ten bits disassembled. According to FIG. 4a, address bits 0 to 9 are generated by decomposer 46 line 56, the module descriptor, i.e. bits 13 to 22, on the line 59 and bits 10 to 8 12 indicating the operating status are placed on line 72. The system support system 17 brought only zeros as operating status bits 10 to 12. As already in connection mentioned with the figure 3, the address bits 0 to 9 get into the stack address selector 42, bits 10 to 12 in the channel description selector 4r and the module descriptor, namely bits 13 to 22 in the channel description stack 43.

In Figure 6 @ everything is through when the system is started the system support system 17 applied signals over time. 2 @@ srst are @@ ei assignment words consisting of 23 bits are shown on line 27, the one from which Display information about the assignment of two of the 1,023 possible sub-channels. The other time plots are similar. The operating status bits 10 to 12 and the module descriptor (bits 13-22) pass through on line 27 solid lines, while the address bits 0 to 9 on line 27 during a shorter, marked by dashed line pieces Time to appear. Furthermore, the transmission of the address bits 0 to 9 is in the line 56, the operating status bits 10 to 12 in this line 72 wid of the module descriptor (Bits -t3 to 22) on line 59 over time.

As already mentioned, the batch address selector 42 selects in dependence from the binary state of the two wires on line 103, either those on the line 54 coming from the control unit 40 or the address bits on the line 56 address bits supplied by the decomposer 46 so that they can be used when the System from selector 102 through line 55 to channel description stack 43. This choice is plotted against time in FIG. 6a on line 54. To the Selection of the one addressable location in the channel description stack 43 for which the system support system 17 supplied the information about the influx of the sub-channel therefore, each value of the address bits becomes the channel description stack over line 55 43 Upper medium. The length of time for the address bits to be transmitted on the line 27 is chosen to be shorter than that for the rest of the assignment information to ensure that during access to one place of the channel description stack 43 in the the latter already have the drive status bits and the module descriptor available.

The operating status bits are output by the decomposer 46 in the line 72 to the channel description selector 45, which is similar to selector 102, but in five places namely via lines 68 to 72 each receives three bits and emits three bits via the line 58, while three more bits via a control line 74 come from the control unit 40. Depending on the binary state of the three The channel description selector 45 looks for one of the five wires of the control line 74 Status lines 68 to 72 for transmitting three bits on line 58. In the figure, however, there is the choice of operation made via the control line 74 State illustrated, the Eits of the decomposer 46 via line 72 to the Line 58 can be brought as in the dialing process by the batch address selector 42 The signals in the control line 74 are used via the line 54 during the start-up of the entire system of definition, the operating state, its bits via the Line 72 come up A consideration of Figure 5 in conjunction with the figure 6a illustrates the initiation of the system, namely the loading of the addressable locations of the channel description stack 43 with the operating status bits and the module descriptor. Another function is reading out the module descriptor from the channel description stack 43, so that the control unit 40 utilizing a Initiate an independent, synchronous, buffered transmission, as soon as it receives the associated command, either directly from the central Computing unit 11 via line 22 or from the spoke unit 18 or 19 via the line 21 is output> as is common practice. A significant one The factor here is that the command does not prescribe a special input / output channel needs, but only specifies a sub-channel. To determine which input / output channel the sub-channel prescribed by the command is assigned, the control unit 40 access the channel description stack 43, where it is the number of the sub-channel from the command and takes them in the form of the 10 address bits on line 54 the stack address selector 42 supplies. At the same time, the control unit 40 is the binary State of the two control wires in line 54 adjusted so that the Selector 102 receives the address bits from line 104 over line 55 to the channel control stack 43 passes through to access the corresponding addressable space of which Content is read out.

The bits indicating the input / output channel within a channel module 18 and 19 are on the line 53 to the integrator 41 indicating the module number Bits 13 to 15 on line 57 to converter 44 and operating status bits 10 to 12, bits 16 that indicate the type of module, and 17 that indicate the word length Bit 20 and parity bits 21 and 22 each via a line 83, 82 or 81 of the structural circuit 80 forwarded. This construction circuit 80 sets the previously designated fields into one 8-bit word that appears on line 73. The timing of such a readout process on the channel description stack 43 is with respect to all essential signals are made clear in FIG. 6b To a The control unit must initiate independent, asynchronous, buffered transmission designate the correct channel module. Therefore, the control unit 40 prepares an introductory one Command word of 25 bits, it transmits it like a wire radio over the Leituny 38 to all channel modules, ensuring that the correct channel module is teaching is now to become active. Receives external channel writing envelope 43 the control unit receives a value from 3 @@@ s, for which the operating status nits, the type of module and the length of the F @ its and parity @@ ts ge @@@@ en This value from eight rits becomes @@@ Kar @@@@@@ ngsetapel 43 for the generation a lower and opera Ferfet @@@@@@ it uses, the compilation itself is known and also the respective four input / output Kanaid the Kanaimoduls for the input / output. The integrator @@ receives from the key description stack 43 this information and @@@@@ ätalich the obflgen 23 pits of the introductory command value from the control unit 40 via the lines 53 and 52 and integrates these two Words, so that the initial reference value on the line 51 in the control unit 40 got. According to FIG. 4b, the integrator @ 1 on line 52 takes the 23 bits of the lower and upper reference word part and on the line 53 the previously mentioned ge Specification from 2 bits. After the integration comes the fully introductory Command word with 25 bits on the line @@ to the control unit 40, which it over the cable 38 supplies all channel modules. Figure 8b gives an overview of the time Sequences for generating the introductory command word.

Un to start an independent, asynchronous, buffered To complete transmission, the correct channel modal must be informed an introductory command word is just being transmitted in cable 38, for this purpose the Module number (Bitgs 13 to 15) from the channel description stack 43 as a word of 3 bits transmitted on line 57 to U @@ etzer 44, which then sends a signal to a which sends out eight control lines, of which only control lines 64 to 67 Figure 3) are shown to the one channel module corresponding to the introductory command word on cable 38 to teach.

The control lines 64 to 67 actually end at the terminals 47 to 50, where they are used to transmit the control and status signals to the Channel modules are combined with lines 60 to 63 via cables 35, 36, 37 and 39 are. In FIG. 6b, the signals are plotted against time which are correct Identify channel module so that it is as the introductory command word transmitted in cable 38 appeals to.

The third function to be discussed in accordance with the invention is that of registered mail or reading of the operating status bits in or from the channel writing stack 43. It is only used in terms of completeness as an indication of the state of a Partial channel be written. The writing is done by transmitting the address bits from control device 40 via line 54 to channel address selector 42, the control wires of line 54 are energized to enable selector 102 to get the address bits off the line 104 passes over the line 55 to the channel description stack 43, on its addressable space is accessed according to the address bits. Figure 6c time the timing of the signals to achieve this access also transmitted the control device 40 three bits via the line 74 to the channel description selector 45, to adjust this. One of the status lines is used to change the operating status 68 - 71 selected. The indication of the operating status is provided by the relevant channel module via the corresponding control and status cable 35, 36, 37 or 39 and the Connections 47 to 50 to the channel description selector 45 in the form of three bits in the Line 68, 69, 70 or 71 transmitted based on the three bits in the three Wires of the line 74 the selected indication of the operating state in the line 58 enters the channel description stack 43 so that it is deposited in the place which is addressed via line 55 from batch address selector 42 The readout the operating state was already used as part of the generation of the introductory command word explained. In FIG. 6c, the signals are plotted against the time required for storage belong to a new specification of the operating status.

In summary, sub-channels are the input / output channels using a random access memory, namely a channel description stack assured of a mutual dependency between the sub-channels and the input / output channel causes. to which they are assigned. Although the channel description stack on different Way can be loaded, this is preferably a special system, namely uses a system support system that also takes on the tasks that normally fall to the control panel, e.g. B. a reorganization of the system, an interface function for the operator of the system, an occasional regeneration, etc.

L e r s e i t e

Claims (10)

PATENT CLAIMS 9 circuit for independent asynchronous information transmission between the input / output unit of a central ray system and several peripheral ones Devices via several input / output channels with one control device, from which the one external device outgoing sub-channel can be assigned to one of the input / output channels, d a d u r c h g e k e n n n z e i c h n e t that in the input / output unit (12) a Memory (43) is arranged with random access, its addressable Places, each of which is assigned a sub-channel, with one to identify the Input / output channel (23) are occupied. 2) Circuit according to claim l, d a d u r c h g e k e n n -z e i c h n e t that the memory (43) has a stack address selector (42) either can be addressed by a system support system (17) or by the control unit (40). 3) Circuit according to claim 2, d a d u r c h g e k e n nz e e .i c i n e t that between the stack address selector (42) and the system support system (7) or the control unit (40) a zenleger (46 or 10 @) is connected, which separates the address bits from other bits. 4) Circuit according to claim 3, d a d u r c h g e k e n nz e i c hn e t that the other units from the Syatemstützantage (17) about the Zerloger (16) can be written into the memory (43). 5) Circuit according to claim 4, d a d u r c h g e k e n nn e i c h n e t that weitore, indicating the nature of the Hetrichszustrandes of partial cans Bits from decomposer (46) via a channel description selector (45) can be written into the memory (43). 6) Circuit according to claims 2 and 5, d a d u r c h g e -k e n n z e i c h n e t that the bits indicating the type of operating status are used of the control device (40) via the channel description selector (45) according to this Setting effected by a channel module (31-34) can be written into the memory (43) are. 7) Circuit according to claim 2, d a d u r c h g e k e n n -z e i c h n e t that a channel module (31 - 34) indicating bits via a converter (44) to inform one of the channel modules (31 - 34) can be read from the memory (43) are. 8) Circuit according to claim 2, d a d u r c h g e k e n n -z e i c h n e t that bits from memory indicating one (23) of the input / output channels (43) can be read out to an integrator (41), which they initiate with bits of an Command value. 9) circuit according to claim 2 and 5 or 6, d a d u r c h g e k It is noted that the bits and further bits can be read out from the memory (43) to a structural circuit (80), which they pass on to the control unit (40) after they have been assembled. 10) Circuit according to claims 1 and 6, d a d u r c h g ek e n It is not noted that the input / output unit (12) has several channel modules (31 hi @ 34) and a channel control module (30), which with the neutral computing situation (11), the system support system (17) and further storage units (18, 19) that are the central Ruchenantage (11) zuge @@ et.