DE2902872A1 - PROCEDURE AND EQUIPMENT FOR THE AUTOMATIC TUNING OF A MULTI-CHANNEL RADIO RECEIVER - Google Patents

Description

Nissan TER meer · möller ■ steinmeister PG23-78194

DESCRIPTION

The invention relates to a method according to the preamble of claim 1 and a device for performing the Procedure. In particular, the invention relates to the automatic channel selection in radio receivers, i.e., to a method and apparatus for automatically tuning such receivers to frequencies of particular broadcasting stations in accordance with a program sequence.

Multi-channel radio receivers are known and have an automatic switching device for selecting tuning elements through which reception is possible on a large number of different channels. The channels can through an automatic controller can be selected which optionally includes various tuned circuitry in the receiver connects. For systems with such an automatic channel selection control can store a large number of desired channels at specific times in a memory unit to automatically connect the various tuned circuits in accordance with a sequence, in which the stored channel data are programmed.

In some cases, to enter additional channel data, it is desirable to reprogram the sequence and possibly beforehand delete saved channel data. There would be a possibility of reprogramming the stored data sequence in erasing all stored data and adding a set of new data in a desired new sequence by means of a manually operated switch.

The need for manual operation for such reprogramming is comparatively time-consuming

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and boring affair, especially with radio receivers is perceived as a nuisance for vehicles that change their regular location more frequently.

The invention is based on the object of a method and a device for automatic reception channel tuning specify for radio receivers through which the stored-programmed Station selection can be made easier, especially when changing channels.

The solution according to the invention is specified in terms of the method in claim 1. Claim 9 contains the device required to implement the invention in terms of circuitry. Advantageous further developments of the The inventive concept are characterized in subclaims.

The method according to the invention and the method for carrying it out suitable facility provides for the use of a large number of storage facilities for storing time and channel data. These data are called up one after the other and compared with new data for verification, whether the latter are later than the stored data with regard to certain points in time. The data accessed will be then, if necessary, to the next storage device transferred to empty the former storage device so that the new data can be stored. In some In some cases it is also desirable to delete a previously stored data record and replace it with new data.

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Nissan TER MEEP MÜLLER STEINMEISTER PG23-78194

Specifically, the stored data is called up cyclically from the memory and compared with the time of day, to determine a match between these dates and activate tuned circuitry of a selected channel of the broadcast receiver.

With an advantageous development of the inventive concept, the successive display is each stored Record possible on a display, with the operator pressing a delete command switch during the

9 -

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Nissan

TER MEER MÜLLER STEINMEISTER PG23-78194

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Time can operate while the unwanted data is displayed and the stored data to each neighboring Storage devices are transferred, so that the relatives resembled the last in the program sequence next storage device becomes free. The invention can also be used with a microcomputer or microprocessors realize.

Further features, advantages and details of the invention emerge from the following description of a preferred embodiment shown in the drawing. It shows:

FIG. 1 is a schematic block diagram according to FIG

Invention;

Fig. 2 is a timing diagram of various generated Follow-up control pulses when the system is in

Data program operation is in progress;

3 shows a timing diagram of various generated Sequence control pulses when the system is in display mode; and Fig. 4 is a timing diagram of the various

Control pulses generated in a data erase mode.

The automatic channel selector of the invention of a multi-frequency radio receiver is shown schematically in Fig. 1 and generally has a file input device 11, by means of which data corresponding to the channel number and the time are entered encrypted into an input shift register 12, a data storage unit 6 with five storage devices for the purpose of illustration or positions 6 to 6 ^, each of which serves as a memory for the selected channel number and the time-representative data, and a sequence circuit 17.

A shift register 13 is used to transfer time data from the memory unit 6 as a function of an addressing signal provided by the sequencer 17 to connect them with the

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Input timing data from the resistor 12 in a comparator 14 for the purpose of comparing the previously stored data with fresh data in the order of the scheduled Radio programs are changed. Shift registers 3 and 8 are provided in order to sequentially ·! Channel and time data via a data bus 7 from the memory 6 as a function of address signals from the circuit 17. the Time data in the register 3 are compared in the comparator 4 with the output of a time counter 5 to obtain an output signal to be delivered when the saved time is reached. A decoder 2 is connected to the output of the comparator 4, in order to decode the channel data from the shift register 3 as a function of the output signal of the comparator 4 into a decimal digit, corresponding to the selection mechanism 1B of the radio receiver of a conventional one Receiver in 1. The latter comprises a power control unit 1C which automatically provides a voltage for the receiver as a function of an output signal from the decoder 2.

The data input to the shift register 8 is applied to a display 10 through a driver circuit 9 to sequentially the programmed channel number and the time depending on the presence of a display signal DSP from the sequential circuit 17 to display.

An up counter 16 is for information storage what the Number of storage locations of the memory 6 concerned, provided for storing additional radio programs are available. This information is also sent via the data bus 7 to the register 8 and then to the display 10 transmitted.

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NISSAN TER MEER - MÜLLER STEINMEISTER PG23-78194 "

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The input data entered into the shift register 12 have been, are to a selected memory location depending on the operation by hand of a Data input switch 18 transmitted. The operation of the Switch 18 resets the flip-flop so that its output has a logic O, which is generated by an inverter 22 with a shift register 13 for receiving data from a external source is connected. At the same time, the flip-flop 19 assumes a logical 1, through which the sequential circuit can switch their control mode from display mode to programming mode. In the latter operation the circuit 17 generates numerous signals from its signal generators 17 ^ to 17c »as shown in FIG. In response to the program input signal PGM (FIG. 2a) from the flip-flop 19, the circuit 17 outputs an address signal CNT (Fig. 2b) and a read command signal R ,, (Fig. 2h) to the Aufabzähler 16 from, so that this is its stored data outputs to a comparator 20, in which the input data are compared with a counter "zero", which the -Stand Indicates the absence of available memory cells. When all storage locations of the memory 6 are filled, is the content of the counter 16 0 and a coincidence is produced in the comparator 20, which is a logical 1 at the output of the comparator 20, which is fed via an OR gate 21 in order to reset the flip-flop 19, so that the circuit 17 go into display mode can.

If at least one available memory location is present in the memory unit 6, for example the memory sections O _x to 6 ^ are filled with program data in the order of the stored program, the memory location 6 is available for the additional input data. The consequence

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TER MEER · MÜLLER ■ STEINMEISTER PG23-78194 ·

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Circuit 17 generates an address signal 4- ,, (Pig. 2f) and a read command signal R ^ j ura to transfer the data stored in the memory location 6 ^ to the shift register 13, which is ready to be received, as has been described above. Then a comparison command C. (CMP; Fig. 20) is issued by the circuit 17 to an AND gate 23 which, as another input signal, receives a signal from the output of the comparator "V \ cnip- \ ir, in which the now in the Shift register 12 and 13 stored data are checked against each other to determine whether the new time data is earlier than the previous data stored in the memory location 6 ^. If the new program is later than the previously stored program, the comparator 14 produces a logic 1 at its output and activates the AND gate 23 to trigger the flip-flop 15 through the OR gate 2 ^L V so that it is a logic 1 accepts. As a result, the shift register 12 can transfer its data to the memory location b _r as a function of a write instruction W- (FIG. 2i) and an address signal 5 ^ (FIG. 2g) which is provided by the circuit 17. Conversely, if the new program is earlier than the previously stored program, the flip-flop 15 will remain reset and, depending on the write instruction W- and the address signal 5 ^, the data now stored in the register 13 are transferred to the memory location 6 ^, the above in the memory location 6 ^, data stored in the location G ₁ - are transmitted. Then the read command R ₃ and the address data 3 / i are generated in order to transfer the data stored in the memory location S ₇ to the shift register 13 for comparison with the content of the register 12 as a function of a comparison command C-. If the latter is earlier than the former, the flip-flop 15 remains reset and the content of the register 15

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stored program corresponds to) v / ground in the memory locations 6 ^ depending on a write instruction W ~ and an address signal ^ o, whereupon the data in the memory location 6- to the register 15 depending on a read command R ^ and an address signal 2 ^ will. As long as the new program stored in the shift register 12 is earlier than the data successively delivered to the shift register 13, the bit drive described above will be repeated until the comparison result in the comparator 14 indicates that the new program is later than the stored in the shift register 13. Assuming that the new program is later than the program in memory location 6p, which has now been entered into register 13, flip-flop I5 is triggered in response to a comparison instruction C so that it has a logical 1 at the output , and the content of the input shift register 12 is delivered to the memory location 6 ^ in response to a write instruction W and an address signal 3g. If this occurs, an AND gate 25 outputs a coincidence output signal via an OR gate 21 to the flip-flop 19 in order to reset it, the program command signal PGM being terminated (as shown at 30 in FIG. 2a). If the new program is earlier than the program stored in memory location 60, the latter is transferred to memory slot G ₇ , and the circuit continues with the generation of an address signal Λ * and a read command R ₁ to transfer the data from the memory location 6 * to the register 13 to be compared with the data in the register 12 in response to a signal C ^, and if the comparison shows that the new program is earlier than the now transferred program, the latter is in the Memory location 62 in response to an address signal 2p and a write instruction W ^, transferred, whereupon the

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ITISSAW

TER MEER MÜLLER STEINMEISTER PG23-78194-

Circuit 17 generates a base address signal B / A. This signal is applied to the set input of the flip-flop 15 through the OR gate 2Ά- in order to transfer the data from the register 12 to the memory location 6 ^ in response to a second address signal 1o and a write instruction W ₁ -; in this case the program instruction PGM is terminated at 51.

Depending on the output signal of the AND gate 25, which, as described above, is always generated when the input program data is in a suitable memory location are stored, one bit is added in the up counter 16 counted below to reduce the number of available memory locations shown on display 10.

When the same program is entered in register 12 by mistake it should be noted that a coincidence output is generated by the comparator 14 and sent to an indicator lamp 26 is issued to indicate an alert for such a condition. Likewise, the input of the Flip-flops 19 reset via OR gate 21 to terminate signal PGM.

During the display operation, the sequence circuit 17 generates command signals as shown in FIG. As shown, circuit 17 generates address signals including CNT (1 to 5) too. predetermined, repeating time intervals, each signal following a preceding signal. The read command signal R is generated synchronously with each address signal, and the write command signal remains in its 0 state during the display operation, whereas the display signal DSP and a radio input command RAD have a logic 1. It should be well understood that the data stored in each of the memory locations 6 ^ to 6, - is in

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Depending on each read command R can be read out and transferred to registers 3 and 8. The time data stored in the register 3 are compared with the primeval time data from the counter 5 » ^{v /} i ^e described above, while the data stored in the register 3 are output to the display 10 via the driver circuit 9. Therefore, program data is displayed at the predetermined, cyclically repeating time interval, which is typically 2-3 seconds.

It is often desirable that one or more of the programs which have already been stored in the memory unit 6, deleted for the purpose of being replaced by a new one Program to be replaced. The deletion is carried out by an delete command switch 27 causes that triggers a flip-flop 28, so that it has a logic 1 at its output, which is applied to the counter input of the counter 16 on the one hand is, so that is counted up by one bit to the number of available additionally stored in the memory unit 6 To increase programs, on the other hand, is applied to the sequential circuit 17. The extinguishing operation arises synchronous with the data display, d. H. the switch 27 is operated when the undesired program data is on the display 10 can be displayed during display operation.

^{Depending on:} in: / ä; -; koit von dom Lüschbofehlciijrial CANCEL, the sequence circuit I7 is switched from the display mode to a delete mode, during which the command sequence is shown in Fig. 4-, the timing diagram according to Fig. 4-corresponds to the state in which the program data in memory location 60 is erased during the time it is being displayed. The erase command signal (Fig. 4a) causes the sequential circuit 17 to generate a second address signal 2 ^ (Fig. 4d) as a function of the trailing edge of the address

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impulses 3, as well as a writing letter W ,, generated. Since an address signal ο * was generated in synchronism with a read command pulse R ^ before the erasure signal was _{generated, the program stored in position 6 7 has} been transferred to shift register 13. Therefore, the write instruction ^] ; L · causes the now transferred data of the register 13 to be transferred again to the memory location 6 ^ as a function of the address pulse 2p, so that the undesired "data are automatically replaced by the data previously in On the condition that the storage locations 64. and 6c are filled with program data, the data in the location 6 ^ are grounded as a function of an address pulse 4v and a read command pulse R ^ read out and sent to the memory location 6 * depending on an address pulse 3o ^{UI1 (} A of a write instruction W ^. In the same way, the content of the memory location 6- is read out depending on a read instruction R ^ and an address pulse 5- |, and then to the memory location 6 ^ output as a function of a write _{instruction W 7} and an address pulse ^ A clear signal CLR (Fig. 4j) is generated by the circuit 17 as a function of the address instruction 4-p is generated and applied to the shift register 13 in order to erase its stored data and to write all zeros into it. This memory content is then transferred to the memory location 6 _r as a function of a write instruction W ^ and an address instruction 5p.

Depending on the fact that the address pulse ^ and the write pulse W ^ are present at the same time, an AND gate 29 is activated in order to generate a reset pulse for the erase command flip-flop 28, the erase command signal being terminated at at. After the erasure, the circuit I7 automatically switches over to the normal display mode, so that the address signals and the read instructions to the periodic

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NISSAN TER MEER - MÜLLER STEINMEISTER PG23-781 ° A

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Time intervals of the display operation are generated.

Thus, briefly summarized by the invention, time and channel data are stored in each of a plurality of storage devices stored, which are sequentially arranged in order of the times at which the selected Programs are broadcast. The stored data becomes periodic time intervals for comparison with time data indicating the time of day to effect a comparison between the data. Dependent on from the comparison, a tuned circuit of a radio receiver is activated. The data is with new data that is additionally entered into the system is compared to all stored data in a new one To rearrange program sequence. The retrieved data is also displayed on a display, and in synchronism with the At display intervals, the operator can input a data erase command signal, with the stored data in each case be transferred to neighboring storage facilities in order to to free a memory device for entering new data.

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Claims (11)

PATENT LAWYERS 291) 2872 TER MEER-MÜLLER-STEINMEISTER Professional Representatives before the European Patent Office Mandataires agr £ e3 pres! 'Office european des brevets Dipl.-Chem. Dr. N. ter Meer Dipl -Ing. H. Steinmeister ~~ ng, F. E, Müller D-8OOO MUNICH 22 D-48OO BIELEFELD 1 PG23-78194 January 25, 1979 NISSAN MOTOR COMPANY, LIMITED No. 2, Takara-cho, Kanagawa-ku, Yokohama City, Japan Method and device for the automatic tuning of a multichannel radio receiver Priority: January 26, 1978, Japan, No. 53-7954 PATENT CLAIMS 1 J method for the automatic tuning of a multi-channel radio receiver to a specific channel in accordance with a program sequence using a plurality of sequentially callable storage devices in which time and channel representative data (time and channel data) are stored corresponding to a respectively selected channel, 909831/07 ^ 9 ' _0Bi G! NAL INSPECTED Nissan TER MEER MÜLLER STEINMEISTER PG23-78194 characterized by the following process steps: (a) loading time and channel data into a first shift register; (b) sequentially comparing the time data of the first shift register with the time data in each Memory means for producing an output signal when the data of each memory means has a channel represent which is later than the channel data stored in the first shift register; (c) transmission of the data from one of the storage devices in a subsequent storage device depending on the output signal to the data-emitting Empty storage device; (d) Transferring the data of the first shift register in the empty storage device; (e) sequentially transferring the data from each the storage means in a second shift register; (f) successively comparing the time data of the second shift register with the time of day to match and (g) Conversion of the channel data of the second shift register into a corresponding channel selection signal for the radio receiver depending on the occurrence of the coincidence or match signal. 2. The method according to claim 1, characterized by successive display of the in each of the storage devices stored data. 3. The method according to claim 1 or 2, characterized by 909831/0748 PG25-7S194 TER MEER · MÖLLER · STEINMEISTER - Determination of the number of storage facilities that are empty, and - Display of this number. 4-. Method according to one of claims 2 or 3, marked is characterized by - Transmission of one or more of the in the storage devices stored) data to the next storage device depending on an erase command signal, when the data to be deleted is displayed v / earth, and - Loading of logical zeros into the memory device for the representation of data not present therein. 5. The method according to claim 4, characterized by - Transfer of one or more of the data to a third shift register before transfer to the next one Storage facilities. 6. The method according to claim 4, characterized that the erase command signal is dependent on the loading of the logical zeros into the memory device is terminated. 7. The method according to claim 1, characterized , - That the data stored in the storage devices are successively transferred to a third shift register will, - That determines a match between the data stored in the first and third shift registers will and 909831/0748 NISSAN TER MEER MÜLLER STEINMEISTER PG23-78194 - that this match is indicated. 8. The method according to claim 1, characterized , - That in process step (b) successively transfer the data in the storage devices to a third shift register, - that a match is found between the data stored in the first and third shift registers will, - that this match is displayed and - That the transmission is made ineffective depending on the occurrence of the match. 9 · Facility for automatic voting of a more ~ channel radio receiver on a selected channel, marked by - first and third shift registers (12, 3 »13); - an input device (11) for inputting time and program data into the first shift register; - A memory unit (6) with a plurality of memory locations (6 ^ -6, -) for the respective storage of different data Transmitter channels; - Control devices (7) for successive transfer of the data from the storage locations to the third Shift register (13); - A first comparator (14) for successively comparing the data between the first and third shift registers to produce an output signal when the data in the third shift register represent a channel later than the channel represented by the data in the first shift register lies; 909831/0748 TER MEER · MÜLLER · STEINMEISTER PG23-78194 - wherein the control device successively the data of the third shift register in the memory locations transmits, which are each arranged adjacent to the memory locations in which the data before the transmission until the occurrence of the output signal of the first comparator are stored to to empty one of the memory locations, and wherein the data of the first shift register to the emptied Transfer memory locations and successively, cyclically repeating the data in the memory locations transferred to the second shift register; - A second comparator (4) for generating an output signal, when the data of the second shift register corresponds to the time data indicating the time of day; and - Means (2) for translating the program data stored in the second shift register into a Channel selection signal for the radio receiver. 10. Device according to claim 9 »characterized by devices (10) for successive View the data stored in the memory locations. 11. A device according to claim 9 ₅ characterized by an up counter (16) for storing the Number of such memory locations of the memory unit representing data which are empty, and wherein the display device record the data stored in the incremental counter to display the number of empty memory locations can. 12 »A device according to claim 10, characterized by devices (27-28) for generating 909831/0748 NISSAN TER MEER · MÜLLER ■ STEINMEISTER a data erase command signal for erasing the data in the memory locations that are displayed, the control device in the presence of the data erase command signal operated devices for successive transmission of the data in the memory locations to neighboring Storage locations and for entering logical zeros in one of the storage locations to the Represent absence of data in it. 909831/07