DE2902488C2 - - Google Patents

Description

The invention relates to an adder for dual numbers according to the generic term of claim 1.

As is well known, the least significant dual digit in the tens system corresponds to the number 0 and the number 1, the next level of importance is given by the numbers 2 and 3, the next level of importance by the numbers 4, 5, 6 and 7 etc. In general, the i- th valency level includes the numbers in the range 2 ^{i -1} to (2 ⁱ -1), where i can take any integer value.

The known electronic adding circuits are designed in such a way that the linkage begins with the lowest value level, that is to say with i = 1, and progresses progressively to ever higher value levels. Such adder circuits are e.g. B. in the book by Ulrich "Fundamentals of digital electronics and digital computing" (1975), pp 99-107, described. The terms "half adder" and "full adder" are also explained there.

From IBM Technical Disclosure Bulletin, Volume 17, No. 1, June 1974, pp. 118 to 119 an arrangement is known, which by the Use of half and full adders and their sensible arrangement short delay times for the transfers carried out allowed.

The invention has for its object an adder for Specify dual numbers, which is particularly simple constructive Set up the arithmetic operation to be performed especially can run quickly.

As was recognized according to the invention, it is possible to drastically reduce the time required for the addition by designing the computing system in such a way that the addition begins with the most significant bits of the two summands A and B and then in the direction of increasingly less significant bits, so dual digits progresses.

The task is therefore according to the invention by Features of the characterizing part of claim 1 solved.

The adder according to the invention has the advantage that it through the sole use of half adders and their reasonable arrangement represents a simple constructive structure and the arithmetic operation to be performed is essential can run faster than is known from the prior art.

Embodiments of the invention are characterized in the subclaims.  

The basis of an adder according to the invention The calculation method works according to the following points:

• - The addition begins at the most significant digit
• - Each bit B _i of the to be added addend B is added individually to the corresponding locations in the dual-bit value A _i of the other addend A
• - After each individual bit addition there is a subtotal formed, which is the starting point for the further in Dual digit value reduced by 1 single bit addition represents.

So you have the two summands

A = A _m , A _{m - 1,.} . . A _{n + 1} , A _n , A _{n - 1,.} . . A ₂, A ₁

and

B = B _n , B _{n - 1,.} . . B ₂, B ₁

With
m ≧ n and A _m ≠ 0, B _n ≠ 0, then the protruding bits A _m to A _{n - 1} present in the case of m < n are _{first adopted} in the result, that is to say they are each additively linked with a zero. Then there is the first link (A _n + B _n ) , which gives a result different from A _i . This result is either a "0" or a "1" or "2 1" = "10". In the first two cases the "result" obtained so far, namely the combination of the protruding bits A _m ,. . . A _{n + 1} unchanged. In the latter case, however, the existing combination of the protruding bits must be changed by inversion of the individual elements up to and including the first "0" following in the direction of increasing dual position value i . The same applies to the additive combination of the two following bits A _{n -1} and B _{n -1} , as for all subsequent combinations. If A _i and / or B _i is "0", the link result (A _i + B _i ) is B _i and / or A _i .

The following generally applies to the addition of the two i- valued bits A _i and B _i :

Is the logic operation result (A _i + B _i) one digit, then no correction of the already existing link results (A _{i + 1} + B _{i + 1),} (A _{i + 2} + B _{i + 2),} etc .. If the linking result ( A _i + B _i ), on the other hand, in two digits, the link results already obtained in their order must be inverted up to and including the first "0", which follows the last link result obtained (A _i + B _i ) in the sense of increasing dual-place value i , to ensure the necessary transfer.

The implementation of a device according to the invention is possible in various ways, three of which are now presented with reference to FIGS. 1 to 3. First, the preferred embodiment according to FIG. 1 is discussed.

The embodiment of the invention shown in FIG. 1 is particularly suitable if particularly short computing times are aimed for.

In the adder circuit shown in FIG. 1, the circuit forming the logic logic consists only of AND gates and exclusive OR gates as well as OR gates. An AND gate is combined with an exclusive OR gate to form a half adder.

The following points are essential for the adding circuit or logic logic shown in FIG. 1:

• 1. The system is designed for m dual digits, so that for the two most significant dual digits A _i and B _i of summands addable with the system i ist m .
• 2. The two inputs A _i * and B _i * of the combination logic to be acted upon by the i th dual position A _i and B _{i of} the two summands A and B each control a number i of half adders, where i is the valence level of the relevant one Input pair assigned dual digits A _i and B _i . Each half adder consists of an AND gate U _ir and an exclusive OR gate E _ir , the first index i indicating the affiliation of the relevant half adder to the respective controlling input pair A _i *, B _i * and the second index "r" runs from 1 to i and indicates the respective number of the relevant half adder among the i half adders assigned to the output pair mentioned.
• This corresponds to that the least significant pair of bits A and B ₁ ₁ to be acted upon input pair A ₁ *, B * ₁ of the combinatorial logic only the half adder U ₁₁, E ₁₁ and z. B. that of the fourth dual-stage valency, ie the input pair A ₄ *, B ₄ * assigned to the value i = 4, four such half adders, namely the half adders U ₄₁, E ₄₁; U ₄₂, E ₄₂; U ₄₃, E ₄₃; U ₄₄, E ₄₄, are assigned.
• 3. The assignment of the i half adders belonging to the relevant input pair A _i *, B _i * is given in that the two inputs of the AND gate U _{i 1} and the exclusive OR gate E _{i 1 of} the first of these half adders U _{i 1} , E _{i 1 are} each connected to one of the two inputs A _i *, B _i * and that - with the exception of the last of these half adders, namely the half adder U _ii , E _ii - the output of the exclusive OR gate E _ir des Half adder in question both to an input of the exclusive OR gate E _{i, (r + 1)} and to an input of the AND gate U _{i, (r + 1) of} the next of these assigned to the input pair A _i *, B _i * Half adder E _{i, (r + 1)} , U _{i, (r + 1)} .
• 4. The exception mentioned under number 3 is due to the fact that the exclusive OR gate E _{ii of} the i- th half adder E _ii , U _ii controlled by the input pair A _i *, B _i * no longer controls a further half adder but to control a circuit part to be acted upon by the i- th dual digit (A + B) _{i of} the sum (A + B) , e.g. B. a memory is used. The signal output of the exclusive-OR gate E _{ii of} the last half-adder E _ii , U _ii assigned to the input pair A _i *, B _i * thus forms the output AU _{i of} the logic logic which supplies the i- th dual position of the result.
• 5. The output of the individual AND gates U _{ir of} the half adders U _ir , E _ir provided in the logic logic is - only with the exception of the cases i = m - at the input of the according to number 4 by that of the dual place value (i + 1) assigned input pair A * _{(i + 1)} , B * _{(i + 1)} applied half adder U _{(i + 1), r} , E _{(i + 1), r} , which is not controlled by the control of the input pair A * _{(i + 1)} , B * _{(i + 1)} mediating exclusive OR gate E _{(i + 1), (r - 1) is} applied.
• 6. In the case of i = m stand for an interconnection in accordance with Clause 5, no half-adder longer available, as the most significant of the dual point _m i = m associated input pair A _m, B is the last input pair. However, to round off the circuit here, too, a number m of OR gates are provided, each having two inputs. The connection of these OR gates O _{r, (r + 1)} is made such that the output of the individual AND gates U _{m, (r + 1)} each have one input of the relevant OR gate O _{r, (r + 1) is} connected, while the second input of the OR gate O _{r, (r + 1)} in the case r = 1 by the output of the AND gate U _{m 2} and in the case r <1 by the output of the OR gate O _{(r - 1), r is} controlled. The output AU _{(m + 1)} , which is assigned to the (m + 1) -valented binary position of the result, is here by the signal output of the last of these OR gates, namely the OR gate O _{(m - 1), m} , given that, on the one hand, according to the circuit diagram just given, there is one input at the output of the AND gate U _mm and the other input at the output of the OR gate O _{(m - 2), (m - 1)} .

The logic of an arrangement according to the invention shown in FIG. 1 is designed for the case m = 5 and therefore has the 1-5 apparent construction, a total of 1 + 2 + 3 + 4 + 5 = 15 half adders and thus 15 exclusive OR gates and 15 AND gates, as well as 4 OR gates. In the general case, one has (m + 1) · m / 2 half adders and (m - 1) OR gates in a corresponding manner. As can be seen from FIG. 1, the circuit shown for summands A and B , each with 5 bits, requires a total of 10 gate delays.

In contrast, a conventional circuit for the addition of 5-bit words requires a total of 2 + 4 × 4 gate delay times, the two bits with the least significance being added up via a half adder with a delay time of two gates. Accordingly, the time saved in a system designed according to FIG. 1 compared to the conventional system designed with full adders with the same number of bits (2 + 4 · 4) - 10 = 8 gate delays or 44.44%, the percentage time saved increasing with increasing value of m asymtotically approaches the value of 50%.

General results for the saving of time Δ t in the addition of two addends A and B with m Dual points of the value

Δ t = [2 + (m - 1) · 4 - m · 2] / [2 + (m - 1) · 4] (1)

In view of the fact that the other basic calculation types, especially the subtraction, can be traced back to the addition, the application of the described calculation method for the subtraction in a correspondingly constructed computer system also leads to a corresponding time saving. If the minuend is in one's complement, the possibility of adding a correction one must be provided. In conventional systems, a full adder, i.e. the combination of two half adders, is required for each digit, and the required computing time results from m dual digits with 4 · m gate delays. In contrast, a system corresponding to FIG. 1 requires m · 2 + (m + 1) gate runtimes, the term (m + 1) of the addition of correction one via the individual AND gates U _ir , U _{(i + 1), r} . . . U _{m, r} takes account.

The time saved in the case of subtraction when the minute end is present in the form of one's complement and a number of digits m is 25% compared to the usual calculation starting with the least significant bit i = 1, as can be seen from the following comparison:

• - Time delay with the conventional method: 4 · m gate running times
• - Time delay with the present method: 2 · m + m + 1 gate running times.

So you win with the present method the usual method a saving of 25%.

If you add the correction One in a conventional manner using half adders performed, one wasted in building the result compared to the present method per bit of the result a gate term. For individual cases this is now shown in the following table:  

(The unit for the time requirement is the gate runtime)

The time saving of the new method compared to the old method in the case of the addition of two dual numbers A and B is evidently also due to the fact that the two summands to be added are available in the finished state at the beginning of the addition, since at least that is at the start of the addition The highest bits that are common to both summands, that is, the dual digits A _n and B _n , must exist for the addition to begin. If several numbers were added, the third number could apparently only be added if the subtotal was calculated. However, there is a way to get around this limitation.

When adding and subtracting BCD numbers, so-called pseudotetrads occur, which can be corrected by the additional addition of the number 6 in binary code, that is, by adding the bit sequence "0 1 1 0". In the case of subtraction, it may also be necessary to add a correction one. However, both correction additions are only required when an additional pseudotetrad detection system or a negative / positive detection system requires the correction to be carried out. Thus, the computing method on which a device according to the invention is based can also be used for BCD numbers A and B , the time saved compared to conventional computing devices also being 50%.

For the following consideration of the addition of several numbers A, B, C, D, E and F present in the binary code , the conventional machines are operated in the manner shown in the following scheme, the individual addend bits also being labeled "A" , "B " , " C " , etc. are designated. "H" and "I" mean sum bits and carry bits (carry bits) of the first subtotal, "K" and "L" the sum and carry bits of the second subtotal, "M" and "N" the sum and carry bits of the third Subtotal and "O" and "P" the sum and carry bits of the fourth subtotal. The total sum bits are finally labeled "S" .

Each intermediate result formation requires a runtime, such as that in a full adder and the formation of the final sum additionally the runtime of a half adder and (m -1) runtimes in a full adder, if m is the most significant bit number of the summands A, B ,. . . F means. The total amount of time thus arises

T = (a - 3) 4 + 2 + (b - 1) 4 (2)

where a is the summand number, b the number of digits, the number "4" means four gate delays of the full adder, the number "2" means two gate delays of the half adder and T the total time required for the addition in gate delays as a unit.

The following new scheme can now be applied:
All summands are combined into groups of three and in places fed to a full adder, which corresponds to the scheme for forming the first subtotal shown above. Each group of three becomes a group of two, consisting of a sum bit and a carry bit row, through processing in the full adder. The process is repeated until two summands finally result. The scheme is thus carried out as follows:

Mean:
A, B, C, D, E, F summand bits
H and I as well as K and L sum bits and carry bits of the full adder chains in the 1st step,
M and N the sum and carry bits of the full adder chain in the second step,
O and P the two desired summands and
S the bits of the total.

Each of the steps shown requires the runtime of a full adder. Thus, with a summand number of n = 6, a full adder running time is saved.

Overview

As the overview shows, the time advantage that arises from the calculation method possible with the aid of the device shown in FIG. 1 compared to the previous method also increases with the addition of several summands with increasing number of summands n .

After as well as the subtraction also the multiplication can be traced back to the addition, the basic principle the invention also for the design of a Multiplication system can be applied. You come with it for a lead time of

t _M = (n _x + n _y - 1) (3)

where t _{M is} the multiplication time, n _{x is} the number of bits of the factor x , n _{y is} the number of bits of the factor y and t _{f is} the runtime of a full adder. For an 8 × 8 bit multiplier, t _M results in 60 gate run times, the full adder run time being 4 gate run times. With a combination of the methods presented, the time t _{M is} reduced to 39 gate delays, as can be seen from the following embodiment of an 8 × 8 bit multiplier.

The multiplier shouldn't just be the size of the product display, but also its sign. Negative results due to further processing in two's complement appear. For an increase in the factor length the multiplier would need additional results from others Multiplier can add to its result.

For this, the one that can be found in the following table Execution of a two's complement expandable 8 × 8 bit Serve multiplier.

table

Compared to standard multipliers, achieve at least a 31% reduction in time expenditure. The more the factors have digits, the greater the relative time gain. The reasons lie on the one hand in the growing difference between interim results and number of steps, but on the other hand also in the also increasing number of total bits.

Since the division continued to apply Subtraction based are also for this basic type of calculation significant time savings can be expected if that too the computer using the principle according to the invention  becomes.

In a device according to FIG. 1, all the inputs A _i * and B _i * are acted upon simultaneously with the respectively associated bits A _i and B _i , so that the first subprocesses play simultaneously in all half adders E _{i 1} , U _{i 1} . The information runtime is one gate runtime in one of the AND gates and two gate runtimes in one of the exclusive OR gates due to their complicated structure. This results in the running times in parentheses in FIG. 1 at the individual points in the circuit.

Accordingly, when using a logic logic according to FIG. 1, all logic operations A _i B _{i are carried} out simultaneously. However, they are taken into account when building the final result in such a way that the result is built up successively according to the calculation scheme given on pages 3 and 4.

On the other hand, however, it is also possible to construct a device according to the invention in such a way that the order of the linkage (A _i + B _i ) is also strictly in the sense of decreasing dual digit value i of the dual digit pairs to be linked. Two such devices are shown in Fig. 2 and in Fig. 3.

In the system shown in Fig. 2 according to the invention, the logic logic consists only of a half adder HA , the two inputs of which are acted upon by the signal outputs of two clock-controlled shift registers SR ₁ and SR ₂, in each of which one of the two summands A and B to be added are stored in such a way that the individual bits are input into the half adder HA in accordance with decreasing valency i in such a way that bits A _i and B _i corresponding to their dual position valency are pending at its two inputs.

In the embodiment shown in FIG. 2, the output circuit controlled by the half adder HA contains a flip-flop system which can be switched over to the operation as a dual counter as well as to the operation as a shift register. In order to make this possible, a logic L or L * is provided between each of the two flip-flop cells of the system, which are designed as two-memory flip-flops, in particular master-slave flip-flops, and correspond to the logic from FIGS. 2a and 2b obvious structure.

The signal output U of the half adder HA given by the AND gate of the half adder HA serves to act upon the one input of a first AND gate A 1 and the output E given by the exclusive OR gate of the half adder serves to act upon the one input of a second AND -Gatters A ₂. The two AND gates A ₁ and A ₂ and the other AND gates A ₃- A ₅ used in the circuit and the OR gates OR ₁ to OR verwendeten used in the logic L or L * each have two logic inputs.

The signal output of the first AND gate A ₁ is used to control the logic L or L * which is effective between two flip-flop cells FF _i . The signal output of the second AND gate A ₂ is used to act on the set input S of the first flip-flop cell FF ₁ and via an inverter I to act on the reset input R of this flip-flop cell.

Serving to control the system, clock generator T _A , not shown, outputs its clock signals both for controlling the two shift registers SR ₁ and SR ₂ and for controlling the switching logic L or L * via a single flip-flop cell FFT , which under construction corresponds to other flip-flop cells in the system.

One input of a third AND gateA₃ and the an input of a fourth AND gateA₄ lie immediately on the clockT _A , the second entrance of the third AND gateA₃ at the exit  and the second exit of the fourth AND gateA₄ at the exitQ of a single flip FlopsFFT. The structure of this single flip-flopFFT corresponds the structure of the flip-flop cells to be described Flip-flop system. The exit of the third AND gateA₃ is on the second input of the first AND gateA₁ and the second AND gateA₂ switched.

The said flip-flop system contains a number of flip-flop cells FF ₁, FF ₂, corresponding to the maximum dual position value i of the system. . . FF _n , where n is 5 in the example case. The flip-flop cells are designed as two-memory flip-flops, in particular as JK-MS flip-flops. The Q outputs of these flip-flop cells also serve as signal outputs S ₁, S ₂,. . . etc., so that finally the result obtained serially can be taken over in parallel from a memory (not shown).

Between the first flip-flop cell FF ₁ and the second flip-flop cell FF ₂ of the flip-flop system is a switching logic L , between two of the other flip-flop cells FF ₂, FF ₃,. . . etc., a switchover logic L * is provided, via which the switchover from counter operation to shift register operation and vice versa takes place. The circuit diagram of the switching logic L is shown in Fig. 2a, the circuit diagram of the switching logic L * in Fig. 2b.

The first switching logic mentionedL consists of three OR Gates with two logic inputs each, like follows, are switched: the one input of the first of these OR gate is onQ- Output of the controlling flip Flop cellFF _i , its second input at the exit of the AND  GatttersA₁. The output of this first OR gateOR₁ is with thatJ-Input of the subsequent flip-flop cell FF _{(i + 1)} connected. The one input of the second OR GateOR₂ the switching logicL is through the exit of the first AND gateA₁ the output circuit and the second input through the output of the fourth AND gate A₄ applied to the output circuit while the output of the OR gateOR₂ with the clock input of the following Flip-flop cellFF _{(i + 1)} connected is. In the end is the one input of the third OR gateOR₃ the circuitL through the - Exit of the antechamberFF _i , the other input of this gateOR₃ through the exit of the first AND gateA₁ controlled the output circuit, during the output of the third OR gateOR₃ with the K-Input of the downstream flip-flop cellFF _{(i + 1)} connected is.

The switching logic L shown in Fig. 2b * includes three OR gates OR ₄, OR and OR ₅ ₆ and-gate AND A ₅, having as well as the switching logic L A as well as the OR gate two logic inputs. In the connection, the OR gate OR ₄ corresponds to the OR gate OR ₁ and the OR gate OR ₆ to the OR gate OR ₃ of the switching logic L. The OR gate OR ₅, like the OR gate OR ₂ of the switching logic L, is controlled by the output of the AND gate A ₄. On the other hand, the control of the other input of the OR gate OR ₅ in deviation from the OR gate OR ₂ takes place through the output of the AND gate A ₅, the two inputs of which are each connected to one of the two inputs of the by the Q output of the pre-cell FF _i controlled OR gate OR ₄.

The circuit shown in FIG. 2 is thus described. In addition, it should also be noted that the pulses occurring at the Q output of the single flip-flop cell FFT serve for clock control of the two input shift registers SR ₁ and SR ₂.

With regard to the effect of the circuit just described, the following can be ascertained: the outputs of the AND gates A ₃ and A also , that is to say the AND gates controlled by the clock generator T _A and by the outputs of the single flip-flop FFT, are alternately in the cycle rhythm, acted upon and switched from zero to one or from one to zero. The output of the Q- applied AND gate A ₄ takes over the control of the flip-flop chain FF ₁- FF ₅ as a shift register and forms the clock for the shift register SR ₁ and SR ₂ controlling the half adder HA .

After executing the shift clock, the next pair of bits is available on the half adderHA at. Half a clock period later the exit of the with  from the single flip-flop cellFFT  acted upon AND gateA₃ switched to what the takeover of the half adderHA at the exits U andE supplied bits into the flip-flop cellsFF₁ and FF₂ is possible. At the same time, the inputsJ  andK of flip-flop cellsFF₂ toFF₅ switched to one, to change from one to zero onQ-Output of each upstream flip-flop cellFF _i  (Q- Output takes over Clock control of the next flip-flopFF _{i + 1}) the flip To make the flop chain work as a binary counter.

Instead of the circuit just described, which is strictly controlled by the clock, the following effect can also be exploited: If the signal output U of the half adder HA assumes the level one, the clock T _A is stopped by a monoflop triggered by the level one of the signal output U in order to flip -Flopchain FF ₂- FF ₅ to work as a counter. For this purpose, the output U of the half adder HA is connected directly (ie without an AND link with a flip-flop FFT and the associated gate to the information input of the second flip-flop cell FF ₂. The clock T _A is switched on again after the monoflop has flipped back Compared to the circuit shown in Fig. 2, the single flip-flop FFT and the AND gates A ₁ to A ₄ are then omitted.

The embodiment shown in Fig. 3 of a device according to the invention corresponds with respect to the shift register SR ₁ and SR ₂ and the half adder and the circuit of the flip-flop chain FF ₁- FF ₃ and the switching logic L or L * of an embodiment according to FIG. 2nd However, here the output U of the half adder HA controls the switching logic L or L * directly (and not via an AND gate U ₁). Likewise, the output E of the half adder is provided here directly (and not via an AND gate A ₂) for controlling the set input S and the inverter I and thus the reset input R of the first flip-flop cell FF ₁.

The - Outputs of the flip-flop cells to be switched as counters FF₂-FF _n  are each via an inverterIN on the Input of a differentiatorDF switched which by means of the first positive impulse (change of Information content of one of the cellsFF _i  from zero to One) the set entranceS a single flip-flop cellFFS  controls their reset inputR through the exitU, the AND gate of the half adderHAis controlled. TheQ- Exit this cellFFS is at an entrance of the AND gateA* whose other entrance is through the ClockT _A  is controlled. The output of the AND gate A* provides the clock for controlling the shift register SR₁ andSR₂ and the flip-flop cells via the switching logic L respectively.L* and thus corresponds to the AND gateA₄ the inFig. 2 circuit shown.

Those to be used in an adder according to the invention Circuit parts are known to be easy in both bipolar and MOS technology without integrate another monolithic. It is also possible  to summarize the entire arrangements on a semiconductor chip. The circuits shown can also be used combine with each other.

Claims (10)

1. adder for binary numbers, in which by means of half-adders each having the same dual points valence i having dual points A _i and B _i of the two respectively to be added addends A and B is an additive link as emergence of the respective dual points valence i associated logic operation result (A _i + B _i) experience, in which there is also an automatic correction of the linking result (A _{i + 1} + B _{i + 1} ) assigned to the next higher dual position value ( _{i + 1} ) in the sense of a carry when a two-digit linking result (A _i + B _i ) is present and in which a control of the temporal order of the links is provided, characterized in that the adders of the adder are formed solely from half adders (E _ir , U _ir ) and that the control is designed such that the addition of the dual numbers with the addition of the Bits with the highest dual position significance begin and to the lowest dual position significance It expires that a subtotal is formed in each case and then combined with the addition result of the bits of the next lower dual digit significance to form a next subtotal, the last subtotal being corrected if the addition result of the next lower dual digit significance has a carry. 2. Adding unit according to claim 1, characterized in that each dual position valence i is assigned a half adder (E _ir , U _ir ) and that a simultaneous application of all of these half adders with the respective binary points A _i and B _{i of} the two summands A and B is provided that there is also a logical link which is effective between the outputs of these half adders and which comes into action when there is a two-digit link result (A _i + B _i ) . 3. Adding unit according to claim 2, characterized in that each dual position valence i two signal inputs (A _i *, B _i * ) are assigned, that in addition by these two signal outputs a total of the dual position valency i corresponding number of half adders (E _ir , U _ir ) is controlled such that the two inputs of the AND gate (U _{i 1} ) and the exclusive OR gate (E _{i 1} ) of the first of these half adders (E _{i 1} , U _{i 1} ) each have one of the two inputs ( A _i *, B _i * ) are connected and that, with the exception of the last of these i half adders (E _ir , U _ir ), the output of the exclusive OR gate (E _ir ) of these half adders (E _ir , U _ir ) for control purposes one input of the next half adder (E _{i, (r + 1)} , U _{i, (r + 1)} ) is provided. 4. Adding unit according to claim 3, characterized in that the exclusive OR gate (E _ii ) of the i- th of the input pair (A _i *, B _i * ) assigned half adder, that is, the half adder (E _ii , U _ii ) is used as the output of the electronic circuit which supplies the i- th dual digit (A + B) _{i of} the sum to be determined (A + B) . 5. Adding unit according to claims 3 and 4, characterized in that the outputs of the individual AND gates (U _ir ) of the individual input pairs (A _i *, B _i * ) assigned half adders (E _ir , U _ir ) each for control one of the next higher Dual points rank (i + 1) associated with the half-adder (e _{(i + 1), r,} U _{(i + 1), r)} - only with the exception of the maximum m of i associated half-adder (e _{m, r,} U _{m , r} ) - are provided. 6. Adding unit according to claim 5, characterized in that for i < m the outputs of the individual AND gates (U _ir ) of the half adder (E _ir , U _ir ) each at the input of the half adder (E _{(i + 1), r} , U _{(i + 1) r} ) which is not controlled by the input pair ( A * _{(i + 1)} , B * _{(i + 1)} ) assigned to the next higher dual position value (i + 1). 7. Adding unit according to claim 6, characterized in that one of the most significant dual digit m corresponding number of OR gates (O _{r, (r + 1)} ) is provided and their connection is made such that the output of the individual AND gates (U _{m, r} ) the half adder (E _{m, r} , U _{m, r} ) to be loaded by the input pair (A _m *, B _m * ) of the most significant dual digit i = m of the system _, each with one input of the OR gate O _{r , (r + 1) is} connected, while the second input of this OR gate (O _{r, (r + 1)} ) in the case r = 1 through the output of the AND gate (U _{m 2} ) of the second through the input pair (A _m *, B _m * ) controlled half adder (E _{m 2} , U _{m 2} ) is controlled, while in the case of r 1 the relevant OR gate (O _{r, (r + 1)} ) is controlled by the output of the preceding OR Gate (O _{(r - 1), r} ) is also controlled, and that the output of the last of these OR gates (O _{(m - 1), m} ) forms a signal output (AU _m * ) of the logic logic. 8. Adding unit according to claim 1, characterized in that with respect to their dual position valency i corresponding dual digits A _i , B _{i of} the summands A and B to be added in accordance with falling dual position valency i are successively applied to the two inputs of a half adder (HA) , that further through the output (E) of the exclusive OR gate of the half adder (HA) the information input of a first flip-flop cell (FF ₁ ) and through the output U of the AND gate of the half adder together with the information content of the first flip-flop cell (FF ₁ ) the information content of a second flip-flop cell (FF ₂ ) is given and that finally the two flip-flop cells (FF ₁, FF ₂ ) form the first elements of a clock-controlled shift register which starts from the second flip-flop cell (FF ₂ ) the operation as a dual counter is switchable. 9. Adding unit according to claim 8, characterized in that the Q outputs of the individual flip-flop cells (FF _i ) of the shift register (FF ₁, FF ₂, ... FF _n ) form the signal outputs (S _i ) of the computer that Furthermore, between two successive flip-flop cells (FF _i , FF _{(i + 1)} ) of the shift register, a switchover logic (L or L * ) which enables the switchover from shift register operation to operation as a dual counter is provided and that the simultaneous control thereof Switching logic circuits ( L or L * ) is such that when a one occurs at the output U of the AND gate of the half adder (HA), a switchover to operation as a dual counter and with the first change in the operating state of one of the flip-flop cells (FF _i ) after this switchover from zero to one, there is a switch back to operation as a shift register. 10. Adding unit according to claim 9, characterized in that a clock(T _A ) for clock control of a single Flip-flop cell(FFT) and to control one of the two Inputs of two AND gates(A₃,A₄) is provided, that theQ-Output of the single flip-flop(FFT) at the other input of an AND gate(A₃) and the -Output to the other input of the other AND gate (A₃) is placed that the signal output of the by the -Output of the single flip-flop(FFT) controlled AND gate(A₃) to apply two AND gates (A₁,A₂) is provided, the second input of each through one of the two exits(E, U) of the half adder is controlled, and that finally through the exit of the through the AND gate of the half adder(HA) controlled AND gate(A₁) a circuit of the series Flip-flop cells(FF₂-FF _n ) on the operation as Dual counter and through the output of the through theQ-Exit of the single flip-flop(FFT) directly controlled AND Gate(A₄) a downshift of these flip-flop cells (FF₂-FF _n ) to operate as a shift register.