DE2855780C2 - Facsimile transmitter - Google Patents

Description

characterized in that

e) the memory (22,192-196) contains code signals for the characters of an identification of the facsimile sender, which is communicated to the recipient,

f) the code signals are read out from the memory (22, 192-196) and fed to a character generator (114, 164) that

g) the character generator (114, 164) converts the code signal synchronously with the scanning of the original into digital character signals for the dot-matrix representation of the characters, and

h) the mixer (118, 160, 163) logically adds these digital character signals to the digital image signals for the edge area of the original to be transmitted

2. Facsimile transmitter according to claim 1, characterized in that the memory (22) is formed by a plurality of memory elements (192-196) .

3. Facsimile transmitter according to claim 2, characterized in that the memory elements (192-196) are detachably mounted line by line on a circuit board (21 1).

4. Facsimile transmitter according to one of claims 1 to 3, characterized by a switching arrangement (133, 138, 139, 169) which enables the reading of the code signals only when scanning the first template of a series of several, related templates.

5. Facsimile transmitter according to one of claims 2 to 4, characterized in that resistors (204) are connected between the outputs of the memory elements (192-196) and an energy source (+ V) .

6. Facsimile transmitter according to one of claims 1 to 5, characterized in that for enlargement of the individual pixels of the characters each character signal is transmitted several times.

7. Facsimile transmitter according to one of claims 1 to 6, with a clock pulse generator for generating first sampling clock pulses for the main scanning direction and second sampling clock pulses for the relative movement between the original and the scanning device in the sub-scanning direction, characterized by a character counter (113) for the first sampling clock pulses (Y) to control the memory (22), and by a parallel / serial converter (116, 134, 136) connected to the output of the character generator (114), which is controlled by the

two sampling clock pulses (XY) is controlled.

8. Facsimile transmitter according to claim 7, characterized in that the parallel / serial converter has a first counter (134) for the first sampling clock pulses (Y) and a multiplexer (156) connected to the first counter (134)

9. Facsimile transmitter according to claim 7, characterized in that the parallel / serial converter has a shift register (116) , the shift input of which is the first sampling clock pulses (Y) and whose parallel loading input is the second sampling clock pulses £ * Q receives

10. Facsimile transmitter according to one of claims 7 to 9, characterized by frequency dividers (111, 112, 121) for the two sampling clock pulses (XY).

11. Facsimile transmitter according to claim 10, characterized in that the frequency dividers (111, 112, 121) have the same division ratio.

12. Facsimile transmitter according to one of claims 10 or 11, characterized in that the Division ratio is adjustable in steps

13. Facsimile transmitter according to one of claims 1 to 12, characterized in that a further character generator (198) for the dot-matrix representation of the characters of another character set is connected to the memory (192-196) in parallel with the character generator (197) .

The invention relates to a facsimile transmitter of the type specified in the preamble of claim 1.
Such a facsimile transmitter is known from DE-OS 22 60 175 and DE-OS 23 66 009 and has a scanning device for generating analog image signals that correspond point by point to a template to be transmitted, and a quantizing device for converting the analog image signals into digital image signals, a memory for further digital signals and a mixer which forms the signal to be transmitted from the digital image signals and the further digital signals. The other digital signals are control signals for the operation of the receiver, which, among other things, are sent before the actual digital image signals.

In such a facsimile transmitter, however, together with an image of the to be transmitted Template information about the sender is also transmitted, so generally an »identifier of the Facsimile Sender ”, for example the name of the owner of a facsimile sender who is to send a document should be transmitted to a recipient. The usual procedure for this, namely the use of a form for the template to be transferred with this name or the additional application of the name a graphic template to be transmitted have various disadvantages: The first method is for the Operator cumbersome and therefore impractical, since these labels are to be transferred to each Template must be applied. There are also many templates on which the subsequent Applying such a label is not possible.

Against the second method speaks that many documents to be transferred do not have the size correspond to existing forms and therefore common use often leads to problems.

On the other hand, it is practically impossible to have preprinted forms of different sizes for all of them To provide template sizes.

The invention is therefore the task ·; based on a facsimile transmitter of the specified type create, with which the identification of the facsimile sender can also be transmitted.

This object is achieved according geiöst 1 _t specified by the features characterizing the 'part of claim

Appropriate embodiments are compiled in the subclaims

The advantages achieved with the invention are based on the following mode of operation: The identification of the facsimile sender is broken down into its picture elements in a pattern, similar to a picture, so that the 1- individual points of this pattern as digital image signals. ·, In a memory of the Facsimile transmitter stored; * can be. If this identification is now to be transmitted together with the digital image signals obtained by the scanning for the original, the stored code signals for the characters of the identification are logically added to the digital image signals for the edge area of the original to be transmitted, that is, on the receiver side In the edge area, instead of the usual, free, unprinted edge, the identifications of the facsimile sender that have been transmitted together with the image signals for the original appear.

So it is no longer necessary to write the identification on each template to be transferred or to use special forms with such a marking. There is also none on the receiving end special adaptation to the facsimile sender is required, as the code signals for the characters of the identification are transmitted and received as "normal" digital image signals, i.e. the conversion of all digital ones Image signals are carried out in the usual way, so that on the receiving end an overall template of identification and the original to be transmitted is recorded.

It is also possible to change the stored identifier without any problems by only using the corresponding memory exchanged or, in the case of a variable memory, a new identifier entered will. This may be necessary, for example, if such a facsimile transmitter is sold and the new owner also wants to use the corresponding marking.

When using a permanent memory this is expediently designed to be pluggable so that it can be exchanged without problems.

The entire sheet area is available for recording the identification on the recipient side Except for the illustration area of the template.

By frequency division of the clock pulses used for sampling, the code signals in stretched form, whereby an enlargement of the marking on the receiving side becomes possible.

The invention is illustrated below on the basis of exemplary embodiments with reference to accompanying schematic drawings. It shows

F i g. 1 is a block diagram of a facsimile transmitter

F i g. 2a to 2e representations to explain the insertion of markings into the to be transmitted Template,

3 shows a perspective view of the scanning device,

4 is a perspective view of the recording device;

F i g. 5 shows a representation of a character as it is transmitted after scanning;
F i g. 6 is a block diagram of a character generator;

FIG. 8 shows a time diagram of the mode of operation of the embodiment according to FIG. 7,

F i 3. 9 is a block diagram of a second embodiment of the part of the facsimile transmitter which combines the code signals for the characters of the identification of the facsimile transmitter and the digital image signals for the original to be transmitted; F i g. 9,

11 is a timing diagram for explaining the Functioning of the embodiment according to Fi g. 10,

Fig. 12 is a block diagram showing a detailed Representation of the various components of the embodiment according to FIG. 10,

13 is a block diagram of a multiplexer of the embodiment according to FIG. 10,

14 shows a perspective illustration of an integrated circuit with plug-in memories, and FIG

15 shows an illustration of the data organization in the stores.

F i g. 1 shows the basic structure of a facsimile transmitter generally indicated by reference numeral 11 with a scanning device 12, each detecting a line of an original, through a series of charge coupled device (CCD) is formed. The scanning device 12 typically includes 32 photosensitive elements 12a arranged along an axis 126.

The scanning device 12 is, starting at the left edge of an original, over a strip-shaped Moves the area to the right edge of the template and then back to the left edge of the template, causing the entire width of the original to be transferred is swept over. During this scanning movement of the Scanning device 12 provide the photosensitive elements 12a analog image signals that correspond to the Original reflected light from light or dark surface areas and thus point by point to correspond to the transferring template.

During the movement of the scanning device 12, the light-sensitive elements 12a are through V-clock pulses controlled so that they output analog image signals that correspond to the associated area of the original.

After scanning a strip-shaped area of the original, the scanning device 12 is through A "clock pulses shifted by a specified distance, after which the scanning movement is repeated to scan the next area of the original.

After the strip-shaped area has been scanned over the entire width of the original, the original parallel to its longitudinal direction and thus to the axis 126 of the scanning device 12 in a vertical direction Direction moved by a defined distance, namely by a distance which is equal to the length of the scanning device 12 is.

The next, strip-shaped area of the original is then scanned in a corresponding manner began.

The analog image signals from the photosensitive elements 12a are serially generated and via a Video amplifier 13, which quantizes the analog image signals and thus converts them into digital image signals, a mixer 14 is supplied.

The digital image signals output by the mixing stage 17 are sent to a compression device 16 supplied, which works with one of the usual compression methods, for example track length coding. The compressed digital image signals are transmitted by the compression unit 16 to a modulator 17 given that mixes the digital image signals with a carrier wave and the modulated carrier wave via a communication link 18, for example a public telephone line, to the dialed Receiver transmits.

The in F i g. 1 also indicated receiver has a demodulator 19 for the received digital Image signals on; the demodulated image signals are fed to an expansion device 21, which the Underscores the compression discussed, for example performs a track length decoding. The stretched ones Digital image signals are then transmitted via a control device 23 to a recording device 24 supplied, which has 32 arranged along an axis 246 pressure elements 24a. These pressure elements 24a can be formed, for example, by electrodes that electrostatically hold a recording medium charge and thus generate an electrostatic, latent image of the received original.

This electrostatic, latent image is developed into a visible toner image by means of a toner, which is then fixed.

On the path of the scanning device 12 are markings made by one with the scanning device movable photoelectric transducer (not shown) are scanned, whereby each Detection of such a mark a -Y clock pulse is produced. These A "clock pulses are applied to the scanner 12, causing the scanner 12 is controlled and synchronized with the corresponding digital image signals from the light-sensitive Elements 12a emit 32 K clock pulses. The scanning device 12 therefore delivers for each / ^ clock pulse 32 K clock pulses as well as digital image signals.

In addition, these markings also serve to monitor the movement of the scanning device 12.

The recording of the transferred template, including the identification, which is of no further interest here of the facsimile sender is done in the same way, i. h "according to the scanning of the markings on the path of the recording device, X clock pulses for the printing elements 24a are the Recording device 24 formed around an electrostatic, latent image of the original on the To generate recording media.

Based on the F i g. 2a to 2b is intended to explain the basic principle of the insertion of characters in a designation of the Facsimile sender will be explained. The recording 101 shown in FIG. 2a and generated in the receiver has an imaging surface 101a and an upper, empty, that is to say white, edge area 1016.

The characters for the identification of the facsimile sender are automatically placed on this white border area printed, which have been transmitted together with the digital image signals for the original. This identifier is generally formed by the name of the owner of the facsimile sender, as in Fig. 2a is indicated by the name "Ricoh". In Figure 2b is a record 102 with a Imaging area 102a shown, which takes up the entire area of the recording 102. So there is no white border area. In this case, the name "Ricoh" will be placed at the top center of record 102 in a free, white area 1026.

The embodiment according to FIG. 2c corresponds to

according to FIG. 2b with the exception that the name "Ricoh" is in a free space 1036 in the upper left corner of the Mapping area 103a of record 103 has been recorded

According to the embodiment of FIG. 2d, a recording 104 has an imaging area 104a, but no edges. In this case, the name "Ricoh" will be in a free space 1046 on the top left Corner of the imaging surface 104a, similar to the embodiment according to FIG. 2c, printed. Additionally however, the name "Ricoh" is in the upper one, this time in Japanese Kana characters right corner of the imaging surface 104a, namely in the area 104c. Between corners 104fc and 104c is the corresponding, strip-shaped part of the imaging surface 104a.

Finally, FIG. 2e shows an embodiment in which the recording 106 has an imaging surface 106a but no borders. In In this case, the letters "R", "I", "C", "O" and "H" of the name "Ricoh" are in associated, free areas 1066 to 106 / at the upper edge of the imaging area 106a of the recording 106, where there are areas of the image area between the individual letters.

In Fig. 7 shows details of the character generator and the mixer 14 as well as their control. the Mixing stage 14 is connected to the memory 22, as can be seen in Fig. 1 so that the mixing stage 14 the digital image signals of the original and the code signals coming from the memory 22 combined as yet to be explained. The memory 22 is a read-only memory, for example a programmable one Read-only memory (PROM) formed in the form of at least one integrated circuit

The X clock pulses generated in the manner explained are obtained via a frequency divider 111 with a division ratio of 4 and over

Such a frequency divider 112 with a division ratio of 8 is fed to a count input of a character counter 113. Parallel outputs of the character counter 113 are connected to parallel inputs of the programmable memory (PROM) 22, the outputs of which are in turn connected to parallel inputs of a character generator 114. The parallel outputs of the character generator 114 are connected to parallel inputs of a parallel / serial converter, which is shown as a shift register (PISO) with parallel input and serial output The output is connected to an input of the OR element. The output of the OR element 118 is connected to an input of the compressor 16. The digital image signals from the video amplifier 13 are present at the other input of the OR gate 118.
The vf clock signals in the manner explained

have been obtained are applied to a parallel input of the shift register 116 via an inverter 119 . The K clock pulses are fed to a serial shift input of the shift register 116 via a frequency divider 121 with a division ratio of 4. The output of the frequency divider 111 is connected to the A "change input of the character generator 114 .

A transmission signal from the control unit (not shown) of the facsimile transmitter 11 is applied to a set input of an RS flip-flop 122 . An end-of-line scan pulse, which has also been generated by sensing the marks, is applied to a reset input of flip-flop 122 . The Q output of the Füp-Fiops 122 is connected to an input of the AND gate 117 . The Q output of flip-flop 122 is connected to inverting reset inputs of frequency dividers 11, 112 and 121 and character counter 113 via an inverter 123 .

The character generator 114 has the same structure as that used in dot matrix printers and is shown in detail in FIG. 6 shown. The character generator 114 can generate the required characters from the points in an ^r 8 × 8 matrix (see FIG. 5) and has an internal A "counter, not shown, which is incremented by the frequency divider 111 by the AV change pulses.

The programmable memory (PROM) 22 stores the characters representing the name, address or the like of the facsimile transmitter 11 in the form of code signals of 6 bits each for the characters. The code signals are stored in successive storage locations in the memory 22 . The successive storage locations of the memory 22 are addressed by incremental advancement of the character counter 113 , whereby the bits of the code signals are applied in parallel to the inputs of the character generator 114 . To print the letter "A" (see F i g. 5), the corresponding 6-bit code signal from the memory 22 to the character generator 14 1 is supplied.

Depending on the count of the internal X counter, the character generator 1 14 forms a single column, that is to say a vertical line, of the character. When the counter reading is “0”, which corresponds to a horizontal (X) position XI, the character generator 114 outputs the first vertical line Yi to YS of the character. With the letter "A" the outputs F1 to YS are 0, 0, 1, 1, 1, 1, 1 or 0. According to an A "change input, the internal Λ'-counter is switched to the count 1, and the Character generator 114 forms the next vertical line X 2. The outputs Yi to YS are then 0, 1, 0, 0, 1, 0, 0 and 0. According to the seventh X change pulse, the internal counter is set to 7 and up the -Υβ-column and the A "8-line output are switched on. The outputs Vl to Y 8 s. Are all zero.

The operation of the embodiment of FIG. 7, the frequency dividers 111 and 121 being omitted for the sake of simplicity; the frequency divider 112 and the character counter 113 are reset The transmission signal sets the flip-flop 122, the high (^ output of the AND gate 117 enables the count in the character counter 113 is zero; the first memory location in the memory (PROM) 22 is characterized addressing the code for the first by the receiving means characters to be printed is read out from the memory (PROM) 22 is applied to the character generator 114th the count in the internal A "counter of the character generator 1 14 is zero, so that the character generator 1 14 forms the leftmost vertical line of the first character.

The rising edge of the first .Y clock signal is inverted by the inverter 119, to thereby generate a falling edge, which is applied to the shift register 16 1 to load characterized in that the first line of the character. The internal counter of the character generator 114 is incremented by the rising edge of the first X clock pulse, so that the character generator 114 outputs the next vertical line of the first character. This, however, the shift register 1 16 is not affected because in this the first line has already been loaded.

The first group of 8K clock pulses is applied to shift register 116 ; characterized the first line of the character is shifted out serially from the shift register 1 16 via the AND gate 117 and the OR gate 118 and applied for transmission to the compressor sixteenth The signals from the shift register 116 are logically added to the image signals from the video amplifier 13. With the embodiment according to FIG. 7, a template can be transferred in which an upper margin is provided. As a result, the data mixed with the character signals can all be logically low, and the transmitted data is effectively composed of the character signals only. The first line of character signals is picked up by the receiver, not shown, which accordingly then reproduces the first vertical line of the first character.

The rising edge of the second A "clock pulse is inverted by the inverter 113 ; this loads the second vertical character line into the shift register 116. The internal counter in the character generator 114 is incremented so that the character generator 114 outputs the third vertical character line On the next 8 V clock pulses, the second vertical line is shifted and transferred from the shift register 116. This operation is continued until the 8 lines which represent the first character have been formed and transferred.

Accordingly, the leading edge of the 8-th A'-clock pulse is the frequency divider 112, an output from which the character counter 113 further switches This is then addressed 22, the second memory location in the memory (PROM) and the code for the second character is the character generator 114 applied The 8 vertical lines of the second character are generated and output according to the next 8 X clock pulses. The character counter 113 is switched on with each of the 8 A 'clock pulses in order to address a subsequent memory location in the memory (PROM) 22 and to generate a new character.

The arrangement described so far, in which the frequency dividers 111 and 121 have been omitted, prints 216 characters, each having a height of 1 mm and a width of also 1 mm. However, the head 51 outputs 32 V clock signals for every ^ clock pulse. After the first 8 V clock pulses are generated and the first vertical line of character data is shifted out of shift register 116 , signals corresponding to the next 24 become logic low

ίο

K clock pulses shifted out of shift register 116. This is the case with every vertical line. As a result, the characters are only printed in the upper 1 mm area of the first scanning area, although the height of the first scanning area is 4 mm. Not only is this a waste of space on the top scanning surface, but letters as small as 1 mm are difficult, if not impossible, to read with the naked eye.

In other words, the characters are too small.

An obvious solution to this difficulty would be to provide a character generator, which puts out a 32 χ 32 character so that all of the available space is in the upper Scanning surface area is used, and the size of the character by a factor of 4 is larger. letters with a size of 4 mm χ 4 mm are perfectly legible. However, this obvious solution would reduce the The complexity and thus the cost of the installation increase unnecessarily.

The solution to this problem is obtained with the aid of the frequency dividers 111 and 121 . A timing diagram of the FIG. The embodiment shown in FIG. 7 is shown in FIG. The frequency divider 121 divides the frequency of the y clock pulses by a factor of 4. As a result, a shift pulse is applied to the shift register 116 at 4 V clock pulses. Thus, each bit is each vertical character line at the output of the shift register 1 16 in synchronism with 4 successive V-pulses to clock. In other words, each bit of each character line is transmitted in synchronism with 4 V clock pulses and is printed by the receiving device as a vertical line the length of which is 4 4 bits. This then increases the vertical size of the characters by a factor of 4.

The X clock pulses are frequency divided by the divider 111 and applied to the character generator 114 as Y change pulses. With these pulses, the character generator 114 forms successive vertical character lines. However, only one X change pulse is applied to the character generator 114 for every 4 X clock pulses. As a result, each character is loaded into the shift register 116 in accordance with the inverted X clock pulses from the inverter 119 four times and shifted out four times in synchronism with the frequency-divided V clock pulses. This has the effect that each vertical character line is printed four times in succession and the horizontal size of the characters is enlarged by a factor of 4. Of course, each character is printed 16 times in 16 adjacent places on the facsimile copy, namely in four vertical and four horizontal positions .

With this arrangement, a maximum of 54 characters can be printed, each having a legible size of 4 mm × 4 mm. The line scan end signal generated by sensing the mark 84 resets the flip-flop 22 . The low C? Output of flip-flop 122 disables AND gate 117 to prevent character data from being transmitted. The high (^ output of the flip-flop 122 is fed through the inverter 123 in order to reset the frequency dividers U1, 121 and 112 and the character counter 113.

The character generator 114 uses wired elements to create an 8x8 matrix. When using the character generator 114 - without the frequency dividers 111 and 121 - characters that are too small would be generated to be readable in the receiver 11. The frequency dividers 111 and 121 , however, increase the size of the characters by a factor of 4 so that they are easy to read. As a result, an inexpensive character generator can be used.

This arrangement also increases the reliability of the transmission of character signals, since each Character line bits in the form of four groups each

ίο is transmitted by four signals. While the The possibility of a single bit being lost due to noise during transmission and the like is relative is high, the possibility that four consecutive bits will be lost is extremely low. Consequently are the character signals compared to a system in which each bit is only once is transmitted with an exceptionally high reliability.

In Fig. 9 shows a further device, designated in its entirety by 131 , which has an RS flip-flop 132 . The transmit and line scan end signals are applied to the set (S) and reset (R) inputs of flip-flop 132 . The (^ Q output of flip-flop 132 is connected to an input of an AND gate 133, whose output is connected to the inverting reset inputs of a K counter 134, an A "counter 136 and a character counter 137 A movable contact of a single pole changeover switch 138 is selectively connectable via a to a fixed contact of the switch 138 connected to resistor 139 to a positive pole of a voltage source + V and with another fixed contact of the switch 138, which is a code control signal absorbs the movable contact of the switch 138 is connected to a further input of the AND gate 133 connected.

The y-TaktimpuIse are frequency dividers 141 and 142 each having a division ratio of 2, applied to one input of an AND gate 143. The output of the frequency divider 141 is connected to an input of an AND gate 144th The outputs of AND elements 143 and 144 are connected to inputs of an OR element 146 , the output of which is connected to a counting input of counter 134

The X clock pulses are applied to an input of an AND element 149 via frequency dividers 147 and 148, each of which has a division ratio of 2. The output of the frequency divider 147 is connected to an input of an AND element 151 . The outputs of the

so AND gates 149 and 151 are connected to the inputs of an OR gate 152 , the output of which is connected to a counting input of the counter 136

A movable contact of a single-pole changeover switch 153 can optionally be connected to stationary contacts which are connected to ground potential or via a resistor 154 to the voltage source + V. The movable contact of switch 153 is connected to inputs of AND gates 143 and 149 and via inverters 153 and 154 to inputs of AND gates 144 and 151 .

The count outputs of the K counter 134 go in parallel to a multiplexer 156. The y counter 134 also has a 2 ³ -bit output which is connected to one input of a NAND gate 157 , the other of the latter

b5 input is connected to the movable contact of the switch 153 via an inverter 158. The output of the NAND element 157 is connected to an input of a NAND element 159 , the output of which is connected to

an input of an AND element 160 and, via an inverter 162, to an input of an AND element 161 connected is. Outputs of AND gates 160 and 161 are connected to inputs of an OR gate 163, the output of which is connected to the compressor 16.

Count outputs of the X counter 136 are in parallel with Inputs of a character generator 164 switched, and a carry output is connected to a count input of the Character counter 137 connected. The character generator 164 forms an 8x8 character matrix and has eight Outputs connected in parallel to the multiplexer 156.

Outputs of the character counter 137 are connected in parallel to inputs of a memory 166. Parallel outputs of the memory 166 are with inputs of the character generator 164 and also with inputs of a NAND gate 167 connected, the output of which is connected to an input of the NAND gate 159. The data from the video amplifier 13 is applied to another input of the AND gate 160. The serial output of the multiplexer 156 is connected to an input of the AND gate 161.

The mode of operation of the device according to FIG. 1 will now be described with reference to FIG. 9 described. The moving ones Contacts of switches 138 and 154 are connected to the source + ^ via resistors 139 and 154, so that logic high inputs are applied to AND gates 133, 143 and 149, thereby enabling them will. The AND gates 144 and 151 are on the movable contact by the inverted high signal of the counter 153 blocked. In this way, the output of the frequency divider 142 is via the AND gate 143 and the OR gate 146 applied to the counting input of the y-counter 134, and the output of the Frequency divider 148 is sent via AND element 149 and OR element 152 to the counting input of the X counter 136 created.

Since the count in the K counter is initially zero, the 2 ³ output is low. As a result, the NAND gate 157 outputs a high output. The first in memory

166 stored characters should not be an empty character, and at least one input to the NAND gate

167 should be logically low. As a result, the NAND gate 167 then outputs a high output. Through the two high inputs on the NAND gate 159, this (159) creates a low output, whereby the AND gate 161 is released and AND gate 160 is blocked. As a result, the passage is from Data signals through the AND gate 160 blocked, while character signals through the AND gate 161 can go through.

The y-clock pulses are frequency divided by a factor of four by means of the frequency dividers 141 and 142 and applied to the V counter 134. According to the count in the K counter 134, the multiplexer 156 leaves one bit of a vertical line of a character from the character generator 164 for one Transmission to the AND gate 161 through. If, for example, the count in the K counter 134 is zero, the topmost or the Yi bit in a character line is passed through the multiplexer 156 to the AND gate 161. If the count in the K counter 134 is seven, the lowest or the V8 bit in the character line is present at the output of the multiplexer 156. Frequency-divided y-clock pulses which are present at the output of the OR gate 146 are referred to as y-change pulses

The X clock pulses are generated by the frequency divider 147 and 148 frequency divided by a factor of four and via the AND gate 149 and the OR gate 152 as X change pulses which are counted by the Λ counter 136 are passed. According to that Count in the ^ counter 136, the vertical character lines lie one after the other at the output of the character generator 164 at. The .V counter 136 has the same function as the internal (not shown) X counter in FIG the character generator 114. Of course, the multiplexer 156 also has the function of the shift register

ίο 116 of mixer 14. The function of inverter 119 is however, not required in the device 131, since the vertical character lines are not each four times in the Multiplexer 156 need to be loaded.

The X counter 136 generates a carry signal, which is a character change signal corresponding to 8 λ 'change signals represents. The character change signal advances the character counter 137, which successive storage locations in the memory 136 corresponding to the address in the character counter 137 addressed. In this regard, the X counter 136 has the Function of the frequency divider 112.

The memory 166 generates codes designating the required characters that are stored in the receiver can be printed according to the count in the character counter 137. The character counter 137 is through Carry signals from the -Y counter 136 are switched on, which indicates the vertical line of the character that corresponds to the character code input to the Character generator 164 is generated. The character counter 137 is incremented each time 8, V change signals are generated and the eight lines of a specific character are generated. the -Y change signals are generated by the X clock signals formed, which are frequency-divided by a factor of four, so that each vertical character line four times is output, increasing the horizontal character size by a factor of four Bit of each vertical character line output four times in synchronism with four successive y-clock signals.

This then increases the vertical size of the characters by a factor of four

Means are provided in device 131 to change the enlargement ratio of the characters. The enlargement ratio can be changed from a factor of four to a factor of two by only switching the switch 153 so that its movable contact is grounded the outputs of the frequency dividers 141 and 147 are applied to the inputs of the counters 134 and 136, respectively. Since the Y and the Λ clock pulses are frequency divided only by a factor of two, the enlargement ratio is reduced from four to two

When the switch 153 is connected to ground potential, a high signal is applied to the NAND gate 157 via the inverter 158. As long as the 2 ³ output of the y-counter 134 is low, the NAND gate 157 gives a high output and the NAND gate 159 from a low output, so that the AND gate 161 is enabled and the AND gate 160 is disabled. However, after eight X change pulses have been received from V counter 134, the 2 ³ output of counter 134 goes high and NAND gate 157 outputs a low output. As a result, the NAND gate 159 then generates a high output which blocks the AND gate 161 and enables the AND gate 160. Consequently, the output of the MultiDlexer is

156 blocked by the AND gate 161, while data signals passed through the AND gate 160 will.

Since the enlargement ratio is two in this case, the height of the characters is only 2 mm. If the NAND gates 157 and 159 were not provided, the count at the 2 °, 2 'and 2 ² bits of the y-counter 134 would be repeated in accordance with the second 8 l ^ change pulses and the characters would again be in the second 2 mm vertical surface area of the reproduction can be printed. However, the NAND gates 157 and 159 serve not only to automatically prevent this double printing, but also to allow the image signals to pass through to the compressor 16 in this area.

This is particularly advantageous for templates that do not contain an upper edge surface, since the the entire image area becomes accessible, which is not covered by the identification marks to be used in If the enlargement ratio of the characters is two, the characters take that and the image data occupy the remainder of the recording including the 2 mm area immediately below the characters. As a result, there is no imaging surface wasted.

The mixer 14 is provided to the OR gate 118, the characters and the image signals logically to add up. This is satisfactory as long as the original to be reproduced has a top margin is provided. However, there are problems when there is no top edge surface and the image is dark May contain surfaces in their upper part. When dark characters are superimposed on dark areas of the image the characters are very likely illegible.

The wrap 131 is useful for any type of original, since an image transfer during a Transmission of the character signals is automatically blocked. As shown in Fig. 2b to 2e, each Characters printed in a 4 mm (or 2 mm) white block on top of the rendering. Neighbors Artboards create a white horizontal strip on which the characters are printed. the black characters printed on a white background are perfectly legible.

Often multi-page templates or a set of templates are to be transferred one after the other. For example, you may wish to transfer the pages of a manuscript one after the other. The switch 138 provides a facility for printing the indicia either on the record of only the first original or on the record of all the originals in the set to be transmitted. In order to print the characters on each record, the switch 138 is connected to the voltage source + V as shown. In order to print the characters only on the first record (or only on the second or another record), the switch 139 is switched over in order to connect the code control signal to the AND gate 133.

If the characters are only to be printed on the first copy, the code control signal is made high first, whereby the AND gate 133 is released. After transmitting the character and image signals for the first original the code control signal is made low. The AND gate 133 gives a low Output which resets counters 134, 136 and 137 in order to disable device 131.

Furthermore, the output of the AND element 133 is connected to an input of the NAND element 159. De The output of AND gate 133 goes high when there is flip-flop 132 by line or line scanning signal is reset. At the low output de AND gate 133 is the NAND gate 159 from a high signal, which enables the AND gate 160 and there; AND gate 161 blocks As a result, image signals are transmitted after the characters are transmitted have been.

The output of the AND gate 133 remains itself The next document to be sent is low because the output of switch 138 is low

This prevents the characters for the second and subsequent originals from being transmitted.

The switch 138 and the resistor 139 form a code control device 168 which is controlled by an in 10 replaces the code control device 169 shown can be. The code control device 169 has an RS flip-flop 170 with a Q output that is connected to one input of the AND gate 133 is connected to the set (S) and the reset inputs (R) of the flip-flop 170 are switched accordingly to display more pages or To record the starting digits.

A start signal is generated at the beginning of every transmission process, regardless of whether it is one-sided or a multi-page original is to be transmitted This resets the flip-flop 170 and that

AND gate 130 enabled for a transmission of the characters in the prescribed manner. A not The switch shown is provided, which the operator can either set to a position »a single page «or» more pages «. When the switch is in the "one side" position is located, the flip-flop 170 remains reset and the characters are transmitted for each page or original. However, if the switch is in the "multiple pages" position, a corresponding signal is sent to the The start of the scanning of the second original is generated, which sets the flip-flop 170. This then becomes the output of AND gate 133 low, and a transfer of the characters for the second and the following original pages is prevented.

A schematic diagram of multiplexer 156 is shown in FIG. The outputs of the V counter 134 are connected in parallel to the inputs of a decoder 171, the outputs of which are in turn connected to inputs of AND gates 172 to 179 and 181 are connected, the outputs of which via an OR gate 182 with the AND gate 161 are connected. The eight parallel outputs of the character generator 164 are connected to the Inputs of the AND gates 172 to 181 connected.

The decoder 171 outputs high outputs to enable the AND gates 172 to 181 in succession according to the respective counts in the counter 184. When the count in counter 134 is zero, decoder 171 outputs a high output to enable AND gate 172 only and to pass the Yi output of character generator 164 to OR gate 182. When the count in counter 134 is seven, decoder 171 only enables AND gate 181 to pass the V8 output of character generator 164, and so on.

Various elements of stage 131 are shown in detail in FIG. The higher quality Bit outputs of the character counter 137 are connected to inputs of a decoder 191. The lower-valued

The bit outputs of the character counter ^ 137 are closed Address inputs of programmed read-only memories (PROM) 192 to 196 are connected in parallel, which together with the decoder 191 form the memory 166. The outputs of the decoder 191 are with release inputs of the memory (PROM) 192, 193, 194 or 196 tied together.

As shown schematically in FIG. 12, each has in stores. (PROM) 192 to 196 stored codes include a 6-bit character code part, an alpha / kana selection bit and a code lock bit. The code bit outputs of memories 192 through 196 are in parallel with Code inputs from alphanumeric or Kana character generators 197 or 198 switched The Alpha / Kana select bit outputs of memories (PROM) 192 to 196 are to a chip select input of the alphanumeric generator 197 and via an inverter 199 with a chip selection input of the Kana generator 198 connected in parallel All eight outputs of the memory (PROM) 192 to 196 are closed Inputs of the AND gate 167 connected in parallel

The outputs of the alphanumeric generator 197 are connected to inputs of a multiplexer 201. The outputs of the kana generator 164 are connected to inputs of a multiplexer 202. The outputs of the multiplexers 201 and 202 are connected to the inputs of an OR element 203, the output of which is connected to the AND element 161. The outputs of the K counter 134 are connected in parallel to vertical bit selection inputs of the multiplexers 201 and 202 in the manner described above. The outputs of the A "counter 136 are connected in parallel to line or line selection inputs of the character generators 197 and 198. A resistor group 204 has eight" pull-up "resistors (not shown in detail), which are connected between the voltage source + V and the outputs of the Memories (PROM) 192 to 196 are connected as shown.

The alphanumeric generator 197 is similar designed to generate alphanumeric characters and symbols. The kana generator 198 is similar designed to generate Japanese, phonetic katakana, and hiragana alphabets. Of course he can Kana generator 198 can also be replaced by a character generator which is designed accordingly to to generate any desired type of alphabet such as Arabic.

The memories (PROM) 192 to 196 are each designed accordingly to store the codes for a quarter of the horizontal drawing line. The memory 192 stores the codes for the furthest characters on the left, etc. The memories (PROM) 192 to 196 are sequentially assigned by the encoder 191 enabled as determined by the higher-order bit outputs of the character counter 137. The single ones Addresses in the memories 192 to 196 are determined by the low-order bit outputs of the character counter 137 set. As a result of this collection arrangement, each count in the character counter 137 addresses a discrete one

Storage location in one of the memories 192 to 196.

The seventh bit of each code stored in memories 192 through 190, indicates whether the character is alphanumeric or kana When the seventh bit is logic high, the alphanumeric generator 197 is enabled and outputs the character lines via the Multiplexer 201 from. When the seventh bit is a logic low, the kana generator 198 is enabled and returns the drawing lines via the multiplexer 202 from. the

ίο character generators 197 and 198 and the multiplexers 201 and 202 are controlled by the X and the y change pulses in the manner described above

The NAND gate 167 outputs a low output to enable transfer of character data

prevent and to enable the transmission of video data when all outputs of the addressed point in memories 192, 193, 194 or 196 are logic high. This can either create a free space or it can image signals between adjacent characters be created. If a free space is desired a corresponding code other than 11111111 is stored in the memory 192, 193, 194 or 196 in the appropriate place. To fill the space with video data, the code 11111111 stored, whereupon the NAND gate 167 outputs a low output, which the AND gate 161 blocks and the AND gate 160 enables.

According to an important feature, the memories (PROM) 192 to 196 store the character codes the same places to which the characters are transmitted and reproduced by the recipient. the Memories 192 to 196 are detachably mounted on a circuit board 211 by means of integrated circuit sockets 212 to 216. When the memory 192 is in the Socket 212 is plugged in, the character codes stored in memory 192 generate the characters in the am furthest left quarter of the drawing area during playback. The one plugged into the base 214 Memory 194 produces printed images as shown Mark in the third quarter of the record, measured from left to right. This makes it easily possible to provide the characters at any desired location on the printed surface.

Resistance group 204 allows images

genes can be provided in areas of the recording where one or more of the memories 192 to 196 are not present.

If in such a case the memory locations in the missing memory 192, 193, 194 or 196 are addressed, all output lines are logical as a result of the connection of the resistor group 204 high. This then has the consequence that the NAND gate 167 outputs a low output and the image signals transmitted in the same way as if a Code 11111111 is stored in a memory location. This makes the image area on the record by printing the indicia only maximized in the areas where they are actually required.

For this purpose 10 sheets of drawings

Claims (1)

Patent claims:
1. Facsimile sender a) with a scanning device for generating analog image signals that point to one correspond to the transferring template, b) with a quantizing device for converting the analog image signals into digital ones Image signals, c) with a memory for further digital signals, and d) with a mixer that consists of the digital image signals and the other digital signals forms the signal to be transmitted,