DE2853058A1 - DEVICE FOR CYCLE RECOVERY IN A RECEIVING STATION OF A DIGITAL DATA TRANSFER SYSTEM - Google Patents

Description

K. Caves 6-1

Device for clock recovery in a receiving station of a digital data transmission system

The invention relates to a device for clock recovery in a receiving station of a digital data transmission system from the digital data received in the receiving station and the line clock of the data transmission system which is derived from the line clock a data clock pulse train, the frequency of which is equal to the nominal bit rate of the received data is.

A well-known method for transmitting a serial data stream to a remote data station is to to provide the data with a line clock, its frequency is many times higher than the data bit rate and the redundantly coded signal via a modem to the To send out the line. After the demodulation in the receiving station, a majority decision based on the η is made last received bits, whereby a basic error correction can be carried out, η is the odd number assigned to the Ratio between the frequency of the line clock and the data clock comes closest. By deriving the data clock from this data signal obtained by the majority decision, it is possible to convert this data signal back into the Bringing the correct time grid and thus completing the error correction.

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It is the object of the invention to provide a device for recovering the data clock as a function of an incoming Specify a data signal that is suitable for use in a digital data transmission system.

The object is achieved with the means specified in claim 1. Further developments result from the subclaims,

The invention will now be explained in more detail with reference to the drawings, for example.

Show it:

Fig.1 shows the data and clock signals of such a system with measures to correct errors,

2 shows a simplified block diagram of the for understanding the invention relevant part of a data receiving station and

3 shows a more detailed block diagram of the in the arrangement shown in Fig.2.

The signal form a in FIG. 1 shows part of an asynchronous data stream to be transmitted in the NRZ coding (NRZ = non-return-to-zero) whereas b shows the line clock whose Frequency, as can easily be seen, is far higher than the bit rate of the data. With this frequency difference each two consecutive data bits close one

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Number of clock periods of the line clock that are not must be constant, but can fluctuate by 1 from one pair of consecutive bits to the next pair. The waveform c shows the link between the data stream a and the line clock b, namely the data transmitted on the line.

The signal form b shows the data of the signal form c as they are received at a receiving station, namely, for example, with two transmission errors A and B. Data stream for each set of the η last elapsed periods of the line clock are counted. In the present case, n = 7, and the majority for the majority decision is 4. As shown at e, this causes the error A to be eliminated within the period of the 1-state, as shown with a ¹ dashed line, while the error B is eliminated , as shown with B ¹ , delaying the end of the first 1-state by one period of the line clock result. The signal form f is the recovered data clock pulse train on its recovery, as will be described below, depending on the received data stream, the present invention relates.

The signal form g shows the data of the signal form e obtained by majority decision, as they are after a first restoration synchronization occur. As you can see, the transition delay is caused by the transmission error B was eliminated. This is shown with B ″. The data obtained by majority decision according to their last synchronization finally shows the signal pulse sequence h,

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and you can see that the normal correspondence with the Data clock is restored, as indicated by C, i.e. the data transitions coincide with the increasing ones Clock pulse edges.

2 will now be described. As "mentioned earlier, is the frequency of the line clock (b) is not an integer multiple of the original data bit rate, so that some of the received data bits include one clock pulse period more than others. In addition, the data and the Line clock, although their frequencies are usually fixed and therefore they are synchronous with each other over a long period should be, in reality, slightly asynchronous to each other are due to tolerances of these two frequencies. The present transmission system aims to address both of these factors Take into account. '

Because the data is in a serial NRZ bit stream via the Line, the only information about the clock rate of the data is in the transitions of the line status. In such a system it is common to insert a synchronizing preamble into the transmitted data stream, if a series of consecutive bits with the same logic level takes longer than a predetermined time t lasts. This is necessary because with such a data stream the line remains in a single state for a relatively long period and the receiver thus has no way of maintaining synchronization when no such action is taken. In this way comes at least a data transition frequency of 1 / t a contribution to the clock information to the receiver.

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Thus the system works under the following conditions:

a) transmission errors (up to a specified limit)

b) Data bits of unequal length

c) Asynchronism between the data and line clock frequencies (up to a given limit) and

d) at least 1 / t data transitions per second.

In the arrangement according to Figure 2, the line clock, its Frequency a multiple of the bit rate (Fig. 1) is applied to a multiplier 1 with a phase-locked loop, whose output signal is in turn fed to a clock divider 2, which generates the recovered data clock pulse sequence (f, Fig. 1) supplies. This has a frequency which is equal to the nominal data bit rate and is thus lower than that Frequency of the line clock.

The received data pass to a phase comparison circuit 3, to which the recovered data clock pulse sequence is also sent is created. This phase comparison circuit 3 represents differences between the times of the transitions of the Line status and the times of the rising edges of the output signal of the clock divider 2 fixed. That The result of this comparison is transmitted to a unit 4, which is referred to as “transmission error reduction” Phase shift control 5 applied, which adjusts the phase of the pulses generated by the clock divider 2. As with 3 will be explained later, there is a phase difference ignored if it is less than a specified amount

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This means a "synchronization window", outside whose synchronization error is only taken into account.

In addition to the control loop, which the units 3, 4 and 5, there is a second control loop which controls the amount of the necessary for phase error detection Information changed in relation to the amount of clock information received. This control loop contains a Clock monitoring unit 6, based on the number of transitions in the incoming information, the amount of clock information determined in the data and the phase shift control 5 via a phase error control 7 accordingly influenced by this amount of timing information.

Now that the arrangement that is to ensure that the Data clock pulse sequence of the receiving data station is correctly synchronized, is described very briefly, let that be considered in more detail shown block diagram according to Figure 3. Here is the data after following the above mentioned Majority decisions have been submitted to a transition detection circuit 10 and from there into the main control loop fed to a unit 11 in which the synchronous data transitions are suppressed. this happens under the control of the clock counter 12, which the recovered Data clock pulse train delivers, via a unit for determining the synchronization window. This unit 13 is controlled by the clock counter 12 so that data transitions, which are within the synchronization window are blocked in the unit 11. As mentioned earlier, this is

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Synchronization window around the rising edge of a clock pulse arranged that this edge is in its center, and a data transition is considered temporal considered correctly if it is within this window period.

The output of the unit 11 for eliminating synchronous transition therefore consists of signals, each of which corresponds to a data transition that occurs outside of the synchronization window. These signals are subjected to a phase error counter 14 supplied, which the above-mentioned up-down counter is. This unit contains a logic circuit, which from the output signal of the clock counter 12 so it is controlled that the phase counter counts up or down by one counting step, depending on the time Relationships between the data transitions on the line and the rising edge of the data clock pulse. if the data transition comes too early, the counter in the unit 14 is switched back by one counting step, and if the data transition comes too late, the counter is incremented by one counting step.

The phase error counter unit 14 has two outputs. An exit is connected to a detector 15 for the counter reading -N and the other to a detector 16 for the counter reading + N. When the counter 14 is incremented by N counts in one direction has been, one of these two counters responds and thus indicates that the threshold of the phase shift has been achieved. It should be noted that neither of these two detectors responds if such a sequence of

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Nonsynchronous transitions occurred alternately before and after the synchronization window lie. When it responds, each of these two detectors gives a signal to a unit 17 for resetting of the phase error counter, the output signal of which resets the phase error counter 14 in such a case.

The clock counter 12 receives its input signals normally from the line clock generator via a multiplier 18 with a phase-locked loop that generates an intermediate clock pulse sequence produced whose frequency is equal to a multiple of the frequency of the line clock. This intermediate clock pulse train is fed to a phase delay unit 19, which it remains unchanged during the synchronous operating state runs through to the clock counter 12, which works as a divider in this case, and the recovered data clock pulse sequence supplies.

If, due to the forwarding of the Phase error counter 14, the detector 16 emits an output signal for the threshold value + N, the phase delay unit blocks 19 a predetermined number of pulses of the originating from the multiplier 18 intermediate clock pulse train their way to the clock counter 12, and thus causes a phase delay in the cycle counter 12 and in its output signal, of the recovered data clock pulse train. However, if the detector 15 responds for the lower threshold value -N, so causes its output signal via the unit 20 for phase forward shift, that the clock counter 12 is a predetermined number of pulse periods earlier than normal resets, which is a phase shift of the

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Clock counter and its output signal, the recovered data clock pulse train caused.

To the second shown in Fig.1 with the units 6 and 7 Describing the control loop from an appropriate point of view will now be the main features in operation of the digital data transmission system briefly explained again.

If a data transition is detected, the currently existing phase of the recovered data clock is checked, and if the transition occurs within a short time interval, the synchronization window set centrally around the rising edge of the clock pulse, see above nothing else happens, since the clock is considered to be synchronous in this case. But if it is found that a data transition occurs outside the synchronization window, the counter reading of the up / down counter is of the phase error counter 14 is changed by one counting step. When the data transition during the high level of the recovered data clock pulse sequence, i.e. if it comes too late, the count of the phase error counter becomes 14 increased and vice versa. So if the data clock and the data are not synchronized with each other, it grows a count in the phase error counter 14, and its sign indicates the direction of the mutual phase deviation at.

If the count in the phase error counter 14 has reached the phase deviation threshold N mentioned above, then

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shifted the phase of the recovered data clock pulse train by a fixed amount in a direction starting from Sign of the counter reading is determined. This is done with the help of a suitable control unit for the cycle counter 12. In addition, the phase error counter 14 is reset and the cycle repeats itself if the phase shift that has been carried out does not yet sufficiently compensate for the phase error has reduced.

Since one transmission error bit usually two erroneous Transitions of the line state caused, but only one more after the data signal of the majority decision (Fig.1) has been subjected, this is done by the majority decision obtained data signal is used as the source of information about the data clock. A bug in The majority decision is then typically a data transition that increases by one pulse period of the line clock occurs early or too late. Such an error in otherwise synchronized data can fall outside the synchronization window and thus the phase error counter 14 by one raise or lower. In the case of accidental errors, an approximately equal number of transitions too early and too late should be used occur, so that errors in the majority decision compensate each other in the phase error counter and thereby to the contribute little to the effective level of error. The accuracy of the recovered data clock pulse train is therefore beneficial regardless of transmission errors.

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As already mentioned with reference to FIG. 1, the ratio is between the line clock frequency and the data bit rate is not an integer, so that some periods of the recovered data clock pulse train comprise more periods of the line clock than others. The synchronization window is usually not wide enough to accommodate both To accommodate bit lengths / which sometimes actuates the phase error counter. In the practical case, that takes place System to equilibrium when there are equal numbers of transitions before and after the synchronization windows.

Asynchronism between the data and line clocks due to clock tolerances can result in a gradual phase shift between the data clock and the recovered data clock pulse train. If it did so Phase shift is large enough, the phase error counter effects a phase shift of the recovered Data clock pulse train to improve synchronization. In this way, the recovered data clock pulse train remain permanently adapted to the asynchronous data.

The requirements for the optimal phase shift threshold of magnitude N lead to a problem. this will again solved by letting the amount N be a variable parameter that depends on the frequency of the transitions between two limit values N. and N controllable

min max

is. This threshold becomes equal to the number of transitions which occur in the time t, the meaning of which is explained above. Thus the phase shift

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Threshold value usually updated at intervals of t, except when Ntransitions have been received

Max

are before the time t has expired, the threshold value N is set and the transitions counter and the time period t are restarted.

For this purpose, the unit 10 has to recognize data transitions in Figure 3 a second output, which is connected to a logic unit 21 for determining the frequency of Transitions is connected, this connection directly and not via the unit 11 to eliminate synchronous transitions runs.

The logic unit 21 for determining the frequency of the transitions is a counter which adds up the number of transitions of the line status received since it was last reset. This counter reading is applied to a holding memory 23 for the phase shift threshold value and to a control unit 22. This control unit 22 passes from the I / eitungstakt a pulse t and checks whether the output signal of the logic circuit 21 has ^erreicnt the limit value ^N max for determining the frequency of transitions.

When either the time t has expired or the limit value

If it is sufficient, the control unit 22 switches Max

that which is just present at the output of the logic unit 21 Output to a latch 23 for the phase shift threshold through and resets itself as well as the counter in logical unit 21. The The output of the latch 23 now holds an updated value of + N, and this value remains until again

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the time t has elapsed or N has been reached in the counter of the control unit 22. The corresponding value for -N A complementing unit 24 supplies on the basis of the corresponding value + N.

By having the phase shift threshold a Can be dynamic variable, which is determined by the second control loop, can be those placed on the system Meet performance requirements more easily.

In this way it is with a low frequency of transitions by means of a low phase shift threshold it is possible that the system keeps its phase adapted to the asynchronous data, and with greater frequencies of transitions allows a higher phase shift threshold effective troubleshooting.

To complete the troubleshooting, takes over the falling edge of the recovered data clock pulse train the majority voting data in the middle of each data bit in its time grid, since this point in time is in a bit obtained by majority decision is the one that is least likely to have been corrupted by transmission errors. Finally you can the data are taken over again with the rising edge of the recovered data clock pulse sequence in a time grid the normal coincidence with the beat is achieved. After all received data bits the Data stream are fed to its actual processing.

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Neglected output errors are caused by phase errors between the data and the data clock, so improvements in clock recovery do not affect the output error rate. However, improvements are possible in the area of clock jitter in certain cases. So could, as well as the phase shift threshold value N is controlled depending on the frequency of transitions, in order to optimize the Fehlerstörfestigkeit _{t is} the step size of the phase shift to be changed one of two types as described below.

In the first of these two possibilities, if the transition frequency exceeds that which is necessary _{to achieve N = v} , there is a phase shift

IUcIX

frequency possible, which exceeds that which is necessary to overcome the assumed asynchronism. Instead of allowing a greater maximum asynchronism, as happens in the arrangement described above, the step size of the phase shift can also be reduced. This can compensate for the possibility of an increased frequency of phase shifts, so that the maximum permitted value & of the asynchronism between the data clock and the line clock remains ^{unchanged at 1.}

In the second of these two possibilities, means are provided to approximate the size of the phase error instead of taking the phase error counter at every transition outside of the synchronization window to advance one. This is done using additional phase counters and a more complex logic for determining the Synchronization error. Every unsynchronized transition

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controls that for the appropriate band of phase error
responsible phase error counter. The step by step of the
The phase shift caused by a phase error counter which reaches + U or -N changes in such a way that counters assigned to a larger phase error band are shifted by larger amounts and vice versa.

The second of these two possibilities is the more comprehensive, since jitter reduction would work for all data transition frequencies, but it is difficult to apply or optimize. The first of these two methods has the advantage of simplicity in terms of analysis and optimization / but since you usually only need a low frequency of data transitions for N to reach the limit value N ^ _v ,

in α χ

so is its effect, which only occurs when there are frequent transitions sets in above this level, not a big advantage.

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Claims (5)

Dipl.-Phys. Leo Thul
Short Street 8
7 Stuttgart 30 K. Caves 6-1 INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK Claims iy device for clock recovery in a receiving station of a digital data transmission system from the digital data received in the receiving station and the line clock of the data transmission system, in which a data clock pulse sequence is derived from the line clock, the frequency of which is equal to the nominal bit rate of the received data, characterized in that it has a unit (10) that monitors the received data stream for state transitions, that it contains a comparator (11, 13) which compares the times of each of these transitions with the phase of the data clock pulse sequence that is currently present, and an up / down counter (14) advances by one step if a transition is outside a predetermined time interval related to the phase of the data clock pulse sequence, the direction of this advancement depending on whether the transition occurs before or after the time interval, and that means (15, 16 ) are present, the firmest llen whether the count of the up / down counter (14) has reached a lower (-N) or upper threshold value (+ N) when advancing in one direction or the other, and in this case the phase of the data clock pulse sequence derived from the line clock in a Kg / Sch
11/30/1 * 78 909826/0690 Change direction depending on whether the upper (+ N) or the lower threshold value (-W) has been reached. 2. Device according to claim 1, characterized / that the up-down counter (14) has two outputs, one of which with a detector (16) for the upper threshold value (+ N) and the other with a detector (15 ) is connected for the lower threshold value (-N), and that each of these detectors (15,16), when the reading of the up-down counter (14) is equal to its set threshold value, emits a signal that in addition to the phase change a Resetting the up / down counter (14) causes it to go to rest. 3. Device according to claim 2, characterized in that the data clock pulse sequence, the phase of which is to be adjusted, is derived from an intermediate clock pulse sequence with a frequency which is high compared to the data bit rate by the frequency of the intermediate clock pulse sequence in a clock counter (12) is divided in such a way that the data clock pulse sequence arises that the intermediate clock pulse sequence is fed to the clock counter (12) via a phase delay unit (19) which responds to an output signal of the detector (16) for the upper threshold value (+ N ) blocks a predetermined number of pulses of the intermediate clock pulse sequence and thus causes the required phase delay and that the output signal of the detector (15) for the lower threshold value is fed to a unit (20) for phase forward shift, which the clock counter (12) by a predetermined number of pulse periods of the intermediate clock pulse train resets earlier than usual and thus the required phase nforward shift causes. 909826/0690 K. Caves 6-1 4. Device according to claim 3, characterized in / that the intermediate clock pulse trains are derived from the line clock by means of a multiplier (18) with a phase-locked loop. 5. Device according to one of the preceding claims, characterized in that the upper (+ N) and the lower threshold value (-N) for the phase shift depending on the frequency of the state transitions of the received data stream in terms of amount between a lower (N.) And an upper Limit value (N) is adjustable. IUaX 909826/0690