DE2849500A1 - DATA PROCESSING SYSTEM - Google Patents

Description

The present invention relates to a data processing system according to the generic term of claim 1 and in particular to a micro-programmed data processing system.

Micro-programmed data processing systems use for the purpose Reduction of the control store size in general techniques by which the execution characteristics of the program instructions is changed. These techniques include the use of conditional branch microinstructions that represent the states of various Test indicator circuitry to determine the appropriate sequence of microinstructions to use to execute the operations specified by a special program instruction required are. It is thus possible to use common microinstruction sequences and thereby the size of the control memory to reduce. Another system uses a second control store that holds a pair of addresses for the Saves definition of start and Zius guide micro-instruction sequences, thereby enabling the greatest possible number of microinstruction routines to be shared and increasing the size of the control memory used to store the microinstructions is reduced. This system also allows new commands to be added without requiring changes to the logic circuitry are. For more information about this system, please refer to the; See U.S. Patent 4,001,788.

While the aforementioned systems have considerable flexibility and size advantages, is the overall performance of such microprogrammed data processing systems lower than that of non-microprogrammed systems. A microprogrammed unit of a system comprises a control memory and a hardware switching circuit, dor on the basis of a / idrosse or control signals from the memory together with 7, ui; tand <; signals additional fixed micro-operation. '; - anwoi r.uncjcn generated at higher speeds. Through this will the? GrüiW; dos nornwilorwei.se required micro-programs

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reduced when processing a special program command. This system is shown and described in greater detail in U.S. Patent 3,872,447. During this system the performance increased, the number of microinstructions that can be obtained from a microinstruction is expanded without any length expansion of the microinstruction would be required. There are thus changes in the hardware switching circuit for different or. new command requirements required. Furthermore, the hardware upgrade circuits very complex when sequences have to be considered for a very large number of instructions.

In the case of high-performance flow systems, these lead additionally typically commands which are stored in buffer units in such a way that for each predetermined Time more than one command is actually being processed. The operation sequences can thus also buffer memory cycles which makes the instruction decoding more complex. the Use of the above-mentioned system proves to be inappropriate here.

It is therefore an object of the present invention to provide a to create a microprogrammed control unit which is able to work together with a high-performance data processing system.

The performance of a microprogrammed control unit becomes even more important in the case of high performance flow processing systems. Such systems typically execute commands that are stored in an Ilochgen speed buffer Small capacity memories are stored in such a way that more than one instruction is given for each given Time is processed. Since commands can be fetched from memory faster, this leads to the increased performance.

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In order to maintain the performance of such systems, it has heretofore been common practice to use non-microprogrammed control units to be used. The reason for this is that microprogrammed control units for the effective control of a data processing units operating in flow mode are not very suitable, although these units are devices that increase the working speed. However, it has been found that they are non-microprogrammed Control units are more complex and changes in hardware circuitry when changing the commands.

To that for the decoding and execution of program instructions To reduce required time in a control store, a processor utilizes in addition to the typical control store a second control store similar to the first. The second memory is connected to the command register via a multiplexer connected to receive part of the program instruction to be decoded, the part and its format by the multiplexer can be specified. In addition to addressing the control memory, the second memory can be used, to implement the part selected by the program instruction so that it forms part of the output microinstruction specified in the decoding sequence is generated.

The aforementioned device is shown and described in U.S. Patent 3,953,833. While this arrangement is the for the decoding of the program instructions reduces the time required, additional circuitry is required to select some of the commands for decoding and format. There v / o the number of possible operations specified by the program commands is also large requires a number of unique microinstructions.

It is therefore the object of the present invention to provide a mikroprograir.mLerbaL-o Control unit to .shafts, dLe reducers: tr. requirements i in the memory. He 'is also the task

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of the present invention, a micro-programmable control unit to create that has an increased machining performance.

The solution to this problem succeeds according to the in one of the independent Claims characterized invention. Further advantageous refinements of the invention are set out in the dependent subclaims removable.

The present invention provides a data processing system with a micro-programmable data processing unit for carrying out data manipulations under the control of commands, the command processing being carried out in a continuous manner and each command being processed in a number of different operational phases until it is fully processed, the data processing unit having: several Register for storing instructions to be processed, each instruction being a multi- bit operation code; a first addressable control memory connected to a first register for receiving signals corresponding to the multi-bit operation code of an instruction to be processed, which has a plurality of memory locations, each of which stores a word with at least one multi-bit control sequence code which has fewer bits than the operation code and an address wherein the control sequence code specifies a number of hardwired control sequences and the address specifies a first microinstruction in one of several processing sequences;

a cyclically addressable second control memory with several memory locations for storing at least one microinstruction in one of different processing sequences; an address register to which the address of the first control store is supplied and connected to the second Stouerspeicher is to read the microinstruction content of a memory location during a Read out operating cycle;

one connected to the second storage tank; Starting ro - gistor for the temporary storage of the operating cycle excluded microinstruction contents;

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a hard-wired control status update device connected to the first control store for generation different control signal sequences, which are different to be executed for each command during a first phase of operation Define operations, the incremental device by each control sequence code within a certain due to the Operation codes of a processed instruction read class is enabled, a predetermined sequence of control signals for the execution of the operations during a first instruction phase to generate the address in the address register for continued processing of the command under the control of the specified processing sequence and to transfer the To put incremental device in a predetermined state, the specified processing sequence being a microinstruction comprising a restart code bit pattern; and to the hard-wired control state incrementer and decoding circuits connected to the output register which, when reading out the restart code pattern from the second Control store in the output register signals for switching the incrementing device from the predetermined one to another Generate state to continue command processing.

According to a further aspect, the invention creates a micro-programmable data processing unit, which includes:

A number of registers, with one of the registers being the storage an instruction to be processed is used and the instruction has a multi-bit operation code;

a first addressable control memory with several memory locations, one memory location being provided for each different instruction operation code and this at least comprises a multibit control sequence field, a control register field and an address field;

a cyclically addressable second control memory with several memory locations for storing at least one microinstruction within several processing sequences;

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a sequence control circuit connected to the first control store to generate a sequence of control signals that is determined by the coding of the control sequence field, v / elches is contained in one of the storage locations and due to a command opcode is read out; a register section with several accessible to the program Registers; and

one to the registers, the first control store and the sequencer circuit connected output selection device, which on the basis of the control register signals generated by the register field, the register field being read out by a corresponding instruction opcode, one of the registers selects and the memory location within a memory location group of the register field an address field for reference to the same processing sequence for processing the operation execution specified by each instruction opcode having.

According to a further aspect of the present invention, a micro-programmable data processing system is provided, this includes:

A plurality of registers, one of the registers being used to store instructions to be processed and the instruction having an operation code;

a first addressable control memory with several memory locations, Each memory location is used to store different instruction opcodes and these at least one Multibit control sequence field, a constant field with a number of bits and an address field; a cyclically addressable second control memory that is connected to the first control store is connected and several memory locations has a plurality of processing sequences for storing at least one microinstruction;

sequence control circuits connected to the first control store for generating a sequence of control signals, which is determined by the coding of the control sequence field in the

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Storage space is included due to each instruction opcode is read out, the control sequence circuits bistable storage devices for the storage of Include signals corresponding to at least one bit of the constant field of the memory location and the bit signals through Their coding defines the differences in the operations, as indicated by differently coded instruction opcodes are defined; and

an execution unit for executing the operation codes provided by the instruction specified operations under the control of microinstructions of the processing sequence as indicated by the address field of the memory location read out from the second control memory is set, the execution unit being connected to different Register and the bistable storage devices is connected and enabled by the bit signal will edit the operations carried out by each of the different coded opcodes are set without a further test of the opcode of the one being processed Command would be required.

According to a further aspect of the present invention, a data processing system is provided with a buffer storage device, a command processing device and a command execution device, wherein the system data manipulations executes under the control of commands, processing of the commands proceeds in a sequential fashion and each instruction in a number of different successive phases of operation until it is completed is processed and wherein the command processing device comprises:

Multiple registers for storing from the buffer storage device received commands to be processed, each command having an opcode having a first number of bits;

a first addressable control store connected to one of the registers for receiving signals corresponding to the opcode to record an instruction to be processed with

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several memory locations for storing a word with at least one control sequence code and an address, wherein the control sequence code has a second number of bits the number of which is less than the first number of bits, which by their coding define a number of hard-wired control sequences, and where the address is one identified the first microinstruction within one of the processing sequences and connected an output register to the memory is to store the word content of a memory location specified by the operation code; a control sequence decoding circuit which is connected to the output register of the first control memory and which Decoding of signals according to the control sequence code; and

a hardware control sequencer connected to the control sequencer decoder circuit for generating control signal sequences to execute those to be executed during selected phases of command processing Define operations; wherein the first control store denotes an instruction stored in the first register on the basis of each operation code Reads out the content of a predetermined memory location in the output register of the first control memory and wherein the decoder circuitry based on the control sequence code enables the hardware control sequence device to a to generate a predetermined sequence of control signals required to complete the operations of so many different Phases as possible under hard-wired control and the transfer of control to the execution sequence that is served by the address read out from the predetermined memory location is fixed.

In a preferred embodiment of the invention, a micro-programmable control unit comprises first and second addressable control memory. The first control store that initially addressed by the opcode of a program instruction is used to set a predetermined constant field to save that by its coding that by the

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Operation code specifies the operation in more detail, with a control sequence field and an address field still serve to further control operations. The second control store stores several microinstruction sequences for processing of the repertoire of program commands.

In the preferred embodiment, hardware decoding and Incremental circuitry within the control unit enabled by the control sequence field to execute part of the program instruction to process, with a completion of the partial processing of the command the control on the second Control memory is transferred to the command processing under To finally complete microprogram control.

According to the preferred embodiment, the hardware sequencer circuits load Signals corresponding to the constant field in a selected register within the control unit. The constant signals influence parts of the data processing unit, so that, for example, the hardware sequence control circuits and sequencing microinstructions of the second control store the particular operation specified by the constant field can edit, this being done in accordance with the operation code of the program instruction being processed.

The arrangement according to the invention means that there are no additional Means required for decoding the instruction opcode. Of particular importance is that through the arrangement according to the invention stipulates the formation of additional unique micro-instruction sequences for similar operations Program commands is avoided.

According to the preferred embodiment, the constant field corresponding signals are loaded into a register within the control unit under hardware control. In addition, you can such signals also in other registers of the control unit

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loaded under control of the hardware sequencer circuitry or under microprogram control. Thereafter v / these signals are used / to enable various devices within the data processing unit to that specified by the instruction opcode Process operation as further defined by the specific coding of the constant field. Such an edit progresses under microprogram control.

In particular, the coding of different bits of the constant field shows the differences between the instruction opcode and another opcode. Such bits indicate that the instruction is functional with another Instruction that has a different opcode. As noted, the specific Differences between the two commands are indicated by the code of the constant field. For example, one bit of the Constant field determine by its coding whether the instruction operation code an operation with data in alphanumeric or determined in numerical form.

Furthermore, the coding of the constant field for certain commands, such as floating point and transfer commands, used to define the results or the type of operation specified by the opcode. For example indicates a first bit of the constant field by its coding whether a. Result requires normalization, While a second bit, through its coding, indicates whether the loaded or stored value is to be rounded off. In the event of of transfer or branch instructions can be the first bit can be used to define the condition on which the branch is to be performed. Furthermore, in the case of certain Commands the second bit can be used to define the format of the operand data to be handled (floating point or fixed point). Allow the different codings of the constant field the use of the same sequence of microinstructions for processing different program instructions.

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The preferred embodiment includes one based on a buffer memory Aligned micro-programmed high-performance data processing unit that works continuously, which is an execution unit for executing program instructions and a device for calling up instructions and data of storage system oriented towards a buffer storage.

According to the preferred embodiment of the present Invention, the address field of each memory location of the first control store is coded in such a way that it is the starting memory location defines a sequence of micro-instructions in the second memory, the micro-instruction sequence for processing operation as specified by the instruction's opcode. The control sequence field is encoded to have fewer bits than the opcode and is a set of predetermined hardware control sequences specifies to be executed by the hardware sequencer circuitry for an instruction.

In operation, the operation code of each instruction is fed as an input to the first control store, with the Content of a predetermined memory location is accessed. Signals corresponding to an address field and a control sequence field are read out. The decoding circuit decodes the bits of the control sequence field and generates signals representing the Enable ilardware control sequencers to send control signals for the execution of a series of operations during a series of hardware operation cycles as they generate are required for command processing. For each command, the hardware sequential control circuits transmit when completing ι Constant of the hardware sequence automatically the control on a "j sequence of microinstructions, which in the second control memory un-.; tor the start address is stored, diä by the from the first control memory read out address signals is specified. This micro instruction sequence is used to complete the instruction ■ ' editing. . .

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In the preferred embodiment of the present invention, certain classes of sequences are established that correspond to the Specify the type of service for processing the entire command repertoire in a flowing manner. For one effective flow operation (command processing in a sequence) It is important that the performance of the execution unit match that of the instruction fetcher for efficient flow processing is adjusted.

According to the preferred embodiment, a number of classes of established sequences define the different ones Types of buffer storage operations, the classes being selected to allow decoding of the buffer storage cycles requiring commands is facilitated. For example, the sequences include single loads, double loads, Single store operations, double store operations, and effective address operations. All different orders in the repertoire that require the execution of a given sequence, e.g. a single load sequence, are within included in this class. If certain consequences, such as If a single loading sequence is set, command processing proceeds primarily under control through the hardware sequencer circuitry.

In any case, the operation code of each such instruction calls for the content of a memory location to be read out the first control store which contains a control sequence field with the same coded bit pattern. For those orders The operations that require the execution unit to require multiple cycles are determined by different hardware sequences the coded control sequence fields. Deliver these consequences the additional cycles required to maintain synchronism between the operation of the execution unit and the fetcher maintain.

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In addition, each command is assigned a hardware sequence that allows command processing under hardware control as possible before instruction processing proceeds under microprogram control. By adapting the Commands to such sequences will increase the overall performance of the data processing system brought to the maximum. Since certain commands are automatically executed primarily under hardware control the performance of the processing units is also increased as a result. This is achieved through the Maintaining the flexibility of a micro-programmed unit, new commands can be added or changed without corresponding changes to the Hardware must be made.

Since the arrangement according to the preferred embodiment specifies a limited number of sequences that normally used by a group of instructions also requires decoding of the instruction's control sequence fields no buffer cycles, so that address development is easier will. In addition, the scope of such decoding circuitry is increased considerably reduced while still maintaining the desired flexibility and performance.

During the command cycle of different program commands, such as load and store instructions, the contents of the control register are used to operate the various register control circuitry to be able to select a register accessible to the program for the operation. In the preferred embodiment, the registers include registers for the accumulator (A), the quotient (Q), the index (XO, X1 ...) and the command counter (IC). The device according to the present invention allows it to be carried out a number of processing micro-instruction sequences common to a group of program instructions. For example there are groups of instructions that perform the same operations on different groups of registers. If the register control field is coded

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selects the special register, all program instructions within the group can use the same microinstruction, selected for processing by the address field.

Furthermore, the register control field can also be used for control the operation of the register-occupied hardware circuitry. Such circuits are normally used to update the various registers accessible to the program from the first cycle (I cycle) up to a last cycle (Ε cycle) of the flowing operation to keep it up to date.

In the present case, the register control field is decoded and selects the data to be stored in a number of occupied registers are to be loaded within the occupied hardware circuits. The register control field can be used when it is decoded specify that none of the registers is occupied, that a single register is occupied (e.g. A, Q, XO, X1, etc.), that the A and Q registers are used in this order or that the A and Q registers are used in the reverse order are. The arrangement according to the present system avoids additional extensive circuitry for the decoding of the different operation codes of certain program instructions or additional micro instructions for testing the values of the Opcodes.

The register control field can also be used to provide a constant value as in the modification of the address content of the program instruction counter of the data processing unit is used. In the case of certain program commands, As with multi-word commands, for example, the register control field can determine the value through its coding, to be added to the command counter content. Again, this avoids the need for additional circuitry for the further decoding of the instruction opcodes.

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From the above it can be seen that the preferred embodiment is the micro-programming of a control unit, which is constructed according to the teaching of the invention, relieved. A major advantage of the invention The arrangement is that it provides great flexibility in controlling the operations of various registers. Controlling a number of different register operations increases the size and number of additional decoder circuitry reduced.

For each program instruction that is not during a flow-through operation can be edited, the control sequence field referenced by the command indicates through its Coding a predetermined bit pattern. Decoding circuitry decodes this bit pattern, whereupon the hardware control sequence circuitry switch to a predetermined state, which is referred to as the escape state. In this State, the cardware control sequencer transfers control to the microinstruction sequence as indicated by the address field is specified in the relevant storage location.

The processing of the program command then falls below Microprogram control continues while the hardware control sequencers remain in the escape state. When reading out of a microinstruction with a restart field, the decoder circuitry disconnects the hardware control sequencer the escape state back to a state in which the Flow operation is started again to command processing to continue.

The restart field defines the type of restart conditions through its coding. For example, a first encoded bit pattern of the restart field a restart, the flow operation, whereby the command processing starting with the next command after the transmission or Release of control is added to the hardware control sequence circuits.

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The type of restart mentioned above is used for those types of instructions where it is possible to guess when the processing of such commands will be completed. In such cases, a microinstruction is in a predetermined location encoded within the sequence of microinstructions so that it has a restart field which, by its encoding, is the first coded bit patterns. The location is chosen so that there is continuity with respect to the instruction work cycles is guaranteed. In the preferred exemplary embodiment, a point is selected at which the read-out microinstruction signals start again at a point in time that corresponds to the time interval is approximate that required for the instruction to pass through the various stages in the flow-through processing is. For example, the flow stages of instruction processing and buffer processing require one Time interval of 2T and the restart field is contained in a microinstruction that occurs at a time 2T before completion the processing phase of this command is. There are thus no idle cycles or interruptions in the flow operation.

According to the preferred embodiment, the second and third encoded bit patterns of the restart field call for a restart the flow-through operation, with the command processing of the same or current command at a special point resumed by setting the hardware control sequencer is specified in a certain state after the control transfer to this.

The type of restart noted above is used for those types of instructions which specify certain types of operations which cannot be efficiently processed during a flow through operation and which require additional operations which can be quickly performed by the hardware control sequencer. For example, those commands include multiple address. Descriptor parts, one of the addresses specifying an indirect operand address which requires additional address development. ₉₀ g _823/05 g ₂

In the preferred embodiment, for each of these commands, the hardware sequencer circuits occur upon completion part of such an order enters the escape state. After that, the additional surgery is under Microprogram control is processed by the sequence of microinstructions specified by the address in the first control store is. Within the selected microinstruction sequence there is a microinstruction which, due to its coding has a restart field which defines second and third coded bit patterns. After the execution of the sequence of microinstructions, microprogram control is released and processing of the same instruction continues under control of the hardware sequencer circuitry.

A fourth encoded bit pattern of the restart field causes a restart to occur when the hardware control sequencer have been placed in a predetermined state and processed certain types of program instructions will. In the preferred embodiment, the command buffer of the processing unit is reloaded with commands, which are predetermined by the content of the instruction counter of the processing unit, and processing begins with a first Command in the buffer. The microinstruction that has this type of restart due to its coding occurs in the Sequence of microinstructions that follow the microinstructions dictating the loading of the instruction counter address.

Other encoded bit patterns of the restart fields permit a restart of the flow-through operation as indicated by the restart field is signaled within a first microinstruction of a microinstruction sequence, this being done before the complete one The command is processed under microprogram control. This is how the hardware control sequence circuits perform an instruction cycle and then a buffer cycle followed by waiting for further operations to be released is done by the restart field in a second subsequent microinstruction within the sequence. This allows one

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more efficient processing of certain types of program instructions, such as floating point arithmetic and shift instructions.

From the foregoing it can be seen that the preferred embodiment is the selective transfer of control from the hardware circuitry on the microprogram control during the continuous processing of program instructions and the restart such a continuous operation. In accordance with the teachings of the present invention, a number of different Restarts can be specified under microprogram control, which enables efficient processing in the event of a A large number of different types of program instructions with different formats and different requirements are ensured v / ird.

The device according to the invention enables a considerable Flexibility in the types of commands that can be processed. It also simplifies micro-programming such program commands as well as new program commands if the command repertoire has to be supplemented.

Based on one shown in the figures of the accompanying drawings Exemplary embodiment is explained in more detail below, the invention. Show it:

Figure 1 is a block diagram representation of a system employing the principles of the present invention.

Figure 2 shows the central processor 700 and the buffer memory

750 according to FIG. 1 in a block diagram representation.

FIGS. 3a to 3i show the various blocks according to FIG. 2 in greater detail.

4 shows the buffer unit 750 according to FIG. 3i in greater detail Details.

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5a to 5e the lines forming the interface according to FIG. 1.

FIG. 6a shows the format of the control store control unit according to FIG. 1.

Fig. 6b shows the format of the microinstruction words of the processing control Memory according to FIGS. 2 and 3.

7 shows a status diagram for describing the cardware advancement the device according to the invention.

Fig. 8 is a diagram for explaining the flow operations of the processor 700 in processing various series of instructions in accordance with the present invention.

FIGS. 8a to 8d show the formats of certain types of commands, such as they are used to describe the operation of the present invention.

Figures 9a through 9c schematically illustrate certain aspects of the operation of the preferred embodiment according to the present invention.

FIGS. 10a to 10e show the starting flow operations according to FIG of the present invention.

Figure 11 is another diagram useful in explaining the flow operations of the processor.

12a and 12b a schematic representation of further Aspects of Operation of the Present Invention.

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Referring to Figure 1, the system according to the present invention comprises at least one input / output processor (IOPP) 200, a system interface unit (SIU) 100, a high-speed multiplexer (HSMX) 300, a low speed multiplexer (LSMX) .400, a central processor 700, a buffer memory 750, at least one memory module corresponding to an internal memory module 500 and at least a memory module corresponding to an external memory module 800. Various of these modules are each connected to one off a number of connections of the system interface unit 100 via a plurality of lines, which in turn different types of interfaces 600 to 603 form. In particular, the I / O processor 200 is the buffer memory 750 and the high speed multiplexer 300 are connected to ports G, E and A respectively while the low speed multiplexer 400, the internal memory module 500 and the main memory module 800 to the ports J, LMO and RMO are connected accordingly. The central processor 700 is connected to the buffer memory 750.

The I / O system of Figure 1 can be viewed as a system comprising a number of "active modules", "passive modules" and "memory modules". The I / O processor 200, the central processor 700 and the high speed multiplexer 300 work as active modules as each has the ability to issue instructions. The active modules are usually connected to ports A through H, while the central processor 700 is connected to port E via the buffer unit 750 and Interfaces 604 and 600 is connected. Several passive modules are connected to junction points J, K and L. These modules are given by the low speed multiplexer and the system interface unit 100 and they are capable of interpreting and executing instructions that are supplied on the lines of the interface 601. The last group of modules is made up of the internal memory modules and formed the main memory modules that are able to process two different types of instructions,

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which are fed to the lines of the interface 603.

The I / O system of Figure 1 normally operates as an I / O subsystem in response to the central processor 700 I / O commands issued. The connection points E and F include interfaces that allow the connection of either multiplexer or processor modules according to FIG. 1 enable. These interfaces are described in more detail.

With regard to the present invention, the central processor 700 may be constructed in a conventional manner and in its execution that described in US Pat. No. 3,413,613 Processor. In the preferred embodiment, the I / O processor 200 initiates and terminates channel programs these, where the channel programs are required for the execution of I / O commands, and it processes interrupt requests that it receives from the system interface unit receives and finally controls peripheral to the low speed multiplexer 400 connected devices. The processor 200 is via the data interface 600 and the interrupt interface 602 connected to the connection points G and H.

The low speed multiplexer 400 may also be of conventional construction in view of the present invention. It is used to connect peripheral devices at low speed via peripheral adapters, with each adapter being connected to the lines of a device adapter interface (DAI). The interface and adapter can be of the type described in US Pat . No. 3,742,457. The low-speed peripheral devices include card readers, card punches, and printers. As can be seen from FIG. 1, the multiplexer 400 is connected to the connection point J via the programmable interface 601.

The high speed multiplexer 300 directly controls data transfer between the group of disk units and

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Tape units 309 through 312 that attach to various channel adapters to 306 are connected. Each of the channel control adapters 303-306 is in turn a channel adapter interface via the lines CAI-301-1 to various channel connection points 0 to 3 connected. The high speed multiplexer 300 is connected to connection point A via a data interface 600, a programmable interface 601 and an interrupt interface 602. Each of the channel control adapters 303-306 can be constructed as described in the aforementioned US Pat. No. 3,742,457.

System interfaces

Before the processor 700 and the buffer unit 750 are described in more detail, these according to the principles of the present invention, let us first consider the interfaces 600 to 604 with reference to FIGS. 5a to 5c.

According to Fig. 5a it can be seen that the lines shown there form the data interface 600, which is one of the interfaces for the exchange of information between an active module and the system interface unit 100 are required. The exchange of information is carried out by Realized control of the logic state of the various signal lines, this control in accordance takes place with previously established rules that are contained in a signal sequence called "dialog".

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According to FIG. 5a, the interface comprises several lines with the following meaning: Active output connection request AOPR / Data for the interface unit DTS OO-DTS 35, PO-P3, · control of data to the interface unit SDTS 0-6, P / identified Multiple connections to the interface unit MITS 0-3, P / active request accepted ARA / read data accepted ARDA; Data from the interface unit DFS 00-35, PO-P3; Multiple Port Identifier from the interface unit, MlES 0-3, P / double precision from the interface unit DPFS and status accepted AST. The interface lines are described in more detail in the following section.

Data interface lines

description

description

This line is used to transmit an / active output connection request in a direction which is from each of the active 'modules to the interface unit SIU-100

extends. If this line is set, it signals the interface unit SIU, that the module requests a transmission path over which an instruction or data is to be transmitted are.

DTS 00-34, P0-P3 These lines provide a data transmission path four bytes wide extending in one direction between each of the active modules and the SIU interface unit and which are used to transmit instructions or data from each active module to the interface unit SIU-100 can be used. ■ These lines extend from each active module to the SIU-100 interface unit. They are used to control data for

SDTS 0-6, P

9.098.23 / 0592 COPt

Interface unit and they are used to • · 'the interface unit SIU-1OO with control information • '. supply when the AOPR line is set2t is. The control information consists of seven bits and. a parity bit, which in the following Ways are coded:

a) The state of bit O indicates the type of instruction which is fed via the DTS line

will. The instruction can be a programmable interface instruction or a storage instruction.
• b) Bits 1-4 indicate by their coding,

which of the modules received the instruction

. And should interpret (storage instructions

are only through memory modules and programmable Interface instructions are interpreted by all modules except the I / O processor 200) .

c) The state of bit 5 indicates whether one or two words of instruction information are between the requesting active module and the

. selected receiving module are to be transmitted (a word determines a transmission with simple 'precision and two words determine one transmission with double precision).

d) The state of bit 6 shows the direction of the * 'transmission between the requesting module

and the selected receiving module.

e) Bit P is a parity bit generated by and by the requesting active module an arrangement contained in the interface unit SIU-100 is checked.

ITS 0-3 / P These lines extend from the active one

Module for the interface unit SIU-100. Their coding indicates which sub-

channel or connection within an active 909823/0592

DFS OOr35, P0-P3

MIFS 0-3, P

'-, 64 "

Module caused the setting of the AOPR lines ...

This line extends from the interface unit SIU-100 to each of the active ones Modules. This line is set to indicate that the selected receiving module accepted the request by the active module, thereby allowing the module to remove the requested information from the data spill lines. This line extends from the interface unit SIU to each of the active modules and it is controlled by the interface unit set to indicate to the active module that it has the previously requested data of a selected Module has to accept.

The data from the interface unit is transmitted on another set of data transmission lines which are of width four bytes and extending in one direction from the interface unit to each active one Extend module. This group of lines is used by the SIU-100 interface unit, to transfer read data to a selected active module.

These four multi-port destination lines plus an odd parity line ¹ extend from the interface unit SIU-100 to each of the active modules. These lines indicate by their coding which connection or subchannel of the active module has to receive the data of a previous read operation from the interface unit SIU-100. . This double precision line extends from the interface unit SIU to each of the active modules. The status of this line indicates whether one or two words of the read data are sent from the active module to

909823/0592

Completion of a transfer cujf are (reading instruction)

BRANCH . This line extends from the intersection

Position unit SIU-100 for each active module · and its status, which is mutually exclusive on the AROA line, signals to the active module that it has received the DFS lines Should include status information.

The lines of the programmable interface 601 are shown in FIG. 5b and they are used to transmit instructions from an active module and a selected module. The transmission is accomplished by controlling the logic states of the various signal lines. This is done in accordance with previously established rules that ^{execute a signal sequence called 'Dialog' 1.} The programmable interface comprises various lines, which are assigned the following meanings: Programmable interface instructions accepted APC / program interface data from the interface unit SIü PDFS 00-35 ,. P0rP3 / programmable interface ready PIR / request for the transfer of read data RDTR / programmable interface data to the interface unit SIU PDTS 00-35 / PO-P3 and read data accepted RDAA Description of the interface lines is given below in more detail.

Programmable interface lines

Name Description

APC 'This line extends from the cut

station unit SLU-100 to each receiving Module and, when set, it signals to the module that instruction information is sent to the PDFS lines the interface has been supplied by the interface: station unit SIU and through the module is to be included.

309823/0592

OCFY

PDFS 00-35 / PO-P3 These lines are four in width

Bytes and they extend in one direction from the interface unit SIU-100 : to each module. They carry programmable interface information to a selected receiving module from the system editing unit SIÜ-100 to. ■

PIR These lines extend from each module

to the interface unit SIU-100 and they In the set state, they indicate that the module is ready to accept a Instruction to include.

PDTS 00-35, P0-P3 These lines are four in width

Bytes and they extend in one direction from each module to the interface unit SIU-100. These lines are used to transmit programmable interface information used for the interface unit SIU-100.

RDTR This line extends from each module,

which is connected to the programmable interface, to the interface unit SIÜ-100. When set, this line indicates that the previously requested Data are available for transmission to a module and through the module the lines PDTS have been fed.

RDAA This line extends from the cut

position unit SIU-100 after each module and when set it indicates to the module that the Data supplied via the PDTS lines have been recorded and that the module has received the information can take away from these lines.

According to FIG. 5 c, the interrupt interface is the further interface 602, which is provided for interrupt processing by the I / O processor 200. This cut

909823/0592

Place allows the transmission of interrupt information from a module to the interface unit SIU-100 as well as the transmission of interruption information from the Interface unit SIU-100 to the I / O processor 200 for processing. According to the other interfaces, the Transmission of the interrupt request by controlling the realizes logical states of the various signal lines / this takes place in accordance with previously established regulators, which are executed by a signal sequence called "dialog". The interrupt interface has several Lines with the following meaning: Interrupt request IR; Interrupt data IDA 00-11, PO-P1 and interrupt multiple connection identifier IMID OO-O3 for modules connected to connections A to D. With regard to the the connections G and H connected modules has the interrupt interface furthermore lines with the following meaning: level zero present LZP; higher level interruption present HLIP; Interrupt data request IDR; Enable RLS and active interruption level AILO-2. As can be seen from Figure 5c, the interrupt interface ports G and H do not have an interrupt multi-port identifier line. A description of the interrupt interface lines is given below in more detail.

Interrupt interface lines

Name Description

IR This line extends from each module

after the interface unit SIU-100 and it indicates in the set state of the interface unit SIU-100 that it is requesting operation.
, IDA 0-3 ( PO These interrupt data lines extend

IDA 4-11, P1 differs from an active module after the interface unit SIU-100. Due to their coding, these lines contain control information,

. 'their transmission to the I / O processor

is requested when an interrupt request

909823 / Ö692

IMID 00-03

tion has been accepted by the processor. These bits are coded as follows: a) The status of bit O is signaled to the interface unit SIUrIOO, which of the two processors are processing the interrupt request target.

b) The bits. 1-3 indicate by their coding the priority or the level number of the interrupt request of the interface unit SIU-100.
c) the bit PO is a parity bit for the bits

0-3.

d) Bits 4-8, through their coding, generate part of an address, the generation of which by the I / O processor 200 is necessary for a reference to the correct procedure in the processing of the interrupt (e.g. an interrupt control blocknuiTJaer ICBN)
e) the bit P1 is a parity bit for the bits

4-11.

These leads extend from each active module according to the interface unit SIU-IOO ₁ ^ and determine, by their coding which specific sub-channel of the active module an interrupt processing is requested. This line extends from the interface unit SIU-100 to the I / O processor and, when set, indicates that the interface unit SIU-100 has sent a request with the highest priority (level zero) to the processor 200 is"

This line extends from the SIU-100 interface unit to the I / O processor 200 and it indicates in the set state that an interrupt request with a higher Level than the level of the process currently being processed on processor 200. 9 0 9 8 2 3/0592

IDR This line extends from the I / O

Processor 200 after the interface unit SIU-100 and it shows in the set state, that from the interface unit SIU-TOO on the lines DFS interrupt data after the Processor are to be sent.

RLS This line extends from the I / O

Processor 200 after the interface unit SIU-100 and it shows in the set state, that processor 200 has finished executing the current procedure.

AIL 0-2 Those carrying the active interrupt level

Lines extend from the interface unit SIU-100 to the I / O processor 200.- These lines, through their coding, give the interrupt level number on the processor 200 procedure to be carried out.

A next group of interface lines, which is used by certain modules according to FIG. 1, is represented by internal memory interface lines according to FIG. 5d. The internal memory interface 603 is used to exchange information between the internal memory 500 and the modules of the system. The exchange of information is accomplished by controlling the logic states of the various signal interface lines in accordance with predetermined rules, which rules execute a signal sequence called "dialog". The internal memory interface has a number of lines, which have the following meanings ·. is assigned: data to memory DTM 00-35, P0-P3; Data identifier to memory RITM 0-7, PO-P1 / destination lines to memory SLTM 0-3, P, * acceptance PI instruction APC / acceptance ZAC instruction AZC ₁ -Pl interface ready PIR / ZAC interface ready ZIR / transmission request read RDTR data / data from memory DFM 00-35, P0-P3 / request identifier from memory RlFM 07-, P0-P1 / double precision, read from memory DPFM / QUAD /

909823/0 * 592

Data accepted RDAA and system clock SYS-CLK. A similar Interface is used to connect the main memory module 800 with of the interface unit SIU-100.

Memory and programmable interface instructions are used transfer the same data lines of the interface. The interface v / e is not a group of lines for processing Interrupt requests, so that the connected to the internal memory via the interface unit SIU-100 • Modules cannot directly cause a memory interruption. A description of the internal memory interface lines is given below in greater detail.

Internal memory "interface lines

Designation DTM 00-35, PO-P3

RITM 0-3, PO RITM.4-7, P1

SLTM O-3, P

description

on,

These lines are 4 bytes wide (36 information lines and four odd Parity lines) which extend in one direction from the interface unit SIU-100 to the internal memory 500 extend. These lines are used to transmit memory or programmable interface instructions used to the internal memory 500. These lines form two groups of four Lines which extend from the interface unit SIU-100 to the internal memory 500 extend and serve to identify requirements. These lines transmit due to its coding information to the internal memory by which the module is determined, who triggered the instruction and they are used to put the requested data in the appropriate Retrieve module.

These lines extend from the interface unit SIU-100 to the internal memory 500 and they comprise two port number selection lines, a read / write line to memory, a double precision line to memory and a parity line. The these Lines are impressed with information signals

909823/0592

coded as follows:.

'' a) Bits 0-1 represent port number selection bits which indicate by their coding, '.. which connection or subchannel within of the attached module receive the storage instruction sent to the module or should interpret '.

• b) Bit 2 is a read / write bit to the memory, ■ that is contained in the control information received from the active module and from the ι - Interface unit SIU is passed on to the internal memory 500 when from the interface unit SIU-100 a new one Instruction is sent to the memory. The state of this bit shows the direction the data transfer to.

c) Bit 3 is a double precision bit for storing • 'rather, which, through its coding, indicates the amount of data to be transmitted. It is also contained in the control information generated by the active module, where it is transmitted through the interface unit SIU-100 to the internal memory module 500 when a new instruction is sent after the memory module.

AZC 'This line extends from the interface unit SIU-100 to the internal memory module 500 and it indicates in the set state to the internal memory module 500 that one of

, · The interface unit SIU-100 on the other

ZAC instruction and control information offered to its lines is to be accepted. Setting this Interface lines are mutually exclusive when the interface line is set APC.

909823/0592

PIR / ZIR

This line is used for the adoption of a programmable interface instruction, and it extends from the interface unit SIU 100 to the internal memory module 500. When set, this line indicates that the present on lines DTM hn transfer information is to be assumed from the internal memory module 500th

This line signals the readiness of the programmable interface and the ZAC interface and it extends from the internal memory module 500 to the interface unit SIU-100. In the set state, this line shows the interface unit SIU-100 indicates that the internal memory module 500 is capable of a programmable interface instruction or to accept a ZAC storage instruction.

This line extends from the internal memory module 500 to the interface input ' · It is called SIU-100 and when it is set, it indicates ... that the was previously carried out by a ZAC or PI instruction requested ^ read data together with the required control information are available and to which the module requesting the data can be sent.

DFM 00-35, P0-P3 These lines are 4 bytes wide

and they extend in a direction from the internal memory module 500 to FIG Interface unit SIU-100. These lines • are used to retrieve requested read data used in an active module via the interface unit SIU-100.

The two groups of lines extend from the internal memory module 500 to the interface unit SIU-100. These lines are used to carry the read data from module 500 back to the requesting module.

909823/0592

RIFM 0-3, PO
RIFM 4-7, P1

DPFM and QUAD

-73 _

The double precision line from the memory and the QUAD line extend from the internal memory module 500 to the interface unit SIU-100. With their coding, these lines indicate the number of words that are to be transmitted via the interface unit SIU-100 to the requesting module during the time interval of the transmission request for the read data. These lines are coded as follows:
QUAD, DPFM
0 O one word, single precision

0 1 two words, double precision

1 'X four words

This line for the status identification of the read data extends from the internal memory module 500 to the interface unit SIU-100. The status of this line signals to the interface unit SIU-100 whether the information present on the lines DFM relates to read data or status information when the line RDTR is set. When set, this line indicates that status information of one or two words (QUAD = O) is to be transmitted. When this line takes the binary value zero ,. this signals that up to four words are to be transmitted, the number of words being determined by the coding of the lines QUAD. and DPFM is specified.
This line mentioned in connection with the programmable interface extends from the interface unit SIU-100 to the internal memory module 500. When set, this line signals to the memory module that the

909823/0 * 592

2349500

data output has been accepted and that this data is therefore transferred to the Can take away lines.

SYS-CLK The system clock line extends from the SIU-IOO interface unit to each module of the Systems. This line is connected to a clock source within the I / O processor 200 and it is used to synchronize the operations of each memory module using the common system clock.

909823 / 0S92

A final group of interface lines that act as an internal interface between the buffer unit 750 and the Central processor 700 are used, corresponds to the interface lines shown in Fig. 5e. The interface 604 is used for the exchange of information and control signals between the processor 700 and the buffer unit 750. The exchange is accomplished by the logic states of various signal interface lines being controlled. The buffer memory / central processor interface includes several lines the following meaning is assigned: Data on the processor (ZDI-O-35j P0-P3); several ZAC and write data (ZADO 0-23, RADO 24-35, POPS); a processor request signal (DREQ-CAC); multiple buffer statements (DMEM 0-3); a storage in the buffer memory (HOLD-C-CU); Delete (CANCEL-C); Rinse (CAC-FLUSH); a read request (RD-EVEN); a read command buffer (RD-IBUF); a read data buffer (DRDS); a trip notice (INIT-IBUF); several commands (ZIBO-35); several address notes (ASFA-M32-33); one Control (DSZ); Read I buffer data (RD-IBUF / ZDI); multiple zone bits (DZD 00-33); a buffer bypass (BYP-CAC); a write signal (WRT-SGN); an empty instruction buffer (IBUF-EMPTY); a ready command buffer (IBUF-RDY); a full instruction buffer (IBUF-FULL); a CP stop (CP STOP) and a CP control (DATA-RECOV).

Instructions, buffer memory instructions and data are sent to the buffer unit 750 directed via various of these lines. Additionally, the operation of processor 700 is controlled by certain of these Lines released or blocked, which will be explained below. A description of the CPU / cache interface lines is given in more detail below.

909823/0592

Central processor / buffer memory interface lines

Designation DREQ-CAC

DMEM 0,1,2,3

description

This line extends from the processor 700 to the buffer unit 750. If this line is set to the binary value "1", a ZAC instruction is issued transferred to buffer 750. In the case of a ZAC write instruction, write data words are in one or two cycles after the ZAC instruction, and data words from the processor 700 are transferred the buffer 750 is sent to the interface unit SIU-100 without modification.

These lines extend from processor 700 to buffer 750. These Lines determine by their coding the instruction that the buffer 750 executes Has. The coding is as follows:

DMEM = OOOO no op No action is taken and no buffer request is made.

DMEM = OOOI Direct The direct instruction allows the processor 700 to carry out a direct transfer of an operand value without intervention on the part of the buffer 750. Thus, no buffer request is generated by this type of instruction.

909823/0592

DMEM = OOIO 0-3 - Cyclic address instruction (ADD-WRAP) The cyclic address instruction is executed in two cycles. At the beginning of the first cycle, data and instruction information is transferred to buffer 750. The processor 700 is then turned off before the next clock interval. During the second cycle the processor is switched on and at the end of the cycle the data supplied to it are made available to it.

DMEM = OIOO 0-3 - Load command buffer command call 1 (LD-IBUF-IFI) The load command buffer instruction is executed in one cycle. Address and instruction information is transferred to buffer 750 at the beginning of the cycle. At the end of the cycle, the block specified by the address is written to the instruction buffer at a predetermined instruction buffer address and the addressed word has been transferred to processor 700 over ZDI lines 0-35.

DMEM «0101 0-3 - Load command buffer command request 2 (LD-IBUF-IF2) The load command buffer instruction is executed in one cycle. Address and instruction information is transferred to buffer 750 at the beginning of the cycle. At the end of the cycle, the block specified by the address is written into the command buffer at the previously specified command buffer address.

909823/0692

DMEM = OIIO - Load Quad
This instruction is executed in one cycle. It is treated in the same way as IF2, but the data is placed in a different part of the I-buffer.

DMEM = OI11 0-3 - Read ahead (PR-RD) The read ahead instruction is executed in a variable number of cycles, with one cycle representing the minimum. Address and instruction information is transferred to buffer 750 at the beginning of the first cycle. During the first cycle, if the address is determined to be a block in buffer 750, the prefetch operation ends and no further action is taken. If the addressed block is not in buffer 750, the request is transferred to main memory at the end of the first cycle. When the requested block has been read from main memory, the data is stored in buffer 750.

DMEM = IOOO 0-3 - Single read (RD-SNG) The single read instruction is processed in one cycle. Address and instruction information is given to buffer 750 at the beginning of the cycle and the data is made available to processor 700 at the end of the cycle.

DMEM = IOOI 0-3 - Read delete (RD-CLR) The read / delete instruction is processed in a variable number of cycles, with a minimum of 9 cycles being used. At the beginning of the first cycle, address and instruction information is 909823/0592

is transferred to main memory and the processor is shut down. While of the second cycle, if the addressed word is contained in the buffer memory, the block containing the word is fetched from buffer 750. If that requested Word has been read from main memory and transferred to buffer 750, the processor is turned on.

DMEM = IOIO 0-3 - read double and odd (RD-DBL-0)

(The DSZ line has the binary value ¹¹ O ".) The odd double read instruction is executed in two cycles. At the beginning of the first cycle, address and instruction information is transferred to the buffer 750. At the end of the first cycle, the word under the the odd address is made available to the processor 700. At the end of the second cycle, the word at the even address is made available to the processor.

DMEM = IOIO 0-3 - read double and even (RD-DBL-E)

(The line DSZ has the binary value "1"). The straight double reading instruction is carried out in two cycles. At the beginning of the first cycle, address and instruction information becomes the buffer 750 transfer. At the end of the first cycle, the word will be under the even address made available to processor 700. At the end of the second cycle, the word becomes made available to processor 700 at the odd address.

909823/0592

DMEM = IOn 0-3 - Read external (RD-RMT) The external read instruction is executed in a variable number of cycles, with a minimum of 10 cycles being used. Address and instruction information is transferred to buffer 750 at the beginning of the first cycle. At the end of the first cycle, the request is transferred to main memory and the processor 700 is shut down. When the requested word pair has been retrieved from memory, processor 700 is turned on and the data is made available to it.

DMEM = I100 0-3 - Write individually (WRT-SNG)

The single write instruction is executed in two cycles. At the beginning of the first cycle, address and instruction information is transferred to buffer 750. At the beginning of the second The data is transferred to the buffer 750 on one cycle. During the second Cycle, the data is written into the buffer 750 when the The block containing the addressed word is stored in the buffer 750 »At the end of the second cycle, the Write request and transfer the data to main memory.

DMEM = I110 0-3 - double writing (WRT-DBL)

The double write instruction is executed in three cycles. At the beginning of the Address and instruction information is transferred to buffer 750 in the first cycle. At the beginning of the second

S09823 / Q592

(third) cycle gets the even (odd) data word to buffer 750 transfer. During the third cycle, the data is written into the buffer, if the block containing the addressed word pair is in the buffer 750 is stored. At the end of the third cycle, the write request and both data words are to the main memory transfer.

DMEM = I111 0-3 - External write (WRT-RMT) The external write instruction is executed in three cycles. At the beginning of the first cycle, the address and instruction information is transferred to the buffer 750. At the end of the first cycle, the request is transferred to main memory. During the next two cycles, the two data words are transferred to buffer 750 which transfers them to main memory.

HOLD-C-CÜ CANCEL-C This line extends from the processor 700 to buffer 750. When set to "1", this asserts control signal notes that the buffer 750 is in a hold state for requests or data transfers occupies.

This line extends from processor 700 to buffer 750. When set to ^Η 1 ", this control signal interrupts any request made to buffer 750.

809823 / 0S92

CAC FLUSH

RD-EVEN

ZADO 0-23 RADO 24 = 35 P0-P3

RD-IBUF

DZD 0-3 This line extends from processor 700 to buffer 750. If it is set to "1", a flushing of the buffer 750 is started.

This line extends from processor 700 to buffer 750. If the Buffer executes a double word request to the interface unit SIU, the even word is stored in a special register secured. If this line is set to the value "1", the content of this register is set to the ZDI lines given.

These 40 one-way lines extend from processor 700 to buffer 750. They are used to execute a ZAC instruction and To transfer write data words to buffer 750.

This line extends from processor 700 to buffer 750. If it is set to "1", it calls the increment of an output pointer of a command buffer for the Processing of a next command in accordance with the state a DRDB line as follows.

These four lines extend from processor 700 to buffer 750. These lines carry odd word zone bits for double write instructions O

S09S23 / 0S9

BYP-CAC

WRT-SGN ASFA 32-33 INIT-IBDF

DSZ1

This line extends from processor 700 to buffer 750. If it is set to "1", it causes buffer 750 to retrieve data words from main memory for read-type instructions to request.

This line extends from buffer 750 to processor 700. You is used to signal processor 700 during write instructions that buffer 750 is completing the transfer of the ZAC instructions and data words to the interface SIU-100 completed Has.

These two lines extend from processor 700 to buffer 750. They put by their coding the next word of one stored in the I-buffer Blockes for reading to the processor when the I-buffer is under hardware control is triggered via the INIT IBUF line.

The trigger instruction for the command buffer is executed in one cycle. At the end of the cycle, a buffer input reference address is reset to "O" and the buffer output pointer is loaded with an initial value.

This line extends from the processor 700 to the buffer 750. The State of the line tells the buffer 750 the order in which the words are given to send to processor 700 when

^{eführt from} 9

DRDB100

RD-IBUF / ZDI ZDI 0-35

^P 0 ^{r P} 1 ' ^P 2' ^P 3

ZIB 0-35 P ₀ / P ₁ /

I BUF-EMPTY I BUF-RDY I BUF-FULL This line extends from the Processor 700 to buffer 750. It is used for the most significant bit of the read address of the I-buffer.

This line extends from processor 700 to buffer 750. You causes buffer 750 to transfer the data on the ZIB lines to the ZDI lines to put on.

These 40 one-way lines extend from the buffer 750 to the processor 700. They feed data from the buffer to the processor 700.

These 40 one-way lines extend from the buffer 750 to the processor 700. They feed instructions from the buffer memory instruction buffer to the processor 700.

This line extends from buffer 750 to processor 700. Im State "1" indicates that the command buffer does not contain any commands at this point in time.

This line extends from buffer 750 to processor 700. Im State "1" indicates that the command buffer contains at least one command.

This line extends from buffer 750 to processor 700. It indicates that the instruction buffer contains more than four instructions, or at least one instruction and a pending instruction fetch request.

909823/0592

~ ^ö5 "28495D0

CP STOP This line extends from the

Buffer 750 to processor 700. In state "1" it indicates that as a result from special conditions determined within the buffer unit 750, the processor 700 will wait or stop must, while the buffer unit 750 the solves special conditions.

DATA-RECOV These lines extend from

the buffer 750 to the processor 700. They are used to store processor registers after the processor 700 has stopped due to the detection of a buffer condition with a missing To blank again.

While FIGS. 5a to 5e show the lines that connect the various modules of the system according to FIG. 1 to the interface SIü-100 and additionally to the processor 700 and the buffer unit 750, it should be noted that others Lines are also provided for other states, such as certain error states and operating conditions to display. With regard to a further explanation of the various modules according to FIG. 1, reference is made to ÜS-PS 4 000 487 referenced. Processor module 700 and buffer unit 750 are described in greater detail below.

General Description of Processor 700-Fig. 2

Referring to Fig. 2, it can be seen that the central processor 700, a processing control unit 701, a control unit 704, a Processing unit 714, a drawing unit 720, an arithmetic auxiliary and control unit AACü-722 and a multiplier / Having dividing unit 728 in the manner shown

3 0.9 823/0592

are connected to each other. The control unit 704 additionally has has a number of connections to the buffer unit 750 as shown.

The processing control unit 701 comprises a processing control memory address preparation and branch unit 701-1 and a processing control memory 701-2. The control store 701-2 and the unit 701-1 are connected to one another via collecting channels 701-3 and 701-6 in the manner shown .

The control unit 704 comprises a control logic unit 704-1, a control memory 704-2, an address preparation unit
704-3, data and address output circuitry 704-4 and an XAQ register section 704-5 which are interconnected as shown.

According to FIG. 2, the interface 600 has a number of
Input lines for the buffer unit 750. The lines of this interface have been described in greater detail above. In connection with the operation of the buffer unit 750, however, certain of these lines are specially coded in the following manner.

1. MITS 0-3 when reading these are coded as follows: Bits 0-1 = 00;

Bits 2-3 s = read ZAC buffer address;

For a write operation: Bits 0-3 = odd word zone

2. MIFS 0-3 are coded as follows:
Bit 0 = 0;

Bit 1 = 0 even word pairs (words 0, 1) j
Bit 1 c 1 odd word pairs (words 2, 3);
Bits 2-3 = ZAC buffer address for memory.

909823/0592

As far as the interface cables DFS 00-35, PO-P3 are concerned, thus, they transmit read data to the buffer unit 750. The lines DTS 00-35, PO-P3 are used to transfer data from Transfer buffer 750 to the interface unit SIU-100.

The control unit 704 provides the necessary control to perform address preparation operations and command retrieval / Machining operations as well as the continuous control of various operation cycles and / or machine states. the Control is provided by the logic circuitry and by the machining control unit 701 are generated for the various parts of the control unit 704.

Register section 704-5 comprises a number of registers accessible to the program, such as index registers, an accumulator register and a quotient register. This section should be referenced in greater detail on Fig. 3 explained. Other registers accessible to the program, such as the instruction counter and address registers are included in the address preparation unit 704-3.

909823/0892

Referring to Fig. 2, section 704-5 receives signals from unit 704-3 according to the contents of the command counter the lines RIC 00-17. In addition, the lines ZRESA 00-35 apply output signals from the processing unit 714 accordingly the results of the operations performed on various operands. Section 704-5 also receives an output signal from the arithmetic auxiliary and control unit via the lines RAAüO-8.

The section 704-5 supplies signals corresponding to the content of a register contained in the section as input signals to the address preparation unit 704-3. The address preparation unit 704-3 forwards the information via a switch to the processing unit 714 via the lines ZDO 0-35. In the same way, the content of certain registers contained in section 704-5 can be transferred to processing unit 714 the lines ZEB 00-35 are transmitted. Ultimately, the contents of selected registers can be transferred from section 704-5 to the Multiplier / divider unit 728 can be transmitted via lines ZAQ 00-35.

The address preparation unit 704-3 generates and sets addresses from the contents of the various registers contained therein the resulting logical, effective and / or absolute address for distribution to the other units via the ASFA 00-35 lines. The address preparation unit 704-3 obtains the results of the with a pair of operands the processing unit 714 performed operations via the Lines ZRESB 00-35 supplied. Unit 704-3 receives. Signals corresponding to the contents of a pair of base pointer registers from control logic unit 701 via lines RBASA and RBASBO-1. Output signals of the multiplier / Dividing unit 728 are supplied to address preparing unit 704-3. Eventually the contents of a secondary instruction register become RSIR is supplied as an input to unit 704-13 via lines RSIR 00-35.

90982 3/0592

The data and address output circuits 704-4 generate the Buffer address signals which are supplied to the buffer unit 750 via the lines RADO / ZADO 00-35. These address signals correspond to the signals that are applied to one of the groups of input lines ZDI 00-35, ASFA 00-35 and ZRESB 00-35 with the lines selected by switches included in the circuitry of block 704-4 are. Word address signals are also provided over lines ASFA 32-33. These circuits will still be further explained in more detail.

The control logic unit 704-1 forms data paths that interface with different units contained in the buffer unit 750. As will be described in more detail below, form the lines ZIB 00-35 an interface with a command buffer in the buffer unit 750. The lines ZDI 00-35 are used to transfer data signals from buffer 750 to control logic unit 704-1. Other signals are transmitted through the other data and control lines are applied to the interface 604 between the buffer memory and the central processor. These Lines include the CP stop line, which is separated in FIG is shown.

Referring to Figure 2, control logic unit 704-1 provides a number Groups of output signals. These output signals include the content of certain registers, for example a basic instruction register RBIR, the content of which is fed as input to control store 704-2 via lines RBIR 18-27. The control unit 704-1 receives certain control signals read out from the control memory 704-2 via the lines CCSDO 13-31.

Control logic unit 704-1 includes a secondary command register RSIR, which is loaded in parallel with the content of the basic command register at the start of command processing. The contents of the secondary command register RSIR 00-35 are applied as input to the address preparation unit 704-3.

909823/0592

Part of the contents of the secondary command register is added as the input of the auxiliary arithmetic control unit 722 via the lines RSIR 1-9 and 24-35.

The control store 704-2 provides an initial decoding of the opcode of the program instruction and therefore includes one Number of storage locations (1024), one storage location being provided for each possible operation code of the instruction.

The signals applied to lines RBIR 18-27 are such as mentioned, supplied as inputs to the control store 704-2. These Signals select one of the 1024 possible memory locations. The content of the selected memory location is shown in FIG the lines CCSDO 13-31 and CCSDO 00-12 are created. The to the Signals applied to lines CCSDO 00-12 correspond to the address signals, which are used to address the processing control unit 701.

The remaining portions of processor 700 will now be briefly described. The processing unit 714 is used to execute instructions and to carry out arithmetic and / or shift operations with operands that are selected at the various inputs. The results of such operations are fed to selected outputs. The processing unit 714 receives data from a data input manifold corresponding to lines RDI 00-35 and having the control logic unit 704-1 as a source. The content of the accumulator and quotient registers in section 704-5 is fed to the processing unit 714 via the lines ZEB 00-35. The signals that are applied to the input collective channel lines ZDO 00-35 by the address preparation unit 704-3 are applied as output signals to the lines ZRESA 00-35 and ZRESB 00-35 according to FIG. 2 via switches contained in the processing unit 714. The processing unit 714 additionally receives a group of buffer address signals from the arithmetic auxiliary and control unit 722 via the lines ZRSPA 00-06. The unit also delivers 722

909823/0592

shift information to unit 714 via the lines ZRSC 00-05.

The drawing unit 720 is used to handle drawing type commands, operations such as translation and output of data fields require. These types of commands are known as the EIS extended command group. Such commands include Shift, scan, and compare type commands. Signals that correspond to operands are transmitted over the lines ZREA 00-35 supplied. Information regarding the type of character position within a word and the number of bits is applied to the drawing unit 720 via the input lines ZPB 00-07.

Information that corresponds to the result of certain data operations is sent to the unit 722 via the lines ZOC 00-08 created. Such information includes exponent data and data in hexadecimal form. The drawing unit 720 provides Output operand data and control information to unit 722 and unit 728 over lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 performs arithmetic Operations with control information, such as exponents used in floating point operations, and it calculates operand lengths and pointer addresses and generates count information. The results of these operations are the processing unit 714 via the lines ZRSPA 00-06 and the lines ZRSC 00-06 in the aforementioned Way fed. Information signals corresponding to characters such as 9-bit characters, 6-bit characters, from input hexadecimal data converted decimal data, quotient information and sign information are transferred to section 704-5 the lines RAAU 00-08 are supplied.

909823/069

- Q2 -

2849

According to FIG. 2, the unit 722 receives a number of input signals. The character hint information is displayed via the lines ASFA 33-36 fed. The EIS numerical weighting factor information and the alphanumeric field length information is provided to unit 722 over lines RSIR 24-35. Other signals that relate to the retrieval of certain commands, are fed in via lines RSIR 01-09. Exponent signals for floating point data are provided to unit 722 supplied on lines ZOC 00-08 while floating point exponent data signals from unit 704-1 via lines RDI 00-08. Shift count information signals for certain commands (e.g. binary shift commands) are applied to the unit via lines RDI 11-17. For the input signals applied to lines RCHU 00-35, lines 24-35 apply signals corresponding to FIG Length of the EIS command field, while lines 18-23 Apply address modification signals to unit 722.

The last unit is the multiplier / divider unit 728, intended for high speed processing of multiply and divide instructions. This unit can do one of conventional construction, reference being made to US Pat. No. 4,041,292 in this regard, for example. The unit 728 receives multiply and divide inputs on lines RCHU 00-35. The multiplicant input signals from register section 704-5 are applied over lines ZAQ 00-35. The results of the executed Calculations are applied as output signals to the lines ZMD 00-35.

As previously mentioned, "the buffer unit" transmits and receives 750 data and control signals to and from the interface unit SIU-100 via the interface 600. The buffer unit transmits and receives data and control signals to and from processor 700 via interface 604. Finally, receives the buffer unit 750 receives address and data signals from the circuitry 704-4 over the RADO / ZADO 00-35 lines and lines ASFA 32-33. 909823/0592

Detailed description of the processor 700

The various sections comprised by processor 700 shown in FIG. 2 will now be described in greater detail described with reference to Figures 3a to 3j.

According to FIGS. 3a and 3b it can be seen that the processor comprises two control stores: 1. The control unit control store CCS-704-200, which forms part of the control unit 704; and 2. the processing control memory ECS-701-3, which is in the processing control unit 701 is included. The buffer oriented processor 700 of the preferred embodiment of the present invention has a three-stage flow. This means that the processor needs at least three processor cycles to to complete the processing of a given program instruction, and to have a new instruction at the beginning of each Cycle can output. Thus, a number of program instructions in any processing stage can become any given one Point in time.

In the preferred exemplary embodiment, the processor 700 has the following stages: an instruction cycle I, in which the instruction interpretation, the operation code decoding and the address preparation take place; a buffer cycle C in which the access to the buffer unit 750 is carried out; and a processing cycle E in which the command processing takes place. For control purposes, during the I cycle, the instruction's opcode is supplied on lines RBIR 18-27 and used to access a memory location within control store 704-2. During a C cycle, this content is applied by the control store 704-2 sn di © lines CCS DO 00-12 and used in turn, on oisien the storage space © äes processing s control memory = 2 lagriff EU aetenen. During the C cycle, the microprograms used are all command requirements! © aslbsltöagssteuerspeietier 701-2 in a 144-bit output? © 1 ° = 4 SMiisf © reado Di © labeled M1S-3Q 00-143

- ^y 2349500

Signals are distributed to the various functional units of the processor 700. During a Ε cycle, the Processor executes the operation specified by the microinstructions.

According to Fig. 2 it can be seen that the control store 704-2 comprises a control unit control store CCS-704-200, the is addressed by the opcode signals on lines RBIR 18-27. The control memory CCS-704-200 has 1024 Storage locations, the content of which is read out into an output register 704-202 during an I operation cycle. Figure 6a Figure 3 shows schematically the format of the words stored in control store 704-200.

Referring to Figure 6a, it can be seen that each control unit control store word comprises five fields. The first field is a 13-bit field containing ECS starting address storage for the instruction whose opcode is supplied on lines RBIR 18-27. The next field is a 3-bit field (CCS0) which provides control of certain operations. The bit interpretations of this field depend on its destination and on whether it is decoded by certain logic circuitry or under microprogram control. The next field is a 4-bit field which specifies certain register control operations. ^s

The next field is a S-bit Folgesteuerfeldi that _g specifies its coding a sequence of operations which, like the buffer operation is carried out under a hard-wired logic controller. In this example this field is coded with -75g. The last field is a β-bit information field _e is for understanding the present "invention without significance.

Fig » 3a will» Sigaals satspreeheHd ä & m CCSJl = FsId

-Steuerspaiehen-iortos üfoss © iaesa W © g 7 © 4 ~ 2 © <l al dea learbQltmigs @ s ^> s © ugöngsschsiltks ⁱ @ is © H 10% ^ l g

" ⁹⁵ " 2349500

Signals according to the CCSR field are used as the input of the Processing unit 714 is supplied via a path 704-206. The same signals are added to the address repair unit 704-3 supplied via a different path 704-203.

Signals corresponding to the sequencer field are input to sequencer logic circuits 704-100 over the channel 704-210 supplied. As explained, these circuits decode the sequencer field and they generate signals that enable the buffer unit 750 to perform the specified operation.

The generation circuit '701-1 for the processing address receives an input address fed to the CCSA field of the Control memory 704-2 corresponds. As can be seen from Fig. 3b, these circuits comprise an input address register 701-10, whose output is connected to a position of a switch 701-12 with three positions, this switch with ZECSA is designated. The output of the switch serves as an address source for the control store 701-2. The first position of switch 701-12 receives an address from the MICA register 701-14 supplied. The content of register 701-14 is updated at the end of each cycle in order to store it within the ECS control memory, whereby this Storage location follows the storage location whose content has been read out during this cycle.

The second position selects the address given by the ZCSBRA branch address selection switch 701-18 is generated. The third position selects the address of the first microinstruction in any microprogram supplied by the CCS control store and loaded into REXA register 701-10. if the output signal at the CCS control store is not available when a microprogram is terminated, a predetermined one is established Address (octal address 14) selected automatically.

909823/0592

The first position of the branch switch 701-18 receives signals corresponding to a branch address read from the memory 701-2 into the register 701-4, which in turn is directed to a return control register 701-20. The second, third and fourth positions of switch 701-18 receive signals from RSCR register 701-20, MIC register 701-15, and from the contents of a number of vector branch registers 701-36. The MIC register 701-15 stores an address referencing the microinstruction word that follows the microinstruction word being processed. This address corresponds to the address of switch 701-12 incremented by one, the increment being effected by an increment circuit 701-16.

The vector branch registers include a 4-bit vector branch register 0 (RVBO), a 2-bit vector branch register 1 (RVB1) and a 2-bit vector branch register (RVB2). These registers are loaded during one cycle of operation with address values derived from signals stored in a number of different indicator flip-flops and registers and used as inputs to a number of groups of input multiplexer selection circuits 701-32 and 701-34 to serve. The outputs of circuits 701-32 and 701-34 are provided as inputs to two-position selection circuits 701-30. These circuits in turn generate the output signals ZVBRO, ZVBR1 and ZVBR2, which are stored in registers 701-36.

The switch 701-36 provides an address based on the testing of various hardware indicator signals and status flip-flop signals selected via an INDGRP field. The branch decision is made by masking (and linking) the selected indicator group with the fields INDMSKU and INDMSKL of a microinstruction word. If a vector branch is selected, then the INDMSKÜ box as a box with 4-bit zero-treated The OR

909823/059?

Combination of the 8 bits is compared with the state that is defined by the microinstruction fields TYPG and GO. the Hardware signals are selected via a number of data selector circuits 701-28, only one of which is shown, the outputs of which are in turn used as inputs to another five position multiplexer selection circuits 701-26 to serve. The output of multiplexer circuit 701-26 feeds a comparison circuit which contains the indicator signals AND with the masking signals to produce the resulting MSKCBRO-7 signals.

The MSKCBRO-7 signals are used in a further comparison circuit which subjects the signals with the condition branch test signals TYPGGO to an AND operation in order to to set a branch decision flip-flop 701-22 or which generates a signal RBDGO, the state of which indicates whether a branch is to be taken. The output signal RBDGO is fed as a control input to the first two positions of switch 701-12. If the branch test condition is not satisfied (e.g. signal RBDGO = 0), the increased address is selected by the MICA register 701-14.

In some cases, it is not possible to test the state of an indicator in the cycle that follows its formation. For this reason, standard registers HRO-HR7, which are not shown, are used for register storage of the indicators of group 2 intended. The states of such stored indicators are selected and in a manner similar to the others Indicators (e.g. mask fields) tested.

The unit 701-1 further comprises a number of indicator circuits, certain of these circuitry being used to control the operation of certain parts of the processor 700 JBU control when through certain types of commands to processing strings have been processed. These indicator circuits are contained in block 701-42 and they

909823/0592

2849S0Q

are set and reset under the control of a field within the microinstruction word of Fig. 5a (e.g. the field IND6). The bits of this field used by the ECS output register 701-4 are read out to an RMI register 701-38 for decoding by a decoder 701-40 fed. Based on the status of received from the various processing units (e.g. 714, 720, 722, etc.) Status indicator signals become suitable auxiliary flip-flops switched to the binary state "I" »The outputs of this Flip-flops have different positions of a four-position switch 701-44 fed to the position GP3 of switch 701-26 for testing. The same exits become one second position of a ZIR switch 701-43 for storage supplied via the ZDO switch 704-340. The ZIR switch 701-43 also receives indicator signals from an indicator register IR-701-41. This register is accessed via the RDI lines 18-30 and 33 loaded due to certain commands "

The indicator status signals include, for example, the outputs of the various adding circuits (AL _f AXP) of the unit 720. These signals do not differ from the signals of a number of sequence information flip-flops, which are labeled PE11, FE12, FE13, FE1E, FE2E, FE2 and FE3 are designated. The flip-flops FE1E and FE2E are set during any FPOA cycle of an instruction. These flip-flops in turn cause the flip-flops FE11, FE12 and FE13 to be set when the outputs of the AL or AXP adding circuits of the unit 720 are present. The setting and resetting of these indicators is described here in more detail in connection with the description of the mode of action. However, the flow hint FXip-Flops that belong to the given example are set and reset in accordance with the following equations see ^{Bool 1:}

Set: FE1E = FPOA + INDβFLD field reset χ FEIE «IND6FLD field set : FE2E« = FPOA + IWD6FLD field reset s FE2E «IND6FLD field

909823/0592

Set

Reset : FE11 Set : FE12 Reset : FE12 Set : FE13 Reset : FE13 Set : FE2

Reset Set

Reset

FE11 = IND6FLD field «FEiE (ALES + AXPES + DESC1 ΑΡΟ-4 = Ο)

+ IND6FLD field'FEIE'DESCI · (APO-5 = O + APZN + ALZN) + IND6FLD field = FPOA + IND6FLD field = IND6FLD field'FEiE · (ALES + AXPES + FE13).

= FPOA + IND6FLD field = IND6FLD field «FE1E-ALES + IND6FLD field

= FPOA + IND6FLD field = IND6FLD field »FEaE-ALES + IND6FLD Field-FE2E * DESC2 * (APO-4 = O + APO-5 = O + APZN + ALZN) + (IND6FLD field) FE2E »DESC2 + IND6FLD. FE2 = FPOA + IND6FLD field FE3 = IND6FLD field DESC3 (APO-4 = 0 + APO-5 = 0 + APZN + ALZN) + IND6FLD field DESC3 + IND6FLD. FE3 = FPOA + IND6FLD field

where IND6FLD indicates a specific code

ALES = AL = O or AL ^ C; AXPES = AXP = O or AXP-C; APZN = APO-7 έ 0; and ALZN - ALO-11 4 0.

909823/0592

- loo - ^ 849500

As can be seen from Figure 3b, signals corresponding to the true and complementary state of bit 0 are made from the ROP register supplied as inputs to various AND gates within a pair of gates 701-25 and 701-26. Each AND gate receives the true and complementary output signal of the masking OR circuit as a second input 701-24 supplied. The outputs of AND gates 701-25 and 701-26 are fed as inputs to an OR gate 701-28, whose output DTRGO is used to set the control indicator flip-flop FTRGO of block 704-110. the Arrangement according to the present invention allows the flip-flop FTRGO to be set in accordance with the state a selected indicator depending on the state of bit 0 of the ROP register.

909823/0592

The ZCSBRA switch 701-18 is normally enabled, when the branch decision flip-flop RBD in the previous cycle was set to the binary value "1". The first position selects a 13-bit branch address from the current microinstruction applied via the RSCR register 701-20. The branch address allows any of the memory locations of the ECS control memory to be addressed directly. The second position selects the chaining of the 6 lower rankings Address bits from the current microinstruction supplied via MIC register 701-15 and the 7 upper bits of the branch address from the microinstruction supplied via the RSCR register 701-20. This allows branching within a 64-word page / the by the contents of the MIC register 701-15 (current storage location + 1) is defined.

The third position selects the concatenation of the 4 low order bits of the RVBO vector branch register, 6 bits of that Branch field of the current microinstruction stored in the RCSR register and of the 3 upper bits of that in the MIC register saved address. This allows for a 16-way branch. The fourth position chooses the concatenation of the two 4-bit low order "O" bits from the vector branch register RVBO and with the 4 most significant bits of the branch address field of the current microinstruction and the 3 upper bits in the address stored in the MIC register. this allows a 16 way branch with 3 control store locations between each adjacent pair of destination addresses.

The fifth position selects the concatenation of the two low-order "C bits" with two bits from the vector branch register RVB1 6 bits of the branch address of the current microinstruction and the 3 upper bits of the MIC register. This allows branching with 4 possible destinations and with 3 control store locations between each adjacent pair of destination addresses.

909823/0592

The sixth position selects the concatenation of two lower rankings Two bit "O" bits from the vector branch register RVB2, with the 6 bits of the branch address of the current microinstruction and the three upper bits of the MIC register. This allows a four-way branch with three control memory locations between each adjacent pair of destination addresses.

The output of switch 701-12 addresses a particular one Storage space within the control memory 701-2, which causes the reading out of a microinstruction word which is a Format according to FIG. 6b. According to this figure it can be seen that this microinstruction word due to its coding has a number of different fields which are used to identify the various functional units within of the processor 700 to control. Only those fields related to the present example are described here.

Bits 0-1 Reserved for future use

Bit 2 EUFMT Defines with which format EU

cooperates. EuFMT = O defines a first microinstruction format, while EUFMT = I defines a different microinstruction format.
Bits 3-5 TRL TR write control down.

Write control of temporary EU registers TRO-TR3, OXX No change

100 Write TRO

101 Write TR1

110 Write TR2

111 Write TR3

909823/0 5 92

Bits 6-8 TRH TR write control up.

Write control of temporary EU registers TR4-TR7.

OXX No change

100 Write TR4

101 Write TR5

110 Write TR6

111 Write TR7

Bits 9-12 ZOPA ZOPB ZOPA switch control of the ZOPA switch. ZRESB switch control unit Choose the Choose the exit TRO O) ZRESA 0000 TR1 1) Choose the 0001 TR2 2) OO 0010 TR3 3) 01 0011 TR4 4) 10 0100 TR5 5) 11 0101 TR6 6) ZRESB 0110 TR7 7) 0111 RDI 8-11) 1OXX ZEB 12) 1100 ZEB 13) 1101 ZEB 14) 1110 O (lock) 15) 1111 ZOPB switch control. Bits 13-16 of the ZOPB switch. exit ZRESA switch control. Bits 17-18 of the ZRESA switch. exit ■ ALU arithmetic unit Shifter Cache / RDI switch ZDO Bits 19-20

Selects the output of the ZRESB switch.

00 ALU arithmetic unit

01 slider

10 buffer / RDI switch

11 ZDO

909823/0 5 92

Bit 21 RSPB Temporary Storage Buffer Blanking Control. Scans RSPB with the data from ZRESB.

0 No sampling

1 scan of RSPB

Bit 22 RSP cache write control.

0 Read buffer

1 Write buffer

Bit 23 ZSPDI buffer / RDI switch

steering.

Selects the output of the buffer / RDI switch the end.

0 buffer output

1 RDI

Bits 24-25 ZSHFOP Shift Operand Switch

steering.

Selects the left operand for the shifter.

00 ZOPA output

01 EIS output

10 O

11 Selects 0 or 1 depending on bit 0 of the right operand for the shift the end.

Bits 24-27 ALU ALU function control.

Selects the operation that is applied to the two inputs (A and B) of the ALU arithmetic unit.

Bits 24-29 N / A

Bits 26-31 RFU Reserved for future use.

Bits 30-31 ZALU ALU switch control.

Selects the output of the ZALU switch.

809823/0592

Bits 32-33 NXTD Next Descriptor Control Samples the RBASB and RDESC registers.

00 RBASB <OO

RDESC <00

01 RBASB f 01

RDESC <01

10 RBASB i Alt

RDESC {10

11 No scans (omission)

Bits 32-35 CCM control constant field to which the

referenced by the CONTF field.

Bits 34-35 IBPIPE IBUF / channel control.

Selects IBUF reading or channel operation.

00 No operation

01 Read IBÜF / ZDI

10 Type 1 renewed start release or

11 Type 4 waiting for restart

Bits 36-37 FMTD Selects loading of various

Cü register and shows the interpretation given to the MEMADR field for a small CU control

* is to be given.

00 No operation

01 RADO <ASFA

10 RADO <ZRESB

11 RADO <ASFA

Bits 38-40 MEMADR Buffer Control.

Selects the buffer memory operations. The full interpretation of this control is a function of the FMTD control.

000 No operation

001 Just read

010 loading quad

909823/05 9 2

011 Read ahead

100 just write

101 Double letters

110 Reading single questionnaire (only for FMTD = 11)

111 Write single word (only for FMTD = 11)

Bit 41 ZONE Zone control.

Indicates a zone or no zone for small CU control.

0 No zone

1 zone

Bits 42-44 TYPA Type A Note.

Indicates that the superimposed fields are of type A to be used.

000 fields of type A = O

100 fields of type A = 4

Bits 44-46 PIPE Channel Control (Pipeline Control)

Selects the type of restart to be triggered.

000 No operation

001 Type 1 restart and release

010 type 2 restart

011 type 3 restart

100 type 4 restart

101 Type 5 enable 110 Type 6 restart

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28A9500

Bits 44-47 AUXREG Auxiliary Register Write Control Selects an auxiliary register, or combinations thereof, into which to key data selected by the AUXIN control field.

0) 0000 No keying in D. 0001 RRDXA 2) 0010 R29 3) 0011 R29, RRDXA, FRL, RID 4) 0100 RRDXB 5) 0101 RTYP 6) 0110 RBASA 7) 0111 RBASA, RTYP 8th) • 1000 • RBASB 9) 1001 RDESC 10) RBASA, R29, RRDXA Bits 45-46 TYPEB Type B note.

Indicates that the overlaid fields are of type B

to be used.

OO fields of type B = O

11 fields of type B = 3

Bit 47 RSC RSC key control

Scans the RSC register (shift count)

Bit 47 RSPA RSPA touch control. Scans the RSPA register.

Bits 47-48 N / A

Bit 47 RAAU RAAU touch control.

Scans RAAU registers.

Bits 48-49 ZLX ZLX switch control.

Selects the output of the ZLX switch.

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¹⁰⁸ ~ 28495

Bits 48-49 ZSPA ZSPA switch control.

Selects the output of the ZSPA switch.

Bits 48-50 AUXIN auxiliary register input control. Selects data to be keyed into the auxiliary register.

Bit 49 ZADSP ZADSP switch control.

Selects the output of the ZADSP switch.

Bits 50-52 ZSC ZSC switch control.

Selects the output of the ZSC switch.

Bits 50-52 ZRSPA ZRSPA switch control.

Selects the output of the ZRSPA switch.

Bits 50-52 ZAAU ZAAU switch control.

Bit 51 RSIR RSIR register scanning.

Scans the RSIR register depending on the AUXIN. Field.

Bit 53 RDW RIDWr, R2DW register scanning.

Keys the register R1DW or R2DW depending on the RDESC register.

Bits 53-54 ZLNA ZLNA switch control.

Selects the output of the ZLNA switch.

Bits 54-57 CONTF Various flip-flop controls » Selects one of four groups of control flip-flops through the control constant field CCM for the Set or reset off »The flip-flops include those of blocks 704-104 and 704-110.

Bits 55-56 ZLNB ZLNB switch control.

Selects the output of the ZLNB switch.

Bits 55-56 ZSPA (2) type A = 2 ZSPA switches, RSPA registers

Steering.

Selects ZSPA switch output and keys RSPA = Register.

909823/0592

Bits 57-58 ZPC ZPC switch control

Selects the output of the ZPC switch.

Bits 59-62 ZXP ZXP switch -, RXP register series-

Steering.

Selects ZXP switch output and the RXP register to write the output signal to is.

Bits 59-63 ZLN (D ZLN switch- _f RLN register row-

(Type A = D control.

Selects ZLN switch output and RLN register to which the output signal is to be written is.

Bits 59-60 ZPA ZPA switch control.

Selects the output of the ZPA switch. OO = RPO.

11 = RP3

Bits 61-62 ZPB ZPB switch control.

Selects the output of the ZPB switch, OO = RPO

11 = RP3

Bits 63-64 ZXPL ZXPL switch control. (Type A = O)

Selects the output of the ZXPL switch, 00 »■ RXPA

11 «RXPD

909823/0592

Bit 63 ZLN (2) ZLN switch, RLN register series (typ A = 2) control.

Selects ZLN switch output and RLN register, in which the output signal is to be written,

Bits 63-66 RDIN RDI input control.

Selects the data to key into the RDI register and selects one of the modification control fields (MF .. - MF-, hint) of a command word the end. RDI keying can also be controlled through the MISCREG field.

Bit 64 ZXPL (D ZXPL switch control. (Type A = D ■
Selects the output of the ZXPL switch.

Bits 64-68 ZRPAC ZRPA switch, ZRPC switch, (Type A = 2) RPO-3 Register Row Control Selects ZRPC and ZRPA switch outputs and that RPO-3 register into which the output signal from ZRPA is to be written.

Bits 65-66 ZXPR ZXPR switch control. (Type A = O)
Selects the output of the ZXPR switch.

Bits 65-66 ZXP (D ZXP switch, RXP register row (typ A = D control.

Selects the ZXP holder output and the RXP register in which the output signal is to be written.

Bits 67-68 ZPD ZPD switch control. (Type A = O)
Selects the output of the ZPD switch.

Bit 67 ZRPAC (4) ZRPÄ switch, ZRPC switch, (type A = 4) RPQ-S register series control. Select CP4 from the ZRPA switch and keys

thus the RP 1 register.

909823/0691

Bit 67 TYPD Type D note.

This note shows the superimposed fields of type D.

Bit 68 ZRPB (4) ZRPB switch, RP4-7 register row-

(Type A = 4) control.

Select O from the ZRPB switch and use it to feel

the RP4 register.
Bits 68-71 MEM Buffer Control.

Selects the buffer operation together with

the SZ control.

O) OOOO No operation

15) 1111 external letter

Bits 68-70 IBUF IBUF read control

Selects the determination of the IBUF data when reading IBUF.

Bits 69-73 AXP ZXPA switch, ZXPB switch, (Type A = O) AXP adder, ZAXP switch,

RE register control.

Selects the ZXPA and ZXPB switch outputs, the AXP addition function, and the ZAXP switch output the end. The RE register is also keyed.

Bits 69-73 ZRPB ZRPB switch, RP4-7 register row (type A = 1) control.

Selects the ZRPB switch output and the RP4-7 register out into which the output signal is to be written.

Bits 69-71 ZRPAC-3 ZRPA switch, ZRPC switch, (Type A = 3) RPO-3 register line control. Selects the ZRPC and ZRPA switch outputs and the RPO-3 register * ⁿ that the ZRPA output

Bits 72-74 ZRPB (3) ZRPB switch , RP4-7 register (type A = 3) row control,

Selects the ZRPB switch output and the RP4-7 register from which is enrolled.

Bits 72-73 SZ extent / zone cache control.

Controls buffer memory operations in conjunction with the control field MEM.

Bits 74-78 ZRPB (O) ZRPB switch, RP4-7 register row (typ A = O) control.

Selects the ZRP switch output and the RP4-7 register out to be inscribed in.

Bits 74-78 AL ZALA switch, ZÄLB switch, (Type A = 1) AL adder control. Selects the ZALA and ZALB switch outputs and the AL adder function.

Bit 74 TYPE Type E note.

The note shows the superimposed type E fields.

Bits 75-77 ZXP (3) ZXP-Sehalter-, RXP-Register series- (Typ A = 3) control.

Selects the ZXP switch output and the RXP register to be written to.

Bits 75-78 MISCREG Various register controls. Selects different operations with regard to different registers (e.g. RBIR, RDI, RLEN, RSPP).

Bits 75-78 ZDO ZDO switch control.

Selects the output of the ZDO switch.

Bit 78 ZIZN ZIZN switch control ₀

Selects the output of the ZIEN switch «

909823/0592

Bits 79-83 AP ΖΑΡΑ switch, ZAPB switch,

AP adder control.

Selects the ΖΑΡΑ and ZAPB switch output and the AP adder function.

Bits 79-81 ZLN (3) ZLN switch, RLN register series

(Type A = 3) control.

Selects the ZLN switch output and the RLN register to be written to.

Bits 79-83 ZLN (4) ZLN switch, RLN register series

(Type A = 4) control.

Selects the ZLN switch output and the RLN-. Register to write in.

Bits 80-81 RAAU RAAU / RE register key.

Selects the data into which the RAAU and RE registers are to be keyed by different Switches and adders in unit 722 can be controlled.

Bits 82-83 AP (3) ZAPA switch, ZAPB switch,

(Type A = 3) AP adder control. Selects the ZAPA and ZAPB switch outputs and the AP adder function.

Bit 84 ZRSC ZRSC switch control.

(Type A = O)
Selects the output of the ZRSC switch.

Bits 85-86 N / A

Bit 86 RLEN RLEN key control.

(Type A = 3)

The RLEN key signals are also through controlled by the hardware or by the MISCREG field.

Bit 87 FMT format note. Indicates the format type.

3Q9823 / 0592

Bits 88-89 TYPF RFU Shows CHROP OO 01 10 11 bit 90 Bits 90-93

Indicates the type of fields overlaid. = Buffer address = Character unit control = multiply / divide control = N / A

Reserved for future use.

Character unit opcode. Selects the one executed by the drawing unit Main operation and gives an interpretation of the CHSUBOP field.

0) 0000 No operation

1) 0001 Loading data

2) 0010 MOP processing

3) 0011 comparisons individually

4) 0 100 comparisons twice

5) 0101 load register

6) 0110 Update CN

7) 0111 undefined

8) 1000 Set RCH operation A

9) 1001 Set RTF1

10) 1010 Set RTF2

11) 1011 Set RTF3

12) 1100 Set RCN1

13) 1101 Set RCN2

14) 1110 Set output notes

15) Delete 1111 CH unit

Bit 90 RCH RCH register key. Keys the OP1-RCH register _o

Bit 90 RFÜ Reserved for future use.

Bits 91-97 SPA cache address.

Contains the address that can be used to make the EU <-Zwisehenspeich @ r to address "

Bits 91-93 N / A

909823 / 06S2

Bits 94r97

CHSUBOP character unit sub opcode. Selects the detailed function of the drawing unit off or can contain a constant. The interpretation of this field is one Function of the CHROP control as shown below.

CHROP = 0000 No CHSUBOP operation,

0-3

XXXX No interpretation

CHROP = 0001 Load data operation CHSUBOP

0-1

00 01 10

CHSUBOP

1X X1

2-3 (suboperation)

OP1 loading through CN1 and TF1 OP1 reverse loading through CN1 and TF1 0P2 loading through CN2 and TF2 and test characters

Load sign
(Filling control)

Filler characters loaded in ZCU Filler characters loaded in ZCV

CHROP = 0010 MOP processing operation

0-1

CHSUBOP

00 01 10 11

CHSUBOP _2-3

XX

CHROP = (suboperation)

MOP set by CN2 MOP processing
Undefined
Undefined

No interpretation of the load register operation

CHSUBOP ₁ CHSUBOP

0-1 2-3 (Selects output from RCH) (Selects output from ZOC switch)

CHROP ■ 1011 Set RTF3-0 operation

CHSUBOP

0-1 (Selects data to be examined for 00, which is a 9-bit character displays.)

909823/0592

94-97 CHSUBOP _2-3 RFU 97-97 CHROP = 1110 N / A 98 CHSUB0P _Q _ ₃ TYPG 1XXX X1XX XX1X XXX1 Bits Bits bit

(Constant field)

Set output hints operation

Bit 99

Bits 99-106 bits 99-106

Bits 99-106

(Constants selection instructions are to be set).

Set ES (end suppression) Set SN (sign) Set Z (zero)

Set BZ (delete if zero).

Reserved for future use

Type G notice
Indicates the type of fields overlaid.

0 = BRADRU field

1 = IND6 field

GO

Conditional branch test status.

BRADRU Upper branch address.

IND6FLD indicator control. Selects an indicator.

Bit 99 = 0 defines an indicator command change fixed.

Bit 99 = '1 defines a setting / resetting of the indicator command (setting or resetting is indicated by the X bit 0 or 1 accordingly).

Bits 100-104 105 = 1 106 = 1 0000

1100X processing 1 1101X processing 3 1110X processing 1 909823/0592

Processing 2

N / A processing 2

849500

Bits 107-112 BRADRL Branch Low Address

Contains the lower part of an ECS address that is used for the branch.

Bit 113 EXIT Selection of the output switch

steering.

The selection of the output indicates the end of the micro program.

Bits 114-116 ZCSBRA ZCSBRA switch control

Defines the ones to be selected in a control store branch address switch Position.

Bits 117-118 N / A

Bits 119-123 INDGRP Conditional Branch Indicator Group Control.

The first two bits (119-120) select the group of microprogram indicators. The last three bits (121-123) select the set of indicators within each group the end.

Bit 124 TYPH type H field.

Displays the overlaid H-type fields.

0 = INDMSKU

1 = VCTR field

Bits 125-128 INDMSKU Upper Conditional Branch Indicator Mask.

Contains the upper four bits of the indicator mask in the H = O type field.

Bits 125-129 VCTR vector selection.

Selects the branch vectors to be entered into registers RVBO, RVB1, and RVB2 are. The most significant bit (125) determines which of two groups 0 or 1, 2 or 3 and 4 or 5 are to be entered in the registers RVBO, RVB1 and RVB2 accordingly.

909823/0592

The remaining three bits select the vector within each group.

Bits 129-132 INDMSKL Lower conditional branch indicator mask.
Contains the lower 4 bits of the indicator mask.

Bits 133-135 N / A

Bits 136-139 CNSTÜ Upper constant.

Contains the upper 4 bits of the constant field.

Bits 140-143 CNSTL lower constant.

Contains the lower 4 bits of the constant field,

909823/0592

Control logic unit 704-1

This unit comprises the sequential decoding logic circuits 704-100, the outputs of which feed several I-cycle control status flip-flops of block 704-102. These flip-flops generate the various required I-cycle control states for processing the program commands on the basis of signals from circuits 704-100 and micro-command signals from register 701-4 (DEMRO38-4O corresponding to address field MEMADR according to FIG. 6b). The block 704-102 further includes gate circuits that generate register hold signals HOLDEOO which are distributed in the processor 700.

According to FIG. 3c, the I-cycle control status flip-flops receive control input signals from the buffer unit 750 via control lines, the control lines including a line CPSTOPOO. The status of the line CPSTOPOO determines whether the processor operation is continued by setting this line to "0" by setting the hold or enable signals for the I-cycle control status flip-flops and other registers to "0" as well "can be set. The hold signals corresponding to the signals HOLDIOO and HOLDEOO are used to hold or freeze the status of the processor 700. Since the control store address cannot be increased, the ECS control store reads the same microinstruction word The following Bool ¹ see equations set: HOLDI = CACHE HOLD + HOLD REL, where the status of the CACHE HOLD signals corresponds to the state of the CPSTOP signal and the HOLD REL signal corresponds to the binary value "1" until the latter is set to the binary value ^H 0 " a microprogram enable signal is switched; and HOLD E = HOLD I.

According to the present invention, each of the commands is a Control sequence code CCSS is assigned, thereby enabling efficient processing in the command cycle. The different

9 0 9 8 2 3/0592

Classes of hard-wired sequences are formed to enable the processing of the entire command repertoire according to Appendix A to enable. The selected hardwired sequence for each command is chosen to be an effective type of service for any required channel operation is established.

The commands are identified by inemic expressions, which are listed in an instruction index in Appendix A. A number of the commands are given in the publication "Serie 60 (Level $ 6) / 6000 MACRO Assembler Program (GMAP) from Honeywell Information System Inc., copyright 1977, available under part number DD08B, Rev. O.

CCS-S FOLLOW-UP.

COMMAND TYPES

000000 LD-SGL

LDA, LDQ, LCQV ADA, ADQ, ADLA, ADLQ, AWCA, AWCQ, SWCA, SWCQ, CMPA, CMPQ, CANA, CANQ, ANA, ANQ, ORA, ORQ, ERA, ERQ, SBA, SBQ, SBLA SBLQ, LDE, SZN, FSZN, LXLN, LDI,

000001 LD-SGL-DEL

FLD, CNAA, CNAQ, ADE

000010 LD-SGL-ESC

MPY, MPF, DIV, DVF, CWL, CMG, CMK, FAD, UFA, FSB, UFS, FMP, UFM, FDV, FDI, LDT, FCMP, FCMG, CCD, ADL, XEC, CIOC, LPDBR, LDDSA, LDO, LDPn, LDEAn, PAS, LARn, AARn, NARn, LDWS,

000011 LD / STR-SGL-ESC

ASA, ASQ, AOS, SSA, SSQ, ANSA, ANSQ, ORSA, ORSO, ERSA, ERSQ, ARAn, ARNn, SARn.

000100 LD-HWU

LDXn, LCXn, ADXn, ADLXn, SBXn, SBLXn, ANXn, ORXn, ERXn, CMPXn

909823/0592

000101 LD-HWU-DEL

CNAXn

000110 LD-KWÜ-ESC 000111. LD / STR-HWU-ESC 001001 LD-DBL

LBAR, LBER, LMBA, LMBB

ASXn, SSXn, ANSXn, ORSXn, ERSXn

LDA (Q, LCAQ, ADAQ, ADLAQ, SBAQ, SBLAQ, ANAQ, ORAQ, ERAQ, CMPAQ, CANAQ, DFLD

001010

LD-DBL-ESC CNAAQ, XED, LDSS, LDAS, LDPS, LDDSD, DFSB, DUFS, DFMP, DUFM, DFDV, DFDI, DFCMP, DFCMG, DFAD, DUFA, QFAD, QFLD, QFSB, QFMP, QSMP,

Oj oooo STR-SGL 010001 STR-HWU 010010 STR-DBL 010100 RD-CLR 011000 EFF ADR 011010 EFF-ADR-ESC

100000 TRF STA, STQ

STXn

STAQ

EAA, EAQ, EAXn, NEG

ARS, QRS ^r , LRS, ALS, QLS, LLS, ARL, QRL, LRL, ALR; LLR, QLR, GTB, NEGL,

TRA, TZE, TNZ, TMI, TPL, TNC, TOV, TBO, TEU, TTF; TRTN, TRTF, TTN, TMOZ, TPNZ

100100

ESC RCCL, LCCL, RPT, RPD, RPL, STCA, STCQ, STBA, STBQ, MME, DRL, JLLOC, CCAC, AWD, SWD, A9BD,

90982 3/0 5 92

100103 ESC-LD 100110 ESC-ST 101000 NO-OP 101001 TSXN 101010 ESC-EA

1011OO DEL-STR-SGL 101101 DEL-STR-DBL

110000 BIT 110001 MTM-MTR 110011 MRL 110100 TCT 110101 TCTR 110110 SCAN-PWD

A4BD, A6BD, ABD, S9BD, S6BD, SBD, CAMP, RPN, RIMR, SFR, LLDF. LIMR, RRES, HALT, SDRn, EPAT

MLDA, MLDQ, MLDAQ MSTA, MSTQ, MSTAQ NOP TSXN

LREG, SREG, STCj, STC2, FSTR, DFSTR, STE, SBAR, TSS, RET, SPL, LPL, STI, SBER, SMBB, SAREG, SXLn, EPAT, EPPRn, CLIMB, STWS, STPn, LAREG, QFSTR, FST, DFST, FRD ', DFRD, FNEG, FNO, STDn, LDAC, LDQC, SZNC, DIS

STT, STZ, STPDW, SEDBR, STPTW, STDSA, STO

STSS, STDSD, STTA, STPS, STASi STTD, SDZn, QFST

CSL, CSR, SZTL, SZTR, CMPB MTM, MTR

TCTR SCM, SOD

909823/0592

111000

NÜM2

MVN, MVNX, CMPN _f CMPNX, AD2D, AD2DX, SB2D, SB2DX, DV2D, DV2DX, MP2D, MP2DX

111001

MVT

111010 111011

CONV

MLR

BTD, DTB MLR

111100 NUM3

AD3D, AD3DX, SB3D, SB3DX, MP3D, MP3DX, DV3D, DV3DX

111101. EDIT 111110 CMPC

MVE, MVNE, MVNEX

CMPC

111111 CMPCT

CMPCT

The various associated hardwired sequences take effect in the following way.

Hardwired episodes

LD-SGL

This hardwired sequence causes the controller to generate the effective address during an FPOA cycle, and it causes the buffer unit to perform a single read memory cycle of operation to execute.

If indirect addressing is specified, the Control to an address preparation micro preprairan routine transfer. The requested data is in the RDI register loaded upon completion of the buffer cycle, and these are then ready for use during the processing cycle available.

809823/0692

LIKSGL-DEL

This hard-wired 2T sequence is the same as an LD-SGL sequence except that in a -1T delay state after the FPOA cycle is entered (FPOA J FDEL ^ FPOA-NEXT)

LD-SGL-ESC

This sequence is the same as the LD-SGL sequence with the Aus-V

flow to the

assume that the continuity is stopped after a running FPOA cycle is completed (the escape state is entered).

LP-HWU .

This sequence is the same as the LD-SGL sequence with the exception that bits 00-17 of the EDI register are loaded from the buffer unit. The memory bits 00-17 and zeros are loaded into the register RDI jg_ ₅ . .

LD-HWU-DEL ^

This hardwired 2T sequence is the same as the LD-HWU sequence except that in a -1T delay state is entered after the FPOA cycle. The result is FPOA V FEDL * FPOA-NEXT.

LD-HWU-ESC

This sequence is the same as the LD-HWU sequence with the exception that the through-after completion of the current FPOA cycle is stopped.

LD / STR-SGL-ESC

This sequence is the same as the LD-SGL-ESC sequence with the Exception that in addition to normal reading exams as well

909823/0892

a write check is carried out. This sequence is used for operations of the type "read-modify-rewrite".

LD / STR-BWU-ESC

This sequence is the same as the LD / STR-SGL-ESC sequence with the Exception that bits 00-17 of the RDI register are from the buffer memory Loading. The memory bits 00-17 and zeros are loaded into the register ß ° 110 ^ 35.

I.P-PBL

Address This sequence causes the control unit to set the effective address during the FPOA cycle and it causes the buffer unit to to process a double read memory cycle of operation. the Requested data are returned to the RDI register during two consecutive cycles.

U) -DBL-ESC

This sequence is the same as the LD-DBL sequence with the exception that the escape state is entered after the current FPOA cycle is completed.

STR-SGL

The 2T sequence (FPOA > FSTR) causes the control unit to

to generate an effective address, and it causes the buffer unit to perform a single write memory operation cycle (FPOA). During the second cycle (FSTR), the Register contents (as selected by the contents of the RRDX-A register) into the RADO register as follows transfer: ZX> ZDO for ZRESB ^ RADO.

909823/0592

28A9500

STR-HWU

This sequence is the same as the STR-SGL-SOlge with the exception that the buffer unit only makes a change in terms of the bits-OO-17 of the memory comes from ..

STR-DBL

This 3T pole (PPOA »FSTR-DBL ^ FSTR) causes the

Control unit to generate an effective address and it causes the buffer unit to do a double write memory cycle of operation (FPOA control status). During the second and third cycles, the even and odd ones become Data words (as selected by the contents of the RRDX-A register) are sent to the buffer unit.

RD-CLR

This sequence is the same as the LD-SGL sequence with the exception that the buffer unit causes the readout and deletion of the memory space.

EFF ADR

This sequence causes the control unit of the RDI register to load the bits 00-17 s with an effective address that is generated during a FPOA cycle, while bits 18-35 of the RDI register are loaded with zeros.

EFF-ADR-ESC

This sequence is the same as the EFF-ADR sequence with the exception that the through * is stopped after the FPOA cycle (the escape state is entered).

909823/0592

2843500

This sequence causes the control unit to issue two instruction blocks with 4 words {while FPOA and FTBF-S are expensive states) for the Request command buffer, _. a transfer of control or prepare for some branch operation.

flusses This sequence causes desßu-ccji- to stop. after the FPOA cycle. No memory cycles are triggered and it will no address preparation carried out,

ESC-LD & ESC-STR

These sequences are the same as ESC and they are used to process test operations «

ESC-EA

This sequence causes the control unit to load a temporary register with an address pointer that will be used during the FPOA cycle is produced. The channel is stopped after the FPOA cycle,

DEL-STR-SGL

This 3T sequence CFPOA ^ FEDL> FESCJ causes the control unit to generate an effective address during the FPOA- cycle and then to switch to a second FDEL cycle. It allows the buffer unit a special cycle to save Retrieve data. When the FDEL cycle is completed, the buffer unit triggers a single write memory operation cycle, and the hardware switches to the FESC cycle. The data to be written are in the register KADO inscribed under control by the microprogram.

909823 / 0S92

DEL-STR-DBL

This sequence is the same as the DEL-STR-SGL sequence with the

around
Exception that it is 3T delayed. The consequence is FPOA?

FDEL> FESC. ! A double write memory cycle of operation

is triggered during the FDEL cycle. The data is stored in the RADO register after the FDEL cycle under microprogram control transfer.

This sequence is as follows:

FPOA ^ FPOPi> "FPOP2 ..> FP0P3. A switchover then takes place on microprogram control, which entails building registers, tables, etc. that are used for processing of the processing operand signals by hardware control circuits Are required when entering cycle FP0P3.

The remaining editing sequences have states similar to those of an EDIT sequence. on.

This sequence causes the processor 700 to calculate the effective address ru and to update the instruction counter. While a second cycle (FTSX1) the updated content of the command counter is in the RDI register for a subsequent one Transfer loaded into the specified index register. The calculated effective address is loaded into TEAO and the processor 700 transfers the control to this memory location (FPI-INIT).

The hard-wired control states that occur during an I-cycle processing according to the present invention, and a brief description of the operations performed select

such control states or cycles are given below.

909823/0592

I-cycle control status / cycle

description

FPOÄ The FPOA preparation operand state is the start control state for all commands. During FPOA, an address is calculated and the opcode is through translates the CCS control store to control further measures.

The FPOP preparation operand flag state is used to To process editing sequence command descriptors.

FSTS The FSTR storage state is used to transfer storage data to the RADO register to transfer in the case of instructions that require sequencing and the second to transfer (odd) word of double precision data into the RADO register in the case of commands, required for double store sequences.

The FSTR-DBL double memory access • tanü is used to transfer the first (even) word of the double precision ■ ioris data into the RADO register for those instructions that require double memory sequences.

The FESC switching state is used about a changeable

909823/0692

to generate a delay for the I processing channel. During the
In the FESC state, the ESC control store has complete control over the processor
700, and it determines when the I processing channel is restarted.

FDEL

The FDEL delay state provides a delay of 1T to the I processing channel.

FWF-IND The FWF-IND state for waiting on an indirect word, the controller supplies signals on the ZDI lines in the RSIR register transferred to.

FTRF

The FTRF transmission status is used to request that the buffer unit receive a second block of instructions to load it into the I-buffer and by · ■ a first instruction for a new instruction stream into the RBIR register of the processor 700 to key in.

PTRF-NG The FTRF-NG state for the idle transmission is used

of the I buffer around the address register with the old address of the command stream to reload.

909823/0 5 92

PPIM-J

The FPIM-1 state of the command address preparation for I-buffer maintenance of type 1 is taken over if the I-buffer

Command
from de »runs. During this state, a command block for the I-buffer is requested. Likewise, a processor stall condition occurs during this condition if the buffer unit signals a mismatch condition.

FPIM-2 The FPIM-2 state of the instruction address preparation for type 2 I-buffer maintenance allows a second one to be requested Command block for the I-buffer. During this state there is no processor halt if the buffer unit signals a mismatch condition. Likewise during this state the next instruction into the processor's RBIR register keyed in.

PPI-INIT The FPI-INIT state of the command address preparation for the I-buffer triggering is used to reset the I-buffer after an overrun (Memory comparison) to reload or restart after a type.

909823/0692

FWF-IBUF

The FWF-IBUF state for waiting for the I-buffer is taken when an instruction is required from the I-buffer and the I-buffer is • in a non-ready state is located.

FPIM-EIS The FPIM-EIS state of the command address preparation for the I-buffer maintenance EIS is activated after the FPOA cycle of an EIS multi-word command taken whenever the I buffer does not contain enough descriptors to process of the command to complete.

FWF-DESC The FWF-DESC state for waiting for a descriptor becomes taken when a descriptor is needed by the I-buffer and the I-buffer is in a Is in a non-standby state.

FIDESC • Via FIDESC ^ state for an indirect Descriptor is the control state used to process indirect EIS descriptors.

FWF-IDESC The FWF-IDESC state for waiting for an indirect descriptor control delivers the control to 'that to the lines ZDI created buffer storage

909853/0

word to the RSIR register 704-154.

FIT-I The FIT-I state for the indirect

te control and the indirect counter control is used to Non-EIS descriptors process the indirect and indirect meter address modifications determine.

FIRT The FIRT state for an indi

right and register test control is assumed during processing of non-EIS descriptors, Set the indirect and register address modifications to determine whether processing of this type of Address modification is complete.

FTSXI 'The FTSX1 state for the over

Transmission and the setting of the index control is used to determine the updated content of the instruction counter to the RDI register in the case where transfer and set index commands are present.

3c shown in FIG signals corresponding to the I cycle control states as input signals to a plurality of control flip-flops of the block-7O4-JO4 to decoding circuits: the block 704-106, a number of control logic circuits of block 704-108, and a ; Number of control indicator flip-flops of the

0 9823/0 5 92

Block 704-110 created. It can also be seen that the various indicator flip-flops of block 704-110 are also Microinstruction inputs on lines MEMDO54-57 received from the machining control unit 701-4.

According to Figure 3d, those from the hardware control logic circuits fall 704-108 generated signals in one of three groups depending on the units whose operation is controlled will. These groups are formed by the command buffer control, the hardware control and the hardware memory control.

In any case, each signal group will. together with by others Sources generated equivalent signals are ORed and then decoded. The other sources correspond Fields within two different formats of the microbe command word according to Figure 6a, which are from the ESC output register 701-4 can be loaded into the RCSR register 704-112.

One field corresponds to bits 32-83 of one format (large format) and another field corresponds to bits 32-41 of the other format (small format). These fields are processed by a decoder 704-114 are decoded into the specified bit groups and converted into the decoders 704-116, 704-126, _7O4r124 and: 704-128 in the combined way shown. Decoding is also performed by the circuitry of blocks 704-118, 704-135 and 704-120. The results of decoding these fields are either in

distributed to the processor 700 or in an RMEM register 704-130, RSZ-

a flip-flop 704-132, a FREQDIR flip-flop 704-136, and a FREQCAC flip-flop 704-134.

In addition, there is a decoding of the large and short CU

from
Fields and signals of the I-cycle circuits of block 704- 112 via a decoder 704-107 and 704-106. Decoder 704-106 generates control signals for loading various registers and enabling various multiplexers / selectors within processor 700. Decoder 704-107 generates signals for setting and resetting a pair of

909823/0 5 92

Basic Notice Flip-Flops 704-144 (RBASB). Other combinations these signals are used to set and reset the descriptor number flip-flops of blocks 704-140 and 704-142 .

According to FIG. 3c, the decoder 704-116 receives a control signal CexHOO which is generated by the decoding circuitry of block 704-117. These circuits receive signals from the RDESC register 704-140 and signals from the processing flip-handles of block 701-1. In accordance with the states of these signals, the circuits set the signal i. . O "to lock EXHOOO to logic ^11, the generation of a buffer store instruction during the occurrence of a Abarbeitungszustandejs The signal £ EXHOOO is generated according to the following Boolean equation ¹ shear:

[eXHOOO = DESCO 'FE.11- + DESC1 * FE2 + DESC2 »FE3.

The flip-flop FNUM is usually dependent on the CCS operand field of the microinstruction word set. When it is on Logical "1" is set, it indicates that the descriptor to be processed is of the numeric type.

The various flip-flops of block 704-104 are now seiafci ± explained in more detail. The FCHAR flip-flop provides certain changes in the control of address generation. If this flip-flop is at logic "1" while processing a load-type instruction that specifies a character modification, is set, the content of the RID register under Hardware

des »space control not changed. This allows RDI registers to be loaded with data under microprogram control from the channel start. If the flip-flop FCHAR is at logic "1" during a Command of the memory type that defines a character modification is set, the command address for this command is shown under Hardware control modified to refer to a unique address of the microinstruction sequence in the ESC control store, that has to process this type of command.

909823/0 5 92

2849

The PDT-POUR flip-flop provides additional control when reading out the address register (ZAR _Q - _g ) of block 704-304. The flip-flop FADR-WD provides an additional control for the ZDO switch 704-340. If this flip-flop is set to logic "1", a word address is selected by 'the ZAR position of the ZDO switch. The flip-flop FADR-B provides an additional control for the ZDO multiplexer switch. If this is set to logic "1", the ZAR position of the ZDO sci-holder selects a byte address. The flip-flop FNUM is normally set due to the CCS operation field of the microinstruction word. When set to logic "1", it indicates that the descriptor being processed is of the numeric type. The flip-flop: FIG-LEN provides an additional control for loading the registers within the unit 722 C (length register) and for memory operations. When set to logic "5", registers RXP and rRLN within unit 722 are not loaded from RSIR register 704-154 during control state FPOP.

The flip-flop FINH-ADR blocks the operation of the address preparation unit 704-3. If it is set to logic "1", an address cycle (FPOA / FPOP) consists of "the addition of the contents of a temporary register for the effective address REA-T with the value "0". The REA-T register may have been loaded with the address before an FPOA / FPOP cycle. The FABS flip-flop allows absolute addresses to be generated. If it is set to logic "1", an absolute address of 24 bits is used. As far as the information or indicator flip-flops of block 704-110 are concerned, the flip-flop FID , when set to logic * i ^w, provides an indication that an indirect address modification with the descriptor for command processing is required.

The Jtlip-Flop FRL shows when it is set to logic "1" indicates that the length in a register is determined by an associated instruction which is stored in the various instruction registers is loaded. The three flip-flops FINDA, FINDB, and FINDC

909823/0592

provide information that is useful when processing commands from the Memory type are used. The FINDA flip-flop is set to logic "1" if the length is specified in a register or if the flip-flop FAFI is set to logic "1". The flip-flop FINDB is set to logic "1" if the descriptor does not contain 9-bit characters. The FINDC flip-flop is set to logic "1" if the descriptor is characters with 6 bits.

The flip-flop FAFI is set to logic "1I"! When the processor circuits determine that the indicator bit 30 of the IR register 701-41 was set to logic "1" while an EIS command was being processed, causing an interrupt in The flip-flops FTRGP, FTNGO and FTRF-TST are set to logic "1" in connection with commands of the transmission type FTRGP receives a microprogram indication that it is set to logic "1" when the processor circuitry detects the reading of a transfer-type instruction while processing a double-process (XED) or repeat (RPTS) instruction. The flip-flop supplies FTNGO a microprogram indication that it is set to logic "J ^H " if the transmission status signaled by the processing control unit 701 is a transmission still ± and (NO GO), ie no transfer has taken place. The FTRF-TST flip-flop in this group shows the logic. "1" means that the command previously processed by the processor 700 was a command of the transmission type, and that the current I cycle is to be executed by the control unit 701 as a function of the presence of a transmission march signal (TRGO).

The circuitry of block 704-110 additionally includes one Number of flip-flops that are used when performing indirect addressing under hard-wired control for other commands can be used as EIS commands. These include flip flops

909823/0592

PIR, FIRT, FIRL and FRI, which are switched to logic "1" depending on the various types of indirect address modifications. For example, the flip-flop FRI then signals an indirect address modification to a register and is switched to logic "1" if an indirect register indicator is set to logic "1". The flip-flop FXR is set to logic "1". switched when an indirect register indicator (IR) is set to logic "1". This flip-flop signals the start of an indirect register address modification. The flip-flop FIRL is switched to logic "1" when an indirect counter indicator (IT-I) is set to logic "1 ^Μ . This flip-flop signals a last indirect operation. Another flip-flop TSX2 provides an indication, which is used in transfer processing and group index commands, while a flip-flop STR-CPR is used · while processing memory commands.

According to FIG. 3c, the outputs of the control indicator flip-flops of block 704-3 30 are used as inputs to the branch indicator circuits of block 701-1 supplied. The output signals of the control notice flip-flops are also fed as input signals to the I-cycle flip-flops of block 704-102.

909823/0592

In accordance with the preferred embodiment of the present invention, section 704-100 comprises a 3-bit ROP register 704-146, to which signals are fed to the CCSO field will. The content of this register is applied as an input to the circuitry of block 701-1. These hardware indicator signals can under microprogram control during the processing of certain commands in the manner explained be tested.

Register section 704-150

According to FIG. 3c, the control logic unit also comprises 704-1 a register section 704-150. This section contains that Base command register RBIR 704-152, the secondary command register RSIR 704-154, a base note A register RBÄSA 704-156, which is used to select one of the address registers RARO to RAR7 of block 704-304, a read index register A. RRDXA 704-158, which is used for the selection of the index register in the section 704-5 (not shown) and for the selection of Outputs of the ZDO multiplexer switch. 704-340 is used A read index backup register RRDXAS 704-159 and a descriptor type register RTYP 704-160, which specifies the type of data characters.

909823/0 5 92

to which the descriptor value {e.g. "9 bit, 6 bit, 4 bits) ^ is proven. Section 704-150 also includes a 1 bit instruction / EIS descriptor register labeled R29 in block 704-162. The state of this bit together with the contents of the RBAS-A register 704-158 is used to set the special to select the address register used for address preparation. When register R29 of block 704-162 is at Logical

ζ Yaws
"0" is set, this indicates that none of the address registers of blocks 704-304 are used during address preparation. The last registers of section 704-150 comprise the data input register RDI of block 704-164 and a read index register B (RRDXB), since it refers to registers which are used by the processing unit 714.

According to Figure 3, the RBIR register 704-152 via a SD holder 740-170 loaded with two positions, the signals from the ones shown Sources (e.g. from a switch ZIB-B 704-172 and via lines ZDI 0-35). The RSIR register 704-154 receives signals from deSi ZDI lines and in the same way the switch 704-172. The RBASA register 704-156 receives signals from the ZDI line 0-2 and another switch ZBASA of block 704-174. The RRDXA register and the RTYP register receive signals from the ZDI lines as well as from a switch 704-176 and a switch 704-178. The RRDXA register also receives signals from the RRDXAS register 704-159.

The switch 704-172 has two positions, the input signals from the switches ZIB and ZRESB from the buffer unit 750 and the processing unit 714 received accordingly. The switch 704-174 has three inputs, two of which are input signals fed from the processing unit 714 and the output of the ZIB switch to the buffer unit 750;

The switch 704-176 has four inputs, two of these inputs being provided by the processing unit 714 and a single input being provided by the buffer unit 750. The first position of the ZRDXA switch 704-175 selects the output of a ZRSXM switch 704-185 . One position of this switch

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2849600

supplies a hint field from bit positions 5-8, 14-17 and 32-35 of the RBIR register 704-152 and bit positions 32-35 of the RSIR registers 704-154, which are used by the ZIDD switch 704-180 and

en, a ZMP switch 740-176 with two positions' can be selected,

The second position of the SChalterS7O4-185 provides a constant Value from the output of the ESC output register 704-1 (CCM field 32-34). The signals on lines ZIDD 27-35 are fed as input signals to the control indicator flip-flops of block 704-130. The switch 704-178 receives an input from the control store 704-2, an input from the buffer unit 750 and an input from the processing unit 714 fed.

The data input register 704-164 receives a number of input signals from a ZIDD switch 704-180, which is connected in series to a ZDIA switch 7o4-181, whose The output supplies an input of a further switch 704-182, which loads the RDI register 704-164 directly. The ZDIA switch 704-181 provides another input to a switch 704-183 with three inputs, to which the other inputs shown are supplied from the buffer unit 750 and the processing unit 714 will.

The ZIDD switch 704-180 receives an effective address via the switch 704-186 from the address preparation unit 704-3 and inputs from the RBIR register 704-152, the RSIR register 704-154 and a ZMF switch 704-187 with two Positions. The positions 18-35 of the REA position of the switch 704-180 are derived from the ZDIA switch 704-181. Of the ZDIA switch 704-181 receives signals from ZDI lines 0-35, and a constant value supplied by the input signals a first switch position and signals from the output of the ZIDD switch 704-80 and the ZRESB switch in the Processing unit 714 is generated. Switch 704-182 receives the output of the ZDIA switch and signals from the ZDI lines 0-35. The RRCDB register 704-189 is through

909823/0692

loaded a switch 704-188 with three positions. The switch receives signals from an RREG register via a first position in the processing unit, a constant value from the control store 701-2 via a second position and Signals from the ZIDD switch supplied via a third position.

Section 704-150 further includes a switch 704-185 with two positions and a buffer information register 704-186, the output of which is used by the AACü-722 unit, to addresses for access to the buffer of the processing unit Form EU-714. The first switch position provides a constant value and is under hardware control selected (FPOA.R29). The second switch position provides the content of the RBASA register 704-156 as an output signal. These. Position is under both hardware and microprogram control selected (e.g. FPOA R29 or MISCREG field).

It should be noted that the required timing signals for the operation of the section 704 as well as for the operation of other sections of the processor 700 and the buffer unit 750 can be delivered by centrally arranged clock circuits. In the preferred embodiment according to FIG For example, the clock circuits are located within the I / O processor 200. Such clock circuits can be used as are considered to be conventional and include a crystal controlled oscillator and counter circuitry. The timing signals of such clock circuits are conventionally distributed to the various parts of the system distributed according to Figure 1 with a view to synchronized operation.

Address preparation unit 704-3

The address preparation unit 704-3 comprises a number of registers and adders. The registers include a number of Basic registers (e.g. TBASEO to TBASEB) of block 704-300,

90 9 823/0592

used to store descriptor values of an instruction, a pair of temporary registers for effective addresses (TEAO, TEA1) and a pair of instruction counters (ICBB, ICBA) ₁ contained in block 704-302 and for addressing the instruction buffer are used, as well as eight address registers CRARO to RAR7) of the block 704-304, which are used during the address preparation. The unit 704-3 also includes an instruction counter 704-310.

The adders include an adder 704-312 which is used for updating of instruction counter 704-310 through switches 704-311 and 704-314, and a pair of adders 704-320 and 704-322. The adder 704-322 is used to generate an effective address value which is in a register 704-342 and which is applied as an input to the control unit 704-1. The effective address will be from a number of sources including: A Z_Y switch 704-326, the output of which is via a / number is applied by AND gates of block 704-327, selected address registers of block 704-304 or selected temporary ones Register TEAO and TEA1 of block 704-302, which are applied via another switch 704-328, or the index address aalals ZXO-20 from the unit 704-5. The adder 704-322 is also used to calculate the contents of the instruction counter of the To update the buffer memory.

According to FIG. 3d, the output signals of the adder 704-322 are also applied as an input signal to the adder 704-320. The adder 704-320 is used to add one stored in any one of the temporary base registers TBASEO through TBASEB Base value with the address signals ASCOSO-19 from the adder 704-322 to combine. The resulting bits are fed as an input signal to a further adder circuit 704-32O, which generates a logical address which is applied to lines ASFAO-36 via an adder 704-321. This The adder sums the operand inputs together with the carry inputs of blocks 704-300 and 704-320. The effective one

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2849

Address is used to get an absolute address, when the system is operating in a paged mode. Since this mode of operation does not belong to the present invention, it is not explained further. For more information on this address development, refer to the US-PS 3 976 978 referenced.

The temporary base registers of block 704-300 are over a switch 704-332 is loaded. The switch receives an input from the processing unit 714 and from the output of block 704-300 supplied. The processing unit 714 also provides inputs to the registers of the block 704-302 via a switch 704-334 and to the address register of block 704-304. One output multiplexer switch ZDO-704-340 allows the selection of the various registers within the address preparation unit 704-3 and the unit 704-5, in order to transmit their content to the processing unit 714 via the lines ZDO 0-35. The switch also allows ZDO-704-340 reading out the contents of various registers and control flip-flops of unit 704-1 via a fourth position ZDO-A. The fifth position allows the selection of the states various indicators within the control store circuitry of block 701-1 for their examination »

XAQ register section 704-5 and data address output section 704-4 according to FIGS. 3e and 3j

Section 704-5 includes accumulator register RA-704-50, quotient QA-704-52 and temporary index register RTX 704-54 used by control logic unit 704-1. The section also includes a group of eight index registers XO-7 within block 704-51. These registers are loaded into the processing unit 714 via the ZRESA collective channel. The selection of the register to be loaded is controlled by the content of the register RRDXB 704-189. It can be seen from FIG. 3j that the selection of the outputs of the registers of block 704-51 is determined by the contents of both registers RRDXA 704-158 and

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RRDXB 704-3 89 is controlled accordingly. The content of the for the program becomes accessible registers RA / RQ, XO-7 and RTX via a ZXA2 switch 704-56, a ZXOB switch 704-57 and a ZX switch 704-58 is read out into the unit 704-3. From there, the register content can be sent to the processing unit 714 or to the buffer unit 750 via the ZDO switch in the unit 704-3.

90982 3/05

According to FIG. 3j, the output of the ZXA2 switch is 704-56 through an AND gate 704-61 and an OR gate 704-62 in Correspondence with the contents of the RRDA register 704-158 created.

The selection of the outputs of the aforementioned switches is made by the content of the RRDXA register 704-158, the FNUM flip-flop of block 704-104 and the RTYP register 704-160 in addition to bits 55-77 (ZX field). The ZXA2 switch 704-56 reads the upper or lower 18 bits of RA and RQ registers 704-50 and 704-52 for address modification the end. The selected output signals of the ZXA2 switch and the ZXOB switch are combined with the ZX switch with the signals of the registers RAAU, RTX and RIC.

The ZX switch selects as the output signal: Bits of the RA / RQ / X register for a 9-bit string over a first Position, X / RA / RQ bits for a 6-bit string via a second position, RA / RQ / X-bits for a 4-bit string via a third position and X / RA / RQ bits for a word type modification.

The fifth, sixth and seventh positions are used to select the contents of the registers RAAU, RIC and RTX accordingly. Another ZXB2 switch 704-59 forms a second data path to the unit 714 for reading out those accessible to the program Register via lines ZEBO-35. A corresponding data path to the unit 728 is formed by the lines ZAQO-35.

The section 704-4 comprises the registers and switches _t which are used for the transfer of instructions and data to the buffer unit 750 . Such transfer operations normally require at least two cycles, one to send an address and another to send the data. Bits 5-8

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an instruction word are derived from the output of a switch 704-40 with four positions. This switch takes a first constant value via a first position, the content of an RZN register 704-42 via a second position, a second constant value over a third position and a third constant value over a fourth position.

Bits 1-4 of an instruction are assigned to an OR gate 704-44 by the circuitry of block 704-1 along with the Bits 5-8 supplied. The OR gate 704-44 also receives bits 1-8 of a RADO register via a ZADO switch 704-46 704-48 supplied. The RADO register 704-48 is an address and data output register that has a first position of a ZADOB switch 704-48 a logical (virtual) address of the address preparation unit 704-3 via lines ASFAO-35 and data output signals from the unit 714 via lines ZRESBO-35 receives. The positions of the ZADOB switch 704-48 are determined by the FMTD field for a small CU format and by controlled by the RADO field in the case of a large Cü format.

As can be seen from the figure, bits 1-8 of either switch ZZN or switch ZADO are used as output signals applied to the RADO / ZADO lines depending on the state of the control signal £ RADO-ZADO]. Bits 0 and 1 are always "1" while bits 10-35 are provided by RADO register 704-46.

The unit 704-5 according to the preferred embodiment further comprises a selection switch ZREG-704-53 with 4 positions, which is controlled by the coding of the CCSR field. The output of the ZREG switch is used to load the RREG register 714-42 with constant values or with signals corresponding to bit positions 24-26 of the RBIR register 704-152. In the next cycle, signals corresponding to the contents of the RREG register 714-42 are transferred to the RRDXB register 704-189. In the case of commands referring to CCS codes and commands

909823 / 0B92

specify within the STR-SGL or the STR-DBL classes, become the same signals to the RRDXA register 7Ο4-Ί58 transfer. Furthermore, the contents of the RREG register 714-42 can be transferred to the RBASA register 704-156 under microprogram control Loading.

According to the arrangement of the present invention, the values selected as outputs from ZREG switch 704-53, which are specified by the coding of the CCSR field, also as inputs of the group of register occupancy circuits of block 704-60 supplied. These circuits keep track of the register updates of those accessible to the program Registers A, Q, Xn and IC from the first cycle of the flow operation with the instruction in the last cycle of the Flow enters the flow and is processed under microprogram control.

According to Fig. 3f, the register occupancy circuitry comprises three 4-bit registers 704-600 to 704-602, the outputs of which with the Contents of the RRDXA registers 704-158 are compared by comparison circuits 704-604 through 704-608. The output signals of the comparison circuits are combined in an OR circuit 704-610 to produce an output signal REGBSY to create. This signal is used as an input to the I-cycle circuits of block 704-102 if the contents of the RRDXA register 704-158 match the contents of any of the registers RBSYA, RBSYB, or RBSYC, compare circuits 704-604, 704-606, and 704-608, respectively, set the QDER gate in the ability to set the REGBSY signal to the binary value "1". This signals the occurrence of the register occupied state and during the control states FPOA and FPOP, the processor 700 causes the processing of the X cycle to be maintained until the register occupied state disappears.

909823/0592

The RBSY registers 704-600, 704-601 and 704-602 are loaded in a cyclical fashion and reset to "0" after the program accessible registers have been loaded , thereby completing the processing of the particular instruction. In more detail, the control circuitry of block 701-610 controls the selection of the RBSY registers to be keyed and reset in accordance with the ZREG-REGBSY and REG signals. The ZREG-REGBSY signal is generated under hardware control during the control state FPOA, while the REG signal is generated under microprogram control. Referring to Figure 3f, the control circuitry of block 704-610 includes a register load counter RLD-704-614 and a register decrement counter RRES-704-612. Both counters are incremented by a common clock circuit, not shown.

The count outputs of the RLD and RRES counters 704-612 and 704-614 are used as input signals Decoding circuit 70.1-616 supplied together with the signals ZREG-REGBSY and REG. The circuit 701-616 additionally receives signals CCSD16-17 according to the high-level upper two bits of the CCSR field.

As explained, the count of the RLD counter 704-614 is increased by one, so that once an occupied register (e.g. RBUSYA register) is loaded with a value due to an instruction, the next available occupied register (e.g. RBUSYB register) is selected for loading . If a register accessible to the program is loaded on the basis of an instruction, which is indicated by the signal REG, one of the RBSY registers is reset to the binary value "0" depending on the count of the RRES counter 704-612. The count of the RRES counter is due to the signal REG by one

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28495

increments if the in both the RLD and RRES counters 704-614 or 704-612 differ from each other (e.g. RLD, 4 RRES).

It can be seen from Fig. 3f that the lower two bits of the CCSR field (18-19) select the code that is applied to the output of the ZREG switch 704-53. The first position of the switch supplies a constant value "0001" which defines the selection of the Α register. The second position of the Switch supplies a constant value of "0010", which defines the selection of the Q register. The third position of the Switch provides the selection of a binary value "1" and bits 24-26 of the RBIR register 704-152, through which one the eight index registers Xn is selected. The fourth position of the switch provides a constant value of "0100", which means the selection of the command counter is determined.

The upper two bits of the CCSR field determine whether one or two registers are to be set and whether single or double loads are to be performed take place. The encoded register value from the ZREG switch is stored in registers RBSYA, RBSYB and RBSYC as a function from the value of the CCS field and the count · ^ value RLD loaded. The type of register load operations, as determined by the coding of the CCSR field, results as follows:

CCSR CODE . OPERATIONS

0000 - 0001> ZREG 0 »FDBL; (A REG);

ZREG ^ RBSYA, B, C in function of

Count RLD; +1> RLD.

909823/0592

CCSR CODE OPERATIONS

OOO1 0010

0011 1000 1001 0100

0101

0110

0111

0010 > ZREG 0>FDBL;QREG;

ZREG> RBSYA, B, C as a function of

RLD; RLD + 1> RLD.

1, RBIR24-26> ZREG; 0— = ► FDBL;

INDEX REG

ZREG> RBSYA, B, C as a function of

RLD; RLD + 1> RLD.

0100 ^ ZREG; 0 ^ FDBL; IC;

ZREG> RBSYA, B, C as a function of

RLD; RLD + 1> RLD.

0001 > ZREG 1 »-FDBL; AQREGS.

ZREG ^ RBSYA, B, C as a function of

RLD; RLD + 1> RLD.

0010>ZREG; 1 > FDBL; QAREGS;

ZREG> RBSYA, B, C as a function of

RLD; RLD + 1> RLD.

No change to RBSY; 0001> ZREG

Register.

No change to RBSY; 0010> ZREG

Register.

No change to RBSY; 1, RBIR24-26-ZREG Register.

No change to RBSY; 01OO—> ZREG 'register.

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-152-20495

In those cases where FDBL = I a double register transfer indicates, the following operations are performed.

If CCSR3 = 1 then 0010> ZREG;

if CCSR3 = 1 then 0001 > ZREG;

0 ^ FDBL; RLD + 1> RLD

ZREG > RBSYA, B, C in function of the RLD.

909823/0592

Processing unit 714 - Fig. 3g

Unit 714 comprises as main units: Addressable temporary ones Registers rows 714-10 and 714-12, an arithmetic logic unit ALU-714-20, a displacement unit 714-24 and a buffer 714-30. Unit 714 also includes one Number of multi-position data selection switches 714-15, 714-17, 714-22, 714-26, 714-28, 714-34, 714-36 and 714-38 to allow flexibility in the selection of operands and output results to accomplish.

During operation, the operands are set using the ZOPA switch 714-15 and ZOPB switch 714-17 from one of the registers in rows 714-12 and 714-10 or from other input lines such as ZEBO-35 or RD10-35 selected. The unit ALU-714-20 and shifter 714.-24 perform operations on the selected operands and the results become selected via the switches 714-24, 714-36 and 714-38 and applied to the output collective sewer lines ZRESAO-35 and ZRESBO-35 « Likewise, the cache location content selected by a cache buffer 714-32 becomes read out via switches 714-34, 714-36 and 714-38.

The selected output results or other data are then loaded into other registers within the processor 700, this in the temporary register rows 714-12 and 714-10 or the buffer memory 714-30 of the processing unit 714 happens.

More specifically, the sources of the operands for the ZOPA and ZOPB switches 714-15 and 714-17 are identical. The selection The position of the switches ZOPA and ZOPB is controlled by means of bits 9-12 and 13-16 of the micro command word. The unit ALü-714-20 has logical, decimal

909823/0592

or binary operations on the selected operand data under control of bits 24-28 of the microinstruction word according to FIG. 6a.

The displacement unit 714-24 1st to shift a logic circuit which is used to binary data _# under microprogram control orient or rotate. The input data signals of the ZSHFOP and ZEIS switches 714-28 and 714-22 can be viewed as concatenated to form a single double word. Shift unit 714-24 provides a 36-bit output which is shifted out in accordance with the shift count. The ZSHFOP switch 714-28 is controlled by bits 24-25 of the microinstruction word, while the shift count is formed by the sequence control constant fields (bits 138-143) of the microinstruction word according to FIG is selected. In terms of the present invention, units 714-20 and 714-24 can be considered conventional.

The buffer memory 714-30 has a working memory area for the storage of various data, such as are necessary for the processing of certain commands, as well as for the storage of various constants and descriptor values. For example, the octal presets 10-15 are used to store a processing command table value which is required for the execution of processing operations. The writing into the buffer memory 714-30 initially includes the loading of the RSPB buffer register 714-32 with input data which are applied via the ZRESB switch 714-38. WSb "At the end of a next cycle, the contents of the register 714-32 are written into the memory location which is determined by the signals supplied by the auxiliary control unit 722 via the ZPSPA lines 0-6. The writing takes place when the bit 22 of the microinstruction word (RSP-FeId) is set to the value "1" .

• 909823/0593

As for the other switches mentioned, the
Results generated by the unit 714 are applied under microprogram control to the switches ZALU-714-26, BSPDI-714-34, ZRESA-714-36 and ZRESB. The switches ZALU and ZSPDI supply a first selection level for the switches ZRESA and ZRESB, which supply a final selection level. Since both switches ZRESA and ZRESB have identical input sources, they can deliver the same output data. The selection of the data of the switch ZALU takes place under control of the bits 30-31 (ZALU-FeId), while the selection of the data of the switch ZSPDI takes place under the control of the bit (ZSPDI-Field). The data of the switches ZRESA and ZRESB are selected under the control of bits 17-18 and 19-20 of the microinstruction word according to FIG. 6a.

The registers in rows 714-12 and 714-10 become independent
appropriately addressed by bits 3-5 (TRL field) and bits 6-8 (TRH field). The first bit in each field determines whether one of the four registers is to be addressed, while the other 2 bits select the register to be addressed. Finally, a four position switch 714-40 is used to load an RREG register 714-42 with constant values or with signals corresponding to bit positions 24-26 of the RBIR register 704-152,

909823/0592

Drawing unit 720-3h

It can be seen that the unit 720 comprises: a series of 4 registers 720-10, a number of registers 720-22, 720-24, 720-28, 720-30, 720-42, 720-46, 720-54, 720-63, 720-64, 720-68 and 720-70, conversion logic circuits 720-27, adder circuits 720-32 and 720-34, a comparison circuit 720-72 and a number of decoder / detector circuits 720-36, 720-38, 720-44, 720-48, 720-50, 720-56, 720-58 and 720-74, which have a number of multi-position selector switches 720-26, 720-40, 720-62, 720-12 to 720-20 are connected to each other. The control and selection "of these switches and the keys of the The various registers are under the control of a number of flip-flop circuits in block 720-80 and a pair of zero detector circuits 720-82 and 720-84.

The series of RCH registers 720-10 are used as operand buffer registers used for the storage of information received from the processing unit 714 via the ZRESA lines 0-35 Will be received. A first register 0P1 is used to store the operand identified by descriptor 1 or the data sent to the unit 728 or the unit 722 is fixed. A second register 0P2 is used to store the store descriptor 2 specified operands. Third and fourth registers (table entry 1, table entry 2) become is used to store edit insertion table entry values obtained from edit unit 714.

The RCN1 register 720-28 stores the current character position data for descriptor 1 which is used to select a character to be selected by the ZCU switch 720-12. The RCN2 register 720-30 stores signals specifying the character position data of the descriptor 2. The content is used to select a character by switch 720-14.

909823/0592

The ZCU and ZCV switches 720-16 and 720-18 are controlled by the ZCU and ZCV flip-flops of block 720-80. The RCN 1 and RCN 2 registers 720-28 are loaded under control of the CN1 and CN2 flip-flops of block 720-80 in response to signals generated by the decoder 720-56. This is done as a function of the character type (4, 6 or 9-bit characters), which is defined by the contents of the RTF1 and RTF2 registers 720-42 and 720-46, and as a function of the start character position signals that are carried out by the conversion logic of block 720-27 are generated. The circuitry of block 720-27 converts signals ZCNO-2, which are applied via switch 720-26 in accordance with an input character position value, into an output character position. No conversion is required for 9-bit characters, that is, the input character position corresponds to the output character position.

The 2-bit register 740-42 stores the character type information related to the descriptor 1, while the 2-bit RTF2 register -720-46 stores the character type information for the descriptor 2. The T-bit RTF3 register 720-52 stores the character type information for the descriptor 3 ... If the descriptor 3 consists of a 9-bit character, the detector 720-50 sets the RTF3 register to the binary value "1" . In all other cases the RTF3 register is set to the binary value ¹¹ O ". As can be seen from the figure, these registers are loaded via the switch 720-40. The 5-bit RMOP register 720-70 stores the micro-operation values which are required for the processing of an edit instruction, while the 4-bit RIF register 720-63 stores the information field values IF for such instructions. The 9-bit RCD register 720-64 is used during certain compare instruction operations, for storing a first operand value. the 5-bit PTE8 register 720-68 stores the signifikantesten 5 bits of the eighth rendition insertion table entry value in response to a load signal from the decoder on the basis 720-74

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2649500

a load instruction is generated. The REFILL register 720-22 is used to store signals received by the unit 704-150 over the ZIDDO-8 lines. That RAD register 720-24 stores character position bits received from unit 704-3 over lines ASFA34-36.

The indicator flip-flops of block 720-80 store the result an operation specified by the contents of the RMOP register 720-70. The indicators include a 2-bit MOP indicator A (MOPIA), a 3-bit MOP indicator B (MOPIB) and a 1-bit end indicator. The MOPIA indicators will be decoded as follows:

00 go to the MOP processing operation

01 go to the load MOP operation

10 test MOPIB

11 N / A.

The MOPIB indicators provide an additional status if the ΜΟΡΙΑ indicators show the value "10". They will be like this decoded:

000 Test of the status of the indicator of length 1 for underflow (L1UDF is set if the output of the AXP adder has the value "0", which means that L1 has been processed) and test the status of the CN1 overflow indicator (CN10VF).

001 test the state of the indicator for the length of 3 to underflow (L3UDF set when the Ausgar -j of the adder AL has the value "0", cat Bede, processed L3 that is) and test of the Zustan ". ~ s a CN3 overflow indicator (CNLOVF) which is set when the output of the adder AP has the value "0".

, 9 09823/0 6 92

010 Test of the states of the indicators L1UDF, C1OVF, L3UDF and CN30VF.

011 Decrease the value of length 2 by 1 and test the states of indicators L3UDF and CN30VF during a first cycle and test the states of an underflow indicator for length 2 (L2UDF) and the CN20VF indicator during a second cycle.

• 100 Test the states of the indicators L3UDF, CN30VF, L1UDF and C10VF during a first cycle, transfer the content of the RAAU register to the processing unit 714, decrease the value of the length 3 by 1 and increase the value CN3 by 1 during a second Cycle. During a third cycle, test the states of the indicators L3UDF and CN30VF, 101 Load the table entry value.

110 Change the table values.

111 N / A.

The END indicator is set to indicate that the through the operation specified by the MOP is completed.

Auxiliary and Control Arithmetic Unit (AACU) 722 - Fig. 3i

The AACU-722 comprises 3 parallel adding circuits 722-2, 722-6 and 722-8 which function as hint adders, exponent adders and length adders, respectively. The note adder circuit 722-2 comprises two rows of 4 registers (RP0-RP3 and RP4- RP7 ) 722-20 and 722-22. Each row has its own multi-position switch 722-23 and 722-24 for the selection of the data to be written in and a pair of output switches with 4 positions for the selection of the data to be read out, e.g. B. switches 722-27, 722-28 and 722-29, 722-30. The 722-20 series also has a second input switch 722-32, the output of which works on the ZRPA switch 722-23 and the selection of additional input data

The ZRPC switch 722-32, the ZRPA switch 722-23 and the Register series 722-20 are shared either by bits 64-68 (ZRPAC field), bits 69-71 (ZRPAC-3 field) or the Bit 67 (ZRPAC-4 field) controlled depending on the microinstruction format. The ZRPA switch 722-23 can be one of the Outputs of the ZRPC switch 722-32 via a first position, a value for loading a character shift for an address modification / das Load address register commands for character unit 720 via a second position and character hint value for a 9-bit character select via a third position.

Select the ZPA switch 722-27 and the ZPB switch 722-28 Data from RP0-RP3 register row 722-20 under control of bits 59-60 (ZPA) and bits 61-62 (ZPB), respectively the end. The ZRPB switch 722-24 and the register row 722-22 are jointly dependent by a single control field controlled by the type of microinstruction format, bits 74-78 (ZRPB-O), bits 69-73 (ZRPB), the Bits 72-74 (ZRPB-3) or bit 68 (ZRPB-4) can be used. The ZRPB switch 722-4 can control the output of the adder output switch 722-36 over a first position, an information field from the drawing unit 720 over a second position, a word or character hint value for a 9-bit character via a third position and a character hint value for select a 9-bit character via a fourth and a fifth position.

Select the ZPC switch 722-29 and the ZPD switch 722-30 Data from the RP4-RP7 register row 722-23 under the control of bits 57-58 (ZPC field) and bits 67-68 (ZPD field) accordingly. Referring to Figure 3, the outputs of switches 722-27 through 722-30 become the A and B operand switches 722-25 and 722-26 created. The outputs of these switches are fed to an indication adder 722-34.

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' ^Ί61 "

The ΖΑΡΑ switch 722-25, the ZAPB switch 722-26 and the Adders 722-34 are shared by bits 79-84 of a single control field (AP field) or bits 82-83 (AP-3 field) depending on the microinstruction format. As can be seen from the figure, the ZAPA and ZAPB switches 722-25 and 722-26 select the outputs of the switches ZPA, ZPC, ZPB or ZPD or a constant value for supply to the adder 722-34.

A ZLX switch 722-36, a ZXC switch 722-38, an RSC register 722-40 and a ZRSC switch 722-42 are operated under microprogram control and are used to deliver Shift count signals to the shift unit of the processing unit. The ZSC switch 722-38 can also for loading data into the RP0-RP3 register row 722-20 via the ZRPC and ZRPA switches 722-32 and 722-23 or into the RP4-RP7 register row 722-23 can be used via the ZRPB switch 722-24.

The selection of the ZLX switch positions is made by the bits 48-49 (ZLX field) controlled. The ZSC switch 722-38 is used to switch one of the outputs of the ZLX switch 722-38 to be selected under the control of bits 50-52 (ZSC field). The RSC register 722-40 is the rightmost 6 bits Loaded from the output of the ZLX switch 722-38 under control by bit 47 (RSC field). The ZRSC two-position switch 722-42 selects one of two sources to provide the processing unit 714 with a shift count. Bit 84 (ZRSC-FeId) selects either bits 138-143 (CNSTU / L-FeId) or RSC register 722-40 as the source for the shift count.

The final group of circuits shown in block 722-2 include a ZAAU switch 722-44 and a RAAU register 722-46 to which the output of switch 722-44 is fed. The ZAAU switch 722-44 is used to

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Transfer data to register 722-46. From there will be transmit the data via section 704-5 to processing unit 714 on ZEB lines 0-35.

The inputs of the ZAAU switch 722-44 are defined by the bits 50-52 (ZAAU-FeId) selected. The first position gives you one 9-bit character output from character unit 720 over the lines ZOC 0-8. The second and third positions are used to set the outputs of the length adder and the exponent adder of blocks 722-6 and 722-8. The RAAU register 722-46 is dependent on the ZAAU switch 722-44 loaded from bit 47 (RAAU field).

Referring to Figure 3i, the exponent adding circuit includes 722-6 a single row of 4 registers RXPA-RXPD. The 722-60 series has a multi-position switch 722-62 for the selection of the data to be written in and a pair of output switches with 4 positions for selecting the data to be read out, e.g. B. switches 722-64 and 722-66. The ZXP switch 722-62 and the register row 722-60 is defined by bits 59-72 (ZXP-field), bits 65-66 (ZXP-1 field) and bits 75-77 (ZXP-3 field) controlled.

A first position of ZXP switch 722-62 is used to load the exponent result into register row 722-60. The second position is used to store the result of length adder 722-8. The next third position will be used to store exponent values obtained from the drawing unit 720. Finally the fourth position used to store numerical weighting factor information received over RSIR lines 24-35.

Select the ZXPL switch 722-64 and the ZXPR switch 722-65 Data from the register row 722-60 under the control of bits 63-64 (ZXPL field) or bits 64 (ZXPL-1 field) and using bits 65-66 (ZXPR field) accordingly. The outputs of switches 722-64 and 722-66 are used as inputs

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a Α operand switch 722-68 and a B operand switch 722-70 supplied accordingly. These switches carry selected inputs to a pair of 12-bit adders (AXP and AXM) Blocks 722-72 which produce an exponent output which is applied to a ZAXP output switch 722-74. A single control field AXP (bits 69-73) controls the operation of the ZXPA switch 722-68, the ZXPB switch 722-70, the ZAXP switch 722-74 adder and loading of a RE register 722-76.

An adder AXM receives the contents of the RE register 722-76 in order to form an absolute value if the sign of the value generated by the AXP adder is negative (e.g., the AXP not shown has a sign indicator control via the ZAXP switch selection).

The ZXPA switch 722-68 can have the Select the content of the RE register 722-76 or the output of the ZXPL switch 722-64 via a second position. Of the ZXPB switch 722-70 can set a constant value via a first position, binary floating point exponent signals via a second position, that are applied to the RDI lines 0-7, via a third position, a numerical weighting factor that is applied to the RSIR lines 24-35 a fourth position the output of the ZXPR switch 722-66 and a fifth position the output of the ZLNA switch Select 722-84.

The third adding circuit 722-8 for processing the operand length data, like the circuit 722-6, comprises one single row of 4 registers RLN1-RLN4. This row of registers 722-80 has a multi-position switch 722-82 for the Selection of the data to be written in and a pair of output switches with 4 positions for the selection of the data to be read out Data, e.g. B. switches 722-84 and 722-86. The ZLN switch

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722-82 and the RLN1-RLN4 series of controllers 722-80 are supported by bits 59-63 (ZLN-1 field), bit 63 (ZLN-2 field), the Bits 79-81 (ZLN-3 field) or bits 79-83 (ZLN-4 field) controlled depending on the microinstruction format.

The ZLN switch 722-82 gives the output of the length adder via a first position as an output signal, the output of the ZAXP switch 722-74 via a second position and a Length field value from RSER lines 24-35 via a third Position. In addition, it provides a numeric length field value from RSIR lines 30-35 via a fourth position, a shift count value from RDI lines 11-17 via a fifth position and a length value from the RCH lines 24-35 via a sixth position as input signals to the register row 722-80.

ZLNA and ZLNB switches 722-84 and 722-86 select data from register row 722-80 under the control of bits 53-54 (ZLNA-Field) and bits 55-56 (ZLNB-Field) as Inputs for an A operand switch, lter 722-88 and a B operand switch 722-90 accordingly.

The outputs of these switches are used as inputs to a 12-bit length adder AL-722-92 supplied. The ZALA switch 722-88, the ZALB switch 722-90 and the AL adder 722-92 are controlled by bits 74-78 (AL-Field). The ZALA counter 722-88 selects the output of the ZLNA switch as an operand via a first position, a constant field via a second position, the output of the ZPC switch over a third position and a numerical length field over a fourth position.

The ZALB switch 722-90 can use a constant field as an operand via a first position, the output of the ZLNB switch 722-86 via a second position, the output of the ZXPL switch via a third position, a shift count value from RDI lines 11-17 through a fourth

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COPY

Position ^ the output of the ZPC switch via a fifth Position / the output of the ZPA switch via a sixth position and bit positions 6 and 7 of the ZPC switch Select 722-29 via a seventh position.

Unit 722 includes another group of circuitry for providing a buffer address to the unit 714. The circuitry includes a ZSPA switch 722-100, an RSPA register 722-102 and a ZRSPA switch 722-104, which are controlled accordingly by bits 48, 49 (ZSPA-field), bit 47 (RSPA-field) and bits 50-52 (ZRSPA-field) will. The ZSPA switch 722-100 can be used as an output bits 91-97 corresponding to a buffer address field via a first position and the output of the hint adder Select 722-34 via a second position.

The ZRSPA switch 722-104 can output the content of the register 722-102 via a first position, a buffer address field via a second position and a descriptor value applied by the RSIR lines 32-35 via a third position and a value of the RSPR register of the unit 704-150 via a fourth position. Unit 722 additionally includes a pair of registers 722-106 and 722-108 which are loaded with signals corresponding to bit positions 21-23 of RSIR register 704-154. A register is loaded when bit 53 of the microinstruction word according to FIG. 6b or the FPOP flip-flop is set to the binary value "1". The registers are selected for loading in accordance with the states of the RDESC register 704-140 (00 or 10 = R1DW; 011 «R2DW).

The various control field signals used by the unit AACU-722 are derived from a decoder 722-110 , to which the various bits of the microinstruction word which is loaded into the register 722-112 are applied as input signals.

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Buffer Unit 750 - Fig. 4

The buffer unit 750 is divided into five primary sections: An instruction buffer section 750-1, a control section 750-3 / a buffer list section 750-5, a buffer storage section 750-7 and an instruction buffer section 750-9.

Instruction buffer section 750-1

The instruction buffer section 750-1 comprises a write instruction buffer 750-100 for four words and a corresponding read instruction buffer 750-102, which are addressed via the counters 750-104 and 750-106 »The write ZAC buffer 750- 100 is used to store a single ZAC write instruction, while the read ZAC buffer 750-102 is used to store up to four read ZAC instructions »

The processor 700 transmits instructions over the RADO / ZADO lines of the interface 605 via the first position of a selection switch 750-110. The processor 700 transmits buffer memory instruction information on the lines DMEM and DSZ via the first position of a selection switch 750-112. " The states of these lines are stored in a register 750-114. As can be seen from the figure, this information is stored. nation is also written into buffers 750-100 and 750-102 .

In addition to the buffer instruction signals, processor 700 asserts a DREQCAC line. The processor 700 sets other control lines (e.g., HOLD-C-CU, CANCEL-C, CACFLUSH, BYPASS-CAC, READ IBUF, READ EVEN) when the buffer storage unit 750 is to perform other types of operations.

The states of the other control lines are decoded by a decoder 750-116 , the output of which is used to convert

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release the ZAC buffers 750-100 and 750-102. The processor 700 additionally transmits zone bit signals for certain types of write instructions via the DZDO-3 lines. These signals are entered into an RDZD register 750-132 via a switch 750-134 loaded. From there, the content of these registers is applied to a group of byte lines CBYSEL via a switch 750-136. The signals on the DZO lines are also applied to the MITS lines via a switch 750-139. Other zone signals (bits 5-8) are stored in an RC address register 750-140 are loaded and then applied to another group of byte selection lines CBYSEL via a switch 750-142.

Multiple occupied bit registers 750-120 and 750-122 are used to determine which of the storage locations in the RZAC buffer 750-102 are available. The states of these registers are decoded by a priority decoder circuit 750-130 which controls the selects the first available buffer space. The generated value is stored in register 750-106 and used as a Write address for the read: ZAC buffer 750-102 used. if the buffer memory request includes a background memory fetch (a buffer memory mismatch is indicated by signaled the state of the BSPD signal), the appropriate busy bit or both busy bits will be in accordance with the number of interface responses (ARDA signals) are set. The busy bits are set by signals transmitted over a pair of lines SETBOTHSSY and SETONEBSY from a non are supplied to the decoder shown, which decodes the specific instruction, which leads to the activation of a signal leads to one of the BSY lines. For example, a single read instruction (which is not bypassed) calls for two SIU-ARDA responses each answer bringing in a pair of words. Both occupied bits are thus set. In case of a Single read bypass statement results in only one SIU-ARDA response. Accordingly, only one busy bit is set. The provision the busy bit finds over due to the ARDA line

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an RSPB register 750-124 takes place, which signals from the Interface unit SIü-100 via the RMIFS lines receives.

In more detail, the contents of registers 750-120 and 750-122 are determined in accordance with the number of ARDA responses set when a signal PENBIT has the binary value "1" (e.g. the pending bit is not set according to the block). The decoding circuit 750-130 decodes the States the occupied bits and sets the counter register 750-106 to the appropriate address value, whereby the next empty Storage space specified within the read RZAC buffer 750-102 will.

The same address signals PRACWO-1 are also sent to a second position of switch 750-139 applied in the case of read instructions. From there the signals are entered into a 4-bit MITS register 750-138 charged and applied to the MITS lines. The main memory 800 overrides the coded signals the MIFS lines to the buffer unit 750 in transit of the requested pairs of data words of a block. Then the signals are stored in a 4-bit RMIFS register 750-125 and then loaded into the RSPB register 750-124 when the control state signal THCFD has the binary value "1". Of the value received calls for the resetting of the associated busy bit indications stored in registers 750-120 and 750-122 emerged.

It should be noted that the RMIF bit signals 2 and 3 are used, around the read RZAC buffer 750-102 to read out the appropriate instruction to address. In addition, signals are used by an output signaling circuit (not shown) COUT in order to activate Access instructions stored in the read ZAC buffer 750-102 are. The busy bit indications stored in registers 750-124 and 750-126 are used as input signals Exclusive-OR circuits of block 750-132 are supplied. These

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Circuits generate output signals that indicate the number of busy bits set. These output signals are in turn supplied to various positions of a selector switch 750-133 with four positions. By choosing the The switch 750-133 supplies a suitable position or memory location depending on the RMIFS bit signals 2 and 3 an output signal SECRCV, the state of which determines when the Buffer unit 750 has received the second pair of words of a block. The SECRCV signal is used as the input signal Block 750-3 is supplied.

The outputs of the write ZAC buffer 750-100 and the read ZAC buffer 750-102 are different switches within a group of switches with 2 positions 750-150, 750-152, 750-154, 750-156 and 750-158. The output signal of the ZAC buffer switch 750-150 is stored in an SIU output register 750-174 charged via switches 750-170 and 750-172. The output of the ZAC switch 750-152 is via the switches 750-177 and 750-178 loaded into a pair of data registers 750-180.

The outputs of switches 750-154 and 750-158 are connected to a Another switch 750-160 is applied and stored in a holding register 750-162. The output of switch 750-156 becomes fed together with the outputs DMEM of the switch 750-160 to a decoder 750-166. The other outputs of this Switches are applied to a decoder 750-168. The output of switch 750-168 is also applied. Furthermore, the output of switch 750-158 is applied to a decoder 750-164.

The decoder 750-166 decodes the buffer instructions and received from the processor 700 over lines DMEMO-3 those instructions read out from the buffers 750-100 and 750-102 and generates signals for transferring the instructions to the buffer storage unit 750-7 and to the list 750-5.

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This means that the buffer decoder uses 750-166 to determine what information is to be written into the buffer storage unit 750-7 by the processor 700 is. The decoder 750-168 decodes the states of the signals BYPCAC and DSZ1. It should be noted that the source of this the last-mentioned signals is given by the processor 700 or the switch 750-154.

The decoder 750-164 decodes the instructions read from the buffers 750-100 and 750-102 and generates signals to the transfer of instructions to memory MEM (background memory) via the interface unit SIU-1OO. This means, the decoder 750-164 is used to control the sending of the information from the instruction buffers 750-100 and 750-102 to the Interface unit to control SIU.

The ZPSW switch 750-178 also selects a first position the ZAC instruction from the processor 700 on the lines RADO / ZADO for transmission to the interface unit SIU-100 the DTS lines via the switch 750-172 or it writes the main memory data via the RDO and RDI data registers 750-180 into the buffer storage unit 750-7. The second position of the ZPSW switch 750-178 sets the data output of the ZALT switch 750-177 to the DTS lines (ZAC data) or writes the main memory data from the DFS lines via the RDO and RDI registers 750-180 in the buffer storage unit 750-7 or transmits the ZAC instructions over the ZDI lines to the processor 700.

The ZACSV / 2 switch 750-170 is used to execute a ZAC instruction to transmit (first position) or to data from the ZAC buffer over the DTS lines to the interface unit SIU-100 transferred (second position).

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Control Section 750-3

This section includes a number of control state flip-flops which generate signals to advance the buffer unit 750 which are required for the cycles of operation in processing various instructions. The section also includes the necessary logic circuits for generating the necessary control signals during the required operating cycles. For the present invention, these circuits can be implemented in a conventional manner. Therefore, in order to simplify the description at this point, only a brief description and the Bool ¹ see equations are given for certain control state flip-flops and control logic circuits which are necessary for an understanding of the present invention.

The control state flip-flops generate a series of timing sequences, which control the following data transfers:

(1) Processor to buffer memory, SIU interface

(Transfer of operation to the buffer memory and to the SIU interface);

(2) Processor to the SIU interface (transfer of Write data to the SIU interface);

(3) ZACBUF to the buffer memory (operational transition to the buffer memory);

(4) ZACBUF to the SIU interface (transfer of operations to the SIU interface);

(5) Processor to ZACBUF (write data saved in the buffer);

(6) SIU interface to buffer memory, processor (2 words transferred);

(7) SIU interface to the buffer memory, processor (1 word transferred).

The transfers use the following flip-flops.

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Control state flip-flops

The OATB flip-flop is the first one set in a first sequence Flip-flop, which enables information transfer from the interface SIU-100 to the buffer memory 750 and to the Processor 750 enables. The OATB flip-flop will be for a Cycle set according to the following Boolean equation: ARDA · DPFS.

The THCFD flip-flop is the next one set in the first sequence Flip-flop that controls the transmission of the information received from the SIU-100 interface unit during the OATB cycle to the processor 700 via the lines ZDI. The THCFD flip-flop is operated for one cycle according to the following Boolean equation set:

Set: OETF = ARDA · DPFS.

The UG COGTH flip-flop allows that when set Setting or resetting an F / F bit, setting an unfinished bit, setting RR bits, writing MSA in the address of the list section and the writing of data in the case of a single write instruction in the buffer memory. This flip-flop is made according to the following Boolean equations set and reset:

Set: HOLD · SET-COGTH

. Reset: (HOLD): CAC-BSY1 · NO-HOLD-CAC «CACBSY1 +

NO-HOLD-CAC

The UGSOGTH flip-flop is the first set flip-flop in a transmission from the processor CPU to the interface unit SIU. In the set state, a first data word is sent to the DTS lines. It is set for a cycle according to the following Boolean 'shear equation:

Set I HOLD · DWRT where DWRT = CWRT · SNG + CWRT · DBL + CWRT'RMT.

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The CAOPR flip-flop is set due to the reading of an AOPR response. This is done for a cycle according to the following Boolean equation ¹ shear:

Set: SSET-IN · CLD-IBUF (CBYP-CAC + BPSD) + CPR-RD.

CBYP-CAC • BPSD + (CRD-SNG + CRD-DBL) • (CBYP-CAC + BPSD) + CRD-CLR + CRD-RMT + CWRT-SNG + CWRT-DBL + CWRT-RMT.

The CPR-FF flip-flop is used to determine when the Buffer unit responds to a signal DREQ-CAC from processor 700. If this flip-flop was at "1" during a previous one Cycle is set, the buffer unit does not respond to a request except in the cases of Statement of the following type: PREREAD, INST-F1, INST-F2, LDQUAD, RD-SINGLE or RD-tDBL. The flip-flop is set and reset according to the following Boolean equations:

Set: (CINST-F1 + CINST-F2 + CLD «QUAD + CRD« DBL + CRD · SNG)

(CBYP-CAC + BPSD) + CPR-RD «CBYP-CAC-BPSD. Reset: HOLD = RD-BSY.

The RBPSD flip-flop is used to switch off the processor 700 in the event of a HOLD-ON-MISS or BYP-CAC state. When the data come back from the interface unit SIU-100, this flip-flop is reset, with the exception of an INST-F1 cycle. In the case of such a cycle, after 4 words have been received by the interface unit SIU-100, this flip-flop reset. It is set and reset according to the following Boolean equations:

Set : SSET-IN · HOLD-CAN • CRP-RMT + CRD-CLR + (CINST-F1 +

CRD-SNG + CRD-DBL) · (CBYP-CAC + BPSD) Reset: (HOLD) = THCFD · SEC-RVC »CINST-F1 + DATA-RECOV.

INST-F1-FF.

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The ZC-DL flip-flop is initially set to "1" in order to trigger a timing sequence for the transition from a ZAC buffer to the buffer memory. This flip-flop remains set until all requests that require the completion of such sequences have been processed. It is set and reset according to the following Bool ^{1 equations:}

Set: SSET-IN PENBIT + UGCOGTH CAC-BSY-1

+ PRE-OK «CAC-BSY1 + TLTHM-CAC-BSYI

Reset: HOLD = HOLD-CAC + CAC-BSY-1 + PREOK +

UGTLTHM + PENBIT - WAIT.

The PRE-OK flip-flop is initially activated during a timing sequence the transfer from the ZAC buffer to the buffer memory is set to the binary value "1". It will be seen according to the following Boolean Equations set and reset:

Set: ZC-DL HOLD-CAC CAC-BSY-1 PRE OK «OK-

TLTHM.PENBIT-WAIT «CET

Reset: HOLD = HOLD-CAC'CAC-BSY1.

The UGOK flip-flop is the second during the transmission from the ZAC buffer to the buffer memory triggering time cycle sequence is set to the binary value "1". That flip-flop allows operations similar to those performed during a DREQ-CAC cycle are executed. It will be seen according to the following Boolean Equations set and reset:

Set: PRE-OKCAC-BSY1.HOLD-CAC Reset: HOLD «HOLD-CAC · CAC-BSY1.

The PENBIT-WAIT flip-flop is set to "1" when there is a request on the reading type defines the same address as a previous request, with regard to the previous Request, not all data have been received from main memory. It will be deferred when all unfinished business Read requests have been processed. It will

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set and reset according to the following Boolean equations:

Set: SSET-IN.PENBIT

Reset: HOLD = RDBSY.

The PENBIT-FF flip-flop is set to "1" on the basis of a single read or double read request, this request defining the address of a previous read request whose data was not received by the main memory. It is reset during a PRE-OK cycle of operation. This flip-flop is used to stop the processor from operating. It is set and reset according to the following Bool ¹ equations:

Set: SSET-IN PENBIT (CRD-DBL + CRD-SNG) Reset: HOLD = PRE-OK + HOLD-CAC + CAC-BSY-1.

Thirdly, the TLTHM flip-flop is set to the binary value "1 ^M " during the transfer from the ZAC buffer to the buffer memory. This flip-flop is set on the basis of a double read instruction after an OK operation cycle. It is set according to the following Boolean equations set and reset:

Set: OK'CAC-BSY! (BPSD + CRD-DBL) Reset: HOLD = HOLD-CAC-CAC-BSY1.

The FRD-DBL flip-flop is used to form the TLTHM clock cycle. If the flip-flop CAC-BSY1 is set to "1" during the TLTHM cycle, a flip-flop ZDBL-FF- is set by the FRD-DBL flip-flop in the event of a double read instruction. This allows the buffer unit to halt the operation of the processor if it is unable to direct a second hoard to the processor during the TLTHM cycle. The FRD-DBL flip-flop is set for one cycle according to the following Boolean equation:

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Set: CRD-DBL.

Control logic signals

1. The CPSTOP signal is the signal which is used to shut down the processor 700.

CPSTOP = FBPSD = REQ CAC fRDTYP RZAC-ALL-BSY + PREF. (PR-RD +

INST-F2 + LDQÜAD + RD-SNG + RD-DBL) + CAC-BSY1 + CAOPR + UGCOGTH] + RBPSD + DBL-FF + PENBIT-FF + (RD-IBUF / ZDI-CAC-BSY-I) + (RD-IBUF / ZDI-LD-QUAD-FF) + (UGCOGTH · RD-DBL · CAC-BSY1).

2. The CAC-BSY1 signal indicates when the buffer storage unit is occupied.

CAC-BSY1 = OATB + THCFD.

3. The [$ F / E-WRT signal is a write enable signal to the
Setting and resetting of the full / empty bit.

[ $ F / E-WRT = CAC · BSY1 · (UGCOGTH) -UGSOGTH-RD-DBL-BYP-CAC ·

DLY-BPSD * (INST = F2 + LD-QUAD) * BYP-CAC * DLY-BPSD.

4. The [$ PEN1-WRT signal is a write enable signal for the
Set the pending bits of the operation.

£ $ PEN1-WRT = CAC-BSY 1 · (UGCOGTH) · (INST-F2 + LD-QUAD + PR-RD4-RD-SNG · DLY-BPSD + RD * DBL-DLY-BPSD).

5 ·. The [$ PEN2-WRT signal is a write enable signal for the Reset the pending bits when all of the data associated with a request has been received from main memory are.

I # PEN2-WRT a THCFD · SEC-RCV · (INST-F2 + LD-QUAD + PR-RD + RD-SNG + RD-DBL · BYP-CAC).

6. The RZAC-ALL-BSY signal shows the occupancy status of the RZAC buffer which is formed in accordance with the states of the busy bits.

RZAC-ALL-BSY «(RBB-OO + RBB-01) * (RBB-10 + RBB-11).

(RBB-2O + RBB-21) · (RBB-3O + RBB-31) ..

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7. The [$ RMIFS signal is a write key signal that the Storage of multi-port identifier bits permitted if data or status information is from main memory Will be received. These bits determine which memory locations in the RZAC buffer that assigned to the received data Contain ZAC word (the data belong e.g. to one of the various possible unfinished read requests f $ RMIFS = ARDA + AST.

8. The ALTSWO-DT signal allows more detailed protection Data from main memory in registers RDO and RD1. ALTSWO-DT = CAC-BSY 1.

9. The ALTSW2-DT signal allows data to be transmitted from the ZAC buffer to registers RDO and RD1.

ALTSW2-DT = DS-ALT + ALTSWO-DT

where DS-ALT - DS-11 + DS-12 + DS-13.

10. The signals OPSWO-DT to 0PSW2-DT control the ZDI switch for the transmission of data words from the buffer memory to the processor 700 via the ZDI lines. OPSWO-DT = RD-IBÜF / ZDI

0PSW1-DT = RD-IBÜF / ZDI (REQ-CAC + UGCOGTH) 'WDSELO. 0PSW2-DT = RD-IBÜF / ZDI + WDSEL1 (RD-SNG + INST-F1)

+ REQ-CAC · UGCOGTH · INST-F1

+ REQ-CAC'UGCOGTH * RDSNG

f REQ-CAC-UGCOGTH · DBL-FF

11. The signals ZACSW1-LC1 and ZACSW2-LC2 control the switch 750-702, which selects the address source for all buffer memory chips. The sources are the processor 700 upon receipt of instructions of the ZAC buffer and the CADR address register ZACSW1 LC1-LC4 = ZACSW1-· CAC-BS-Y LUGCOGTH. ZACSW2-LC2 β CAC-BSY1 + UGCOGTH.

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12. The DATA-RECOV signal allows processor 700 to resume operation from a stop state (e.g., renewed Buttons of the registers). DATA-RECOV = THCFD (CINST-F1 + CRD-SNG)

(FMIFS-1'WDSELO + THCFD

CRD-DBL (FSMIFS-1'WDSELO + FMIFS-1.WDSELO + FMIFS-1 WDSELO + CBYP-CAC) + THCFD * CRD-RMT.

13. The RD-BSY signal determines when certain status flip-flops are postponed.

DR-BSY = RBB-00 + RBB-01 + RBB-10 + RBB-11 + RBB-20 + RBB-21 + RBB-30 + RBB-31.

14. The SSET-IN signal is used to set certain status plip-flops to put.

SSET-IN = RBPSD · CDBL-FF · PENBIT-FF-UGCOGTH-CAOPR-CAC-BSY1

fCPR-FF-CPR-RD'CINST-F2-CLD-QUAD-CRO-SNG'CRD-DBL]

[CRD-TYP'RZAC-ALL-BSYJ'DREQ-CAC

15. SEC-RCV = RMIFS-2'RMIFS-3 * [RBB-00 Q RBB-01] +

RMIFS-2-RMIFS-3 * [RBB-10 © RBB-11] +

RMIFS-2-RMIFS-3- [RBB-20 © RBB-21J + RMIFS-2'RMIFS-3 '[RBB-30 © RBB-31]

16. The BPSD signal indicates a buffer memory match condition at.

BPSD = BYP-CAC · > (ZADO1O-23 = SP-i-00 »14)

F / Ei'PENi

where SP-i-00 ' -E> 14 corresponds to the address list outputs (the saved address bits), F / Ei corresponds to the full / empty bit "i" and PENi corresponds to the pending bit "i".

909823/0 5

In the above equations, have the following symbols the following meaning:

• denotes an AND operation, + denotes an OR operation, and © denotes an exclusive OR operation.

Cache List Section 750-5

This section comprises a control list 750-500 with 4 levels and an associated address list 750-502 also with 4 levels. The list 750-502 comprises 128 columns, each column being subdivided into 4 levels, and the levels have a length of 15 bits, creating space in each column for 4 blocks. The control list 750-500 comprises 128 memory locations of 10 each Bit, with each memory location storing a control information word of 10 bits. The control information for each of the blocks comprises 2 cyclic bits RR, 4 full / empty bits F / E and 4 bits for a pending operation as shown.

The full / empty bits indicate whether a special list address has some meaning (e.g. is valid). For a match in the buffer memory to occur, the F / E bit must be set to "1". A value of "0" indicates the presence of an empty block. The cyclic bits provide one Count showing which block was last replaced. This count is under the control of a counter 750-512 incremented by 1 and used to identify the next block to be replaced. According to Fig. 3, this operation takes place when the cyclic bits and the full / empty bits are read out into a pair of output registers 750-504 and 750-506. The full / Empty bits are also read into a register 750-510 which controls the increment of the cyclic bits. This means that the cyclic bits are used after all full / empty bits are set to determine which of the full blocks for the new data is to be used. The resulting value ADDRRO-1

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is provided as an input to switch 750-518. All full / empty bits are reset by a trigger signal. The full / empty blts can be stored in a register 750-516 be set. When processor 700 issues a read request that results in a missing during state UGCOGTH If there is a match, a value "1000" is loaded into register 750-516. This value is put in the tax list 750-500 enrolled. With the next request, the value "1100" is loaded into register 750-516 etc. until all full / Empty bits are set.

The pending bits are used to indicate when a certain operation is pending. For example, when set, the pending bits indicate that all regarding data read in a specific block has not been received. Accordingly, if the Address list signals a match, with the pending bit is set, the buffer unit 750 stops the operation of the processor 700. As a result, there is no new request to the main memory.

The circuitry for setting and resetting the pending bits includes a 4-bit buffer register 750-520, a block decode register 750-524, and a decoder 750-512. Registers -750-520 are written through during a write cycle of operation. PRZACWO-1 signals are addressed via an address register 750-522 and during a read cycle by the MIFS2-3 signals. The block decoding registers 750-524 set various output signals BKDCODO-3 to the binary value "1" under the following conditions: If at least one full / empty bit has the value "0", the corresponding unfinished bit is via the decoder-750 -512 set. When all full / empty bits are set, the next value for the cyclical count is coded and this bit position within the group of 4 unfinished bits is set to "1". An unfinished bit is only reset via the decoder 750-512 when the buffer memory 750 has received all information (eg 4 words) from the interface unit

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SIU-100 has received. The contents of registers 750-520 show the position of the pending bit to be deferred. The unfinished bits read from the control list 750-500 are fed as input signals to the decoder 750-514 for updating in the required manner.

The pending bits are set according to the following conditions and postponed:

SET I INSTF2 (BYPCAC + CACMISS) + LDQUAD (BYPCAC + CACHEMISS

+ PREREAD (BYPCAC-CACMISS) + READSINGLE · CACMISS + READDBL · BYPCAC · CACMISS.

RESET: INSTF2 + LDQUAD + PREREAD + RDSNG + RDDBL * BYPCAC.

The actual control signals are in the form listed above.

The address list 750-502 contains 128 groups of 4 words, each word being 15 bits in length. Each 15-bit word corresponds to the address of a 4-word block in the buffer storage section 750-7. Whenever a ZAC instruction is processed and concerns the writing or reading of the buffer unit 750, the 15 bits of the block address contained in the ZAC buffers 750-100 or 750-102 are compared on a group basis with the address contents of the list 750-502 to determine the status of a match or a mismatch. In particular, the list meets their assignment 750-502 ^T calculations of bits 0-14 of the ZAC address to determine a match or a mismatch in terms. These bits correspond to the address signals which are applied either to the ZAC lines 11-18, 20-26 or to the ZADO / RADO lines 10-24, these lines being selected via the ZACSW switch 750-530.

The address of the list group is defined by a buffer address (CADDLO-6), which is activated via an input switch 750-702 is created with three positions. This allows reference to 4 block addresses which are read out and used as an input signal each of a group of 4 comparator circuits 750-536

9 (198 23/0592

to 750-542 can be fed. Each of the comparator circuits compares its block address with bits 0-14 of the ZAC address. The results produced by circuits 750-536 through 750-542 are connected to corresponding inputs of a first group of AND gates 750-544 to 750-550 together with corresponding signals of the full / empty bit signals of the register 750-506 are applied. A second group of AND gates 750-552 through 750-558 combine the outputs of AND gates 750-544 through 750-550 with signals ZEXTBKO-3, which indicate which block is selected via register 750-518.

AND gates 750-552 through 750-558 provide a group of output block select signals (e.g. the signals CBSELO-3), which are used as input signals to a buffer memory 750-700 and to a Group of list match detection circuits of the Blocks 750-560 can be created. The circuitry of block 750-560 includes a group of AND gates 750-562, the signals corresponding to the pending bits mLt of the block selection signals combine logically, the results being combined in an OR gate 750-564 to provide a list match signal on the BPSD line. the Circuitry of block 750-560 sets the BPSD line to the binary value "1" if the address bits 0-14 with the list contents match, the corresponding full / empty bit has the binary value "1" and the corresponding pending bit has the binary value "0". It is assumed that there are fault conditions.

Buffer storage section 750-7

The section 750-7 comprises a memory unit 750-700 with 2048 (2K) word memory locations for 40 bits, which are organized in 128 groups with 4 blocks. The unit consists of conventional bipolar chips. The buffer storage unit 750-700 is addressed by the 7-bit address CADDLO-6, which is via the

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Switch 750-702 is applied. The address is stored in a holding register 750-704. This calls the feeding of 4 Blocks of 4 words as inputs to a group of not shown 1 out of 4 selection switches. The appropriate block (level) is determined by the state of the lines Block selection signals fed to CBSELO-3 were detected. the supplied via the lines CBYSELO-7 via the switch 750-708 Signals provide the appropriate selection of the even or odd word byte. Between words O, 2 and 1,3 is that Byte selection independent and proceeds as follows:

OBYSELO (byte 0 selected) for words O, 2

CBYSEL3 (byte 3 selected) for Worce 0, 2

CBYSEL4 (byte 0 selected) for words 1, 3

CBYSEL7 (byte 3 selected) for words 1,3.

The over the lines CWSELO-3 via a decoder 750-706 supplied signals are used to define the words. This ensures that the content is in the appropriate bit positions the group of memory chips comprising the unit 750-700 is selected.

The words of a selected block are used as inputs to a number of groups of OR (NAND) gates 750-712 through 750-716 fed. Each tag group chooses the word of the selected one

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Blocks off. The word outputs of the OR gates are used as input signals a command buffer 750-900 via a second position of the switch 750-902 and the first position of one Output ZDI switch 750-720 for forwarding to the processor 700 supplied. The fifth position of the switch supplies the word content of registers 750-180 via a ZBP switch 750-902 to the processor 700. Finally, the sixth position of the ZDI switch 750-720 outputs the output of the command buffer 750-900 via the ZIB lines 0-39.

As can be seen from the figure, during a write cycle of operation the word content of the register 750-180 is supplied as an input to the unit 750-700.

Command buffer section 750-9

This section includes a 16-word command buffer 750-700, which is supplied with data inputs from registers 750-180 via switch 750-902. As previously mentioned, be the output signals of the buffer memory 750-700 are also written into the buffer 750-700 via the switch 750-902. Control signals and .A ^ ressignale, which via the switch 750-904 are decoded by a decoder 750-906 and used to generate a read address counter 750-908 and set a write address counter 950-910 to the appropriate state. The address outputs of the counters are via a Switches 750-912 and 750-914 are fed to the 750-900 buffer and used to set the appropriate addresses during read and write To deliver visual frictional operation cycles.

909823/0592

With reference to FIGS. 1 to 10e, the mode of operation of the present invention is now in connection with the processing of various different types of commands with the formats shown in FIGS. 8a-8b described-

However, before these commands are discussed, reference should first be made to the state diagram according to FIG. This diagram illustrates dia Fort circuit of the I cycle control state memory circuits of block 704-102 in dependence on the coding of the CCS sequence field that is applied across the lines 704- 210th According to FIG. 11, the control state FPOA is an initial state for the processing of all commands.

The FPOA status is entered when the FPOA control status flip-flop of block 704-102 according to FIG. 3 switches to the binary value "1". This flip-flop is set to the binary value "1" under hardware control according to the following Boolean equation switched:

SET = (HOLDI (DIBFRDY 'DIBFEMTY * CSTRCPR DXEDRPTS DPIPEi-4)

This means that the FPOA cycle is entered after an END cycle if there is no hold status with regard to the channel (e.g. signal HOLDI = D, the command buffer 750-900 is not empty (e.g. DIBFEMTY = I), at least one command for transmission to the processor 700 is ready (e.g. DIBFRDY = I), the "previous" command did not generate a memory comparison state (e.g. CSTRCPR = J), no processing or repeat command is present (e.g. DXEDRPTS = I) and the Channel has been triggered again (eg DPIPE1-4 = 1) The STR-CPR message is set to the binary value "1" during a buffer write operation if the address of the buffer instruction corresponds to the address of the command block.

In the control state FPOA, the RBIR register 704-152 stores the operation code of the command and the remainder of the command word with one of the formats as shown in FIGS. 8a and 8b. The RSIR register 704-154 also stores the same command word. In the case of an instruction with the format ge-Figure 8a, the RBASA register 704-156 stores the above

909823/0692

BAD ORtGlNAL

3 bits of the y field, while the RRDX-Α register 704-158 denotes the td part of the information field (TAG) of the command word. The R29 flip-flop 704-162 stores the value of the AR bit 29 of the command word.

During the control state FPOA, the hardware circuits decode of block 704-101 the CCS sequence field obtained from the CCS control store 704-200 depending on the 10-bit opcode (Bits 18-27), this code being applied via the RBIR register 704-152. The coding of the CCS follow-up field defines which route the command processing takes. The coding of the CCS subsequent field corresponds to the during the types of operations to be performed in the FPOA cycle and subsequent cycles by which each command is processed as far as possible under hardware control. Examples of the specific operations are given in the "Hardwired Control State Actions" section.

Looking at the circuit path in more detail, it can be seen from Figure 11 that the hardware circuits of block 7o4-i02 from the FPOA status to the control status FTRF-NG switch on if a control message flip-flop FTRF TST indicates that the previous command is within ' the transfer class and that the condition for the transfer or branching was not met (TRGO = I). While In response to the control status FTRF-NG, the processor hardware circuits generate signals for re-triggering the command buffer on the content of the command counter. This allows the discontinuity of the instruction stream and a change back to the current instruction stream, the address of which is indicated by instruction buffer circuitry. The tax status FTRF-NG then follows one of the cycles FPI-INIT to FWF-IBUF depending on the Coding of the I-buffer status lines.

909823/0592

In the case of normal command processing, this follows the path in the decoding of the CCS sequence field that is set by FTRF-TST + IJTRGO is specified. This path indicates that the previous one Command was not within the transfer class (FTRF-TST = I) or, if it was within this class, that the Transfer condition was met ([TRGO = I). This way thus leads to a continued processing of an instruction of the Transfer class under hardware control. It should be noted that with a previous command of the transfer class (FTRF-TST = I) and the hardware circuits when a transfer class (TRF) command is in progress of block 704-102 remain in control status FPOA (e.g. follow the path TRF to FTRF-TST).

Point X in Figure 7 takes from the coding of the CCS subsequent field whether the special command is in class EIS of class ESC or TRF- (EA © that of class EIS-ESC * CEÄ · TRF * or EIS.ESC- \ EA is located. In the case of class EIS encoding the CCS sequence field specifies required ■ 'how many descriptors for this particular EIS instruction. Each EIS instruction has the multi-word format according to 8b and can be up require to 3 descriptors. the CCS Fields for all instructions requiring one, two, and three descriptors are grouped together within the decoder circuitry. In addition, signals applied over the address lines of instruction buffer circuits of the buffer unit 750 are decoded to determine how many descriptor values Xizv. Words are currently stored in the instruction buffer. These groups of signals are compared and if there are not currently enough descriptors in the I-buffer _{to complete the instruction, the circuitry of the Blo will switch} ckes 704-102 from the FPOA status to the control status FPIM-EIS. During the FPIM-EIS control state, the processor circuitry generates signals to prepare the buffer unit 750 to perform an instruction fetch operation to fetch 4 more words from main memory or backing memory which are read into the instruction buffer.

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When the required number of descriptors are fetched once is and the buffer unit 750 signals that the instruction buffer is ready (IBUFRDY = I), then the oHardvare circuits are of block 7O4- * O2 in point C. If the command buffer is not ready (IBUF-RDY = I), the hard-vare circuits switch 704-102 to the control status FWF-DESC, in which the processor 700 waits for the descriptor. If the Command buffer is ready (IBUFRDY = I), the Hardware circuits again in point C.

It should be noted that all commands of the EIS type (CCS codes 130000-11di1D follow a path to point C. If the CCS PeId indicates that the instruction is a bit-type EIS instruction (BIT = D so hardware circuits 704-102 turn on control status (FESC) without any FPOP operation cycles are executed. If the CCS following field indicates that the command is not within the class of the bit type (e.g. BIT = D, so the hardware circuits 704-102 switch for one cycle of operation to the control status FPOP. Be it it is pointed out that the number of descriptors within the EIS multi-word instruction determines the number of FPOP cycles.

A maximum number of descriptors is under hardware control processed before the circuits 704-102 toggle to the FESC control state, causing the control transfer to occur a microprogram routine within the machining control memory 701-2 enables jsrird. For those EIS multi-word commands, the one address preparation with three descriptofliFernahmrrr "" the hardware circuits 704-102 remain in the FPOP control state for the execution of two cycles during which the processor circuit addresses for the first and second descriptors generate, frozen, switched to tax status FESC V ± rd.

E * can be seen from Figure 7 that depending on the command type defined by the control sequence field and the type of necessary address preparation, the address preparation

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for the various descriptors advances until established will) that the address preparation is no longer under Hardware control can be done. In particular, the address preparation for descriptors of the instruction classes executed, the instruction types NUM2 to MVT and are based on the fact that the descriptor Ice is an indirect descriptor (FID = I), that the descriptor does not specify an indirect length (FRL = I) and that the descriptor is not of type 6 (TYP6 = 1) or the address preparation to be completed under hardware control (FINH-ADR = I) in addition to other unusual situations under Hardware control cannot be handled (e.g. FAFI = I). When the circuitry of block 704-104 asserts the FINH-ADR set to the binary value "0", this indicates that the address preparation has been completed under microprogram control and therefore does not execute during an FPOP cycle is.

The circuits of block 704-110 set the signal FAFI to "H" when the address preparation during the FPOP cycle can be completed and there are no special conditions, such as the occurrence of an interruption in dei ~> Mitte.des command. - ~ ^ ~ "

Finally, the state RDESC = OO is caused by the states of the flip-flops of block 704-142jäejEj ^^^ i ₃ sa "% eigt the occurrence ^^^ E ^ Sli ^^ i ^ F ^^ felurläiiSBSirend which the processor circuits the Prepare the address of the first descriptor.

In the event that there are some special type conditions defined by the function f, switch the hardware circuitry of block 704-102 to the control status FESC. This enables the transfer of control to Routines stored in the ECS control store 701-2 for the Continuation of command processing under microprogram control

909823/0592

In accordance with the preferred embodiment of the present invention the circuits of block 704-102 also include flip-flops, the control states FIDESC and FWF-IDESC for provide indirect operation processing and descriptors for EIS commands under hardware control.

For a first indirect descriptor, it becomes necessary to complete the I cycle and have the processing unit 714 perform its operation. As soon as the E cycle is completed, the processor circuitry, under hardware control, fetches the indirect descriptor. In more detail, this means that the first descriptor of the EIS command is an indirect operand if the CCS field indicates that the command has an EIS command ^v and bit 31 of the RSIR register has the binary value "1" (see Fig Fig. 9c).

The hardware circuits hold during the control state FPOA of block 704-102 the completion of the I cycle (e.g. HOLD-I = D maintained for one cycle. This means that a Control flip-flop FPOAID switched to the binary value "1" within block 704-102 on the basis of a first clock pulse Is set, whereby the signal HOLDIOO is set to the binary value "0". When the next clock pulse occurs, the FPOAID flip-flop reset to "1", which means that the HOLDIOO signal can be set to "1" _ (see & behind FPOA control state in under the "Hardwired Control State Actions" section Expressions).

The hardware circuits hold the remaining EIS descriptors of block 704-102 does not maintain the completion of any further I-cycle after control status FPOA. From Figure 7 it can be seen that in the control status FPOP is entered. However, the hardware circuitry of block 704-102 switches immediately upon detection of an indirect Descriptor to the tax status FIDESC. This status is followed by a switch to the FWF-IDESC control status and a return to the tax status FPOP after complete

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processing of a first indirect operand descriptor. These cycles are repeated for each descriptor word _f is marked as an indirect operands exhibiting instruction word by the MF-field of the instruction word tsiehe Fig. 3b).

If one considers other commands compared to the commands of the EIS type, FIG. 7 shows that when the command is specified by the CCS subsequent field within the switchover class or within the transmission class and if indirect address modification is required, the hardware circuits 704-102 immediately switch from the control state FPOA to the control state FESCl. As mentioned, the controls become the appropriate ones Transfer microprogram routines stored in ECS control store 701-2. Then the processing takes place of the command under microprogram control. As indicated in Figure 7, the occurrence of certain micro-op codes causes the switching of the hardware circuits 704-102 to the control status FPOP.

In the case of the present invention, over dxfe ilardware circuits of block 704-102 the control to the ECS control memory 701-2 to complete the processing of certain types of commands that are not in a flow-through operation mode __ " (Pipeline mode) can be edited.

The aforementioned ^ BWfeh Ie = - include EIS-type commands as well as those instructions, both of which are the hardware circuitry of the block 704-102 switch to the EESC tax status when processing them. It should be noted that, in accordance with the present invention, the specific coding of the CCS sequence field enables processor 700 in enables you to determine at an early "point in time" whether a command can be processed in the flow operating mode ^. \ _

It can also be seen from Figure 7 that commands which are not of the EIS type and are not in the transmission class CTRF = D, which require indirect addressing, and

909823/0592.

those commands that are not within the switching class (ESC = D, follow a path that the hardware control circuits of block 704-102 to switch to the control status FWF-IND. For processing double and repeat commands XED or RPT switch the hardware control circuits 704-102 to the control status FESC. After that it becomes an indirect one Address preparation carried out under microprogram control.

In accordance with the preferred embodiment of the present invention indirect address modifications are carried out for commands with the format according to FIG. 8a under hardware control. These include: first register then indirect addressing (RI), indirect addressing then register (IR) and indirect addressing and then counter (IT). Other IT address modifications, which require other than indirect / teaching are carried out under microprogram control.

According to FIG. 7, the hardware control circuits of block 704-102 switch from the control status FWF-IND to the control status FPOA if an indirect register address modification is required (e.g. the tm field a modification of the RI type provided that the CCS field indicates that the command is not a double or repeat command (e.g. RIXES * RPTS = D.

The RI address modification is a 2T operation (e.g.

FPOA (RI) * ■ FWF-INT * - FPOA). During the control state

FPOA, if the tm part of the command word in RSIR register 704-158 indicates an RI address modification, the processor circuitry will disable loading the CCS field address into the ECS address register 701-10 according to Figure 3b. The processor 700 also retrieves from memory the indirect word that is represented by the effective Address is specified, which results from the modification of type R, (e.g. a memory single read instruction is in generated in the manner explained here).

The processor transmits while the FWF-INT control status is in effect

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_ 193 _

under hardware control the indirect word with the format according to

the
Figure 13d of buffer unit 750 and sets the RI flip-flop of block 704-11O to the binary value "1". The RI flip-flop remains in the binary state "1" during the next FPOA control state. This flip-flop is used to set the R29 register 704-162 to the binary value "0", since the indirect word fetched from the memory with its AR-B ± t 29 is set to the binary value "1" (see FIG 8d).

If the tm field of the command according to FIG. 7 is an IR address modification and the command is not a double or repeat command (e.g. (IR + FIR) .XED-RPTS = I), so switch the hardware control circuitry of block 7D4-1O2 of the FWF-IND control state to the FIRT control state. The IR

Modification is a 3T operation (e.g. FPOA (IR) - FWF-IND

h> FIRT * ■ FPOA). The same related to the RI

Modification mentioned operations are performed during the control state FPOA executed.

During the control state FWF-IND, the control state flip-flops FIRT and FIR set to the binary value "1". This state is followed by the control state FIRT, during which the ordinal content of the RRDXA register 704-158 saved in the RRDXAS register 704-159 to the RRDXA register 704-158 where the address modification specified by the indirect word is either R or T type. At at this point the development of an effective address is completed (last indirect addressing).

The control flip-flop FIRL is also set to the binary value "1". The flip-flop FIRL that indicates the last indirect addressing remains set to "1" for the duration of the next FPOA control state. Since the operation is not completed , the FIR flip-flop remains at the deft binary value "1" during the control state FPOA.

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During the next control position PPOA, the FIRL flip-flop sets the R29 register 704-162 and the RSIR indication bits 30-31 to the binary value "0". This becomes the I cycle of operation ended for this command. The same sequence follows in the case of a double or repeated non-processing command, which requires an IT address modification. This is a 3T

Operation C e.g. FPOA (IT) - ♦ - FWF-IND - * ► FIT-I ¥ ■ FPOA).

During the control state FWF-IND, in addition to loading

of the indirect word in the processor register (e.g. ZDI * ■

RSIR, RDI and RRDX-A, R29) the control state flip-flop FIT-I is set to "1" and the RRDXAS register 704-159 is set to "0".

During the control state FIT-I, the "0" content of the RRDXAS register becomes 704-159 loaded into RRDXA register 704-158. Furthermore, the FIRL flip-flop is set to the binary value "1". In the same As previously described, the R29 register becomes 704-162 and the RSIR notice bits 30-31 are set to the binary value "0" by the FIRL flip-flop. The Hardwired Control State Actions Section illustrates the operations described above in greater detail.

According to FIG. 7, commands of the non-EIS type follow which are not lie within the switching class and do not require the generation of an effective address (EIS »ESC» EA), one way to get to the XX point. These commands have the format according to FIG. 13a and the tm part Your note field is coded in such a way that it does not specify any indirect addressing (e.g. code 00). The tm part of an instruction is checked for indirect addressing during the FPOA cycle and if such is not specified, it is the control notice EA is set to the binary value "1".

Referring to Figure 7, the various groups of commands that follow this path are those that reference CCS control sequence fields Refer to ^ which, through their coding, define sequences, which are listed within group A, group B, group C, TRF, STR-SGL, STR-HWU and STR-DBL. Commands that Require consequences of group A, as well as those commands whose

909823/0 5 92

work has reached point B, follow the car to the point XXX. Point XXX in Figure 7 indicates the point at which processor 700 completes the I cycle of instruction processing and on which he received the next command from the I-Puffar must get for processing. Before this can happen, the processor 700 must ensure that the has just completed Command has not put it in a double or repetitive processing loop (e.g. the command must not have XED or RPT command). When the processor 700 is in a Loop operation has been placed, the hardware circuitry of block 704-102 switches to the control state FXRPT followed by the control state FESC. This ensures that the processor 700 does not fetch the next command and instead transfers control to the ECS control store 701-2, so that the next operations are carried out under microprogram control . will . In particular, during control state FXRPT, processor 700 is placed under hardwired control the ECS control store 701-2 to the appropriate address and transfers control of the during the control state FESC Hardware circuits.

If the CCS control sequence field indicates that the command is not a Double processing or repeat command 1st, and if-the Control message STR-CPR is set to the binary value "1", which indicates that the command buffer is due to a If a memory operation needs to be reloaded, the hardware circuitry of block 704-102 will enter the control state PPI ^ INIT. The STR-CPR notice is displayed during a buffer write operation set to "1" if the address of the buffer instruction corresponds to the address of the command block. During this condition, processor 700 overrides the instruction buffer the circuitry of block 704-128. Hardware circuits then switch -of block 704-102 to control state PPIM-2 to fetch the next command. In this state there follows a return to the control state FPOA, as shown in FIG. 7 '.

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If the CCS control sequence field indicates that the instruction is neither a double process nor a repeat instruction and the instruction buffer does not need to be reloaded due to a memory compare operation (CsTR-CPR = I), the hardware circuits of the block switch 704-102 to one of the three control states FPIM-1, PPOA. and FWF-IBUF. In the case where the loading. error buffer is empty (IBUF-EMPTY = I), switch to the control state FPIM-1 to enable commands to be called up and the command buffer to be filled. After the command buffer is filled, the hardware circuits switch the block 704- 102 to the control state FPOA to begin processing the next instruction. In the case where the buffer is not empty (IBUF-EMPTY = I), but is ready to read out the next command (IBUFRDY = I), the hardware circuits of block 704-102 immediately switch back to the control state FPOA.

It can be seen from FIG. 7 that if the command buffer is not in a ready state (IBUFRDY = I), the hardware circuits of block 704-102 switch to the control state FWF-IBUF and remain in this state until the command buffer is ready (IBUF-RDY = I). When this is ready, the hardware circuits of block 704-102 switch to the control state FPOA.

It should be noted that the commands which refer to CCS control fields which, by their coding, define the control sequences listed in group B, follow the path denoted by group B, in which the hardware circuits of block 704-102 leave the control state Switch FPOA to the control state FESC. In the same way, the hardware circuits of block 704-102 switch to the control state FDEL after the control state FESC if the CCS control sequence called up by the commands refers to the control sequence listed in group C by its coding. In any case, these commands require operations that cannot be processed by the processor 700 under hardware control, but rather certain micro-

909823/0592

require command routines for complete processing.

According to FIG. 7, the commands that are sent to CCS control fields refer, which by their coding STR-HWU- or. STR-SGL sequences defined, edited under hardware control, provided that these commands do not have any character address modifications (FCHAR =]) require. In such cases, the hardware circuits of block 704-102 switch to the control state FSTR around.

Those commands that refer to CCS fields that define by their coding, STR-DBL result cause the hardware Schaltkre i se the block 704-102 to switch from the control state FPOA to the control condition: FSTR-DBL and then to the control state FSTR. In the case of any of the three types of sequence mentioned, the hardware circuitry of block 704-102 follows a path back to point B for the fetch of the next instruction from the instruction buffer.

According to the preferred exemplary embodiment, the path denoted by TSXn is followed when the CCS field defines TSX commands within the class by means of its coding. Initially, the path is the same as it is followed for commands within the ESC-EA class. Thus, similar operations for generating an effective address are performed by processor 700 during control state FPOA. In addition, the command counter is updated by increasing its count by 1.

The hardware circuits of block 704-102 then switch to the FTSX1 control state. During this state, the updated content of the command counter is loaded into the RDI register 704-164. The hardware circuits of block 704-102 switch the control Note flip-flop FTSX2 in the Bi- '■ när state "1" and then switch to the control state FPI INIT. The control pointer flip-flop FTSX2 causes the processor 700 to refer to the effective address used during

909823/0592

of the control state FPOA was generated and during the control state FPI-INIT is stored in TEAO. It should be noted that normally the processor 70Q v / uring the control state FPi'-INIT uses the address value IC + O + o. the Hardware circuitry of block 704-102 then switches to control state FPIM-2, which is followed by control state FPOA.

It should be noted that Figure 7 shows only the hardware operations related to the I operation cycle. As mentioned, the processing of a given instruction is carried out under hardware control to the extent possible. Depending on the class into which an instruction falls, which is determined by the CCS control field, the predetermined operations are carried out during the FPOA control state and the subsequent control states. As explained here and as can be seen from the section "Hard-wired control status measures", the hardware circuits of block 704-102 generate the required depending on the coding of the CCS control sequence. Appropriate type of cache instruction during control state FPOA. This measure as well as the other measures occurring during the control states according to FIG. 7 are specified in the following section «

909823/0592

Fixed control state measures FPOA security state

1. If FINH-ADR = 1 then

[y (29) + X (RRDX-A) + ADR (29) 1 ^ ASEA;

C """ 1 + ZBASE £ ASFA;

If RSIR _30-31 = OO then 1> EA *;

If RSIR _30-33 5 * OO then O ^ EA; RBAS-A (29)>RSPP;

2. If FINH-ADR = 1 then

Co + O + REA-tO> ASEA;

.C "" 3 + ZBASE> ASFA;

1> EA

3. ASEA> REA; ASFA ^ RADO

[^ CACHE-REG = 1

4. If FTRF-TST = 1 then O »FTNGO

5. If FMSK-29 = 1 then MASK R29 to If FIRL = 1 then MASK RSIR 30,31 to OO

O »FIR

O-> FRI

O * FIRL

6. If (FTRF-TST ♦ TRGO) - TRF-EA · EIS = 1 and if EA · CLD-SGL + LD-HWU + RD-CLR + EFF-ADR + NO-OP) then

1 >END; and

if EA · (STR-SGL + STR-HWU + STR-DBL) = 1 then

ZREG> RRDX-A; O> R29; and

if TSXn · EA = 1 then IC + 1 \ IC

CCS >CCS-REG; CCS-O _0-1 \ RTYPq _-1 and

* The bracket sign (Z) has been suppressed in the expression EA for the sake of clarity.

909823/0592

If EA IpEL-STR-SGL + DEL-STR-DBL + TSXn -1- INST-GlO + p ^ ESCTJ = 1 where INST-GR = LD-SGL-ESC + LD-DBL-ESC + LD-HWU-ESC + EFF-ADR-ESC + ESC-EA then OO JRBAS-D

7. If FTRF-TST * TRF * EA = 1 then

a. SnIT-IBDF = 1;

b. CCS »CCS-REG;

If 'FTRF-TST. TRGO «EIS if FREQ-DIR = 1 then [HOLD χ = ι if FREQ-DIR = 1 then RBIR _27-35 --—- ^ ZIDD _27-35 - ■ -> R29

RRDX-A, FID, FRL; if BIT = 1 then 01 -— ■ -} RTYP.; if MTM-MTR = 1 then 00 if BIT. MTM-MTR = 1 then ¹ BIB

RIR ₃₀ >FAPI;

ZIB 3RSIR, RBAS-A;

if (NEED-DESC) · (IBUF-RDY) = 1 then FTRF-TST = 1 then JREAD- IBUF / ZIB (CUR) = FRTF-TST = 1 then [reAD-IBUF / ZIB (OPS) = CCS ) CCS- REG

9. If FPOA-ID-RSIR ₃₁ then HOLD-I - $

If FPOA-ID-RSIR-J ₁ [HOLD-E then 1 ^ FPOA-ID;

If FPOA-ID · | HOLD-E then 0> FPOA ID

909823/0592

10. If FTRF-TST = 1 and

If [TRGO = 1 then switch to FABUF-ACTV; if XED-RPTS = I

then 1 Λ FTRGP

If | nd = 1 then

11. If J.TRGO - 1 then block IC keying;

1 1 FTNGO

12. 0> FTRF-TST

DMEM and values generated during the control state FPOA

C MEM, (SZ for FPOA

When FTRF-TST. TRGO = 1 then [HEM = Not; If (FTRF-TST + I ¹ RGO). ESC = 1 then | meM = not; If (FTRF-TST + fJRGO). EIS = 1 then & EM = Not; If (FTRF-TST + | TRG0) · ESC »EIS" «EÄ = 1 then fiEM = single read; fs Z = SgI;

(FTRF-TST + & RG0-EA
If ESC-EA + DEL-STR-SGL + TSXn + DEL-STR-DBL + NO-OP = 1

then YWAM = Not;
If LD-SGL + LD-SGL-ESC + LD-SGL-DEL then

FCHAR · RRDX-A = DU ^ DL = 1 then flEM = single read; | Z = SgI;

FCHAR. RRDX-A = DU = 1 then | mem = direct; [SZ = HWU; FCHAR · RRDX-A = DL = 1 then ^ EM ■ Direct; fJZ = HWL; FCHAR = 1 then &! EM = Not;

909823/0592

If LD-HWU + LD-HWU-ESC + LD-HWU-DEL = 1 then RRDX-A = DU DL = 1 then YWAM = single read? ^ Z = HWU KlDX-A = DU = 1 then flEM = direct? ·. fS2 = HWU RRDX-A = DL = 1 then ΪΪΕΜ- = direct) gz = zero

If STR-SGL = 1 then

If FCHAR = 1 then YWAM = single write? SZ = SgI and if PCHAR = 1 then | MEM = Wicht

If TRF = 1 then

if FTRF-TST * FABUF-ACTV = 1 then fMEM = command sequence-1; = B and

if FTRF-TSTtFABUF-ACTV = 1 then YWAM = command sequence-1 ;

§3Z = A and
if FTRF-TST = 1 then J ¹ EM = Not

If EFF-ADR + EFF-ADR-ESC = 1 then §5EM = direct? [SZ = HWt

If LD-DBL + LD-DBL-ESC + LD-DBL-FP-ESC = 1 then | Mem - double reading

If RD-CLR = 1 then (flEM = release-reading

If STR-DBL = 1 then £ meM = double writing? f§Z = DBL

If STR-HWU = 1 then YWAM = single write? ^ Z = HWU

909823/0592

If LD / STR-SGL-ESC = 1 then [MEM = single read; (| z = SgI

If LD / STR-HWU-ESC = 1 then {mem = single read; | SZ - HWU; [k / W = 1

FSTR * control state

1. REG (RRDX-A)> ZX;

2. (ENAB-ZX-A2 = 1;

3. ZX , ZX-A2>ZDO;

4. ZRESB '■> RADO;

5. [ßND = 1.

FSTR-DBL control state

1. REG (RRDX-A)> ZX;

2. (ENAB-ZX-A2 = 1;

3. ZX, ZX-A2 τ- >ZDO;

4. ZRESB VRADO;

5. 0Oi O> RRDX-A;

6. 1 3R29.

909823/0 5

FESC control state

1. If [piBUF / PIPE = 10 + 11 or [PIPE = 001 + IOO ^ then

| end = 1.

2. If JpiBUF / PIPE = 11 or fpiPE = 10§ then 1 FWF-IND-S is expensive

ZDI * RDI

If (RI + IR + IT-I) = 1 then ZDI - * RSIR

ZDI ^ -RRDX-A, R29

If Ri · (DXED-RPTS) = 1 then 1

If (IT-I) · -JH- - = 1 then 0-> RRDXAS _Q _ ₃

If IR · -H- - = 1 then RRDX-A—— $ ZRDXAS _Q _ ₃ and

1> FIR.

FIT-I control state

1. RRDXAS ^ RRDX-A _Q _ ₃

2. 1 VFIRL

FIRT control state

1st If KSIK-J 1 «= 1 then RRDXAS ^ RRDX-A and

1> FIRL

809823/0592

FXRPT control state

1. CCS} CCS-REG

FTSXT control state

1. IC) ZX

2. ZX> ZDO

3. ZRESB> RDI

4. 1 * FTSX2

909823/0592

FDEL control state

1. (p + 0 + REA-ff -4 ASEA; and

[Ö + O + REA-χΙ + ZBASE ASFÄ.

2. ASEA> REA; ASFA - 4 RABO; and

; - # RBASE _33-35 ; and

3. [sSCACHE-REG = 1.

4. If DEL-STR-SGL = 1 then [MEM »Write SGL; JSZ = SGL.

5. If DEL-STR-DBL = 1 then YmEM = write DBL? ^ Z = DBL.

6. If DEL-STR-SGL * DEL-STR-DBL = 1 then [MEM = Not.

7. If LD-SGL-DEL + LD-DBL 4- LD-HWU-DEL = 1 then JEND.

FPI-INIT control status

1. If FTSX2 = 1 then [0 + RIC + Oj

Werih FTSX2 = 1 then [θ + 0 + REä-tJ -JASEA;

ASEA + ZBASE * iSFA.

2. O> FTSX2

3. ASEA ^ REA; ASFÄ— -4 RADO.

4. ßCÄCHE-REG = 1.

5. ASEA ^ REA-T.

6. Switching between FABUF-ACTV.

7. JmeM = command retrieval- 1.

8. JINIT-IBUF-OPS = 1.

809823/0 5

FTRF control state

Ji J4 + O + REA-τΙ ¥ ASEA and

[5 + O + REA-τ] + ABASE> ASEA.

2. ASEA>REA; ASFA ) RADO (set OO > RADO _32-33 )

3. icache-reg - 1.

4. rbas-b ^ zbas-c; 0, rea > rdi; 1 »ftrf-tst.

5.zdi ^ rbir, rsir, rbas-a, rrdx-a, r29.

6. [read-ibuf / zib (ops) = 1.

FTRF-NG control state

1 . [Ο + O + REA-iJ > ASEA; and

& + O. + REA-Τΐ + ZBASE »■ ASFA.

2. AND = 1.

FPIM-1 control state

1. g + 0 + REA-t] »ASEA and

6 (set 00 »RADO _32-33 ) + 0 + REA-T] + ZBASE> ASFA.

2. ASEA - ^ - SEA; ASFA Ϊ RADO (set.OO > ■ RADO _32-33 ) and

! CACHE-REG = 1.

3. ASEA >REA-T; and

^ EM = command request. 1 ; and RBAS-B> ZBAS-C.

909823 / 0B92

. FPIM-2 control state

. p + O + REA-T } ASEA.

2. ASEA ^ REA; and ASFA ^ RADO (set 00> RADO ₃₂ _ _33);

And (äCACHE-REG.

3. If ASFA-C2 7 = 1 then ASEA) REA-T; ASFA, ZWS »RIB-VA,

RIB-WS; and [HEM = Befenlsabruf. 2; IPTR-CUR-SEL

> [SZ; and

If ASFA-C27 = 1 then YWAM = Not; and

RBAS-B * ZBAS-C, and

ZDI ^ RBIR, RSIR, RBAS-A, RRDX-A, R29, and

[read-ibuf / zib = 1st FWF-IBUF control status

1. If IBUF-RDY = 1 then JREAD-IBUF / ZIB (CUR) and ZIB -> RBIR, RSIR, RBAS-A, RRDX-A, R29.

909823/0592

- 209-2849S0Ö

FPIM-EIS control state

1. [4 + 0 + REA-iJ> ASEA; and

. (4 + O + REA-t) + ZBASE> ASFA.

2. ASEA-> REA, and ASFA> RADO (set OO

ß & CACHE-REG = 1.

3. ASEA ^ REA-T; and

= Command request "1; and

RBAS-B- * ZBAS-C; ASFA-C27> FEIS-STR-CPR; and

ZIB * ■ RSIR, RBAS-A; and

If BIT-MTM-MTR = 1 then ZIB> RTYP ₀ ^ ₁ ; and

If IBUF-RDY = 1 then tilEAD-IBUF / ZIB, and

CCS 5 »CCS-REG.

FWF-DESC control state

1. If IBUF-RDY = 1 then JreaD-IBUF / ZIB; and

CCS> CCS-REG.

ZIB— ■ -> RSIR, RBAS-A; and

If BIT'MTM-MTR = 1 then ZIB ^

909823/0 6

FPOP control state

1. If FINH-ADR = 1 then

| y (29) EIS + X (RRDX-A, RTYP, FNUM) + ADR (29,

RTYP ₀ 3>ASEA;

(Υ (29) EIS + X (RRDX-A, RTYP, FNUM) + ADR (29, RTYPqJJ ZBASE ^ ASFA.

2. If FINH-ADR = 1 then

[O + O + REA-TJ - ^ - ASEA;

(Ö + O + REA-t] + ZBASE -9 · ASFA.

3. If FID = 1 then
HOLD-E = 1

RSIR ^ ZIDD

ZIDD > RHDX-A, R29

4. ASEA »REA7" ASFA ^> 'RADO;

ÜCACHE-REG = 1;

If FIG-LEN = 1 then ZLN > RLEN

ASEA> REA-T (RDESC);

{FID + FRL + FAFfJ - ^ FINDA; (TYPE = 6) * FINH-ADR ^ FINDC;

TYPE = 9 + FINH-ADR> * FINDB; FINDC + (SET-FINDC>DINDC;

PINDA + (SET-FINDA ϊ DINDA;

PINDB + ^ ET-FINDB * DINDB.

909823/0 S92

6. RDESC = 00 (first descriptor) If FNUM.EDIT = 1 then

RSIR

21-23 "

R1DW;

If FIG-LEN = 1 then RSIR 24-35 "

If FINH-ADR = 1 then ASFA

ASFA 34-35 "34-35"

RTF1;

RXPA, RLN1 4 RP4

RPO if

RSIR21

ASFA 34-36 RSIR21 =

RPO if

If FNUM * EDIT = 1 then

RSIR

21-23

RCN1

0-2

RSIR

24-29

R1DW;

RXPA; RTF1; ASFA

If FIG-LEN = 1 then RSIR 30-35

If RSIR ₂₁ = 1 then ASFA _34-35 If RSIR ₃₁ = 1 then ASFA _34-36

If FNUM = 1 then

RSIR

24-29 "

RTF1; ASFA ₃₄ ^ ₃₆ If FIG-LEN = 1 then RSIR 30-35

If RSIR ₂₁ = 1 then ASFA _34-35

When RSIR

21st

1 then ASFA 34-36

_34-36 -

RXPA; RSIR _21-23 >R1DW; RTYPO (0)

RPO.

909823/0592

Ai if [fID-FRL * FAFI * (TYP = 6 + FINH-ADR) I = 1 then . O> FINH-ADR, FIG-LEN

2. If MTM-MTR where DREV = MRL + TCTR + SCAN-REV = 1 then = DLEAD-IBUF / ZIB; ZIB> RSIR, RBAS-A;

> RDESC; If TRANC = 1 then IR3O> FAFI;

If TRANC = 1 then RBIR _9-17 £ ZIDD _27-35

· "'/ R29, RRDX-A, FID, FRL; If TRANC = 1 then ZIB> R29, RRDX-A;

If SCAN * CMPC'CMPCT = 1 then ZIB V RTYP;

If EDIT = 1 then 0> FNUM.

3. IffrcT + SCAN-FWD + MVT + CONVf. [zLN ,,

24-35

FIG-LEnJ-FEH then
[MEM = PRE-READ.

4. If (NUM2 + NUM3 + EDIT) (ZLN _30-35 = O + FIG-LEN) FE11 then

= PRE-READ)

5. If MLR (ZLN _34-35 = O + FIG-LEN) * FE11 = 1 then (TYP = 9). FESCD = 1 then ^ MEM = LD QUAD;

1 = ^ NIT-IBUF; and if (TYP = 9 FESCD = 1 flÄnnjMEM = PRE-READ.

6. If (CMPC + CMPCT) (ZLN _24-35 = O + FIG-LEN) * FE11 ' ■ 1then

(TYP = S) FESCD = 1 then [MEM = RDSGL; JSZ-ZONED;

(TYP = 9) I ¹ ESCD = 1 then £ mEM = PREREAD. 7. Name otherwise = 1 then | mem = not.

909823/0592

28A950Ü

B. If. [FID-FRL.FAFI * (TYP = 6 + FINH-ADR = 1 then 1. [MEM = Not

7. RDESC = 01 (Second Descriptor) If EDIT * FNuM = 1 then

_1-23 * R2DW, RTYPO-1

RTF2;

If FINH-ADR and RSIR21 = 1 then ASFA

RP1 RSIR21 = 1 then ASFA RP1

_34-35

_34-36 -

ASFA

33-35 If FNUM «EDIT = 1 then

R2DW, RTYPO-1-> RP6.

RTF2;

^ASFA

34-36

^RCN2

o-2

If FIG-LEN = 1 then RSIR _30-35 ^ RLN2.

If FNUM = 1 then RSIR

RTYPO, (0)

_24-29 >RXPB; RSIR _21-23

> R2DW; RTF2; ASFA-. - ,,. > RCN2

If FIG-LEN = 1 then RSIR -V RLN2.

_30-35 -A. If FID-FRL-FAFI * (TYP = 6 + FINH-ADR) = 1 then

1. 0 ^ FINH-ADR, FIG-LEN.

2. If (NUM3 + EDIT) = 1 then

ZIDD R29, RRDX-A,

_27-35 FID, FRL;

READ-IBUF / ZIB (CUR); IR30 ^ FAFI

ZIB > RSIR RBAS-A, RTYP.

909823/0

3. If (NUM2 + NUM3 + EDIT) (ZLN _30-35 = O + FIG-LEN) - FE2T then
{MEM β PRE-READ,
10> RDESC if NUM2 + NÜM3.

I. (ZLN _24-35 = O + FIG-LEN) * FE21.

5. If (CMPC + CMPCT) = 1 then ^ MEM = PRE-RD.

6. If otherwise = 1 then [MEM = Not.

B. If FID-FRL-FAFI (TYP = 6 + FINH-ADR) = 1 then 1. [MEM = Not.

8. RDESC = 10 (third descriptor) If FNÜM-EDIT = 1 then

R1DW if RTYP-I = OO = 1 then

if RTYP- 1j * 00 = 1 then 0> RTF3

If FIG-LEN = 1 then RSIR _34-35 J RLN1

If FINH-ADR = 1 then ASFA _34-35 >RP4;

When RSIR ₂ -. = 1 then ASFA _34-35

> RPO.

If FNÜM-EDIT = 1 then

_21-23 > R1DW if RTYPO-I = OO = 1> RTF3

if RTYPO-I = OO f .1> RTF3

If FIG-LBN = 1 then RSIR, _O , _c ^ rln1

If RSIR_j - 1 then ASFA. . _ _c ^ RPO

If RSIRo ₁ - 1 then ASFA ,. "," RPO.

9098 ^ 3/0592 ³⁴ " ³⁶

If FNUM = 1 then

RSIR

23-23 "

-> R1DW; If RTYPO = O = 11 then 1> RTF3

If RTYPO ^ O = 1 »then O $ RTF3

If FIG-LEN = 1 then RSIR

30-35 If RSIR ₂₁ = 1 then ^ASFA 34_35

4 RLN1

If RSIR ₂₁ = 1 then ASFA _34-36

RPO.

A. If (FID-FRL-FAFI (TYP = O + FINH-ADrJ = 1 then 1. IiEM = Not

B. If [sET-FESC = 1 then 1 ^ FESCD.

FIDESC control status

+ X (RRDX-A) + ADR (29) [»ASES;

C "" "J '+ ZBASE 9 ASFA;

ASEA> REA; ASFA »RADO;

^ ACHE REG = 1;

If DU + DL = 1 then [] MEM = READ-SNGL; (SZ = SINGLE); 1 = ChOLD-E; 0> FID; RBIR3O> FAFI;

If RDESC = OO then RBIR _27-35 -

RRDX-A, FRL;
If RDESC = 01 then

RRDXA, FRL;
If RDESC = 10 then RBIR ₀ _g-

RRDX-A, FRL.

ZIDD > R29 _f

ZIDD

ZIDD

R29,

R29,

909823/0 5 92

FWF-IDESC control state

. ZDI ^ RBIR, RBAS-A;

HOLD-E = 1

If RDESC = OO and

If BIT · MTM-MTR = 1 then ZDI = RTYP If RDESC = 01 and

if (SCAN + CMPC + CMPCT) = 1 then ZDI V RTYP

If RDESC = 10 then ZDI * ■ RTYP.

909823/0592

Abbreviations of the expressions used for the fixed tax status measures

1. YC29)

R29 =

R29 = RSIR,

ZY

ZY

2. Y (29) EIS = R29 = RSIR ₁

0-20

-> ■ ZY

R29 = RSIR

3,3,3,3-20 "

ZY

3. X (RRDX-A)

RSIR ₃₀ = ENAB-ZX in function of RRDX-A RSIR ₃₀ = DISABLE ZX

4. ADR (29)

R ₂₉ = 0

R29 = Z

currently

_o _ _2o

-> ZZ

5. RBAS-A (29) RSPP

= 0010 ) ■ RSPP _0-3

.R29 = 1, RBAS-A _0-2 ^

READ-IBUF / = [read-ibuf / zib - ■ ZIB (CUR) FABUF-ACTV - O FABUF-ACTV = 1 -> DRDB - DRDB

909823/0592

7. (rEAD-IBUF /

ZIB (OPS) = [READ-IBUF / ZIB

FABUF-ACTV = i > DRDB

FABUF-ACTV = O> DRDB

8. [END = if XED RPT RPL RPD XEC then

ZIB > RBIR, RSIR, RBAS-A, RRDX-A, R29;

If FTRF-TST »{trGO = 1 and

if <t IBUF-EMPTY · IBUF-RDY) = 1 then [rEAD-IBUF / ZIB (OPS);

If FIRF-TST = 1 and

if EIS -fc FTRFNG = 1 then IC +

> IC;

If EIS FTRFNG = 1 then IC + IC;

If (IBUF-EMPTY .IBUF-RDY) = 1 then JrEAD-IBUF / ZIB (CUR);

If FTRF-TST s 1 then 0>

FINH ADR.

9. RI » RSTR 30 · 31.

10. IR - RSIR 3O ^ 31.

- (RSIR 3O.3T) (RRDX-AO.T.7.3).

909823/0 5 92

12. X (RRDX-A, RTYP, FNUM = ENABLE ZX in function of RRDX-A,

RTYP, FNUM.

13. ADR (29, RTYP ₀ )

R29 R29 - ο

Currently

_0-20

_-19

_-19 ;

RTYP ₀ = ZAR20 + 21.22 +

21.23> ZZ20

RTYP ₀ = O> ZZ20.

14. ASEA

REA-T

(RDESC)

= ASEA } REA-T

RDESC = OO = 000-

- ^ ZBAS-C

.RDESC »ΟΙ = 001 > ZBAS-C

RDESC = 10 = (01, FABUF-ACTV) -ZBAS-C.

15. (^ RTYP-B

When BIT = 11

RTYP-B

_0-1

If BIT = RTYP _Q , RTYP ₁

FNÜM

RTYP-B

0-1 *

16. ¹ OCACHE REG

■ «Buffer control register key

17. CCS ^ CCS-REG = ZREG (CCS-R ^ RREG-

RRDX-B

at the next clock pulse; CCS-02- PNUM.

909823 / 0B92

849500

18. TYP9 = RTYP ₀ - γ + RTYPO.FNUM.

19. ΤΥΡ6 = RTYPg ₁ . FNÜM.

Β09823 / 0Β92

While it is desirable to have processor 700 process instructions in a flow-through fashion, there are various types of commands that cannot be processed in the flowing fashion. These include commands within of the ESC class, commands that process data in byte or number form and commands within other classes, such as the classes ESC-EA, LD-SGL-ESC etc.

If the processor 700 determines by means of the CCS code that the instruction cannot be completely processed in a continuous operating mode, the I-cycle circuits of block 704-102 switch to the control state ESC. It can be seen from FIG. 7 that the point of the I cycle processing at which this switchover occurs varies as a function of the instruction type or the CCS sequence. At this point, processor 700 transfers control to the microprogram sequence to complete instruction processing.

After the sequence has been completely processed, the processor 700 triggers a new start of its flow mode of operation. According to a preferred exemplary embodiment of the present invention, the restart of the flow operation from the control state ESC is specified by various code combinations in the PIPE microinstruction field.

The types of restart are coded as follows: PIPE CODE DESIGNATION OPERATION

0001 Type 1 This is a restart and

Release operation in which the processor 700 returns to the control state FPOA in order to begin processing the next program instruction. This means,

• 909823/0592

that this code loads the register RBIR with a new instruction, the advancement of the I-buffer address hint and the execution of an END cycle of operation evokes. These operations are as follows:

ZIBO-35> RBIRO-35;

ZIBO-35> RSIRO-35;

ZIB29 = ► R29;

ZIB32-35 > RRDXA; and

ZIBO-2 »RBASA.

Type 2 This is a restart and

Release operation in which processor 700 returns to control state FPOA for processing of the current command. This means that this code will restart without a load the registers RBIR, RSIR etc. with a new instruction.

Type 3 This is a restart operation,

in which the processor 700 returns to the control state PI-INIT. At this point, processor 700 fetches two blocks of four of instructions that are loaded into the I-buffer and a first command will be transferred to the register RBIR, RSIR etc. causes. The command input and output address notes are triggered to refer to the start of new command blocks. Before restarting 909823/0592

the registers RIC, IBASE, etc. become under microprograinm control loaded and command processing begins under hardware control with the control state FPOA.

0100

Type 4 This is a restart and wait operation in which the flow through operation is started under microprogram control before processing the current command is completed. This means that this code causes the processor 700 to execute an END cycle Load the registers RBIR, RSIR etc. with the next instruction and execute the control on the state FPOA attributed. Processor 700 waits for a Type 5 enable under microprogram control is generated before the following buffer cycle is completed.

0101

Type 5 This is a release operation in which the waiting processor 700, restarted by a type 4 code, with the flow through operation after release of type 5 begins.

0110

Type 6 This is a restart operation that occurs while processing EIS commands is used, with the processor 700 in the control state FPOP is returned.

90982 3/0 5 92

0111 Type 7 No

Operation performed.

The foregoing restart operations will now be described in greater detail with reference to FIG. 11 and FIG Figures 10a to 10e considered in more detail. The type 1 restart is shown in FIG. 10a. Assume that the instruction being processed specifies a byte storage operation of the Q register (STBQ). This command has the format according to Fig. 8a. Bytes of the Q register are in the corresponding byte positions of the specified by the Y address field Transferring storage space. The binary values "1" in the information field of the command define the byte positions of Q and Y that are affected by the command.

During the control state FPOA, the opcode value (552) of the instruction takes a memory location within the CCS memory 704-2 reference containing a CCS word encoded according to FIG. The applied via busbar 704-204 The CCS address is loaded into the ECS address register 701-10 as shown in FIG. 3b. Likewise, offsets the CCSR field of the CCS word enables switch 704-53 to load the Q register setting code for selection into RREG register 704-55.

At the beginning of the next cycle, the cardware circuits of block 704-102 switch from the control state FPOA to the control state FESC according to FIGS. 11 and 10a, since the CCSS field specifies through its coding that the command STBQ is within the ESC class. No buffer instruction is generated during this state. The contents of the register RREG 704-55 but loaded into the RRDXB registers 704-189.

During the third cycle, the processor 700 performs an operation specified by the instruction under the control of the Microinstruction routine is defined, the start address of which is defined by the CCSA field of the CCS control word. This means,

909823/0592

that during the third cycle, which is a first E cycle corresponds to the address preparation unit 704-3 under microprogram control sums the values Y (29) + X (RRDXA) + AR (29) and generates a resulting effective address, which is loaded into the RADO register 704-46 via the lines ASFA. Under microprogram control (e.g. DMEM field) processor 700 also generates a zoned single write command via switch 704-40. This instruction, which includes the address in the RADO register 704-46 is transferred to the buffer unit 750 over the RADO / ZADO lines.

During the next cycle (second Ε cycle), the content of the selected by the content of the RRDXB register 704-189 is used Q register loaded into RADO register 704-46. It is also 10a shows that the buffer unit 750 executes a single buffer write cycle due to the buffer instruction executes in which the buffer unit 750 transfers the instruction transmits lines DTS to main memory 800. When the word memory location specified by the buffer instruction address is in the buffer memory 750-700, the selected bytes of the contents of the Q register written into the buffer memory 750-700. During the next cycle, the buffer unit 750 transfers the contents of the Q register via the lines DTS to the main memory 800.

According to FIGS. 11 and 10a, the microinstruction word controlling the operations of the processor 700 comprises a DPIPE field which defines a type 1 restart by means of its code. As can be seen from FIG. 7, the processor hardware circuits of block 704-102 switch to one of four control states FXRPT, FPI-INIT, PPIM-1 or FPOA (eg position B) depending on the conditions shown.

In more detail, the circuitry of block 704-102 switches to the FXRPT control state if the instruction is either an XED or an RPT instruction type. If the command doesn't

909823/0592

is of the type XED or RPT and is not a memory comparison state was present, the circuits of block 704-102 switch to the control state FPI-INIT. The circuitry of the block 704-102, however, switch to control state FPIM-1 if neither a command of the type XED or RPT is present, there is no memory comparison status, and the I buffer is empty. if the above states are the same, but the I-buffer is not empty but is in a ready state is located, the circuitry of block 704-102 switches to the control state FPOA.

From the above it can be seen that the PIPE field, which defines a restart of type 1 with its coding, the processor 700 is able at the beginning of the to start the next command processing with a continuous processing, regardless of the command type, its processing had to be completed under microprogram control.

It should be noted that in the case of the STBQ command it It was not necessary to check the information field (TAG) of the command before the control could use routines within the ECS control memory 701-2 was transferred. However, there are a number of instructions that the processor 700 will use the hint fields checks. These instructions pertain to basic operation instructions such as those relating to load and store operations determine.

Figure 10b shows the manner in which an A load instruction (LDA) is processed. This command, which has the format according to FIG. 8a, is to have a note field which is preceded by its coding defines an address modification "indirect then counter" (IT) which is different from an indirect one Addressing required. According to FIG. 10b, the address preparation unit generates 704-3 of the processor is an effective address that serves as an instruction address. This address is in the FADO register 704-46 loaded. Since the CCS field is an LD-SGLr Sequence is established by the circuitry of block 704-108

a single read instruction that is sent to the Buffer unit 750 is output. The instruction bits 1-4 and the zone bits 5-8 are defined in the aforementioned manner by the Circuits 704-118 and switch 704-40 are generated. Zone bits 5-8 are set to the binary value "1" as they are used for Reading instructions are not used.

The processor circuitry within block 704-110 decodes the contents of bit positions 30-31 of the RSIR register 704-154, while the circuitry of block 704-102 decodes the CCS sequence field. Since the information field indicates an IT address modification that requires other than indirect addressing, and the CCS field indicates that the command is not within the class EA, ESC or EIS, the circuits of block 704-102 switch to the control state FWF-IND at. In this state, processor 700 sets ECS control store 701-2 to memory location 12.

According to FIG. 10b, the buffer unit 750 processes on the basis of the Single read instruction during the second cycle one buffer cycle of operation. Assuming that this was requested Word is in the buffer memory 750-700, the buffer unit 750 reads out the word and applies it to the lines ZDI. During the simultaneous I cycle, processor 700 loads the Word in RSIR register 704-154. Next, the circuitry of block 704-102 toggle to the FESC control state. At this point in time, control is transferred to the IT routine, which begins at memory location 12.

During a number of Ε cycles, the IT routine generates an effective address as a function of the specified IT address modification. The resulting address is loaded into the TEAO register in row 704-302. Before completing the processing of the IT routine, the processor 700 reads out the last microinstruction word of the routine, which has a PIPE field which, through its coding, defines a restart of the type. According to FIG. 10b, the processor circuits generate the

9Ö9823 / 05Ö2

Block 704-114 when decoding the PIPE code signals, which puts the circuits of block 704-102 in the control state Toggle FPOA. ■

At this point (fifth cycle) the processor 700 begins processing the LDA command using the effective address as generated by the IT routine. According to FIG. 10b, FPOA the effective address content of register TEAO is loaded into RADO register 704-46. Likewise during the control state FPOA loads the address of the CCS word into the ECS address register 701-110 according to FIG. 3b. Generated in the manner previously described the processor 700 under hardware control a buffer single read instruction using the generated effective address. Likewise, the CCSR field of the CCS word offsets switch 704-53 able to load the code into the RREG register 704-55 which defines the Α register for the selection.

During the next cycle (sixth cycle), the buffer unit 750 processes one based on the single read instruction Buffer cycle of operation. Assuming the requested word is in buffer 750-700, reads the buffer unit 750 extracts the word and applies it to the lines ZDI. The content is also controlled under hardware control of RREG register 704-55 is loaded into RRDXB register 704-189.

During the Ε cycle (seventh cycle), the processor 700, under control of the microinstruction word specified by the CCS address, completes the processing of the instruction by transferring the word from the buffer unit 750 to the A register, which is defined by the contents of the RRDXB register 704-189 has been selected.

From the foregoing, it can be seen that processor 700 is able to continue processing the same instruction after performing certain address generation operations which are more rapidly performed under microprogram control. This is done on the basis of the PIPE field, which is defined by its

909823/0592

Coding a restart of type 2 within a routine specifies. .

Certain types of commands require transfers of control when switching between different modes of operation must be executed under microprogram control. One such command is the transmit and slave mode set command TSS, which has the format according to FIG. 8a. According to FIG. 10c, the restart of type 3 facilitates the processing of this Type of operation by processor 700 when in flow mode is operated.

As can be seen from Fig. 11, a CCS word is read from the control memory 704-2 by the operation code (715) of this instruction, which is encoded in the manner indicated. During the first cycle that the processor 700 is in the control state FPOA is located, the address preparation unit 704-3 generates an effective address which is stored in the temporary register TEAO will. Since the CCS field defines an ESC-EA sequence, switch changes the circuitry of block 704-102 to the FESC control state. At the end of the second cycle, processor 700 transmits the Control on the routine at memory location 2066 of the ECS control memory 701-2, which was previously used during the control state FPOA set the address loaded into the ECS address register 701-10 is.

Referring to Figure 10c, under microprogram control, processor 700 loads the instruction counter with the address of a new instruction block and sets a major / minor mode indicator to the minor mode. During the last cycle (fourth cycle) of the routine is read out a microinstruction word from the ECS control store 701-2, which specifies with his PIPE-field a restart type. 3 The decoding circuits of block 704-114 in turn generate signals which switch the I-cycle control circuits of block 704-102 to the control state FPI-INIT.

As can be seen from FIG. 10c, the processor 700 transfers the IC address to the RADO register and the temporary storage register TEA in the fifth cycle under hardware control and generates a buffer instruction IFETCH1 which contains the address to the buffer unit 750. The processor 700 also sets the INITIBUF line to the binary value "1", which clears the other part of the I-buffer. The circuits of block 704- 102 may be able to switch to the control state FPIM-2.

During the next cycle (sixth cycle), the address preparation unit 704-3 increments the IC address by 4 and loads these into the RADO register 704-46 and into the temporary storage register TEA. The processor 700 also generates a buffer instruction IFETCH2 to the buffer unit 750.

Assuming that the instruction blocks are located in the buffer 750-700, the instructions causes the buffer unit 750 during cycles 6 and 7 due to IFETCH1 and IFETCH2 first and second instruction blocks from the buffer 750-700, and loads it into the I -Buffer. It should be noted that at the end of cycle 6, the I cycle circuitry of block 704-102 switches to the FPOA control state to begin processing the next instruction while generating the IFETCH2 buffer instruction.

The above example shows how the processor 700 is enabled, under microprogram control, to perform operations required to switch control to a different mode of operation, and how it is then brought into a predetermined control state to allow its continuous mode of operation in one place at which the requested command blocks are automatically retrieved so that the processing of a new command block can be started.

909823/0 5

Fig. 10d illustrates the restart of type 4 and 5. It is assumed that the processor 700 is processing a Floating point addition instruction (FAD) after a series of A-load ~ command (LDA) begins, the load commands all having the format according to FIG. 8a. When processing such commands the processor 700 must perform a series of E-operation cycles, to fully edit the command. However, it is advantageous to start processing other commands in one go Way to start such editing at the same time. The arrangement according to the present invention permits such processing.

As shown in Fig. 11, the processor generates address preparation unit 704-3 during the control state FPOA (first cycle) an effective address. The opcode of the FAD instruction causes processor 700 to refer to a memory location within control store 704-2, which has the illustrated format and corresponding values. Since the CCSS field by coding this command as being in the LD-SGL-ESC class, the I-cycle circuits of the block switch 704-102 to the control state FESC at the end of the first cycle.

The processor circuitry additionally generates, in accordance with the CCS code, a buffer single read instruction which contains the instructions in the RADO register 704-46 has the effective address loaded. In response to the buffer instruction, the buffer unit 750 performs one Buffer operation cycle (second cycle) to fetch the requested data word. Assuming that the data word is in the buffer memory 750-700, the buffer unit 750 transfers the data word on the lines RDI during this Cycle.

At the beginning of the third cycle, processor 700 is in control of processing the floating point add operation by the microprogram routine to begin, this routine having the start address memory location that was determined by the previously

909823/0692

CCS word used is specified (e.g. storage location 272). When the processing of the addition operation has progressed to a particular point, which can be seen from Fig. 10d is, the processor 700 reads out a microinstruction word that has a PIPE code that a restart of type 4 specifies.

When decoding the PIPE code, the decoding circuitry generates 704-114 Signals that the hardware circuits of the block 704-102 at the end of the fourth cycle in the control state FPOA unl - switch. This allows the processor 700 to begin processing the next two instructions (LDA) in one flow Way to start. This means that the processor 700 is under hardware control of the indicated I cycle and buffer operations executes during cycles 5 and 6.

As can be seen from Figure 10d, processor 700 holds the I and C operation cycles while processing the add operation under microprogram control until the release of type 5 is generated. During a final Ε cycle of the addition operation the processor 700 reads a microinstruction word which is a PIPE field which, through its coding, defines a type 5 release. The decoder circuits 704-114 generate Reason for this code Signals that allow the circuits of block 704-102 to be released from their existing control state, whereupon command processing can continue in a sequential fashion. As can be seen from Fig. 1Od, the circuits of block 704-102 remain in the control state FPOA in order to proceed with the processing of a third LDA command (ninth cycle) to begin. Simultaneously with this, the buffer unit 750 executes a buffer operation cycle, and the Processor 700, under microprogram control, executes an I operation cycle through which the processing of the first LDA instruction is completed.

As previously mentioned, through the combined use of type 4 and 5 restart, processor 700 is able to process I- and C cycles of operation concurrent with the completion of the

90982 3/0592

Execute Ε cycles of another command.

Fig. 10e illustrates the use of a restart from Type 6 in connection with an EDIT command (MVE). This command has the format according to FIG. 8b. It is assumed that the instruction specifies by its coding that the first descriptor or operand is of an indirect length (e.g., the RL bit of Figure 9c has the binary value "1"). During the control state FPOA are the circuits of block 704-110 through the MFI field stored in the RBIR register 704-152 in the Positioned to switch the control information flip-flop FRL to the binary value "1". The processor 700 also generates a single read instruction to buffer unit 750 to fetch the next word of the instruction (descriptor 1).

During a next cycle, the circuitry of block 704-110 will have switched to the FPOP control state. Also edited the buffer unit 750 performs a buffer cycle based on the single buffer read instruction. Since the signal FRL has the binary value "1", the circuits of block 704-102 switch to the Control status FESC and set the indicator flip-flop FINDA (see Fig. 7).

During the third cycle, processor 700 begins processing the MVE instruction under the control of the routine determined by the CCS address of the CCS word , which word is referenced by MVE opcode (020,1) will. As can be seen from FIG. 11, during the processing of the MVE routine, the processor 700 executes a branch operation which is based on the test of the state of the flip-flop FINDA. Since the flip-flop is set to the binary value "1", the ECS control store 701-2 branches to an indirect length routine. Processor 700 generates the required address for retrieving the indirect length descriptor while processing this routine.

909823/0592

Referring to Fig. 10e, a final microinstruction word in the routine which is extracted from ECS control store 701-2 (cycle 5) is read out a PIPE field, which by its coding specifies a restart of type 6. Because of this, the decoding circuits 704-146 generate signals representing the Enable circuitry of block 704-102 to switch to the FPOP control state (cycle 6), such as this is shown in Fig. 10e. This allows the processor 700 to continue processing the remaining operand descriptors continue under hardware control. Be it. pointed out that there is a similar sequence of operations for each operand descriptor with an indirect length is to be carried out. In either case, the circuitry of block 704-102 will be disabled due to a restart of type 6 in toggles the control state FPOP, causing the processor 700 the continuation of the processing of the MVE command in a flowing way is permitted.

In the way mentioned, the CCSO field provides an additional one Information that the processor 700 uses during its processing of the various types of instructions within the processor repertoire can interpret. Fig. 9a schematically illustrates the manner in which the CCSO field is used during the processing of multi-word instructions can be used by the processor, these multi-word instructions having different types of operand descriptor data treat.

Assume that processor 700 initially has a numeric Move command (MVN) processed, followed by an alphanumeric move command from left to right (MLR) « Both commands have the general format shown in Figure 8b. The main difference in terms of the facts at hand is that the operand descriptor format of the MVN instruction has a 6-bit N field (30-36) during the MLR instruction has a 12-bit N-field (24-35) according to FIG. 8b.

909 ^ 23/0592

Both commands are two descriptor commands and are therefore not contained in an MF3 field and a third descriptor word.

Referring to Figure 8a, the opcode value 300 causes the MVN instruction processor 700 for reference to a CCS word of control store 704-2, which has the format of Figure 8a.

During the control state FPOA (first cycle), the value is in accordance with bit 3 of the CCSO field Match the coding of the CCSS field contained in the FNUM flip-flop of block 704-104 in FIG Way is saved. Since the MVN instruction relies on operand data characters acts of the numeric type, becomes the FNUM flip-flop switched to the binary value "1" by the CCSO field.

During the control state FPOP (second cycle) the dials State of the FNUM flip-flop between the third and sixth Positions of the ZLN switch 722-82 off. The third position provides a 12-bit length value as an output signal through the RSIR bits 24-35 (for alphanumeric type data characters), while the sixth position of switch 722-82 is an output signal with a 6-bit length value through RSIR bits 30-35 (for numeric type data characters).

In the case of the MVN instruction, the FNUM flip-flop causes a 6-bit length value corresponding to RSIR bits 30-35 (ie field N1 in FIG. 8b) to be loaded into the RLN1 register of block 722-80. The 6-bit length value N1 indicates the number of characters within the descriptor data field of the first descriptor. In the case of numeric commands, therefore, no more than 63 characters can be specified.

During the next FPOP cycle (third cycle) the dials Processor 700 under hardware control another 6-bit length value corresponding to RSIR bits 30-35 (e.g. the field N2 in Fig. 8b) for loading into the RLN2 register of the block

909823/0592

722-80. The 6-bit length value N2 shows the number of Characters within the descriptor data field of the second descriptor.

Referring to Figure 9a, the buffer unit 750 executes buffer operation cycles to retrieve the descriptor data, with this data are specified by the Y1 address field of the MVN command. Processor 700 operates during the E operation cycles under control by the microprogram routine / whose start address is specified by the CCSA field of the CCS word. It processes the operation specified by the operation code, adding the retrieved data of descriptor 1 to the Moves storage space determined by the Y2 field of the second descriptor. While the move operation is being processed the length values N1 and N2 are each reduced by the processor by the number of those already processed Bear in mind sign. This operation continues until the received length value N1 has been processed (e.g. to Zero is decreased).

After the MVN command has been completely processed, the processor 700 begins processing the MLR command. According to Fig. 9a is referenced by the opcode value 100 of this instruction to the other CCS word / the one shown Format. During the FPOA cycle, the value corresponding to bit 3 of the CCSO field is in agreement with the Coding of the CCSS field in the FNüM flip-flop of the block 704-104. Since the MLR command is operand data characters processed of the alphanumeric type, the FNüM flip-flop is switched to the binary value "0" by the CCSO field.

During the control state FPOP (second cycle), the state of the FNÜM flip-flop selects the sixth position of the ZLN switch 722-82. This results in a 12-bit length value corresponding to RSIR bits 24-35 (i.e. the Ni field in Fig. 8b) loaded into the RLN1 register of block 722-80. Again, the 12-bit length value N1 shows the number of characters within the

909823/0592

28A9500

Descriptor data field of the first descriptor. In the event of A considerably larger number of characters can thus be specified by alphanumeric commands.

During the next FPOP cycle (third cycle) the dials Processor 700 under hardware control has a different 12-bit length value corresponding to RSIR bits 24-35 (i.e. field N2 in Figure 8b) for loading into the RLN2 register of the block 722-80. The 12-bit length value N2 shows the number of characters in the descriptor data field of the second descriptor at.

Referring to Figure 9a, the buffer unit executes 750 buffer operation cycles to retrieve the descriptor data generated by the Y1 address field of the MLR command are specified. During the E cycle of operation becomes the processor 700 under control operated by the microprogram routine, the start address of which is determined by the CCSA field of the CCS word. He edited the operation specified by the operation code, transferring the fetched data of descriptor 1 to the memory location moved, which is determined by the field Y2 of the second descriptor.

Again, when the shift operation of the processor is performed, the N1 and N2 length values are each decreased by to take into account the number of characters already processed. This operation will normally continue until the received Value of the character string N1 has been processed.

From the above it can be seen how the arrangement according to the invention allows the effective processing of commands, these having different types of descriptor data. By using the CCSO field, the processor 700 do not process additional microinstructions to decode an instruction's opcode and type of descriptor data to interpret.

909823/0532

As previously mentioned, the coding of the CCSO field can also can be used to distinguish between the opcodes of different instructions, these for example Specify floating point and transfer operations. Fig. 9b shows various examples for illustration, how the CCSO field facilitates the execution of such commands. The CCSO field is coded as follows for these command types:

CCSO2 for binary floating point commands:

0 = the command does not require any

Result normalization.

1 = the command requires a

Result normalization.

CCS01 for binary floating point addition /

Subtraction / comparison commands:

0 = the command is not a floating point

Size-type addition / subtraction / comparison instruction.

1 = the command is a floating point

Size-type addition / subtraction / comparison instruction.

CCS01 for binary floating point memory load

commands:

0 = the command is not a floating point

Load / save command.

1 the command is a floating point loader / «. Save command.

CCSOO selects the condition (true value or

complementary value) at which the branch for the transfer of the Commands takes place.

909823/0 S92

- 239 - 28A9500

It is assumed, for example, that the processor 700 with the processing of the four groups of commands shown begins. If you look at the first group of commands, then begins the processor 700 with the processing of a floating point addition instruction (FAD) to which a non-normalized floating point addition instruction (UFA) follows. The operation code (475) of the FAD command calls for a CCS word to be read out of the Control store 704-2 having the illustrated format.

The 3-bit CCSO field is used during the control state FPOA in the ROP register 704-146 is loaded. These bits are used as input signals fed to the test circuitry associated with the ECS control store 701-2. According to Fig. 9b transmits the processor 700, after the CCSS sequence LD-SGL-ESC has been completely processed, the control to the microinstruction routine at the storage location 272 of the control store 701-2, which is addressed by the CCSA field of the related CCS word. As previously discussed, the transfer of control occurs when the circuitry of block 704-102 is in the FESC control state toggle (see Fig. 7).

The processor 700 begins executing the FAD instruction under the control of the microinstruction routine. Referring to FIG. 9a, the processor reads 700 during the execution of the routine, a microinstruction word which includes a field that the test of bit 0, as stored in the ROP register 704- 146 (eg Ccs02) defines by its encoding . On the basis of the microinstruction, the processor 700 branches either to a normalized floating point addition microinstruction sequence or to a non-normalized floating point addition microinstruction sequence, which depends on the state of bit 0.

Since bit 2 is a binary "0", processor 700 begins processing a non-normalized floating point addition microinstruction sequence. According to FIG. 9b, the processor 700 is currently processing a UFA command in the same

909823/0692

described way. However, the opcode records reference a different CCS word, which results in the CCS2 bits loaded into ROP register 704-146 denoting the Have code "001". As a result of this, the processor 700 branches when testing the state of the bit ROP2 or it locks on converts the normalized floating point addition microinstruction sequence.

In the case of the next group of instructions, the processor begins 700 with the processing of a floating point comparison command (FCMP) to which a floating point size comparison command (FCMG) follows. The operation code of the FCMP command calls for a CCS word to be read from the control store 704-2 with the one shown Format. During the control state FPOA, the 3-bit CCSO code is loaded into the ROP register 704-146. at When the CCSS sequence LD-SGL-ESC has been processed completely, the processor 700 transfers control to the microinstruction routine at the memory location 462 of the control memory 701-2, whereby the address is given by the CCSA field of the related CCS word. The processor 700 then begins with the processing of the FCMP command under microprogram control.

According to FIG. 9a, the processor 700 reads out a microinstruction word during the processing of this routine, which by its coding specifies the test of bit 1 of the ROP controller 704-146 (e.g. CCS01). The processor branches on the basis of the microinstruction either to a comparison microinstruction sequence (the comparison includes the signs) or to a size comparison microinstruction sequence (the comparison includes absolute values). Since bit 1 has the binary value "0", the processor 700 begins with the processing of the comparison microinstruction sequence »

According to FIG. 9b, the processing of the FCMG command is carried out in a executed in a similar manner. However, a different CCSO code is put into the ROP register 704-146 during the control state FPOA loaded, which is indicated by the opcode of the

909823/0592

Command FCMG is due to the selected CCS word. Accordingly the processor 700 branches when testing the state of the ROP1 bit for the size comparison microinstruction sequence.

From the above two examples it can be seen / as enabled by processor 700 during instruction processing by testing the values contained in the CCSO field will distinguish between a pair of commands at a given point so that it is able to share a common Use sequence of microinstructions for both types of instructions. The next two examples provide similar ones Advantages in the case of other types of commands.

The third group of instructions comprises a floating point memory instruction (FST) to which a floating point round down memory command (FSTR) follows. The processor 700 refers to the CCS word according to FIG. 9b on the basis of the operation code of the FST instruction. During the control state FPOA, the 3-bit CCSO code is in the ROP register 704-146 is loaded. According to FIG. 7, the switches Processor 700 to the control state FESC, whereupon it the Transfers control to the microinstruction routine which is located in the indicated memory location of the control memory 701-2, this memory location being referred to by the CCSA field of the CCS word.

The processor 700 takes during the execution of the FST instruction with respect to a microinstruction word that contains a field which defines by its encoding the test bit 1 of the ROP register 704- 146th Since this is a binary "1", processor 700 processes those microinstructions necessary to complete a floating point store operation.

In the case of an FSTR command, bit 1 of the ROP register is 704-146 set to the binary value "0". The processor 700 operates hence those microinstructions required to complete the floating point memory rounding operation,

909823/0592

whereby the result is rounded down to 28 bits of normalized precision and is saved.

The last group of commands make up a transmission Zero command (TZE) to which a transfer is not based on zero command (TZN) follows. The processor 700 reads the CCS word from the control memory based on the operation code of the TZE instruction 704-2, which has the format shown. During the control state FPOA, the CCSO code is written to the ROP registers 704-146 loaded. Referring to Figure 7, processor 700, under hardware control, requests two 4-word blocks of instructions to prepare for a control transfer. The processor 700 then transfers control to the microinstruction word in the control store 701-2, which is provided by the CCSA field of the CCS word is set.

The processor 700 reads out the microinstruction word by which the test of the zero indicator of the indicator register 701-41 is specified will. In accordance with the teaching of the present invention, this indicator then becomes dependent on bit 0 of the ROP register tested, whereby it is determined whether the transmission or branching with the true or complementary Status of this indicator has to take place. Since there is a TZE command, bit 0 has the binary value "1", which means that a Control transfer occurred due to the test of the true state of a zero indicator bit position. From Fig. 3b it can be seen that only the AND gate 701-25 is partially enabled due to the input signal ROPO. It will be through the true State of the indicator bit fully enabled, which is supplied from the output of block 701-24. So if that If the zero indicator bit has the binary value "1", the signal DTRGO switches to the binary value "1", whereby the transmission flip-flop FTRGO is set to the binary value "1". This causes a transmission and the circuits of the Blocks 704-102 return to the control state FPOA according to FIG. 7 return.

909823/0592

It can be seen that processor 700 performs a similar sequence of operations in processing a TNZ instruction executes. However, a code of "000" is loaded into ROP register 704-196 during control state FPOA. When the ROPO bit is tested, the processor 700 therefore causes a control transfer that is based on the test of the complementary State of the zero indicator bit. This means that only the AND gate 701-26 by the complementary input signal ROPO is partially released. If the complement of the zero indicator bit is a binary "1" then so the signal DTGO switches the transmission flip-flop FTRGO to the binary value "1". Such a transfer of control involves replacing the contents of the command counter with the Contents of the memory location, which is determined by the Y address, which progresses during the control state FPOA.

From the last two examples it can be seen how the requirement is met by the arrangement according to the present invention further decoding of the opcode of an instruction is eliminated. This leads to a saving in terms of of time, of microinstructions and circuits.

Fig. 9c illustrates the manner in which the CCSO field is used to specify additional information, such as a character type, which is appropriate for the correct Processing of commands is required, with these commands having the option of replacement, addition to or subtraction of the contents of an address register on a word-to-character or bit-address basis. Assume that the processor 700 handling a 9-bit character add shift to a specified address register instruction (A9BD), followed by a 4-bit character add shift for the specified address register command (A4BD). These commands have a format similar to that in

909823/0592

8a with various differences. The main difference is that bits 0-2 of the command word (AR =) are used to determine the address register, the content of which is to be changed, while bits 32-35 (DR) determine which Register contains a shift value. Bits 3-17 of the Y field are used as a word shift in the same way used as they were used during effective address preparation.

From Fig. 9c it can be seen that due to the operation code of the A9BD instruction, the processor 700 the CCS word from the Reads out control memory 704-2 with the format shown. During the control state FPOA, in accordance with the coding of the CCSS field, the upper two bits of the CCSO field (e.g. CCSOO-1) is loaded into the RTYP register 704-160 .

Referring to Fig. 7, the processor circuits of the block switch 704-102 to the control state FESC, whereupon the control is transmitted to the microinstruction sequence which is determined by the CCSA field of the related CCS word. Since the Operation is a register-to-register operation, no additional buffer cycles are required.

The address preparation unit is under microprogram control 704-3 enables the addition of a 9-bit character shift value to the contents of the specified address register to execute. In accordance with the arrangement of the preferred embodiment, the ZX switch 704-58 in Fig. 3f is used to select the address modification field or index value used during the address preparation cycle.

The ZX switch 704-58 is controlled in the aforementioned manner by the ZX field of the microinstruction word. if the ZX field contains a code of 001, the ZX output is selected depending on the character or operand data type.

909823/0592

The output ZXOB4-23 is selected for a 9-bit character and the output ZXOBO-23 is selected for a 6-bit character. The output ZXOB3-23 is selected for 4-bit characters. In the case of a word type modification, the Output ZXOB6-23 selected. Such a selection is made depending on the character type code explained above 00-11.

In this example it can be seen that the code "00" stored in the RTYP register 704-160 indicates the selection of the first Position of the ZX switch 704-58 causes the signals ZXOB4-23 as the output index value of the address preparation unit 704-3 feeds. It should be noted that processor 700 processes the A4BD instruction in a similar manner. During the control state However, FPOA loads a code of "10" into RTYP register 704-160. This will make the selection of the third Position of the ZX switch 704-58. This applies the signals ZXOB3-23 as an output index value to the unit 704-3.

From the above it can be seen that by using the CCSO field to form the index alignments for various shifts of the character type, further operation code decoding can be dispensed with and microinstructions can be saved. In the same way, for the reasons given above, the need for additional micro-instruction sequences can be suppressed when processing a large number of different instruction types. It should be understood that, while the above examples have been given in terms of specific commands, similar arrangements can be used with other commands which result in a significant saving in the capacity of the ECS control store 701-2.

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-246- 28A9500

The operation of the device according to the present invention will now be further described with reference to various different types of instructions. At a first For example, which will be described in connection with Fig. 8, assume that the instruction buffer contains four instructions, the following commands correspond to: add to A (ADA), store to A (STA), load indicator (LDI) and load A (LDA). Each of the commands has the format shown in Figure 10a. For a simplified explanation it is assumed that that the tm portion of the hint field of each of the four instructions does not specify an indirect address operation. It is also assumed that the commands do not specify a direct upper (DU) or direct lower (DL) type of operation.

According to the preferred exemplary embodiment, the operation codes of the instructions ADA, STA, LDI and LDA refer to memory locations in the CCS control store 701-2 which have CCSS fields with the following codes: 000000, 010000, 000010 and 000000. This means that the Commands ADA and LDA are within the class LD-SGL, that the command STA is within the class STR-SGL and that the command LDI is within the class LD-SGL-ESC. The various control states assumed by the hardware circuitry of block 704-102 and the operations performed during the I , C, and E cycles of operation in processing the four instructions in a scrolling fashion are illustrated in FIG.

Referring to Figure 8, it can be seen that the hardware circuitry of the processor completes I cycles of operation. The path taken in Fig. 7 is as follows: FPOA-> Digit XXX-> FPOA. During the FPOA control state, processor 700, under hardware control, performs the indicated operations . This means that it generates an effective address depending on the content of the R29 register 704-162j, the RBAS-A register 704-156 and the RRDX-A register 704-158. the

90 9 8 2i! 0592

28A9500

The resulting effective address is loaded into the REA register. It is also added to the base address and then loaded into the RADO register 704-46 according to FIG. 3e. Since the tm part of the instruction's information field does not specify any indirect addressing, the EA control information is set to the binary value "1". Furthermore, a code defining the A register (RBIR 24-26) is loaded into the RREG register 714-42 as shown in FIG. 3g.

As mentioned, there is the CCS field accessed by the ADA command Reference is made to an LD-SGL sequence by its coding. Since the td part of the information field of the Command does not specify a DU or DL operation the processor circuitry of block 704-108 a single read instruction, which is output to the buffer unit 750 under hardware control.

909823/0592

In more detail, the generated address is used in accordance with the absolute address loaded into the RADO register 704-46 Descriptor as instruction address. In addition, instruction bits 1-4 and zone bits 5-8 are passed through the circuitry 704-118 according to Figure 3c and the switch 704-40 is generated. These

the

Signals are passed through switch 704-40 instead of VBits 1-8 of is applied to switch 704-46 while bits 0 and 9 are set to the binary value "0". The zone bits become 5-8 set to the binary value "1" because they are not used for read instructions. Instruction bits 1-4 are converted into a Code 0111 by the decoder circuitry of block 704-118 converted. This instruction code specifies a memory QUAD read for the retrieval of a 4-word block from the main memory 800.

The circuitry of block 704-108 generates based on the CCS field and the control status signals of block 704-102 Hardware buffer memory instruction control signals (MEMOTB through [J4EM3TB. In the case of a cache single read instruction the signals CMEMOTB to [MEM3TB correspond to a code of "1000". Generate in accordance with the teachings of the present invention the circuits of block 704-108 see the signals [MEMOTB to [MEM3TB according to the following Bool * equations:

(mEMO-TB = FDEL DELSTRG

+ TERMG.EA-EIS ESC TRF

f TERMG.FCHAR · EA-DU-DL · (CTRL + ■ RDCLR + LDDBLG + LDHWUG + LDSGLG). (mEMI-TB = FPOA · TRF · EA-FTRF-TST

+ FTRF + FPIM-2 + FPI-INIT + FPIM-1 + FPIM-EIS + FDEL · DELSTRG

£ FPOA «TERMG. EArFCHAR-STRG + EIS TERMA + EIS TERMB. JMEM2-TB = TERMG ♦ EA «(lDDBLG + STRDBL + FDEL · DEL-STR-DBlI + EIS TERMA + EIS TERMB.

809823/05 9 2

MEM3-TB = FTRF + FPIM2

+ TERMG-EA. C (DU-DL) FCHÄR -fr RD-CLR 4- EFFADRGJ + EISTERMA.

Where TERMG = FPOA * (FTRF-TST + TRGO);

EIS TERMA = FPOP »DESCOoFEi IN» (CMPC + CMPCT + SCAN-FWD t / MVT + TCT + CONV + DNUM2 + DNUM3 + EDIT) + FP0P »DESC1cFE2N CDNUM2 + DNUM3 + EDIT + CMPC + CMPCT); and,

EIS TERMB = FPOP DESCO-FE11N.MLR.

These equations show the relationship between the CCS codes and the instruction signals applied to the DMEM lines will.

Other circuits within block 704-108 decode the CCS field and generate the [sz signals which indicate which half of the RDI register 704-164 is to be loaded. The (SZ signals serve as a size indicator that provides information provides whether there is a direct upper (DU) or direct lower (DL) operation or a single operation. In the case of a single read operation, the [sz signals have the binary values "0".

According to FIG. 8, the circuits of block 704-106 set the register key signals CCACHE-REG and CCCS to the binary value "1". The signal fCACHE-REG loads the single read instruction code into the RMEM register 704-130, while the (CCS signal ' the address of the CCS word, which is applied via the collective channel 704-204, in the ECS address register 701-10 according to Figure 3b loads. The buffer instruction code stored in the RMEM register 704-130 is transmitted via the decoding circuitry of the Block 704-118 is applied to lines DMEM, while the instruction word loaded into RADO register 704-46 is applied to the Buffer unit 750 is applied via the lines RADO / ZADO. Furthermore, the decoder circuits 704-120 set due to the Signals [MEMOTB to [MEM3TB] the REQCAC flip-flop 704-134

909823/0592

the binary value "1". This signals the instruction to the buffer unit 750. During the control state FPOA, the Processor under hardware control from an END operation in which it updates the command counter and the next Instruction (STA) loads into registers RBIR, RSIR, RBAS-A, RRBX-A and R29. The hardware circuitry of the Block 704-102 to return to control state FPOA to continue processing the STA command to begin.

The STA instruction requires two cycles to be complete Editing. These include an FPOA cycle and an FSTR cycle. Referring to Figure 8, processor 700 performs operations similar to those associated with the first cycle have been described. However, the operation code of the STA instruction causes a control word to be read from the control memory 7O4-2jWelch.es contains a CCS field which, through its Coding defines a STR-SGL sequence. Accordingly, the circuitry of block 704-108 asserts the [memOTB through [MEM3TB to the code of "1100" which is a single write operation specifies. The [sz signals again have the binary value "0". Likewise, there is a value that is transmitted via the ZDO lines Specifies the registers to be loaded (e.g. A register), transferred to the RRDX-A register 704-158. At the end of the second Cycle switch the hardware circuitry of block 704-102 to the FSTR control state, which causes the I processing cycle for the STA instruction is continued.

According to FIG. 8, during the second FPOA cycle, the buffer unit 750 executes a buffer operation cycle in parallel with the I operation cycles. Assuming that the requested data word is in the buffer memory 750-700. is located, the buffer unit 750 reads out the requested word and applies it to the lines ZDI. The processor 700 loads the data word into the RDI register 704-164 on the basis of a key signal generated by the decoder of block 704-106. It should be noted that in the case where

909823/0592

the requested data word is not in the buffer memory 750-700, the processor 700 stops its operation until the buffer unit 750 has fetched the word from the main memory 800. During the buffer cycle, the processor performs 700 also perform required boundary and access checks in a conventional manner.

According to Figure 8, the processor 7oo also executes a processing cycle during the second cycle, which leads to a Idle cycle leads. The reason for this is that while of the first cycle the processor 700 completes the processing of the previous instruction and the CCS address to the ECS address register 701-10. The processor 700 remains in an idle state until this transmission takes place. During the idle state, the microinstruction word with the format shown in FIG the CCS address is specified, is read out into the ECS output register 701-4. Furthermore, the processor 700 transmits the in the RREG register 714-42 loaded contents to the RRDXB register 704-189. It is the contents of this register that hold the register within the processing unit 714 for operation selects (e.g. for an addition operation). During the next cycle, processor 700 completes the Processing of the ADA instruction under microprogram control in the manner explained.

According to Firur 8, the code value determining the Α register, which was previously loaded into the RRDX-A register 704-158, the ZX switch 704-58 enables the content of the A register 704-50 to be selected for storage. Thus, the contents of the A register 704-50 go into the RADO register 704-46 via the ZDO switch 704-340 and the ZRESB switch 714-38 loaded. Referring to Figure 8, it can be seen that processor 700 is performing another END operation in which it fetches the next instruction (LDI) from the instruction buffer and loads the processor registers. The hardware circuits also switch of block 704-102 at the end of the FSTR

909823/0592

Cycle to control state FPOA. This completes the I processing cycle for the STA instruction.

During the third cycle, the buffer unit 750 determines whether or not based on the buffer single write instruction the address of the block containing the data word is in the buffer memory 750-700. If so, so the buffer unit 750 writes the block .... . by writing the data word into the memory 750-700. As can also be seen from FIG. 8, the buffer unit aligns 750 during the fourth cycle a write instruction to the main memory 800 together with the data word that is via the RADO register the ZAC-SW2 switch 750-170 and the switch 750-172 is applied to the DTS lines.

During the third cycle, the processor 700 processes un-

the

The microprogram control also VADA command. This means that the adder 714-20 of the processing unit according to FIG. 3g adds the content of the Α register, which is selected as a function of the RRDXB register content, to the value which is read from the memory via the RDI lines. The result is transferred to the Α register, which is selected as a function of the RRDXB register content via the collective channel ZRESA and the switch 714-36. This completes the processing of the ADA command by the processor. According to FIG. 8 , the microinstruction word which is defined by the CCS address read out from the STA instruction is transferred to the ECS output register 701-4. Since the processor 700 completes the processing of the STA command essentially almost entirely under hardware control, the microinstruction word read out is one that does not specify an operation, as is indicated in cycle 4.

During the fourth cycle, processor 700 begins the I cycle of operation for the LDI instruction. The operational

809823/0592

the
The code of the command refers to the Vccs word which contains a CCS field which, through its coding, specifies that the command is within the class LD-SGL-ESC. This instruction is a 3T instruction which processor 700 cannot process in a scrolling mode. The reason for this is that the EIS commands test the value of an indicator bit during the control state FPOA, the state of which can be modified during a subsequent E cycle of operation. The processor 700 therefore ensures that all instructions from the processing unit which could change the state of the mentioned indicator bit have been completed. This is done in that the hardware circuits of block 704-102 interrupt the continuous mode of operation by switching to the control state FESC and resume it under microprogram control in the manner explained here.

According to FIG. 8, the processor 700 operates during the control state FPOA is the same set of operations that were performed during the first cycle. The Processor 700 a buffer memory single read instruction for reading out the data word, which by the address part of the LDI instruction is fixed. Assuming that the data word is in the buffer memory, the buffer unit loads 750 during the next buffer cycle (cycle 5J das RDI register 704-164 with the data word read from the memory 750-700.

As previously mentioned, the buffer unit 750 sets up during of cycle 4 the content of the Α register during the buffer operation cycle to main memory 800. Therefore, nothing remains to be done. There are thus no operations during of the E-operation cycle executed. The microinstruction word, which is specified by the CCS address and which is read out on the basis of the LDI command, however, becomes the ECS output register 701-4 transferred.

0O9823 / OS92

"2843500

As can be seen from FIG. 8, the hardware circuits of block 704-} 02 remain in the control state FESC bis a microinstruction word has been read out into the ECS output register 701-4, which causes the processor 700 to restart the continuous processing signals *. Assume that this occurs during cycle five. At this time the processor 700 performs an END operation in which the instruction LDA is fetched from the I-buffer and into the registers the processor is loaded.

As previously mentioned, during the buffer cycle, the indicator data word loaded into RDI register 704-164. Likewise, the microinstruction word that contains the restart code for the Continuous operation, from the ECS control store 701-2 to the ECS output register 701-4 during the E-idle cycle read out in cycle 5. According to FIG. 8, the processing unit 714 completes the processing of the LDI command when transmitting the indicator data word into the indicator register 701-41 under the control of the Microinstruction word read out during the idle cycle. It is because of this word that the hardware circuits switch of block 704-102 to the control state FPOA, whereby the ongoing operation is started again.

The operation code of the LDA command causes the readout a CCS word from control store 704-2, which word contains a CCS code which specifies that the LDA command is within of class LD-SGL. Since this command is in the same class as the ADA command, the Processor 700 in an iterative manner the same sequence of operations as related to the ADA command was explained. The only difference is in the Ε cycle in which a different microbe command is specified by the CCS address. Accordingly, a further explanation of this command does not appear necessary.

909823/0592

From the above it can be seen how the processor 700 does the processing executes a series of commands in a scrolling fashion. The preferred embodiment of the present Invention allows processor 700 to process as many instructions as possible under hardware control. Furthermore it facilitates decoding of instructions that do not require buffer operation cycles. These commands are those that lie within the effective address class (e.g. those commands that provide a path to position XX in Figure 7 follow). For example, if the ADA instruction has a td field that defines a direct upper (DU) or a direct lower (DL) operation (code 0011 or 0111), so set the hardware circuitry of block 704-102 sets the signals ItiEMOTB through [MEM3TB to a code of "0001". The SZ signals are set to a code of either 10 (DU) or 11 (DL).

During the control state FPOA, processor 700 generates an effective address in the same manner as shown in cycle ^. However, since the buffer instruction code specifies a direct store operation, no buffer cycle is performed by the buffer unit 750 during cycle 2. This means that during this interval the effective address content of the REA register 704-314 is loaded into the RDI register 704-164 in FIG. 3c. For a DÜ operation, bit positions 0-17 of RDI register 704-164 are loaded with the effective address stored in REA register 704-314. In the case of a DL operation, bit positions 18-35 are loaded with the generated effective address. Since there is no buffer cycle, no limit or access checks need to be carried out. The decoder circuit 704-120 in Figure 3c does not switch the REQCAC flip-flop 704-134 to the binary value ¹¹ V "due to a direct code. The buffer unit 750 therefore does not respond to a buffer instruction code which specifies a direct operation and is effective Create the hardware circuitry of blocks 704-108 and 704-X24

909823/0592

"2843500

due to the CCS code only those signals which are necessary to transfer the contents of the REA register 704-314 to the RDI register 704-164 to transfer.

Processor 700 processes other commands within the effective address class in a manner similar to this previously described. Likewise, the other add, load, and store instructions are similar to those previously discussed ADA, STA, and LDA commands processed in a sequential fashion.

The arrangement according to the present invention will now be described with reference to FIGS. 12a and 12b. Figure 12a shows schematically the manner in which register selection in accordance with the teachings of the present invention Invention takes place. As mentioned, the coding of the CCSR field provides the register selection for commands from Load and storage type, the control for the register occupancy function and an incremental value for the command counter for an EIS command with the format according to FIG. 8b.

The CCSR field is coded as follows:

register

Q X

IC

AQ

QA

Xn

IC

According to Figure 12a it can be seen that the low ^ angigen two bits (e.g. CCS 18-19) can be used to select the value

909823/0 5 92

CCSR code Allocated tab 0000 A. 0001 Q 0010 Xn (1-RBIR 24-26) 0011 IC 1000 A then Q 1001 Q then A 0100 N / A οίοι • N / A 0110 N / A 0111 N / A.

to be selected, which is switched via the ZREG switch 704-53. Assume that processor 700 begins processing an LDA command, followed by an LDQ command. The operation code of the LDA instruction refers to a CCS memory location within the control memory 704-2, the
Contains word with the format shown. During the control state FPOA in a first cycle, the address preparation unit 704-3 of the processor generates an address and a buffer instruction which contains the address which, through its coding, defines a single read instruction.

According to FIG. 12a, the lower-order bits (00) of the CCSR field select the first position of the ZREG switch 704-53. When selecting, the code from 0001 is loaded into the RREG register 704-55. During the next cycle, the contents of register 704-55 are loaded into RRDXB register 704-189. Fertner processes the buffer unit 750 during this cycle
a buffer operation cycle to call out the word specified by the buffer instruction.

During a third cycle (Ε cycle), processor 700 refers to the microinstruction word in memory location 1103 defined by the CCSA field of the CCS word. Of the
Processor 700 operates under microprogram control
specified operation, in which the fetched word applied to the RDI lines loads into the A register, which

the
Register is selected by VccSR field.

Processor 700 performs the same sequence of operations
off when processing an LDQ command. It should be noted, however, that in this case the CCSR field contains a code 0001. The low-order two bits enable the ZREG switch to specify the code of 0010 as the output signal. This code selects when loading into the RRDXB register
704-189 selects the Q register as the register to which the word fetched by the buffer unit 750 is applied. The arrangement according to the present invention allows the processor

Ö09823 / 05Ö2

700 the processing of both commands using the same processing routine here by the microinstruction word is specified in the memory location 1103. Similarly, other types of commands can be edited in the same way will.

Figure 12b also further illustrates the manner in which the CCSR field controls the operation of the register occupancy circuitry of block 704-60. It is assumed that the processor 700 begins processing an A load instruction (LDA), then executes an AQ load instruction (LDAQ), which is followed by a modified Α load instruction (LDA, A). Both the Α-load instruction and the modified A-load instruction refer to the same CCS word, which contains a CCSR field with a ¹¹ O "in all bit positions. The instruction LDAQ, however, refers to the CCS word with a CCSR- Field that contains a code 1001.

Assume that both the load (RLD) and reset (RRES) counters of block 704-610 and the registers RBSYA through RBSYC have been cleared to "0". During a first FPOA cycle in which the processor 700 begins processing the first LDA instruction, all registers are thus reset to "0", which indicates that none of the registers is occupied. During the cycle FPOA, the processor 700 generates the signal ZREG-REG-BSY under hardware control. This signal along with the "O" count in the RLD counter selects the RBSYA register 704-600 as the register to be loaded with the value selected by the ZREG switch 704-53.

As previously mentioned, the low order two bits of the CCSR field enable switch 704-53 to select the first position code (e.g. 0001 = A) which will be loaded into the Α register during the next cycle. According to FIG. 12b , the count of the RLD counter is increased by 1 to a count of 01. The RRES counter remains on the

809823/0592

Count O. The A register is selected and loaded in the same manner previously described.

The next command is an AQ load command, which is based on a CCS word Refers to which has a CCSR field, which by

of
its coding specifies the LadenVQ register and then the A register (e.g. by the code of 1001). The upper two bits of the CCSR field indicate that the two registers are to be loaded in the order Q and then A. During the second FPOA cycle, the processor 700 generates the signal ZREG-REG-BSY again. At this point, since the RLD counter has a count of 01, the RBSYB register 704-601 is selected as the register to be loaded with the value selected by the ZREG switch 704-53. Then the count of the RLD counter is increased by 1 for the next cycle.

Since the low-order two bits of the CCSR field are a code

of 01, the second position of the switch

704-53 selected, resulting in a code of 0010 (Q register)

is loaded into RBSYB register 704-601.

During the second FPOA cycle, the buffer unit 750 also services a buffer cycle of operation to get the word determined by a buffer instruction generated during the first FPOA cycle.

the
According to FIG. 12b, the ^v A register is loaded at the end of the next cycle (FDEL), at which point the signal [REG is generated under microprogram control. This signal in turn causes the resetting of the RBSYA register 704-600 to the binary value "0" and the increment of the RRES counter to a count of 01. The RBSYA register 704-600 is determined by the O count in the RRES- Counter selected at the time the signal [REG is generated.

During the third FPOA cycle, processor 700 generates

909823 / 0S92

a key signal ZREG-REG-BSY. Since, the RLD counter on a When the count was 10, the RBSYC register 704-602 is selected as the register to be identified by the ZREG switch 704-53 selected value is to be loaded. This results in a code of 000 (Α register) being loaded into the RBSYC register 704-6Ot. The RLD counter is increased again by 1 to a count of 00. Since the information field of the next command the Α register defines and the RBSYC register has a value of 0001, the comparison circuit switches 704-604 the signal REGBSY to the binary value "1". The RRDXA register 704-158 thus stores the identity of the register, which is to be used for the address modification. When this value is compared with the contents of the RBSYC register 704-602 the signal REGBSY is set to the binary value "1".

The REGBSY signal offsets the I cycle circuits of the block 704-102 are able to set the I hold signal to the binary value "0" toggle, causing processor 700 to continue executing I-operation cycles is prevented. According to Figure 12a this takes until both registers Q and A have been loaded, whereby the LDAQ command is completely processed. In particular During the third FPOA cycle, that which has been fetched by the buffer unit 750 on the basis of a previous FPOA cycle Word loaded into the Q register, which is selected via the CCSR field. At this point the Processor 700 a signal [REG which resets the RBSYB register 704-601 which is determined by the count 01 of the RRES counter selected. Furthermore, the count of the RRES counter is increased by 1 to a count of 10.

During the next cycle (5th cycle), the processor 700 completes the processing of the LDAQ command by adding the from the buffer unit 750 due to the third FPOA cycle

fetched word is loaded into the A register. This redurch

gister becomesV the constant field (CCM) of the microinstruction word selected, which is read from the control store 701-2 during the second cycle of the LDAQ instruction. To this

90982370 5 9a

At this point in time, the processor 700 generates the signal QREG which resets the RBSYC register 704-602, which is selected by the count 10 of the RRES counter. Furthermore, the
RRES counter switched from a count of 10 to a count of OO (completed cycle).

When the RBSYC register 704-602 is reset, the
Signal REGBSY switched to the binary value "0", whereby
the processor 700 is enabled with further
I cycle of operations to begin. According to Figure 12b, this leads
to load the RBSYA register 704-600 with a code of 0001 (Α register) and to increase the RLD counter by 1
due to the generation of a key signal ZREG-. PEGBSY during the next FPOÄ cycle.

From the above it can be seen how the inventive
The arrangement provides additional advantages in controlling the flow operation of processor 700 through the register-gate-write hardware circuitry without the need for additional instruction routines.

Also from the previous listing of the CCSR field codes it can be seen that the arrangement according to the present invention also provides an incremental value for the EIS commands can deliver, which have the format according to Figure 8b.

As previously mentioned, processor 700 starts under hardware control upon completion of each command processing, processing of the next command at point B according to FIG 7. This includes the execution of an {END cycle of operation, in which the measures given for the signal [END are carried out in the measures section.

9823/0 5

2549500

A group of measures includes the following measures:

If FTRF-TST = 1 and.

EIS + FTRFNG = 1 then IC + 1 ^ IC.

If FTRF-TST = 1 and

EIS * FTRFNG = 1 then IC + CCSR1-3 IC.

This means that if the instruction being processed is an EIS instruction type, the processor 700 will use the ZICN switch 704-314 of the address preparation unit 704-3 enabled signals corresponding to the CCSR field as input to the Add adder 704-312 via a second position. In the event of a processing command, the CCSR field saves the code 0100. The adder 704-312 increases the value stored in the RIC register 704-310 by 4 in this case.

From the above it can be seen that by changing the coding of the CCSR field in accordance with the specific Type of EIS command the update of the command progresses automatically, eliminating the need to execute additional micro-commands are not required. It can be seen that the arrangement according to the present invention substantially reduces the microinstruction requirements of processor 700. In addition, the performance

he. of processor 700 improves a number of instructions

can perform within his repertoire.

909823/0592

A η h a η g A.

Data allocation

LDA drawer A

LDQ drawer Q

LDAQ Loading AQ

LDAC Load A and Delete

LDQC Load Q and Delete

LDXn load Xn (n = O, 1, 7)

LXLn load Xn from below (n = O, 1, ....?)

LCA loading complement A

LREG loading register

LCQ charging complement Q

LCAQ charging complement AQ

LCXn load complement Xn (n = O, 1, .... 7)

EAA Effective address for A

EAQ Effective address to Q

EAXn Effective address for Xn (n = 0, 1, .... 7)

LDI load indicator register

STA Save A

STQ Store Q

STAQ Save AQ

STXn Store Xn upwards (n = O, 1, .... 7)

SXLn store Xn down (n = 0, 1, .... 7)

SREG Save registers

STCA Store characters from A (6 bit)

STCQ Store characters from Q (6 bit)

STBA Store characters from A (9 bit)

STBQ Store characters from Q (9 bit)

STI Store indicator registers

STT Store timer registers

SBAR Store base address registers

STZ store zero

STC1 Store command counter plus 1

909823 / 05P?

STC2 Store command counter plus

ARS. A right shift

QRS Q right shift

LRS Long shift to the right

ALS A left shift

QLS Q left shift

LLS Long left shift

ARL A legal logic

QRL Q legal logic

LRL Long legal logic

ALR A left rotation

QLR Q left rotation

LLR Long left rotation

Floating point arithmetic

ADA Add to A

ADQ Add to Q

ADAQ Add to AQ

ADXn Add to Xn (n = O, 1, 7)

ASA Add saved to A

ASQ Add saved to Q

ASXn Add stored to Xn (n = O, 1, 7)

ADLA Add logic to A

ADLQ Add logic to Q.

ADLAQ Add logic to AQ

ADLXN Add logic to Xn (n = 0, 1, 7)

AWCA Add with carry over to A

AWCQ Add to Q with carry

ADL Add to AQ below

AOS Add 1 to memory

SBA Subtract from A

SBQ Subtract from Q

SBAQ Subtract from AQ

SBXn Subtract from Xn (n = O, 1, 7)

SSA Subtract stored from A

SSQ Subtract stored from Q

909823/059?

28495

SSXn SBLA SBLQ SBLAQ SBLXn SWCA SWCQ MPY

MPF

DIV

DVF

NEG

NEGL

Subtract stored from Xn (n = O, 1 ,

Subtract logic from A.

Subtract logic from Q

Subtract logic from AQ

Subtract logic from Xn (n = 0, 1, .... 7)

Subtract from A with carry

Subtract with carry from Q

Multiply whole number

Multiply fraction

Divide whole number

Divide fraction

Negate A

Long negate

.Boolean operations

ANA

ANQ

ANAQ ANXn ANSA ANSQ ANSXn ORA

ORQ

ORAQ ORXn ORSA ORSQ ORSXn ERA

ERQ

ERAQ ERXn ERSA ERSQ

AND to A
AND to Q
AND to AQ

AND to Xn (n = 0, 1, 7)

AND to memory A

AND to memory Q

AND to memory Xn (n = 0, 1, .... 7)

OR to A

OR to Q

OR to AQ

OR to Xn (n = 0, 1, .... 7)

OR to memory A

OR to memory Q

OR to memory Xn (n = 0, 1 , .... 7)

Exclusive OR to A

Exclusive OR to Q

Exclusive OR to AQ

Exclusive OR to Xn (n = 0, 1, .... 7)

Exclusive OR to memory A

Exclusive OR to memory Q

809823/0592

ERSXn Exclusive OR to memory Xn (η = O, 1, .... 7)

comparison

CMPA compare with A

CMPQ compare with Q

CMPAQ Compare with AQ

CMPXn Compare with Xn (n = O, 1, 7)

CWL Compare with border

CMG comparisons with size

CMK comparisons masked

SZN Set negative zero indicators from memory

SZNC Set negative zero indicators from memory

and delete

CANA compare "AND rait A

CANQ Compare AND with Q

CANAQ Compare AND with AQ

CANXn compare AND with Xn (n = 0, 1, 7)

CNAA DO NOT compare to A

CNAQ DO NOT compare to Q

CNAAQ DO NOT compare to AQ

CNAXn DO NOT compare with Xn (n = O, 1, 7)

Floating point

FLD. Sliding loading

DFLD double precision sliding loading

LDE Load exponent register

FST sliding storage

DFST double precision sliding storage

STE memory ,; Exponent register

FSTR Sliding storage rounded

DFSTR double precision sliding storage rounded

FAD Sliding addition

UFA Non-normalized sliding addition

909823/0 5 92

DFAD double precision sliding addition DÜFA double precision non-normalized sliding Add

ADE add to exponent register

FSB sliding subtract

UFS Non-normalized moving subtract

DFSB double precision sliding subtract DUFS double precision non-normalized sliding Subtract

FMP sliding multiplication

UFM Non-normalized moving multiplying

DFMP double precision sliding multiplication DUFM double precision non-normalized sliding multiplication Multiply FDV Moving division

FDI floating division inverted

DFDV double precision sliding dividing

DFDI double precision sliding dividing inverted

FNEG sliding negation FNO sliding normalization

FRD sliding rounding

DFRD double precision sliding rounding FCMP sliding comparison FCMG sliding comparison size DFCMP double precision sliding comparison DFCMG double precision sliding comparison size FSZN sliding setting of negative zero indicators From the store

Control transfer

TRA transmit regardless of conditions

TSXn transmit and set index register

909823/0 5 92

_ 268 _

TSS transmit and set secondary mode

RET return

TZE carry over to zero

TNZ carry over to non-zero

TMI transfer to minus

TPL transfer to plus

TRC carry over to carry over

TNC carry over to non-carry over

TOV carried over to overflow

TEO carry over to exponent overflow

TEU carry over to exponent underflow

TTF Transfer to counter expiry indicator OFF

TTN Transfer to counter expiration indicator ON

TPNZ - carry over to plus and non-zero

TMOZ Transfer to minus or zero

TRTN transfer · to abbreviation indicator ON

TRTF ■ Transfer to abbreviation indicator OFF

Different

NOP No surgery BCD Binary coded in binary / decimal GTB Gray in binary XEC Edit XED Edit twice MME Main mode entry DRL Derailments RPT Repeat RPD Repeat double RPL Repeat connection RCCL Reading: - Tent clock SPL Save notes and lengths LPL Loading notes and lengths Address register

LARn Load 'address register η

909823/0592

LAREG Load address register SARn Save address register n SAREG Store address registers

AWD Add word shift to specified AR

A9BD Add 9 bit character shift to specified AR

A6BD Add 6 bit character shift to specified AR

A4BD Add 4 bit character shift to specified AR

ABD Add bit shift to specified

tem AR

SWD Subtract word shift from fixed

AR

S9BD Subtract 9 bit character shift from fixed AR

S6BD Subtract 6 bit character shift from fixed AR

S4BD Subtract 4 bit character shift from fixed AR

SBD Subtract bit shift from specified

AR

AARn Alphanumeric descriptor for ARn NARn Numeric descriptor for ARn ARAn ARn for alphanumeric descriptor ARNn ARn for numeric descriptor

Main mode

DIS delay until interruption

LBAR Load base address register

LDT Load timer register

LLUF Load Interlock Error Register

SCPR Replaced with SFR

SFR Store error registers

LCCL charging timer

909823/0 5

RIMR Read-Interrupt Mask Register

LIMR Load interrupt mask register

RRES read reserved memory

CIOC Connect I / O channel

Extended storage

LBER Load base extension register

LMBA drawer main runner A

LMBB drawer main runner B

SBER Store basic expansion registers

SMBA storage main rail A

SMBB storage main rail B

MLDA bulk load A

MLDQ main charge Q

MLDAQ bulk AQ

MSTA main storage A

MSTQ main storage Q

MSTAQ main storage AQ

RPN read. Processor number

Stop stop

Multi-word commands alphanumeric

MLR Shift alphanumerically from left to right

MRL Shift alphanumerically from right to left

MVT Shift alphanumerically with translation

CMPC Compare alphanumeric strings

SCD key double character down

SCDR key double character reversed

TCT Test characters and translate

TCTR Test characters and translate vice versa

SCM key down with mask

SCMR key down with mask reversed

909823/0 5 92

Numerically

MVN Shift numerically.

CMPN Compare numerically

AD3D Add using three decimal operands

AD2D Add using two decimal operands

SB3D Subtract using three decimal operands

SB2D Subtract using two decimal operands

MP3D Multiply using three decimal operands

MP2D Multiply using two decimal operands

DV3D Divide using three decimal operands

DV2D Divide using two decimal operands

Bit string

CSL Combine bit strings on the left

CSR · Combine bit strings on the right SZTL Set zero and abbreviation indicator with bit string Left

SZTR Set zero and abbreviation indicator with bit strings on the right

CMPB Compare Bit-String Conversion

DTB decimal / binary conversion

BTD binary / decimal conversion

809823/0 59 2

Postponement of output

MVE Shift alphanumeric output

MVNE Shift numeric output

Multiple word

CMPCT Compare characters and translate

MTR Move to register

MTM move to storage

MVNX Shift numerically expanded CMPNX comparisons numerically expanded

AD3DX Add using three extended decimal operands

AD2DX Add using two extended decimal operands

SB3DX Subtract using three extended decimal operands

SB2DX Subtract using two extended decimal operands

MP3DX Multiply using three extended decimal operands

MP2DX Multiply using two extended decimal operands

DV3DX 'divide using three expanded Decimal operands

DV2DX Divide using two extended decimal operands

MVNEX Shift numerically extended edition

90982 3/0592

Virtual memory management Privileged commands

Load workspace registers Save workspace registers Load memory save registers Store memory save registers Load argument stack Load parameter stack Load page table hint list base register Save Page Table Hint List Base Registers Load Data Stack Descriptor Registers Store Data Stack Descriptor Registers Load Data Stack Address Registers Store Data Stack Address Registers Delete allocated page-divided memory Delete buffer memory Effective address and reference to test

All-mode commands

Load option registers. Store option registers. Store parameter stack registers Store argument stacks POP argument stacks Load descriptor (register) η Save descriptor register η Save reference address η Load reference address (register) η Save descriptor register η Effective reference to reference address (register) η Load extended address η domain transfer

909 823/059

Claims (1)

HONEYWELL INFORMATION SYSTEMS INC. Smith Street 5202714/16/17 / Waltham, Mass., USA Data processing system Patent claims: DV ~ system with a micro-programmable DV unit for execution of data expansions under the control of commands, with command processing in a continuous. Manner, and each instruction takes place in a number of different phases of operation until it is fully processed is processed, characterized by several = registers for storing commands to be processed, each instruction having a multi-bit opcode; a first addressable connected to a first register Control memory for receiving signals according to the multi-bit operating code of a command to be processed, which has several memory locations, each storing a word with at least one multibit control sequence code, the having fewer bits than the opcode and an address, the control sequence code being a number of hard-wired control sequences and the address specifies an established microinstruction in one of several processing sequences; a cyclically addressable second control memory with several memory locations for storing at least one microinstruction in one of various processing sequences; 909823/0592
ORIGINAL INSPECTED
:/do an address register to which the address of the first control memory is supplied and which is connected to the second control store to the microinstruction content of a memory location read out during an operation cycle; an output register connected to the second control store for temporary storage of the microinstruction content read out during the operating cycle; a hardwired one connected to the first control store Control status progression device for generating different control signal sequences, which different during a first operation phase to define operations to be carried out for each command, the incrementing device by each tax sequence code within a specific due of the operation code of an instruction being processed is enabled to use a predetermined sequence of Control signals for the execution of the operations during a first instruction phase to generate the address in the address register for continued processing of the command under the control of the specified processing sequence and to put the indexing device in a predetermined state, the specified processing sequence comprises a microinstruction having a restart code bit pattern; and decoding circuitry connected to the hard-wired control status incremental device and the output register, the signals for switching when the restart code pattern is read out from the second control store in the output register of the stepping device from the predetermined state to another state in order to continue the command processing. 2. Data processing system, characterized by an addressable main memory with several word storage locations for storing information including data and commands; 909823/0592 a buffer unit connected to the main memory for obtaining direct access to from the main memory retrieved data and commands ^ with multiple storage locations and control means for retrieving information from the main memory; and , a xmicroprograitimbaren DV unit, which is connected to the buffer unit and data manipulation under the control of Executes commands, command processing being in a continuous fashion and each command up to its completion Processing is dealt with in a number of different operational phases and the data processing unit comprises: Multiple registers for storing instructions to be processed, each instruction having a multi-bit opcode; a first addressable control store connected to a first register for receiving signals corresponding to the Multi-bit operation code of an instruction to be processed, which has several memory locations, each one word store with at least one multibit control sequence code that has fewer bits than the opcode and one address, wherein the control sequence code is a number of hardwired control sequences and the address is a first microinstruction in one of defines various processing sequences; with a cyclically addressable second control memory several memory locations for storing at least one microinstruction in one of different processing sequences and microinstructions of a number of operand address processing routines; an address register to which the address of the first control store is supplied and which is connected to the second control store is to read out the microinstruction contents of a memory location during one cycle of operation; an output register connected to the second control store for the temporary storage of the microinstruction content read out during the operating cycle; 909823 / 0B92 2649500 a hard-wired control status update device connected to the first control store for generation different control signal sequences, which different ones to be executed during the first and second phases of operation for each command Specify operations, the incrementing means comprising: Sequence decoding circuitry connected to the first control store for decoding the control sequence codes; several connected to the sequential decoding circuits bistable elements produced by the sequential decoding circuitry switch to different states in order to generate the different sequences of control signals, the decoding circuitry based on each tax sequence code within a certain class, predetermined bistable elements switch to the binary value "1" and the address in the address register for transmit continued processing of the command under the control of a specified processing sequence, the predetermined processing sequence comprises a microinstruction having a restart code bit pattern; and decoding circuitry connected to the hard-wired control status incremental device and the output register, the signals when the restart code pattern of the microinstruction is read from the second control store into the output register for switching predetermined bistable elements to the binary value "O" and another bistable element to the binary state Generate "1" to continue command processing. System according to claim 1, characterized , that. the hard-wired incremental device comprises: Sequence decoder connected to the first control store ^ circuitry for decoding control sequence codes; and a plurality of bistable connected to the sequential decoding circuits Elements that switch to different states in order to generate different sequences of control signals, the Decoding circuits switch a predetermined bistable element to "1" based on each control sequence code, whichever State corresponds to an escape state. 909823/0592 -s- 2649500 4. System according to one of claims 1 to 3, characterized in that the restart code has a first coded bit pattern that the decoding circuitry signals on the basis of the first coded bit pattern for switching the hard-wired stepping device from the predetermined state to one of several Create states to load the next instruction to be processed into the first of the registers. 5. System according to claim 4, characterized in that that the one of several states according to the coding of the sequence control code and status signals accordingly certain conditions is selected. 6. System according to claim 5, characterized in that the system further connects one to the DV unit Connected buffer storage device for quick access to commands and data stored therein having first, second, third and fourth bistable elements (FXRPT, FPI-INIT, FPIM-1 and FPOA) signals correspondingly the first coded bit pattern representing a restart of type 1 are supplied and this according to the following Bool ' see equations toggle to the binary value "1": FXRPT = XED + RPTS; FPI-INIT = XED + RPTS * STR-CPR; FPIM-1 = XED + RPTS'STR-CPR-IBuF-EMTY; and FPOA = XED + RPT * STR-CPR * IBUF-EMTY in which equations the terms used have the following meaning: XED - double processing RPTS - repetition STR-CPR - "Memory comparison" status is available. IBUF-EMPTY - "Empty buffer" status is present. 909823/0592 - 6 - 2049500 7. System according to claim 5, characterized that the instruction containing the restart code bit pattern at a predetermined location within the specified processing sequence is included, so that there are no interruptions within the number of different Operation phases result. 8. System according to claim 7, characterized that each command contains at least one address, that the system also has one connected to the DV unit Has buffer memory device for quick access to commands and data stored therein and that the different phases of the operation include: An instruction cycle (I cycle) in which an instruction operand address is produced; a buffer cycle (C cycle) in which the buffer storage device one specified by the instruction operand address Fetches operands; and a processing cycle (E cycle) in which the the instruction opcode specified operations with the Operands are executed by the DV unit; wherein the predetermined location is within the specified Processing sequence occurs at a point in time two cycles before the completion of the processing of the command lies during the Ε cycle. 9. System according to any one of claims 1 to 3, characterized in that the system further comprises a Buffer storage device connected to the DV unit for quick access to commands stored therein and data comprises that the restart code contains a second encoded bit pattern that the decoding circuitry on the basis of the second coded bit pattern, signals for switching over the hard-wired stepping device from the escape state to the other state corresponding to a first state within a number of states 909823/0592 2B49500 produce that the hardwired stepping device means for generating signals during the number of states to the buffer storage device to be able to automatically retrieve blocks of commands under hard-wired control to the DP unit to allow a new block of commands to be processed. 10. System according to one of claims 1 to 3, characterized characterized in that the restart code contains a third encoded bit pattern that the decoding circuitry on the basis of the third coded bit pattern, signals for switching over the hard-wired incremental switching device from the escape state to a trigger state produce that the hardwired stepping device other predetermined different sequences of control signals in accordance with the encodings of others from the first Control memory generated on the basis of the operation codes of successive commands of read control sequence codes, the successive instructions being stored in the first of the registers for use during certain phases to carry out operations in parallel with the reading of microinstructions from the second control memory. 11. System according to claim 10, characterized that the specified processing sequence includes a last microinstruction with a different restart code bit pattern includes the hardwired incrementing device generating further sequences of control signals after a predetermined time interval, the second control memory stops with the successive reading of micro-commands, including the last microinstruction, continues into the output register and that the decoding circuitry by the other restart code bit pattern enabled to send signals to enable the hard-wired switching device of a last running state to a next state 909823/0592 to continue editing other commands. 12. Data processing system with a micro-programmable data processing unit for Execution of data manipulations under the control of commands, with command processing in a continuous Manner and each command is carried out in a number of different ways until it is fully processed Operation phases is processed, characterized by: Several registers for storing commands to be processed, each command being a multi-bit operation ccde with at least one address and a hint field, which hint field by its code the type of defines address modification to be carried out with the address; a first addressable connected to a first register Control memory for receiving signals according to the multi-bit operation code of a command to be processed, which has several memory locations, each of which stores a word with at least one multibit control sequence code, which has fewer bits than the opcode and an address, the control sequence code being a number of hardwired Control sequences and the address specifies a first microinstruction in one of several processing sequences; a cyclically addressable second control memory with several memory locations for storing at least one Microinstruction in one of several processing sequences and microinstructions of a number of address modification routines ; an address register to which the address of the first control memory is supplied and which is connected to the second control store to the microinstruction content of a memory location read out during an operation cycle; an output register connected to the second control store for temporary storage of the microinstruction content read out during the operating cycle; 909823/059 2 "G - Control advice indicator circuitry attached to the first Register and are connected to the second control memory and based on a predetermined coding of the Indication field generate an output control signal indicative of a predetermined type of address modification; a hard-wired one connected to the first control store and the control advice indicator circuitry Control status progression device for generating different control signal sequences, which different during a first operational phase stipulate operations to be carried out for each command, the incremental device read out by each control sequence code within a specific one based on the operation code of an instruction being processed Class and is enabled by the control signal, a predetermined sequence of control signals which lead to the fact that the incrementer is switched to a state in order to have an address development to run under microprogram control and to transfer the control to one of the address modification routines for the generation of an effective address, the one address modification routine a final microinstruction comprising a restart code bit pattern; and to the hard-wired control state incrementer and decoding circuits connected to the output register, when reading out the restart code pattern of the microinstruction from the second control store into the output register Generate signals for switching the incrementing device from the predetermined to another state in order to process the command to continue. 13. System according to claim 12, characterized in that that the restart code contains a fourth coded bit pattern, that the decoding circuit the second coded bit pattern enables signals for switching over the hard-wired incrementing device from the predetermined state to a release control state that the hardwired 909823/0592 -ίο - 2549500 Incremental means a predetermined sequence of control signals to complete the first and second Operation phases and for the transfer of control to one of the processing sequences generated by the address is set based on the instruction opcode is read out for the completion of a third operational phase. 14. Data processing system with a micro-programmable data processing unit for Execution of data manipulations under the control of commands, with command processing in a continuous Manner and each command is carried out in a number of different ways until it is fully processed Operation phases is processed, marked by: Several registers for storing commands to be processed, whereby certain commands correspond to multi-word commands, which each have a multibit opcode, several addresses and a corresponding number of operand modification fields contain, and at least one of the operand modification fields by its coding determine that the associated operand has a predetermined characteristic; a first addressable control store connected to a first register for receiving signals corresponding to the multibit operation code of an instruction to be processed, which has several memory locations, each one word with at least one multibit control sequence code store that has fewer bits than the opcode and one address, where the control sequence code a number of hard-wired control sequences and the address of a first microinstruction in one of several Defines processing sequences; a cyclically addressable second control memory with several memory locations for storing at least one Microinstruction in one of several processing sequences 909823/0 5 92 and from microinstructions of a number of address modification routines; an address register to which the address of the first control memory is supplied and which is connected to the second control store / to the microinstruction content of a memory location read out during an operation cycle; an output register connected to the second control store for temporary storage of the microinstruction content read out during the operating cycle; Control advice indicator circuitry attached to the first register and are connected to the second control memory and based on a predetermined coding of the information field generate an output control signal indicative of a predetermined type of address modification; a hard-wired control status advancing device connected to the first control memory and the control advice indicator circuits for generating different control signal sequences, which are different during a first Operation phase determine the operations to be carried out for each command, with the incrementer by each Control sequence code within a specific read out on the basis of the operation code of a processed command Class is enabled to generate a predetermined sequence of control signals for transferring the address to the Address register for continued processing of the command under the control of the specified processing sequence transmitted and to put the incrementing device in a predetermined state, the specified processing sequence has as a first microinstruction one which, by its coding, encodes that of the control indication indicator circuits tests generated signal states, and wherein the second control store by the first Microinstruction branches to one of the operand address processing routines and the one operand address processing routine contains a final microinstruction with a restart code bit pattern; and 909823/0 5 92 to the hard-wired control status update device and decoding circuits connected to the output register which, when reading out the restart code pattern from the second Control memory in the output register signals for switching the incremental device from the predetermined State to another state within the predetermined sequence of control signals to start processing of the multi-word command. 15. System according to claim 14, characterized in that the hard-wired control status progressing device is enabled to provide control signals for the completion of the predetermined Generate sequence to continue processing the remaining addresses under hard-wired control. 16. System according to claim 15, characterized in that dx i comprises hard-wired incrementing device: Sequence decoder connected to the first control store circuitry for decoding control sequence codes; and a plurality of connected to the sequential decoding circuits bistable elements that switch to different states! wherein the decoding circuitry a predetermined bistable based on each control sequence code of the predetermined class Switch element to binary state "1" according to an escape state. 17. System according to claim 16, characterized in that the restart code is a fifth encoded bit pattern contains that the decoding circuit signals for switching on the basis of the fifth encoded bit pattern the hardwired incrementer from the predetermined state to one of the plurality of states generated to continue processing the multi-word instruction. 909823/0592 18. System according to claim 17, characterized that the one of the plurality of states in accordance with the coding of the sequence control code is selected. 19. System according to claim 18, characterized in that there is also one to the DV unit connected buffer storage device for fast Has access to commands and data stored therein and that the various phases of operation include: An instruction cycle (I cycle) in which an instruction operand address is produced; a buffer cycle (C cycle) in which the buffer storage device fetches an operand specified by the instruction operand address; and a machining cycle (E cycle) in which the operations with the operand specified in the instruction operation code are carried out by the DV unit. 20. Micro-programmable data processing unit, characterized by: A number of registers, one of which is used to store an instruction to be processed and the instruction comprises a multibit opcode; a first addressable control store having a plurality of Storage locations, one being arranged for each different instruction opcode and this at least a multibit control sequence field, a control register field, and includes an address field; a cyclically addressable second control memory with several storage locations for storing at least one microinstruction within one of several processing sequences; a sequence control circuit connected to the first control store for generating a sequence of control signals as defined by the coding of the control sequence field 809823/0592 is set in one of the memory locations, this field being read out on the basis of a command operation code will; a register section with several accessible to the program Registers; and one to the registers, the first control store and the Sequence control circuit connected output selector, which on the basis of the control register signals generated by the register field, the register field is read out by a corresponding instruction operation code, selects one of the registers and the memory location within a location group of the register field, an address field for reference to the same Processing sequence for processing the execution of the operation specified by each instruction operation code having. 21. Micro-programmable data processing unit, marked by: A number of registers, one of which is used to store an instruction to be processed and the instruction comprises a multibit opcode; a first addressable control store having a plurality of Storage locations, one storage location being provided for each different instruction operation code, and this comprises at least a multibit control sequence field, a control register field and an address field; a cyclically addressable second control memory with several storage locations for storage at least a microinstruction one of several processing sequences; a register section having a plurality of registers; and an output selection device connected to the registers and the first control store, which on the basis of of the control register signals generated by the register field, the register field being activated by a corresponding command ™ Operation code is read out, one of the registers is selected and the memory location within a memory location group 909823 / 0B92 of the register field, an address field for reference to
the same processing sequence for processing the
has operation execution specified by each instruction opcode. 22. Micro-programmable data processing unit, marked by : A number of registers, one of which is used to store an instruction to be processed and
the instruction has a multibit opcode;
a first addressable control memory with a plurality of storage locations, one storage location being provided for each different instruction operation code and with at least one multi-bit control sequence field, one control register field and one address field, and with certain groups of storage locations having identical values of the multi-bit control sequence fields and the address fields in addition to various values of the multibit control register fields; a cyclically addressable second control memory with several storage locations for storing at least one microinstruction within several processing sequences; a sequence control circuit connected to the first control memory for generating a sequence of control signals which is determined by the coding of the control sequence field which is contained in one of the memory locations and on the basis of a command operation code
is read out; a register section with several accessible to the program Registers; and an output selection device connected to the registers, the first control store and the sequence control circuit, which on the basis of the control register signals generated by the register field, the register field is read out by a corresponding instruction operation code, selects one of the registers and the memory location 909823/0592 within a storage group of the register field an address field to refer to the same processing sequence for the processing of the operation execution specified by each instruction opex "ation code, thus allowing the different types of instructions within each to share processing routines of groups is made possible. 23. Unit according to one of claims 20 to 22, characterized in that the control sequence field and the control register field of each memory location within the group of memory locations of the first control memory their coding uses the same sequence of control signals and a different register accessible to the program Specify the use of the specified processing routine by different command types that refer to the Reference to a group of memory locations. 24. Unit according to claim 23, characterized in that that different types of instructions each have an operation code which determines a load operation. 25. Unit me claim 24, characterized in that that different types of instructions each have an opcode indicating a memory operation certainly. 26. Unit according to claim 23, characterized that the command processing takes place continuously, with processing up to its completion happens in a number of different phases of operation and that the sequence control circuit is one of the sequences of control signals generated to perform those operations necessary for completing the first and second phases of operations of each command are required. 909823/0 5 92 27. Unit according to claim 23, characterized in that the command further comprises at least one Address on v / eis that the DV unit also has a processing unit for processing the commands, whereby it is connected to the second control store and the output selector of the register section and that the processing unit is enabled by the one microinstruction of the same processing sequence that perform the operation specified by each instruction opcode on the contents of the register specified by the Coding of the corresponding control register field is set during a third operational phase. 28. Unit according to claim 27, which cooperates with a buffer unit to provide quick access to stored therein To deliver commands and data, thereby characterized in that the various phases of the operation include: A command cycle (I cycle) corresponding to a first Phase in which an instruction operand address is generated from the one address; a buffer cycle (C cycle) corresponding to a second Phase in which buffer instructions are generated by which the buffer unit receives one through the instruction operand address fetches specified operands; and a machining cycle (E cycle) in which the the operation specified in the instruction opcode is performed on the operand. 29. Unit according to one of claims 20 to 22, characterized in that the accessible for the program Registers include: An accumulator register (A); a quotient register (Q); a number of index registers (Xn); and an instruction counter (IC). 909823/0592 30. Unit according to one of claims 20 to 22, characterized in that it further comprises: A control register selector having output ports, control ports and multiple groups of input ports, each group of input ports Control register signals are generated with a different coded bit pattern and the control connections signals accordingly certain bits of the multibit control register field are supplied, the selection device through this Signals is enabled to match one of the groups of input terminals with the output terminals with the control register signals. 31. Unit according to claim 30, characterized in that one of the registers is connected to certain input connections one of the groups is connected to signals corresponding to part of the instruction opcode that the registers accessible to the program include a number of address registers and that the Control register selector by a predetermined pattern of certain bits of the multibit control field in the Is able to send signals to the output terminals corresponding to the part of the instruction opcode to be selected create one of the address registers. 32. Unit according to claim 31, characterized in that each of the commands comprises at least one address and that the address registers have a corresponding number of index values for selection when the addresses are modified. 33. Unit according to claim 30, characterized in that first, second, third and fourth groups of input connections generate control register signals with the codes 0001, 0010, 1RBIR25-26 and 0100, wherein 909823/0592 - 19 - 2849bOO the pair of least significant bits of the multibit control register field is connected to the control terminals of the control register selection device. 34. The unit of claim 33, further characterized by: A first temporary register to which the control register signals supplied from the control register selector will; and a second register to which the control register signals from the first register for supply to the output selector supplied v / earth. 35. Unit according to one of claims 20 to 22, characterized characterized in that each command further includes at least has a Yidresse and a note field, whereby represents. Registers to be used during a 7 \ address modification it is determined that another register is connected to the one register in order to receive signals according to the information field to save, and that the register section also includes: Several occupied status registers to control the update the contents of the registers accessible to the program, each storing encoded values based on Control register signals are generated, which from the memory locations of the first control memory in accordance with the operation codes of various commands will; a corresponding number of comparison circuits, dir are connected to the registers and the other register; Control circuitry attached to each of the busy status registers, the slave control circuits and the first control memory connected and the determined control register signals are supplied which by their coding the number of registers to be loaded with coded values and the order of charging, with the control circuitry on Reason for certain control register signals TastsignaJe for loading 909823/0 Ϊ * 92 ■ '*: Κ? (? Ϊ 49500 the specified number of occupied status registers in Generate a predetermined order and these are loaded with fourth of the control register signals, which by others Control register signals are fixed; and one connected to each of the comparison circuits Output gate for generating an output register occupied signal which compares the contents of any Busy status register and the other register, to block the use of the register accessible to the program, which is determined by the contents of the control register is how it is required for the processing of the next command. 36. Unit according to claim 35, characterized that the command processing takes place continuously and each command up to its completion in a number of different operational phases is processed that the sequence control circuits are connected to the output gates and are enabled by the output register occupied signal to continue generating the sequence of control signals to block until what is accessible for the program Register is no longer occupied, avoiding conflict between instructions during the flow through operation will. 37. Unit according to claim 36, characterized in that the control circuits to the second Control memory are connected and on the basis of each register signal that is generated by reading out the one Microinstruction of a specified processing sequence is generated from the second control memory, an output signal is generated, to reset a previously loaded occupied status register to the binary value "O", so that the command processing can be resumed. 909823/0592
ORiGfNAL JNSPECTED 38. Unit according to one of claims 20 to 22, which with a buffer unit works together to provide quick access to commands and data stored therein, where certain instructions are in a multi-word format with a multi-bit opcode and have several operand addresses, characterized by an instruction counter update device, which comprises: an instruction counter for storing the address value of the next instruction to be fetched from the buffer unit; an increment selector with output ports, control ports and multiple groups of input ports, an increment value of 001 being fed to a first group of input connections, a second group is connected by input connections to the first control store for supplying the control register signals and a third group of input terminals is supplied with increment control signals from the second control store are, and wherein the control connections to the sequence control device are connected; and an adder circuit having first and second groups of input terminals connected to the instruction counter and the Increment selector output terminals are connected accordingly, and with a group of to the command counter connected output terminals, the increment selector by the sequencer when completing the processing of a multi-word command is enabled to apply a value corresponding to the control register signals to the second group of input terminals of the adder / and wherein the control register signals from one of the memory locations of the first control memory be read out based on the operation code of the multi-word instruction and the adding circuit the content of the Command counter is increased by a value that is contained in the control register field of one memory location. 909823/0592 28495 39. Micro-programmable data processing unit, marked by: Several registers, one of which is used to store commands to be processed and the command is one Opcode includes; a first addressable control memory with several memory locations, each storing a different instruction opcode and storing at least one multibit control sequence field, has a constant field with a number of bits and an address field; a cyclically addressable second control store, which is connected to the first control store, and several Having memory locations for storing at least one microinstruction within a processing sequence; a sequence control circuit connected to the first control store for generating a sequence of control signals, which is determined by the coding of the control sequence field in the memory space that is based on a each instruction operation code is read out, the control sequence circuit bistable storage devices for Storing signals corresponding to at least one bit of the constant field of the memory location which Bit signals, through their coding, determine the differences in the operations that are coded by differently Command opcodes are defined; and an execution unit for the execution of the Instruction opcodes set operations under the control of machining routine microinstructions such as it is determined by the address field of the memory location read from the second control memory, the execution unit is connected to different registers and to the bistable memory device and through the bit signal is enabled to perform operations by each of the differently encoded operation codes are set without a further test of the operation code of the instruction being processed would be required. 909823/0592 28495ÖQ 40. Micro-programmable data processing unit, characterized by: A register for storing an instruction to be processed, the instruction having an operation code; a first addressable control memory with several storage locations, one storage location for a different one Command opcode is provided and this at least one multibit control sequence field, one constant field having a number of bits and an address field; a cyclically addressable second control memory that is connected to the first control store is connected and several memory locations for the storage of at least one Having microinstruction within a processing sequence; bistable storage devices for storing signals corresponding to at least one bit of the constant field of the memory location, these bit signals by their coding specify the differences in the operations as defined by differently encoded instruction opcodes are; and an execution unit connected to the second control store for executing by the instruction operation code specified operations under the control of microinstructions of the processing routine as indicated by the address field of the memory location read from the first control memory is determined, the / execution unit to the Register and the bistable storage devices is connected and enabled by the bit signal to perform the operations specified by each of the differently coded operation codes without reading out additional microinstructions for testing the operation code of the instruction being executed would be required. 41. Unit according to claim 39 or 40, characterized that each of the registers has multiple bit positions; that operand type selectors 909823/0592 rait output ports, control ports and groups of input terminals are provided, with first and second groups of input terminals at the bit positions of the one register and at least one control connection are connected to the bistable memory device or is, and that the operand type selection means by the state of the bistable memory means in the Is enabled to selectively apply the content of the first and second numbers of bit positions to the output terminals, to set the difference in the operations defined by different opcodes of the instructions are. 42. Unit according to claim 41, characterized in that certain commands multi-word formats each format having a number of operand address fields which are a corresponding number of fields with at least first and second lengths which, through their coding, have a characteristic of the associated operands define that the bistable memory device stores the bit signal which is represented by its Coding the type of data characters in the operands specifies that the operand type selection device by a first state of the bistable memory device is enabled to output signals of the first number of bit positions corresponding to the first length field and that the operand type selection device is enabled by the second state of the bistable memory device to the output terminal Apply signals of the second number of bit positions corresponding to the second length field. 43. Unit according to claim 42, characterized in that the processing unit is arithmetic and logic circuitry for handling operands identified by operand addresses on a character basis be determined, the signals of the first and second 909823/0592 - 25 - 2649500 Number of bit positions determine the number of characters within the operands through their coding. 44. Unit according to claim 42 / characterized / That the first and second states are operand data of the numeric and alphanumeric type display accordingly. 45. Unit according to claim 39 or 40, characterized that the differently coded operation codes enable the first control store to Read out memory locations that contain the multibit control sequence fields with the same bit patterns. 46. Unit according to claim 39 or 40, characterized that the differently coded operation codes enable the first control store to Read out memory locations that contain the multibit control sequence fields with different bit patterns. 47. Micro-programmable data processing unit, characterized by: Several registers, one of which is used to store an instruction to be processed and this instruction comprises an operation code; a first addressable control store having a plurality of storage locations, each storage location being the storage a different command operation code is used and this at least one multibit control sequence field, a constant field with a number of bits and an address field and the storage locations of a group of address fields Storage locations store the same bit pattern and the constant fields store different bit patterns to save; a control register connected to the first control memory for receiving signals corresponding to the constant field ; 909823 / 0B92 a cyclically addressable second control memory, the is connected to the first control memory and a plurality of memory locations for storing at least one microinstruction has a plurality of processing sequences, these processing sequences comprising a number of common sequences; branch control circuitry connected to the control register and the second control store for control the address advancement of the second control store; and an execution unit for executing the operation codes provided by the instruction specified operations under the control of microinstructions of the processing sequence as they are carried out by the address field of the memory location read from the second control memory is defined, the second Control store by the in a first memory location a Group of memory locations based on a first instruction operation code is read out with a first bit pattern, the address field contained is enabled to carry out microinstructions to read out a first common sequence comprising a microinstruction which, through its coding, tests a of the bits stored in the control register and causes the branch control circuitry by the state of the a bit cause the second control store to advance to a processing sequence of a pair of sequences, in order to read further microinstructions and to enable the execution unit to carry out the execution of the by the first Command opcode to complete specified operation. 48. Micro-programmable data processing unit, characterized by: Several registers, with one of the registers used to store an instruction to be processed and the instruction one Opcode includes; a first addressable control store having a plurality of storage locations, each storage location being the storage a different instruction opcode and at least one multibit control sequence field, a constant field 909823/0592 with a number of bits and an address field and the storage locations of a group of several storage locations address fields with the same bit pattern and constant fields save with different bit patterns; a control register connected to the first control store for receiving signals according to the constant field; einai cyclically addressable second control memory with several storage locations for storing at least one microinstruction of several processing sequences, wherein the processing sequences include a number of common sequences; connected to the control register and the second control store Branch control circuitry for controlling the address advancement of the second control store; sequence control circuits connected to the first control store for generating a sequence of control signals, which is determined by the coding of the control sequence field in the memory location based on each instruction operation code is read out; and an execution unit for executing the operation codes provided by the instruction specified operations under the control of microinstructions of the machining sequence as specified by the Address field of the memory location read from the second control memory is defined, the second control memory by being in a first memory location of a group of memory locations that are based on a first instruction operation code is read out with a first bit pattern, the address field contained is enabled to carry out microinstructions to read out a first common sequence comprising a microinstruction which, through its coding, makes the test causes one of the bits stored in the control register and that the branch control circuitry by the state of the one bit cause the second control store to advance to a processing sequence of a pair of sequences, in order to read out further micro-commands and to enable the processing unit to process the by the first 909823/0592 Command opcode to complete specified operation. 49. Unit according to claim 47 or 48, characterized in that the second control store through the address field in a second memory location of the group of memory locations that is due to a second Instruction opcodes with a second bit pattern are read out, is enabled to use the microinstructions of the first common sequence and that the branch control circuitry by the state of one bit the second control store to advance to the initiate another processing sequence of the pair of sequences in order to enable the processing unit to carry out the Complete processing of the operation specified by the second instruction opcode. 50. Unit according to claim 49, characterized in that the first and second instruction operation code bit patterns define sliding and non-normalized sliding addition operations through their coding, and that the one and the other processing sequences standardized and non-standardized floating point addition operations by their coding and that one bit corresponds to a first bit of the control register. 51. Unit according to claim 47 or 48, characterized in that the first and second instruction operation code bit patterns determine by their coding comparison and size comparison operations and that one and the other processing sequence by their Define coding comparison and size comparison operations and the one bit to a second bit of the control register is equivalent to. 909823/0592 52. Unit according to claim 47 or 48, characterized in that the first and second instruction operation code bit patterns sliding memory and sliding rounded memory operations by their coding specify and that the one and the other processing sequences by their coding floating point memory and Define rounded sliding conuna storage operations and one bit corresponds to the second bit of the control register, 53. Micro-programmable data processing unit, marked by: Several registers, with one of the registers used to store commands to be processed and the command one Has opcode; a first addressable control store having a plurality of storage locations, each storage location being the storage a different instruction operation code is used and this at least one multibit control sequence field, a constant field having a number of bits and an address field; en
a cyclically addressable second control memory which is connected to the first control memory and has several memory locations for storing at least one microinstruction from several processing sequences; Branch control circuits connected to the second control store for controlling the addressing of the second control store, these branch control circuits comprising: Logic circuits connected to the control register for receiving signals according to the true and complementary State of one of these bits; an indicator register for storing information and statuses which occur during the operation of the processing unit appear; and Masking circuitry connected to the indicator register for the selection of one of the indications for test purposes and for the supply of signals according to the true one 909823/0592 and complementary state of the selected references to the logic circuit; and an execution unit for executing the operation codes provided by the instruction specified operations under control of machining sequence microinstructions as they is determined by the address field of the memory location read from the second control memory, the second Control memory by being contained in a memory location 2 and on the basis of a first instruction operation code read out address field is enabled to generate a microinstruction to read out a processing sequence, whereby this microinstruction, through its coding, enables the selective test of the specifies the true and complementary state of the note determined by the coding of the one bit. 54. Unit according to claim 53, characterized in that the first instruction operation code by its coding defines a transfer operation, whereby the one microinstruction by its coding the test the true and complementary state of a zero indicator specifies. 55. Micro-programmable data processing unit, characterized by: Several registers, one of which is used to store commands to be processed and the command is one Has opcode; a first addressable control store having a plurality of storage locations, each storage location being the storage different instruction operation codes is used and this at least one multibit control sequence field, a constant field having a number of bits and an address field; a cyclically addressable second control memory, the is connected to the first control store and several Has storage locations for storing at least one microinstruction of a plurality of processing sequences; 909823/0592 sequence control circuits connected to the first control store for generating a sequence of control signals which are determined by the coding of the control sequence field contained in the memory location read out on the basis of each instruction opcode; a control register connected to the first control store for storing the number of bits of the constant field, which defines the character type through its coding; a register section having a plurality of registers; an output selection device connected to each of the registers and to the control register, which on the basis of the Control register signals generated by each memory location based on a corresponding instruction opcode are selected between at least first and second shift values that are read from one of the registers will; and an execution unit connected to the second control store for performing the operations specified by the instruction opcodes under the control of microinstructions the execution routine, as indicated by the address field of the memory location read from the second control memory is specified, with the execution unit connected to various registers and the output selector and is enabled by the microinstructions to perform the operation specified by the instruction opcode using the shift value selected according to the coding of the constant field. 56. Unit according to claim 55, characterized in that the command operation code by its coding defines an addition 9-bit character shift, with the high-order bits of the constant field enable the output selection device to read out the first shift value by means of their coding. 909823 / 0B92 57. Unit according to claim 55, characterized that the instruction opcode is encoded with an addition 4-bit character shift defines / whereby the high-order bits of the constant field are coded in the output selection device in enable the readout of the second shift value. 58. DP system with a buffer storage device, a command processing device and an instruction execution device, wherein the system performs data manipulations under the control of commands, processing the commands progresses in a sequential fashion and each instruction in a number of different consecutive ones Operation phases are processed until its completion, characterized in that that the instruction processing device comprises: a plurality of registers for storing data from the buffer memory device received commands to be processed, each command having an operation code with a first number of bits; a first addressable control store connected to one of the registers for receiving signals corresponding to the Record the operation code of an instruction to be processed, with several memory locations for storing a word with at least one control sequence code and an address, the control sequence code having a second number of bits, the number of which is less than the first number of bits which by coding a number of hardwired Define control sequences, and wherein the address identifies a first microinstruction within one of the processing sequences and an output register to the memory is connected to store the word content of a memory location specified by the operation code; a control sequence decoder circuit connected to the output register of the first control store and is used to decode signals according to the control sequence code; and 909823/0592 one connected to the control sequence decoder circuit Hardware control sequencer for generating control signal sequences during selected phases of command processing define operations to be performed; wherein the first control store based on each operation code an instruction stored in the first register contains the content of a predetermined memory location in reads out the output register of the first control memory and the decoding circuitry enabling the hardware control sequencer, based on the control sequence code, to generate a predetermined sequence of control signals necessary to complete the operations of so many different phases as possible under hard-wired control and the transfer of control to the execution sequence, which is provided by the predetermined memory location read address is set. 59. Data processing system with a micro-programmable data processing unit for executing data manipulations under the control of Instructions, wherein the execution of each instruction proceeds in a number of different successive phases of operation, characterized in that that the processing unit comprises: several registers for storing instructions to be processed, each instruction having a multi-bit opcode; an addressable control store attached to one of the registers is connected to receive signals corresponding to the operation code of a next instruction to be processed, with several memory locations for storing a word with at least one multibit control sequence code, wherein the multibit control sequence code has a fewer number of bits than the multibit opcode identified by its Coding defines a number of hard-wired control sequences, with different groups of storage locations being multibit control sequence codes save with the same bit pattern; 909823/0692 28495 an output register connected to the memory for Storage of the word content of a memory location which is read out on the basis of the operation code; control sequence decoding circuitry connected to the output register for generating signals resulting from the decoding of the multibit control sequence code; and hard-wired control sequencers connected to the control sequence code decoding circuitry, which are controlled by the Signals of the decoding circuits are enabled to define a predetermined sequence of control signals of the series of operations within a number of consecutive operation cycles, wherein the operation cycles for completing the operations of as many instruction processing phases as possible under fixed wired control are required before switching to microprogram control. 60. System according to claim 59, characterized in that each memory location of the control memory furthermore has an address field for defining a first microinstruction of a different processing sequence. 61. System according to claim 58 or 59, characterized in that the command processing device also includes: A cyclically addressable second control memory with several memory locations that contain at least one microinstruction store an execution sequence required for operation execution as determined by the operation code during a final phase of operation; an address register to which the address is supplied from the output register of the first control store and which is sent to the second control store is connected to the microinstruction content read out during an operation cycle; and 909823/0592 an output register connected to the second control store for the temporary storage of the microinstruction content read out during the operating cycle, whereby the Hardware control sequencer generates signals upon completion of the predetermined sequence to assign the address to the Transfer address register and read out the one microinstruction of the execution sequence, whereby the operation code The execution of the operation determined during the last phase of the operation is completed. 62. System according to claim 61, characterized in that the hardware control sequence device also includes: An instruction cycle controller connected to the decoder circuitry to generate signals in accordance with the sequences of control states which the the processing means defines sequences of operations to be carried out during the first phase; and Hardware logic decoder circuitry connected to the instruction cycle controller and the output register of the first control memory are connected, wherein the instruction cycle control means by the decoding circuitry is enabled to generate signals according to a first sequence of control states, which the hardware logic decoding circuitry into the Enable to generate control signals during hardwired operation cycles determined by the control states the predetermined sequence are defined. 63. System according to claim 62, characterized in that the hardware logic decoding circuits Have circuits for generating signals which enable the retrieval of a next command from the buffer memory device and cause it to be loaded into the one register. 909823/0592 64. System according to claim 62, characterized in that certain commands have a single word format with an address which, through its coding, specifies that certain types of indirect address modifications with the address to be executed that the cycle controller through the decoding circuitry and signals from the instruction address are enabled to output signals according to a second predetermined sequence of generating control states, thereby reducing the hardware logic decoding circuitry Generate control signals that enable the processing device, the fixed indirect address modification under hardwired Control. 65. System according to claim 62, characterized in that certain commands have a multi-word format having a plurality of addresses that the cycle control means through the decoding circuitry into the Enabled to generate signals corresponding to a third predetermined sequence of control states, whereby the hardware logic decoding circuitry generates control signals which enable the processing device to perform those operations under hard-wired control that are necessary to fetch various operands which are determined by each of the addresses. 66. The system of claim 65, characterized in that those operations include operations which are required when any of the addresses define an indirect operand address by their encoding. 67. System according to claim 66, characterized in that each command has at least one address and that the different phases of processing include: 909823/0 5 92 An instruction cycle (I cycle) in which the operand addresses of the instruction are generated, a buffer cycle (C cycle) in which the buffer storage device gets an operand specified by the instruction, and an execution cycle (E cycle) in which the the instruction operation code specified and operations to be carried out with the operand by the processing device executed, the first phase corresponding to the I-cycle. 68. System according to claim 67, characterized that the hardware logic decoding circuitry comprises buffer instruction decoding circuitry, which are enabled by the control sequence code and the signals from the cycle controller Buffer instruction signals for forwarding to the buffer storage device to fetch the operand specified by the instruction address that is required for execution of the command is required during the C operation phase cycle. 69. System according to claim 68, characterized in that the processing device further a memory request decoder circuit connected to the buffer instruction decoder circuitry, which is enabled by certain encodings of the buffer instruction signals, a memory request signal to signal the buffer memory device to execute a C cycle of operation, whereby bypassing the C cycle of operation according to the encoding of the control sequence code. 90982 3/0 5 92 70. System according to claim 69, characterized that the control sequence code indicating an instruction in the effective address class the buffer instruction circuitry enabled to generate instruction signals specifying a direct memory operation, and that the request decoding circuit is prevented on the basis of the instruction signals from generating the memory request signal to create. 71. System according to claim 58 or 59, characterized in that the memory locations of the first control store comprise a number of different groups of storage locations, each of which contains a control sequence code with the same bit pattern to the same predetermined hard-wired control sequence determine the number of instructions within the possible sequences for executing a different class of instructions corresponds to the number of storage locations within one of the assigned groups. 72. System according to claim 71, characterized in that the number of different Groups of memory locations contain control sequence codes with bit patterns representing a number of hardwired numbers within a specify a limited number of operational cycles executable control sequences, with the command execution primarily under Hardware control advances. 73. System according to claim 72, characterized in that g e k e η η τ indicates that the number of hardwired control sequences a first executable within one cycle of operation Group of sequences includes, the first group including a single load sequence during which the buffer storage device to perform a single memory read cycle of operation. 909823/0592 74. System according to claim 72, characterized in that the number of hard-wired control sequences comprises a second group of sequences which can be executed within two operating cycles, which second group includes a double load sequence during which the buffer memory device performs a double memory read operation cycle has to perform. 75. System according to claim 72, characterized in that a number of different groups of memory locations contain control sequence codes with bit patterns that define a different number of hard-wired control sequences, which require more than the limited number of cycles of operation. 76. System according to claim 75, characterized in that the other number of hardwired Control sequences comprises a double storage sequence. 809823/0 5 92