DE2828836C2 - Non-volatile memory that can be electrically erased word by word - Google Patents

Description

The invention relates to a non-volatile memory which can be electrically erased word by word and is in the form of a matrix arranged memory cells.

From IEEE Transactions on Electron Devices, Vol. ED-24, No. 5 May 1977, pages 606-610, there is one Floating gate memory cell for the production of non-volatile, electrically reprogrammable memories known These field effect transistors have a floating memory gate and a controllable control gate arranged vertically above the channel path, the control gate covering the entire channel path covers while the floating gate only ίο overlays part of it The so-called split gate structure Avoids errors when reading deleted memory cells with a depletion character. Loading the floating memory gates are carried out by means of channel injection. To do this, electrons are in a short channel accelerated and conveyed to the storage gate by means of an additional electrical cross-field. Discharge or the floating gate is erased by tunneling back the electrons at a high applied electrical voltage between the control gate and a diffusion region

In the German patent application P 27 43 422.6-53 a non-volatile memory that can be erased word by word is used proposed in fioating gate technology. Both charging and discharging of the floating gate takes place by means of a direct transfer of electrons between the floating gate and substrate, whereby a high electric field of suitable polarity between the floating gate and a diffusion region is created.

30. With all previously known stores that are from the specified memory cells are built up, the erase time is fixed via an external timer . and set The deletion times are to be selected so large that manufacturing-related fluctuations the erasing properties of the individual cells not only within a chip, but also with regard to different production batches can be taken into account. In addition, they must also be through the timer self-induced tolerance fluctuations in the duration ■ to be included. Usually that's not why it is to avoid having at least one in ten of the memory transistors until it is deleted in the depletion state. These over-erased memory cells represent during the Readout represents an undesirable shunt to the selected memory transistors. As a rule Therefore, the memory cells of an electrically erasable memory must have an additional atis selection transistor own. This selection transistor can indeed in many cases with the memory transistor to one Split-gate structure can be summarized. Through this however, the technological problems increase and the manufacturing yield decreases. In addition, the long deletion times of the memories described cause the risk of neighboring word interference and often also cause programming properties to deteriorate, in particular in the case of memory cells in which the writing process takes place by means of channel injection. Long deletion times also reduce the number of permissible write-erase cycles and thus the service life of such cycles Memory.

The object of the present invention is to equip a memory in such a way that minimum erase times can be achieved for each individual memory cell.
This object is achieved in that a control is interconnected with the memory matrix in such a way that each memory cell of a memory line has an individual erase duration, the end of which

is determined by the achievement of a predetermined erased state of the memory cell.

The memory according to the invention has the advantage that a depletion state of transistors in memory cells to be erased is prevented. Once can not enter the Deplelionszusiani to erase memory transistors can be of inventive storage and one-transistor memory cells use, which again the advantage of a smaller space requirements corresponding memory chips yields As., ^1. · .W inimmalen erasing time for memory cells is also a consequence of the advantage a minimal oxide change during erasing, which in turn results in an increased number of write-erase cycles, ie an increased service life of memories according to the invention compared to conventional memories

The control of the memory according to the invention has the further advantage that it is at a minimum additional circuit effort also allows the definition of the total deletion time, as it is in the am Patent application P 28 28 855.0-53 filed on the same day by the same applicant is described. An external timing element can thus be saved.

A further development of the invention consists in that in order to achieve a variable erase duration Storage cell and for checking the state of erasure of the storage cell, which is adjacent to the storage cell Erase voltage is divided into a time sequence of individual pulses, so that in the pulse pauses in each case a control reading process is switched on.

This measure has the advantage that single-transistor cells can also be used to construct a memory can. Furthermore, dividing the entire erasing pulse into many individual pulses has the advantage of being one overall lower crystal heating during the quenching and thus a reduction in the damage that can occur due to a corresponding heating during the extinguishing process. That advantage is up the more significant, the greater the extinguishing currents, d. H. ever the heating is greater during the entire extinguishing process. Such extinguishing currents come z. B. by unwanted breakthrough effects occur.

In the case of cells that do not have an erasure area electrically isolated from the channel area, simultaneous erasure and control reading is not possible as z. B. in n-channel memory cells for erasing a high positive voltage must be applied to the source. while the source must be at ground for control reading. In p-channel technology, the same applies with the signs of the applied voltages exchanged with '°. These two conditions cannot be met at the same time. Dividing the erase voltages into a time sequence of individual pulses enables control reading during the erase pulse pauses. It is advantageous that the erase period of a memory line has ended. if the memory cell has a threshold voltage Vr ("0") during a control read operation, where the relationship applies | Vr ("0") | less than or equal to \ U <, i \. if uai. means a predetermined threshold value of the memory cell used.

In the case of memory cells using n-channel technology, the above-mentioned relationship between the lower threshold voltage value Vr (nO «) and the control ^{read voltage h} Uni> Vr (» 0 «)> 0 ensures that the cell to be erased cannot go into the depletion state. To ensure the above relationship, the duration of the individual erase pulses is determined so that the line to be erased during fine ·; !, eschimpulses cannot get into the depletion state, but is switched off beforehand.

It is also advantageous that the variable erase duration is achieved by means of a temporally continuous erasure voltage and by means of simultaneous control reading, the erase duration of a memory cell being ended when it has a threshold voltage of VV ("0") less than or equal to Um. but has greater than 0

Continuous erasing and simultaneous reading can be carried out with memory cells of the floating gate type, which have an erasure window that is electrically isolated from the channel area, so that with n-channel technology the Source voltage can also be 0 volts during the entire erase period, while the isolated Diffusion area in the erase window has a high positive voltage. Such a cell is in DE-OS 26 43 987 described.

A registered letter with individual bit writing time has a comparatively _o -.ringe practical significance. While programming, run; all welding voltages asymptotically towards final values, the fluctuations of which are on the one hand small and on the other hand the exact value is unimportant. There is no excessive writing, analogous to over-erasing in the depletion state. When writing, the control is expediently designed as it is described in patent application P 28 28 855J-53, filed on the same day by the same applicant, in order to save an external timer and to receive a defined minimum value of the status »1« at the same time.

Furthermore, it is advantageous that during the erasure period and within a control reading process in the case of a gate voltage Ugi, the erased state is indicated by the decrease in the absolute value of the drain voltage I i / o).

As is well known, the conductivity is changing. from Floating gate transistors depending on the state of charge of the floating gate. This change in the conductivity state can be used as a signal to terminate the erase state. When switched bit by bit Drain lines to which a certain read voltage is applied. the drains float during the Erase time during the control reading process is then high to a certain voltage value if the transistors have been sufficiently deleted. Requirement is. that the unselected memory cells that have no depletion character allowed to achieve, fed by a sufficiently low gate voltage of almost zero volts are. It is advantageous that those drain output signals which indicate the end of an erase period of a memory cell, for switching off the at this cell applied erase voltage can be used.

Furthermore, it is advantageous that the relationships of the Field effect transistors used word by word to build up memory cells and the drain lines are managed bit by bit. When using a cell with an electrically isolated diffusion area inside the most extinguishing. As described in DtOS 26 43 987, among other things, the erase window lines run always bit by bit, the source lines in this case being at zero potential. In the cells without isolatedf-t. On the other hand, the Snurrc'citungen are really nice separated from each other bit by bit.

Finally, it is advantageous that a control circuit is interconnected with the memory matrix.

ilaB the gate voltage, which is required as a predetermined threshold voltage value (Ua) for control reading during erasure, and the gate voltage for reading out the memory (Uc; r) a \ xs are taken from one and the same voltage divider, so that Uai. less than -. ίΛ, -K applies.

This measure guarantees in an advantageous manner a safe minimum distance between the gate voltage Uc, R when reading and the threshold voltage Vy ("O") of the erased state of a memory cell, m where: VV ("0") smaller than Uor- It can therefore always can be read out safely. Different erase properties of a memory cell within a memory due to tolerances do not have an effect on the reliability during reading, but only on the r> duration of the erase process. Because the unprogrammed state can be determined very precisely with this measure relative to the read voltage, the width of the electrical erasing window, ie the potential difference between the gate voltage 2 " during control reading during the erasing Ugl and the" I "state of the programmed state, can be reduced can advantageously either the voltages be low during programming or the programming time is particularly short.

The invention is explained in more detail below using exemplary embodiments and the drawing. Execution in Examples and figures relate to memory in n-channel technology, which is indicated by corresponding Change of sign also transferred to p-channel technology leaves.

Show it:

Fig. La - e data of an erased by means of pulses Memory transistor during the erase time r of a memory line:

F i g. 2 a control for a: memory according to the invention composed of single-transistor cells with a source-side -m Reloading area during unloading;

3 control of a memory according to the invention from single transistor cells with an isolated charge transfer area during the erasure.

Fig. La indicates the erase time r of the memory line. 4-, while the flip-flop inputs 130 and 230 from FIG. 2 and the gates of transistors 113 and 213, respectively F i g. 3 can be raised from the voltage state "0" to the voltage state "1".

Fig. Ib shows the time course of the difference v> between Sourceootentiai Us and gate potential LU, or between the charge reversal potential Ul and the gate potential Ug of a transistor cell. As shown in a memory according to FIG. 2 or according to FIG. 3 is provided. Here are a cell to be erased so π Iong high voltage pulses in sufficient numbers, indicated here by the pulses 10,11,12 submitted until the cell to be erased a certain threshold voltage VY ( "0") reached <Ugl. After that, the erase time are τ until the end of the whole <■ * -> memory line only very small voltage pulses, indicated by 13, 14 or delivered, no further voltage pulses to the cell to be deleted. Fig. Ic shows the time profile of the gate voltage Uc, during the erase pulse pauses. The -ί entire erase pulse pause is determined by the control duration 7V /. Fulfills. The control read duration can also be shorter than the erase pulse pause; it only has to be within an erase pulse pause. In the following figures and general examples, the control reading duration 7V / is chosen to be equal to an erase pulse pause. The control pulses 15 to 20 have a fixed voltage value Ur.i. on. which defines a certain predetermined threshold voltage value of the cell used and is significantly smaller than the height of the quenching miniature pulses according to FIG. Ib.

Fig. Id shows the threshold voltage VV of a memory cell as a function of time t. The threshold voltage then falls during the erase pulses 10, II, 12 in FIG. 1b from the initial level 21 to the levels 22, 23, 24 in sequence. The level 24 is smaller than the specified Galley voltage Ugl. the in F i g. Id is shown as a dashed line. As can be seen from Fig. Ib and Id, after reaching a level 24 which is below a voltage Ugl , no further erase pulses are emitted to a cell to be erased, so that the threshold voltage Vt no longer changes from this point in time. FIG. 1e shows the drain voltage Ud as a function of the time t within the erase duration r of a memory line (cf. FIG. 1 a). The drain voltage Ud is during Kontrollesedauer T _K l equal to the drain relatively small read voltage Loo adjacent the drain voltage during the erase pulse duration Ti., Depending on the driving method within the hatched B'reiche 29, 30, 31 may be large or small. The drain voltage level has during the erase pulse duration Tl no influence on the function of the circuit described. After the threshold voltage Vr (see FIG. Id) has fallen below the value Ucl, the memory cells to be erased become conductive. The drain voltage Un thus falls during the control read period 7V /. on the values 35, 36, 37, 38, 39. which are approximately equal to 0.

F i g. 2 shows a control of a single transistor cell without an isolated diffusion region in the area of the erase window. For reasons of clarity, only four memory cells 100, 200, 300, 400 with their associated control have been shown. The m-th bit-wise switched source line 120 connects the sources of the memory cells 100 and 300. Correspondingly, the π + 1-th source line 220 connects the sources of the cells 400 and 200. The n-th bit-wise switched drain line 140 has an electrical potential U _D " and connects the drains of the memory cells 100 and 300, the bit-switched drain line 240 has an electrical potential Uo _{n +} I and connects the drains of the memory cells 200 and 400. The gate line 160 with a gate voltage . · L'cm connects the gates of the memory cells 100 and 200, the gate line 360 with a gate voltage Ucm + \ connects the gates of the memory cells 300 and 400. The source line 120 and 220 can switch between a low voltage {of approx ) at connection 123 or and a high voltage (from approx. 25 to 40 V) at connection 124 or 224. The source line 120 or 220 is then at a lower potential when the transistor 121 or 221 is turned on. The gate of the transistors 121 or is controlled by the output 126 or 226 of a NAND element 125 or 225. An input 127 of the NAND gate 125 and an input 227 of the NAND gate 225 leads in each case during the erase pulse duration Tl a "1", which has been indicated in the drawing symbolically by Tl, during this connection to

all other lines lead to a "0". At the second entrance 12? b / .w. 228 of the NAND element 125 or 225 is an output of a flip-flop 129 or 229. An electrical signal is present at the input 130 or 230 of the flip-flop 129 or 229, which is »1 «While a» 0 «is used for all other times. The drain lines 140 and 240 are connected to the second input 131 or 231 of the Fl:;, .- flops 129 or 229 AND gate β shown (indicated by an arrow), the output of which, after the erase process has ended on all cells of a memory cell, switches off the signal r present at inputs 130 and 230 for the erase phase. During the entire deletion period r, the input 130 or 230 of the flip-flop 129 or 229 always receives a “1”. Correspondingly, the second input 131 or 231 of the flip-flop 129 or 229 also carries a positive voltage LOo of about 5 to 15 V via the load transistor 135 or via the transistor 235 during the entire erasing phase. Output 128 or 228 therefore carries a »1« until the selected cell of the associated bit has been deleted. The second input 127 or 227 of the NAND element 125 or 225 has a “1” during the duration of the erase pulses Ti. , While it has a “0” at all other times. The output 126 or 226 of the NAND element 125 or 225 thus carries a “0” during the erase pulses, ie the transistor 121 or 221 is blocked, the source line 120 or 220 is thus based on Up ι ~ 30 V to 40 V via the switched on transistors 122 and 174 or 222 and 174 at a high positive potential (25 V-40 V). During the erase pulse pauses, however, a “0” is present at the input 127 or 227 and thus an “I” is present at the outputs 126 and 226 of the NAND element 125 and 225, respectively. As a result, the transistor 121 or 221 is switched through and low voltages of approximately equal to 0 V are thus applied to the source line 120 or 220 via the transistor 121 or 221 in the erase pulse pauses. so that a low voltage at the source and a small positive voltage (U _D d) at the drain can be checked. If a selected cell is now in a bit, e.g. B. in the / j-th bit, sufficiently erased, this cell becomes conductive. The drain voltage LOn thus drops to a low voltage of approximately 0 in the subsequent erase pulse pause. From this point in time on, the input 131 of the flip-flop 129 carries a "0", while the second flip-flop connection 130 carries a "1" during the total erase time r of the memory. The flip-flop output 132 thus toggles to "1", while the second flip-flop output applies a "0" to the input 128 of the NAND element 125. The "1" at the output 132 can be connected to an input of an AND, not shown -Gate β are placed, whose output signal emits an electrical signal after the end of the deletion period of the last selected cell, which can be used to switch off the signal for the extinction period r. The output 226 at the NAND element 125 always has a "1" for the entire subsequent erase period, which is why transistor 121 is always switched on and the source line 120 thus carries a potential of approximately V for the entire subsequent erase phase of the memory Each individual row is thus switched off individually and the AND gate switches after the end of the deletion period of the last cell

β via its output signal from the electrical signal for the Löschcliuier r of the selected memory line. The flip-flops are reset only after the entire l.öschvorgangs once during the erase period simultaneously with the zero levels at the inputs 130 and 230 of the drain voltages üo "or U \)" ± \ at the inputs 129 and 229 at least briefly go to "I".

For gate control, let m + I be a selected memory line, while m is a word that has not been selected. The word selection is made with a logical "0" from the address decoder. indicated by the signal word. A “0” is thus fed to input 390, which is why transistor 366 is switched through via inverter 391, while transistor 367 is blocked at the same time. The gate line 360 thus carries a gate voltage Ur: “, *., Of approximately equal to 0 V above the level indicated by Tut. and inverter 172 turned on transistor 170. Thus, during the erase pulse duration Ti. a voltage of approximately 0 volts is applied to the gate line of a selected word, while at the same time a high positive voltage is applied to the source lines of 25 V to 40 V, as has already been shown. During the erase pulse duration, however, the Gat are there of unselected neighboring words z. B. of word m on a high positive voltage, so that neighboring word interference are switched off when deleting. The input 190 of the unselected word carries a “1”, which is why the transistor 166 is blocked via the inverter 191, while the transistor 167 is switched on and the transistor 168 is blocked via the inverter 173 during the erase pulse duration Ti. A high positive voltage of approximately Up \ = 25 V is thus applied to the gate line 160 of an unselected word via the switched-on transistor 169. The gate voltages of the neighboring words are thus at such a high positive potential that the voltage differences Us-Uc = 0 V to 15 V are not sufficient to erase the neighboring cells. The fact that transistor 169 is switched on during the extinguishing pulse duration 77 results from the fact that during this time transistor 175 is blocked by means of inverter 176 and transistor 174 is switched on via resistor 177 and thus a positive voltage of approximately LV ₂ = 30 V to 40 V leads to the gate of transistor 169.

During the control read duration Tkl, in the erase pulse pauses, the transistor 170 is not turned on because of the inverter 172 . The gate line 360 of the selected word, word / n + 1, is thus connected to the control reading voltage Ugl via the switched-on transistor 171. which can be taken from a potentiometer, similar to that provided for in application P 28 28 8553-53 filed by the same applicant and filed on the same filing date

The gate line 160 of an unselected word is at a voltage Ucm approximately equal to 0 V during the control reading period Tkl via the through-connected transistors 167 and 168 and because of the blocked transistor 169. This eliminates neighboring word disturbances during the control reading

The transistor 169 is blocked because during Tkl the input of the inverter 176 carries a "0" and its output a "1", which is why the transistor 175 is switched on and the transistor 174 (resistance of 177

> Resistance of switched transistor 175) is blocked. which has the consequence that transistor Ib ¹ J is also blocked.

Fig. 3 shows a control of a floating gate F.intransistorzclle with an insulated charge transfer area in the area of the erase window. For the sake of clarity, only four memory cells !; _ · Η 101,201,301,401 shown with their associated control. The memory cells 101, 201, 301, 401 used are described in DE-OS 26 43 987.

As one can see from FIG. 3, different parts of the control are identical to parts of the control according to F i g. 2. Identical switching elements from FIG. 3 and F i g. 2 have been given the same reference numerals.

The gate control of FIG. 3 corresponds identically to the gate control according to FIG. 2, why regarding the gate control according to FIG. 3 to the corresponding Rr-srhrpihiing from F i g. 2 is referenced.

F i g. 3 differs from FIG. 2 in that, in the case of FIG. 3, the memory cells 101, 201, 301, 401 each have a charge-reversal area electrically isolated from the source, indicated by 117, 217, 317, 417 , which are bit by bit by means of the charge-reversal line 119 or 219, analogously as in FIG. 2 can be switched between a low voltage of approximately 0 V and a high voltage of approximately 25 V to 40 V by means of the transistors 121, 122 or 221, 222. The sources 118, 218, 318, 418, which are electrically isolated from this charge transfer region, are, however, each grounded. The drains of the memory cells according to FIG. 3 are analogous to the drains of the memory cells according to FIG. 2 connected by means of a bit-wise drain line 140 or 240 , respectively. The function of the flip-flop 129 or 299 and the connected NAND element 125 or 225 from FIG. 2 is shown in FIG. 3 taken over by the memory cells 101, 301, in connection with the transistors 112, 113 and the inverter 114 or by the memory cells 201, 401 in connection with the transistors 212, 213 and the inverter 214 , which each together represent a flip-flop. As in Fig. 2, the control according to the invention ensures that the erase voltage of each individual memory cell is switched off when a cell to be erased has fallen below a certain predetermined threshold voltage. The decrease a voltage Ud at 131 and + Uon ί increased at 231 via the inverter 1 14 and 214, the gate voltages on transistors 112 and 212. Since the transistors 113 and 213, respectively τ turned on during the entire erase operation due to concerns of signal the voltages are further reduced to 131 and 231 when the transistor 112 and 212 are switched on. After falling below a threshold value

from Ui) _n or Uonti , the circuit toggles into ■ -'ine by itself; .ibile end position with Ud " or LO _{n +} I near OV. As a result of the toggle process, the transistors J21 and 221 are switched on at the same time and the respective erase voltages at the recharging areas 117, 217 and 317, 417 are thereby reduced to small values. A reset also takes place in FIG. 3 only after the erasure has been completed by blocking the transistors 113 or 213 because r = 0. To switch off the entire erase time of the memory, the drain voltage of each selected cell can e.g. B. the drain voltage LO _{n of} the selected cell in the nth bit through an output 141 on the drain line 140 via an inverter (not shown) to an AND gate (not shown) /? be guided. The same applies to the drain voltage (Λ> _η + ι at the π + 1-th memory bit with respect to the output 241 and the drain line 240 Value of approximately 0 V drops, each erased cell puts a "0" on an inverter attached to output 141 and thus a "1" on an input of an AND gate connected to the inverter ß. After the erased state of the slowest cell is selected Word, all inputs of AND gate β have a “1” so that the output issues an “I.” This end signal can be used directly to switch off the erase time r of the memory.

With a control according to FIG. 3 and single transistor memory cells, as they are provided according to Figure 3, a memory similar to that shown in FIG. 2 impulsively to be deleted. As can be seen from the drawing, a control according to FIG. 3 a saving in components in comparison to a control according to FIG. 2, moreover, faster readout is possible.

With a control according to FIG. 3, it is also possible not to erase a memory in pulses, but to erase by means of a time-constant erasing voltage with simultaneous control reading. Included but it must be taken into account that the memory cells not selected, whose gate voltages during the Erasure on a high compensation voltage, are well conductive and therefore the control reading process would disturb. In this case, either an additional selection transistor, i.e. a two-transistor memory cell, required or the memory only consists of a single value.

Memory according to the invention with a control according to FIG. 2 or F i g. 3 can be used for tuning memory or number memory, e.g. B. in telephone exchanges, use.

For this purpose 3 sheets of drawings

Claims (8)

Patent claims: 1. Non-volatile memory that can be electrically erased word by word and is arranged in a matrix Storage cells, characterized in that such a control is carried out with the storage matrix is interconnected so that each memory cell of a memory line has an individual erase duration possesses, the end of which by reaching a predetermined erased state of the memory cell is determined. 2. Memory according to claim 1, characterized in that that to achieve a variable erase duration of a memory cell and for control of the erased state of the memory cell, the erase voltage applied to the memory cell into a temporal sequence of individual pulses is divided so that a control reading process in each of the pulse pauses is switched on. 3. Memory according to one of claims 1 or 2, characterized in that the erase period of a memory cell is ended when the memory cell has a threshold voltage Vt ("0") during a control reading process, the relation | VY ("0") | less than or equal to \ Ugl \ if Ugl means a predetermined threshold value of the memory cell used 4. Memory according to claim 1, characterized in that the variable erase duration is achieved by means of a temporally continuous erase voltage and by means of simultaneous control reading, the erase duration t_ <ier memory cell being ended when it exceeds a threshold voltage · όπ VY ("0") less than or equal to Ugl, but greater than 0 5. Memory according to at least ei ^ m of claims 2 or 3, characterized in that during the erasing period and within a control reading process at a gate voltage Ugl, the erased state by the decrease in the absolute value of the drain voltage I LO | is shown. 6. Memory according to at least one of claims 1 to 5, characterized in that those Drain output signals, which indicate the end of an erase period of a memory cell, for switching off the erase voltage applied to this cell can be used. 7. Memory according to at least one of claims 1 to 6, characterized in that the gate lines the field effect transistors used to build memory cells word by word and the drain lines are managed bit by bit. 8. Memory according to at least one of claims I to 7, characterized in that a control circuit is interconnected with the memory matrix. that the gate voltage, which is required as a predetermined threshold voltage value (Ugl) for control reading when erasing, as well as the gate voltage for reading out the memory (Ugr) are taken from one and the same voltage divider, so that always ('(, / less than ( /(,"is applicable.