DE2748453A1 - Recording and reproducing appts. for video signals - has twin consoles with vertical stack of flat magnetic record discs which register digital data and control time sequences - Google Patents

Abstract

The recording and reproduction appts. is esp. for video information on magnetic media. It includes a number of circular discs (75) with a number of plane disc surfaces upon which a number of digital signal components are simultaneously recorded. The time basis is controlled by means of a number of series arranged data storage cells with a data input and data output such as ante and read pulse terminals. The digital pulses are recorded at various levels. Phase differences are used to split the chrominance auxiliary carrier signals and synchronise them with the horizontal time base. The circuits also include a number of digital filters.

Description

Recording and reproducing device

The present invention relates to a recording and reproducing apparatus, and in particular such an apparatus for recording and reproducing television signals in digital form.

The ongoing technological advances have led to various changes in devices that are used in television broadcasting stations. One One of the more significant changes is seen in the fact that photographic techniques are in favor from magnetic media in many locations on commercial television broadcasting stations were abandoned.

For example, movies that are broadcast often no longer come from you Film strip but from a magnetic tape. News departments also go from Television broadcasting stations predominantly related to video tape recording systems above; More and more, film cameras are used to visually display new news pushed back. In addition, mobile transmission stations are often used, which send information either directly from their location or to a Station, from which the information is either sent live or on recorded on videotape, edited and broadcast at a later date can be. One of the many advantages of such a procedure is that it is simple Handling, flexibility and processing speed compared to to see a photographic film. These advantages are coupled with the possibility of to be able to use the magnetic tape again if the information recorded on it is no longer needed.

One of the last remaining domains of film in today's commercial TV broadcasting stations is the image projection using film transparencies with 35 mm. This image pro Jection is used to gain standing Television images, which are used, for example, for program information, advertising and news be used. In general, the aforementioned option is used wherever where a stationary image is necessary in operation. The effort for such image projections can be seen from the fact that a medium-sized commercial television broadcasting station a total inventory of around 2000 to 5000 slides 35 mm leads. The maintenance of such a total stock requires one a lot of work, the introduction of new slides, the sorting out worse Slides and the constant keeping of an exact list compilation makes it necessary to make slides easily accessible when needed are. If program sequences are to be compiled from such slides, so the individual slides must be carried by hand to the projection device, cleaned and can be used manually. Just during the cleaning process, for example Dust particles and scratches unsatisfactory even with careful handling Produce results. In addition, the slides must be after their use removed for broadcasting purposes and returned to their storage location. The whole Process of compilation, use for broadcast purposes and return the slide requires one because of the manual activities involved great amount of work. The projection process is common in many modern broadcasting stations to a large extent out of date and with a fully automatic station operation in principle incompatible.

The present invention is therefore based on the object of an improved, Specify a recording and playback device that is particularly suitable for television signals, that in particular - but not exclusively - for recording and playing back still images.

In particular, such a device should have computer-controlled disk drive units work, these disk drive units without affecting their very reliable operation for recording and playback of television signals can be modified are.

In addition, with such a disk drive units working device the various significant bits of sample values of a digitized TV signals recorded simultaneously on separate surfaces of a stack of discs can be.

Generally speaking, the device according to the invention makes the opposite on projection equipment or the use of opaque graphic material recording and playback as a source for generating still video images of still images possible, with the video information in the form of still images Images are stored on magnetic media. In the device according to the invention generally computer-controlled standard disk drive units (which are, however, in certain Aspects are modified) used with magnetic storage media, reducing the Problems associated with the projection of slides can be avoided. Since the Still images are recorded on magnetic media, problems of the mechanical impairment, for example from dust particles or scratches not on. Since the recorded information is still easily accessible, the same still image by operators in different places is practical can be used at the same time.

Although a preferred embodiment relates to the invention First the recording and playback of still images; however, the device can designed so that a sequence of images is also recorded and reproduced can be, with an image movement with both changed and unchanged Time base effects is realizable. The device facilitates due to various Design features the use of digital recording and playback techniques of television signals, with available standard computer controlled disk drive units can be used as a magnetic storage device.

Reliable recovery of the digitized television signal When playing back from the magnetic medium, this ensures that time shift errors, which the digitized television signal suffers during recording and playback, can be eliminated. According to a particular feature of the invention, the device has a time base correction circuit with a multi-digit register represented by a data-related clock signal and a stable reference clock signal is clocked so that the data after passing through this register at a fixed repetition rate are present. A subsequent read-write memory takes the data with a fixed repetition frequency and sets its timing with respect to a stable reference timing signal so means that all time base errors found in the data are compensated.

According to a further feature of the invention, this is processed here in The recording and reproducing device in question is a composite video information signal for recording on disk stacks of computer-controlled disk drive units, the horizontal sync signals during the Processing off separated from the signal, after which the analog video information signal is keyed and the sample values are converted into a number of digital data sequences. In connection with this feature of the invention, the device preferably adds in each second television line at the point of the previously separated horizontal sync pulse a unique digital sync word. This synchro word serves as a reference for correcting time base and skew errors, which are found in the multitude of Data bits can occur in the data sequences which are used to obtain the amount each duty cycle must be combined. Since the sync word inserted in the data sequence is a multi-bit word, the bits defining this sync word may possibly appear arbitrarily in the active part of the television line. This is why it is for this ensured that the horizontal blanking interval apart from the presence of the unique Synchronization word does not contain any information content in the data sequences. on in this way the circuit for the reproduced part of the signal can be used as Reliably and precisely determine the synchronization word used in relation to the time base. The entire information content of the data sequences is also used in the device according to the invention eliminated during approximately the first half of the vertical blanking interval so that in every other line approximately in the first 10 to 20 lines of the vertical blanking interval only the synchronization word is available. Should the circuit come from any Basically cause a misorientation, it is due to the aforementioned measure there is sufficient time to determine the synchronization word. That Device puts the sync word in the right place during alternate Lines in the horizontal blanking interval without the generally continuously running Data sequences are interrupted. No active video information is lost, there the synchronization word is inserted during the horizontal blanking interval.

According to a further feature of the invention, the device samples the video information signal with a sampling frequency which is equal to a multiple of the subcarrier frequency, so that a number of samples are obtained during each period of the subcarrier will. According to a particular embodiment of the invention, the keys through Key clock signal controlled device the video information signal with a frequency, which is equal to three times the subcarrier frequency, so that for each period of the Subcarrier, i.e. three sample values can be obtained for phases of 00, 1200 and 2400. As the phase of the samples with respect to the subcarrier for a color video information signal determines the color value of the video signal during playback, the keying of the information signal performs in other than the correct phase positions ultimately result in poorer color rendering. The device ensures that the sample values are exactly in the desired phase positions can be obtained so that the color will be accurately preserved in a subsequent reproduction remain. In order to achieve keying in a narrow range of the preferred key positions, i.e. within of about 200 of the desired key positions of 00, 1200 and 2400 can be achieved in the preferred embodiment of the device according to the invention a phase-locked one Loop provided. The actual sample values are then examined to determine whether there is actually a phase error. The tactile cycle is then set so that that the sample values are obtained precisely in the phase positions 00, 1200 and 2400. In order to errors are corrected in the effect, for example due to temperature drift effects can arise.

According to a further feature of the invention, a complete NTSC video information sequence with four fields taking advantage reproduced only a recorded information image with two fields. In this context, the device has a comb filter circuit for separating and Processing of the chrominance information provided to the chrominance information to invert the two fields of the recorded information when reproducing.

As the analog color video information signal with an odd multiple the chrominance subcarrier frequency is sampled, it is when using the comb filter circuit expedient to clock the video information with a tactile clock whose phase in each consecutive line is changed. This technique is hereinafter referred to as PAL clocking designated. The device also contains a circuit which ensures that the sample values in the correct phase positions relative to each period of the subcarrier frequency be won. A precision circuit with a phase-locked loop is provided, which makes it necessary that the phase of the burst signal of the chrominance subcarrier, that occurs in the horizontal blanking interval, in terms of phase in successive ones Lines is not changed. Generated according to a particular feature of the invention the device a control signal that both the phase change of the tactile clock and other parts. of the device so that generally only the active part of the Video line is changed in phase in successive lines and that the Color sync signal of the periods of the chrominance subcarrier occurring in the horizontal blanking interval is not affected.

According to a further feature of the invention, the composite Color video information signal fed to the recording and reproducing device will. subjected to a number of processing steps, initially being the amplification of the signal, an expression of its equation voltage level, a determination of the peak value of the horizontal sync pulse and its limitation, a separation of the horizontal sync pulse to generate a regenerated one Synchronous signal and the generation of a regenerated subcarrier signal, preferably from the color sync signal of the chrominance subcarrier present in the signal is derived. According to this feature of the invention, regression occurs in the device of the DC voltage level of the analog video signal, with an error signal for an amplifier through which the video signal passes. This error signal is generated by the DC voltage level of the composite video signal while the chrominance subcarrier burst is present, which occurs in the horizontal blanking intervals is investigated.

The DC voltage level of the signal is measured by an integration, where the integration over an exact integer number of periods of the subcarrier is carried out.

This eliminates the need for low-pass filtering of the video signal, to separate the burst signal before performing a clamping operation.

According to a further feature of the invention are in the present Device recorded still video images on disk stacks of disk drive units, wherein utilizing a continuous NTSC color sequence signal comprising four fields only two fields of the recorded information is reproduced. During the recording process, the analog video information signal is with keyed at a keying frequency which is equal to three times the subcarrier frequency, whereby the sample values are converted into a large number of digital data sequences, which are then processed and recorded.

The horizontal sync pulses of the analog video information signal are separated, with a new line in alternating lines in the horizontal interval defined digital synchronous word is inserted. The synchronized words are with synchronized with three times the subcarrier frequency.

During playback, the sync word is during the second playback process of the recorded two fields, which are used for the recovery of an NTSC sequence is required, due to the reversal in the phase of the subcarrier (and necessarily of the triple subcarrier signal) of the third field relative to the first field the full sequence with four fields by half a period of the triple subcarrier signal misplaced. This is due to the incorrect positioning of the horizontal sync word in alternating images by half a period of the triple subcarrier to one visual flickering or a horizontal movement of the displayed image, According to a special feature of the device according to the invention, the identification the second reproduction of the two fields possible, with the incorrect positioning can be adjusted by half a period so that the flicker is eliminated.

According to a particular feature of the invention, recording occurs and reproducing video information signals on b7w. of stacks of discs from computer-controlled Disk drive units in the recording and reproducing apparatus in question a digital technology to use. During the recording process, the Horizontal sync pulses separated from the analog information signal as the NTSC television signal no specifically defined relationship between what appears in each line Horizontal -Sync pulse and the phase of the chrominance subcarrier signal having. At an early stage of the recording process, the horizontal sync pulses separated from the signal, after which the signal is sampled at a frequency which is preferably equal to a multiple of the subcarrier frequency. In particular takes place the keying with three times the subcarrier frequency. The sample values are in a multitude of digital data sequences transferred to magnetic media to be recorded. Before the recording, however, there is a newly defined horizontal sync signal in the form of a digital synchronous word with several bits in alternating lines of the data sequences inserted so that the synchronization words with the subcarrier (and also with the triple subcarrier key signal) are phase locked. This means that the synchronization word is relative to the subcarrier (and threefold Subcarrier signal) kept in a constant phase relationship.

In this way, the newly defined horizontal sync signal, i.e. the digital sync word especially for the playback of the recorded Digital information can be used as a basic reference signal for the system.

According to a further feature of the invention, the disk drive units feature preferably one field of the video information during each revolution of the stack of discs on a sour of the stack of slices. Two fields of information can be used with successive revolutions of the disk stack are recorded, i.e. one field is on a set of surfaces of the disk stack and the other Field then recorded on a second set of faces of the disk stack. By synchronizing the speed of the disk stack with the vertical synchronization of the video signal can display each field during one full revolution of the stack of discs to be recorded, it is only necessary between one set of reversing heads recording a field to another set to switch to recording the second half-frame. During a consecutive Recording or playback of the two fields is therefore not a new setting of heads required. Because each stack typically has 815 different radial locations has, which are referred to as tracks in the following, can be applied to any stack of discs 815 separate still images can be recorded.

Since the video information is a permanent collection of still images for example in a commercial television broadcasting station, it is important to that the information is not easily destructible or by a wrong one Operation of the transducer heads can be lost. According to another feature of the invention the information recorded on the stacks of discs is protected by ensuring is that the transducer heads operated as a function of command signals controlling them will. Since one transducer head does everything at the same time during a recording operation deletes what was previously on a track, the operation of the transducer heads monitored by determining the value of the recording current. Lead the transducer heads a recording is made, a recording tron of high level is to be detected will. On the other hand, if the transducer heads are not to carry out a drawing process, so no current should be detectable. By comparing these operating conditions With the command signals controlling the tanning, the disk drive units for be switched off in the event that the actual operating conditions do not match coincide with the command signals. It should be noted here that either at the beginning or at the end of recording operations performed by the transducer heads necessarily jumps appear. For this reason is with the The device in question here provided a predetermined waiting time so that the electricity can assume its new value before the determined operating state with the Command signals is compared to determine a malfunction.

According to a further feature of the invention, the video information for stationary images in parallel on a large number of surfaces of the stack of discs of the disk drive unit is recorded with an image of the video information in recorded in a separate radial point or track on the stack of discs will. In the case of standard stacks of disks, there are a total of around 815 tracks which information can be recorded. According to an embodiment of the Invention, each still picture is recorded on a track by having a Field during one revolution of the disk stack on a set of surfaces is recorded while the second field is in the same radial location another set of surfaces is recorded. As the recorded in the tracks standing images are a permanent part of a commercial television broadcasting station can form, it is useful that the information against false or unauthorized Deletion or overwriting is protected by operators, which different operate the input devices that control the recording and playback device. on the other hand it is desirable to have other operations such as assembling of sequences of still images for broadcast purposes is possible without restrictions.

For this reason, certain tracks are created in the device according to the invention defined as fixed tracks and other tracks as working tracks, whereby certain operations cannot be carried out with regard to this classification of the tracks are. In one embodiment of the invention, the majority of the 815 are tracks defined as fixed tracks, so that only a total of 64 tracks are working tracks be available. These traces of work can be used without any significant restriction can be used to record and reproduce still images.

With regard to the fixed tracks, deletion is used in the device according to the invention or dubbing when you are absent. a control signal prevented by a key-lockable switch or another safety switch is produced. This means that only certain authorized persons can operate the switch, to delete or

To perform dubbing of the information recorded in the fixed tracks. On the working tracks is a compilation of a sequence of still images possible for program displays, for example, in the absence of the control signal a destruction of the information is prevented (in one operating mode of the device is an erasure of the entire sequence as a function of a single set of instructions possible).

According to a further feature of the invention can be described in Apparatus various embodiments of a digital chrominance separation and processing system can be used by adding predetermined degrees of desaturation in the color images to those Color edges can be generated in the image where a comb filter is not complete Can perform separation of the luminance and chrominance signals.

Therefore, a digital comb filter forms together with a digital one Bandpass filter a way of separating the chrominance and luminance signals, furthermore a broadband delayed by one horizontal line (1 H) Television signal arises. It is a circuit for performing a digital inversion of the chrominance signal is provided, whereby the separated chrominance signal is so processed can be that at those color edges of the image where the comb filter a Do not perform a complete separation of the luminance and chrominance signals can, a predetermined degree of desaturation during alternately repeated reproductions with field or frame rate is guaranteed. To the inverter circuit is a digital recombining circuit that records the luminance signal or the broadband signal coupled to digitally reconstruct the repeated reproductions.

According to one embodiment of the invention, the aforementioned includes Inverter circuit a digital transversal filter with odd symmetry, which the Selectively rotates the phase of the chrominance component with respect to the luminance component, around in both color images on those color edges where one is incomplete Separation occurs, a compromise in the degree of desaturation of the chrominance component to ensure.

According to a further embodiment, the digital inversion process applied to the separated chrominance component which is then used to form the composite color television signal with the delayed by one horizontal line2n Broadband signal is digitally recombined.

According to another feature of the invention, includes a frequency equalizer a differentiation circuit and an integration circuit which have a through a reproduced signal to a playback head. The differentiation circuit provides a differentiated signal that is in phase with respect to that reproduced Signal advanced by 900 while the integration circuit is an integrated signal delivers, that in phase with respect to the reproduced signal lags behind by 900. A circuit forming a difference generates from the differentiated and a difference signal from the integrated signal. This resulting difference signal is for all reproduced signal frequencies with respect to the reproduced signal in equalized in amplitude and phase.

In one embodiment of the frequency equalizer, a signal of the combination of a playback head and a preamplifier as one input signal fed into a parallel connection of an integration and a differentiation stage. The integration stage provides an output signal that is related to the input signal lags by 900 in phase, while the differentiation stage has an output signal which leads in phase with respect to the input signal by 90 °. By a subtraction stage forms a difference between the corresponding susgang signals. The signal at the output of the subtraction stage is a function of the special polarities the corresponding output signals from which the differential signal is obtained, either in phase with or related to the originally recorded signal inverted in phase to this signal.

Since magnetic playback heads in a known manner the property own the reproduced signal as a time derivative of the recorded To deliver flux, has the output voltage of the playback head and the associated Preamplifier with respect to the phase of that recorded on the recording medium magnetic flux a phase lead of 900. The equalizer by the frequency The signal supplied therefore has a constant phase shift from Oo or 1800, i.e. it is al Function of the direction of the phase shift of 900 caused by the equalizer either in phase or inverted. The overall phase characteristic of the resulting The equalized frequency channel therefore has the in the entire frequency range of the channel required phase linearity.

The frequency equalizer ensures simultaneously with the phase equalization also an amplitude equalization of the transmitted through the recording / playback channel Signal. It is known per se that the amplitude characteristic of a recording head has a rise of 6 dB per octave, which is due to various signal losses (explained with reference to Fig. 4 of the drawing) both on the low frequency and at the high-frequency end of the amplitude characteristic decreases. The one provided here Equalizer compensates for the aforementioned non-constant amplitude characteristic as well the losses due to the realization of a complementary frequency characteristic in the following Senses. The integration level of the equalizer ensures an increase in the low frequency End with an amount of 6 dB per octsve, while the differentiation stage is a Increase at the high frequency end causes the same amount. By linear subtraction the amplitude characteristic of one of the stages results from that of the other stage a resulting characteristic (see Fig. 5 of the drawing), which at Combination with the characteristics of the playback head (see Fig. 4 of the drawing) to a resulting straight overall amplitude characteristic in the entire frequency range of the canal.

The invention is explained below with reference to in the figures of the drawing illustrated embodiments in more detail explained. It shows: Fig. 1 is a perspective view of a device according to the invention with its own device Input device and two disk drive units that make up the overall appearance of the device is visible; 2 is an enlarged perspective view of a representative remote input device that is controlled by an operator the functions of the device according to the invention can be used; Fig. 3 is an enlarged Top view of the keyboard field of the device's own input device according to FIG. 1, from which in particular the various keys and which can be actuated by an operator Buttons are visible; dough. 4 shows a simplified block diagram for explanation the general functions of the entire device according to the invention; Figure 5A shows a Part of a typical television signal to explain its vertical interval; 5B shows part of a color television signal, from which in particular the horizontal sync pulse and the burst signal can be seen; 6 is an explanatory block diagram the basic mode of operation of the signal flow path through the device during a Recording operation; Fig. 7 is a block diagram for the basic Explaining the signal flow path through the device during a playback operation; Fig. 8 is a block diagram of an internal computer control system by which the operation the signal system, the disk drive units with the associated control system and the input devices to be operated by operators can be regulated; Figure 9A and FIG. 9B is a block diagram of the signaling system for the apparatus of the present invention including the regular connections between the various blocks; Figure 9C is a timing diagram to explain the keying of a television signal and the phase relationships different points of the signaling system; Figure 10 is a block diagram of a video input circuit (similar to a reference signal input circuit) which is part of the signal system according to Figure 9A; 11A is a block diagram of a reference logic circuit; which forms part of the signal system of Figure 9A; Figure 11B is a timing diagram for a PAL error code generator in the reference logic circuit according to FIG. 11A; 12A is a circuit diagram of a reference clock generator which is part of the Signal system according to Figure 9A forms; Figure 12B is a timing diagram to explain the mode of operation of parts of the reference clock generator according to FIG. 12A; Fig. 12C is a timing diagram for explaining the operation of parts the reference clock generator according to FIG. 12A; Figures 13A, 13B, 13C and 13D collectively a circuit diagram of a coding switch, which is part of the signal system according to Figure 9A forms; Fig. 13E is a block diagram of a blink cross clear signal generator in the coding switch according to FIGS. 13A to 13D; 13F shows a representation of the for two television fields generated during playback blinking cross cancellation signal; Fig. 14 a block diagram of a coding and sync word insertion circuit, which a Forms part of the signaling system of Figure 9A; 15A is a block diagram of a data and time base correction circuit which is part of the signal system of Fig. 9A forms; Figures 15B and 15C each show a timing diagram for the data and time base correction circuit according to FIG. 15A; 16 is a block diagram of a data transfer circuit which forms part of the signaling system of Figure 9A; Fig. 17 a A block diagram of one embodiment of a chroma separation and processing circuit in the signal system of FIG. 9A, in which the chroma converter part is replaced by a digital Transversal filter with odd symmetry is formed; Fig. 18 is a more detailed one Block diagram of the chroma inverter part shown in FIG. 17 as a block diagram Circuit; 19 and 20 each show a block diagram of a further embodiment the chroma separation and processing circuitry of the signal system of Fig. 9A; Fig. 21 Figure 3 is a block diagram of another embodiment of a regression circuit from four fields of color television signals from a single stored field; Fig. 22 is a block diagram of a video playback output circuit which has a Forms part of the signaling system of Figure 9A; 23 shows a block diagram of a digital-to-analog converter and Color synchronous and synchronous signal insertion circuit, which is a part of the signal system according to Figure 9A; Fig. 24 is a block diagram of a reproducing circuit which the equalization circuit includes the signal system; Fig. 25 is a block diagram of a Embodiment of the equalization circuit according to FIG. 24; Fig. 26 a Block diagram of a further embodiment of the equalization circuit according to FIG. 24; Fig. 27 is a reproduction characteristic diagram of a conventional combination from playback head and preamplifier; 28 is a diagram of an equalizer curve the equalization circuit according to FIG. 24 for compensating the curve according to FIG. 27; Fig. Figure 29 is a block diagram of a central processor interface circuit of the computer control system in the device; Figure 30 is a block diagram of an interface circuit for remote input devices the computer control system of the device; Fig. 31 is a block diagram of a remote input device and a device-internal input device of the computer control system of the device; Fig. 32A and 32B are collectively a circuit diagram of the signal system interface circuit of FIG Computer control system of the device; 33A and 33B are each a block diagram of one first data track interface circuit of the computer control system of the device; Fig. 34A to 34H as a whole show a circuit diagram of a second data track interface circuit the computer control system of the device; Figs. 35A and 35B are a circuit diagram an interface circuit for disk drive units of the computer control system of the device; 36 is a block diagram of a phase servo control circuit for disk drive units of the device; 37A and 37B are a circuit diagram of the recording-reproduction control circuit for disk drive units of the device; Figs. 38A and 38B are a circuit diagram of a Recording timing circuit for disk drive units of the apparatus; Fig. 39 is a circuit diagram of a timing generator for disk drive units of the apparatus; 40A and 40B are a circuit diagram of an error checking circuit for disk drive units of the device; 41A and 41B are a circuit diagram of the phase locked loop of the circuit according to the block diagram of FIG. 36; 42A to 42D are a circuit diagram of the inputs circuit of the signal system according to the block diagram of FIG. 10; Figures 43A through 43D is a circuit diagram of the reference logic circuit of the signal system according to the block diagram according to Fig. 11; 44A to 44D are a circuit diagram of the reference clock generator of the signal system according to the block diagram of FIG. 12A; 45A to 45D a circuit diagram of the coding and synchronous word insertion circuit of the signal system according to the block diagram after Fig. 14; Fig. 45E is a timing chart for explaining the operation of the data encoding circuit 45A to 45D; 46A to 46D are a circuit diagram of the data decoder as a whole and the data and time base correction circuit of the signal system according to the block diagram according to Fig. 15; 46E shows a timing diagram to explain the mode of operation of the The circuit of Figures 46A and 46B; 47A and 47B are a circuit diagram of FIG Data transfer circuit of the signal system according to the block diagram of FIG. 16; Fig. 48A to 48C as a whole a block diagram of the chroma separating sub-circuit of the chroma part the signal system according to FIG. 17; Figures 49A and 49B are collectively a circuit diagram of the chroma inverter circuit for the embodiment of the chroma part according to the block diagram of Fig. 18 as well as the timing control provided for this; 49C is a block diagram of the Timing control part of the chroma inverter circuit of the signal system according to FIG. 48A to 48D; 49D is a timing chart for explaining the operation of timing control of the chroma inverter ge-118 Fig. 49C; Figures 49E and 49F as a whole a circuit diagram of the chroma inverter circuit for the chroma part according to the embodiment according to the block diagram of FIG. 20 and the timing control provided for this; 50A and 50B are a total circuit diagram of the chroma band pass filter circuit of the Chrome part of the signal system according to the block diagram of FIG. 17; Figures 51A and 51B together a circuit diagram of the video playback output circuit of the signal system according to the block diagram of FIG. 22; FIGS. 52A to 52D are a circuit diagram of FIG Digital-to-analog converter and color synchronous and synchronous insertion circuit of the signal system according to the block diagram of FIG. 23; 53A and 53B are a circuit diagram of FIG Equalizer circuit of the signal system according to the block diagram of FIG. 24; Figure 54A and FIG. 54B as a whole is a circuit diagram of the preamplifier in the reproduction circuit according to FIG Block diagram according to FIG. 24; Figs. 55A to 55D are a circuit diagram of the interface circuit as a whole for remote input devices of the computer control system according to the block diagram of Fig. 30; 56A through 56D are collectively a circuit diagram of the keypad circuit for remote input devices and the device's own input device of the computer control system according to the block diagram according to Fig. 31; Figs. 57A and 57B are collectively a circuit diagram of the first Data track interface circuit of the computer control system according to the block diagram according to Fig. 33; 58A through 58D are a collective diagram of the central processor interface circuit the computer control system of the device; 59A and 59B show a circuit diagram as a whole the driver part of the circuit according to the block diagram of FIG. 36; Figs. 60A and 60B is a circuit diagram of the data interface circuit of the device; Fig. 61 is a plan view an input allocation control keypad with various operator inputs actuatable buttons and buttons; 62A to 62C are a circuit diagram as a whole for the input and allocation control keypad according to FIG. 61; and Figs. 63A through 63 63VV Flow charts for a control program of the computer control system from which the Successive program steps necessary for the functional operations in the device can be seen.

Generally, a recording and reproducing device 70 according to the Fig. 1 to 3 two frames 71 and 72, which the associated electrical cables as well as the display and .egel hardware included. The latter components are shown in particular in the upper part of the frame 72. The device still has a pair of disk drive units 73 disposed adjacent to the right frame 72 each disk drive unit 73 carrying a disk stack 75. Next to the two disc drive units shown specifically in Fig. 1 can the Device wcitere disk drive units can be allocated to its direct storage capacity to increase. On the other hand, only a single disk drive unit can also be used be used. However, as can be seen from the following explanations, however, not many useful functions with a single disk drive unit will be realized. Operators can control the operation of the device via multiple remote input devices, such as a remote ring output device 76 2 or via a device-specific input device 78 provided in the frame 72 will. In the frame 72, a video monitor 79 and a vector and an '.f' oscilloscope 80 may be provided. Above the device's own finger device 78 sinci phase control switch cl provided.

The device is operated by an operator either via the device's own Input device 78 or a remote input device 76 controlled, which each digit and function buttons and keys and a display field 82 for thirty-two characters exhibit. Ä.t this display field is the reading of information, which for Performing the functional operations in the company is necessary, as well as the- It is possible to display the information which determines the identity of the addressee standing pictures and other information. The one shown in FIG Remote input device 76 is representative of all remote input devices with up to seven remote input devices being provided for controlling device 70 can. The keyboard field of the device's own, generally designated 83 in FIG. 1 Input device is shown in Fig. 3 in an enlarged partial view. This The keyboard field is functionally more extensive than the test keyboard fields of the remote input devices, which have fewer function keys. As explained in more detail below is, the keypad contains a larger key matrix 84 as well as a smaller one Matrix of function keys 85 on the left side of the keypad. Farther a rotary knob operated switch 86 can be provided with which switching between normal and extinguishing mode is possible. With that there is a security against the possibility of incorrect or unauthorized deletion of actively used standing pictures possible.

According to the greatly simplified block diagram of FIG. 4, this takes place Device receives a video input signal which is passed through a recording signal processing circuit 88 processed and then fed to a recording signal branching circuit 89 which feeds the signal to all disk drive units 73. Fine in each of a specific disk drive unit 73 provided gate circuit is effectively switched to the signal on a given disk drive unit to record. For recording the output from the recording signal branching circuit 89 delivered Cignals can also be more than one disk drive unit 73 at the same time to be selected. Instead of the signal branching circuit and its associated Gate circuits can also be provided to switch the circuit from the recording signal branching circuit 89 only to a specific disk drive unit with disk stacks 75 on which the signal is recorded. During playback, a from one of the S-hot drive units into one Playback switch circuit 90 fed, which it on one of several playback channels 91 link, which each form a video output code. To control the overall operation the various components of the device is connected to the recording signal processing circuit, the recording signal branching circuit and the drive units as well as the Remote Lingabgerate and the device's own input device a computer level set (m 92 pounded. As will be explained in more detail below, an operator can select a specific target on which a picture is to be saved, provided that the S h.-ibcnstapel is connected, i.e. in other words, it is in one of the Disk drive units 73 inserted. In this context, it should be noted that that the device addresses disk stacks and not disk drive units. Of the The reason for this is that the device can identify up to 64 separate Disc stacking is used, of which only one is used in a disc drive unit at the same time can be introduced. If the device has two disk drive units, so can only two stacks of disks can be connected at the same time. The operator can use a keypad 83 of an input device, with the assistance of the Computer system to enter the address of a stack of discs on which an image is recorded is to be, the disk drive unit in which the selected stack is introduced, the ;; recording process on the selected connected disk stack can perform. In a corresponding manner, an operator can take a picture of the Play stacks of discs in a drive unit and define the playback channel, through which the image should run.

The device has four main operating modes, namely 1.Recording / erasing, 2. Play or playback, 3. Sequence composition and 4. Sequence reproduction. First, the recording and reproducing operations will be explained using 6 and 7, which are simplified block diagrams of the signal flow paths when recording or when playing back in cooperation with one of the disk drive units 73 show. According to the recording signal flow block diagram of Fig. 6, the composite video input signal fed to an input circuit 93, in dr this signal is clamped and the synchronous and auxiliary carrier components are separated will. The synchronous and auxiliary carrier signals are also used in the initial circuit recovered for later use during playback. The recovered synchronous and subcarrier signals are fed to a clock generator 94, which train signals generated to control the following components. The clamped analog video signal with the color synchronous component is fed into an analog-digital converter 95, which has an output signal with a sampling frequency of 10.7 x 106 samples per second generated, each sample comprising eight bits of information. The digital video signal is in an NRZ code, <I.h. it is a binary code, the short a Lins is defined as the high level and a llull is defined as the equivalent low level is. The digitized.

Videcosignal appears on eight parallel lines with a pit per line and is fed into a coding and synchronous word input circuit 96, which it translates into a special recording code. This code is shown below called the? iller code or nuadretian Miller code. This ode is suitable especially for a digital magnetic recording, because it contains the direct voltage content of a data stream is minimal. The circuit continues in every second TV line in relation to a specific phase angle of the color synchronous component represented color subcarrier a sync word. This S. The chronological word serves as a reference for the correction of time base and skew errors, which occur during playback in the eight parallel data bits that determine of the value represented by each keying must be combined. The digital Video information on the eight parallel lines is then fed into a record amplifier circuit 151 and fed to a head switch circuit 97 which is the selected pad drive unit 93 and between two groups of eight recording heads for recording of the digitized video signal by the disk drive unit. the Disk drive unit is servo-controlled so that its speed is based on the SertiRal synchronous signal is related, the disk speed is 3600 revolutions per minute. By The device records the definition of the shaft speed on the vertical synchronous signal one television field and eight data sequences at the same time per revolution of the stack of disks on eight disc surfaces. After the complete recording of a field the recording amplifier circuit 151 and the head switch circuit 97 become so controlled that another set of heads for simultaneous .. recording of the second half-bilcles is activated on a further set of eight segments, so that a full television picture through 16 pigtails with two revolutions of the disk drive unit can be recorded. Each disk stack on a disk drive unit preferably contains 815 cylinders each having 19 recording areas and therefore can store 815 digital television images.

For each of the 19 disk recording areas of a disk stack a chrc-ib read head is provided, with all heads aligned vertically on a common carrier are mounted, its position by a linear motor is regulated. It should be noted in this context that a cylinder is like this is defined as having all recording areas includes which are arranged on the same i? .adius of a stack of discs. Pn position of the term In the present context, however, the term track is preferably used as a cylinder used, which means that such a track covers all recording areas on the same radius, i.e. includes all surfaces of a cylinder. Hence relates The term was addressed by epur for the recording or reproduction of an image suf the 19 individual surfaces on the cylinder in this radius. from One of the 19 areas available for recording is used for recording address and other identification information and not for record of active video information. This area is specifically referred to as the date trail. Two of the 19 areas are available for recording a parity bit while 16 areas are available for recording video data. This fact is explained in more detail below. Likewise, one of the heads runs, which one is referred to as the servo head, on the twentieth disk stacking surface, which contains only servo track information prerecorded by the batch maker. The servo tracks are used to perform two functions. First, the head track is running following a search command by servo stages, which are used to determine the moment position of heads are counted. After completing a search phase, the servo head generates a Error signal that is used to regulate the position of the linear motor around the head carrier centered on the appropriate servo track. When using such a With the feedback system, it is possible to achieve a radial packing density of around 400 tracks per inch or a total of 815 tracks per stack of discs.

As the device in question because of the frequency limits of stacks of disks does not record analog video signals, the video signal is used for recording digitized. Since this digitized signal is recorded, ds is the signal-to-noise ratio of the system primarily through the quantization noise and not through ds the recording media and the preamplifier, as with conventional ones Video tape recorders. The device in [-ede guarantees a signal-to-noise ratio of about SC dB, with effects such as I-: oirC- and residual time base errors are absent, so the digital statistical Error in the memory channels is typically small enough to avoid possible transmission errors to make it virtually invisible.

By recording a digital data sequence with a follow-up frequency of 10.7 vegabits per second on each of the eight disc surfaces is the linear one The device's packing density roughly equals 6000 bits per inch, which is 60 "above the packing density in the case of conventional disk drive units lies in the data processing.

When reproducing, as shown in Fig. 7, the heads read the digital video information of eight areas per field, the recorded encoded digital video information is obtained per channel from the odd and even fields. The reproduced Signal is fed into a reproduction amplifier circuit 153 and the head switch circuit 97, which are assigned to the selected disk drive unit 73, are fed in, wherein the data sequences of the digital video information carried through the eight data bit lines and fed into an equalizer and data detector circuit 99. The equalization part of this circuit causes phase and amplitude distortions in the signal due to band limiting effects of the recording and playback processes compensated, ensuring that the Kull passages of the reproduced Signal are precisely defined. Kach's equalization will be the encoded signals on each data bit line of the channel to be described in the following Way for transmission to the playback circuit of the signal system via each a twisted pair is processed. The processed coded signals lie per channel in the form of a pulse for each zero crossing or for each change in the signal state of the coded channel signal. The twisted wire pairs for the eight data bits the processed coded channel signals carry the digital video information to a decoding and time base correction circuit 100 of one or more of the Playback channels 91 of the device.

The decoding and time base correction circuit 100 converts the received Signals back into channel code format, decodes the signal into NP.Z digital form and time-base corrects the digital signal with respect to a station reference signal to correct timing errors between the data bit lines (usually as Skew errors) and timing distortions in the through the data bit lines to eliminate guided data sequences. The time base correction part of the circuit 100 is used to correct the eight bits in the sense of a single keying as well relative to the elimination of time distortions in the individual data title lines to the station reference signal. It should be noted that each playback channel 91 has one Equalizer and data detector circuit 100 contains and that in each playback channel a sequence of eight data bits through a separate equalizer and data detector circuit runs. The output signal of the circuit 100 is then in a comb filter and Chroma inverter circuit 1C1 fed in, which separates the ear domain information and the signal for the reconstruction of a t; T <-renuence with four fields selectively inverted and recombined. This reconstructed digital signal is then converted into a Digital-Analog! 'Onverter' 102 fed in, which 'delivers an analog video signal. To the Generation of a composite analog video output signal of the playback channel 91 are then new by a processing amplifier 103 Synchronous and color synchronous signals added.

Description of the operation of the device when using single stations The general mode of operation of the device is now related to the operation by an operator via the keypad either of the device's own input device or a remote input device for performing the various by the device executable functions. The device can also use a Auxiliary input device 116 (see FIG. 8) can be operated, which according to FIG. 8 either via a remote input device 76 or a device's own input device 78 operates. As stated above, has the remote input device according to FIG. 2 as well as the device's own ring output device in the device frame 72 according to FIG. 1 in the left-hand part a matrix of function keys 85. This matrix 85 of the remote input device only has four function keys as opposed to nine keys on the device's own input device, so that through the gersite's own input device compared to a remote input device more functional operations can be performed.

The device's own input device has a total of nine function keys, one of which is a space bar while the other can be pressed to to bring the device into a certain operating state. It is about Among other things, a play button to play or play back a still picture, a record / delete button (REC / DEL) for a recording or a deletion, a key to assemble a sequence of images (SEQ AsSY), and a button for playing back a sequence of pictures (SEQ PLAY). These four Operations can be carried out by an operator via the device's own input device as well as the remote input device. In addition to these functional ones Operations can also use the device's own input device to perform the following additional operations be performed. A purely electronic operation (E-E operation) in which the video input signal through the entire recording system up to the disk drive processed and then given to the playback switch circuit, so that apart of the recording of the signal on the disk drive units with the video input signal all operations are performed (essentially a test operation). One Check operation for the identification data which is on the data tracks of a specific Disk drive unit are recorded (PACK IDE'T operation), one operation for feeding the identification data on all data tracks of a new stack, which part of a stack of slices is to be (PACK DEFINE operation), an operation to create an exact duplicate data stack that contains the entire contains digital video information stored on a special stack of discs (PACK DUPE operation). Define the above eight functional operations in a broad sense, the functionality of the device expressed in operating modes or Operating conditions.

The remote input devices 76 as well as the device's own input device 78 have furthermore a right-hand matrix of buttons 84, which for both Devices are identical. As shown in Fig. 3, the keyboard array includes 84 numeric keys O to 9 for entering addresses, Sequence dictionary data words and the like, "+ 1" and '§ keys to increase or decrease the input Addresses around 1, A, B and C keys for entering video channels or sequence directory letters, a key labeled LIST for specifying sequence index data words in a memory, a key labeled EOL for information to the computer system, that the last data word of a sequence directory is to be entered, one with KYBD Key labeled PTH (keypad return key) for changing the origin display information and a trigger button (IN'ITIATE) for generating trigger commands for completing the entry of data into the computer system. Farther there is a delete / spring / release key 104 (DEL / EDIT EITI; BLE) on the keypad 83 provided, which when operated together with the above-mentioned key switch 86 a deletion of individual images in large numbers of traces or entire Sequences in traces of work enabled. In this context, 64 tracks are the 815 tracks on each disk stack defined as working tracks (addresses 1 to 64), whereby sequences of images are combined on one of these tracks for reproduction are.

With the exception of two tracks, the remaining tracks define the permanent information stock. Certain precautions have been taken in the device to ensure that images are not deleted simply, or at least not erroneously or otherwise destroyed. The delete / edit trigger button can be used to Editing of information to be pressed in the work lanes. However, she must operated together with the key switch 86, so that images from the inventory or a whole sequence of images in the work tracks can be erased.

As shown in FIGS. 1 and 2, the display devices 76 and 78 have a display device 82 which is used to display of information origin codes, Data input by an operator as well as requests and responses from the computer system serves. The display device is a self-scanning display with an alpha-numeric Dot motrix and a display capacity of 32 characters. The computer system 92 is preferably programmed to display indicator words and symbols, which indicate a condition or claim or an incorrect or impermissible one Identify input or another error. As in the following in more detail is explained, requires a certain mode of operation to be performed by an operator is entered on the left-hand keyboard matrix of an ingat) e device, the Input of data in a specific loan order. If an operating mode is selected, so the display device guides the operator by means of a pointer symbol through the display sequence that the display device runs through until all elements the data information are entered. The input can be made at any time before the Press the release button, which triggers the workflow in the computer system 92, evaluate deleted and corrected. The computer system switches when the data is recorded 92 the display device to a response information (EPU), which either can be a data acknowledgment or a device status response. Is the data is confirmed, the selected operation or the selected operation is carried out is carried out.

Each operation identified in the left-hand matrix of keys 85 is carried out in three basic steps. First, the operator presses one Operating mode selection button, then gives the data in the form of channel selection information, Memory addresses and instructions and finally presses the trigger button, to request the operation to be performed.

The following are the different modes of operation in terms of interaction the display device and the keypad operated by the operator explained.

In playback mode, random access is available to each switched on Image, i.e. possible for every image that is present on a stack of slices, which is on a disc drive unit. An image is selected by that the video channel letter (A, B or C if three channels are provided) and a five-digit image address number can be entered. The computer system 92 does A requested image can be accessed when the shutter button is pressed and the 1 press is displayed on the display device. will be a non-approved or a picture address that is not connected is requested, this is done for the operating percon displayed by the computer system on the display device. If the address reading the image identification data differs from the entered address and that Computer system cannot resolve the discrepancy (real signal error), it will Video output signal black, with an error information on the display device is shown. If an adjacent image is to be addressed in a stack, then the next or previous picture by pressing either the "+1" - or the - 1 "test and subsequent pressing of the release button.

To compile a sequence directory, the operator gives direct or indirect five-digit addresses in the memory, which in two Sections of 64 data words each is divided. These two sections are referred to as LST A and LST B. Each directory comprises data word digits 1 to 64. To compile an address, the picture is first created by entering the Video channel letter and then selected by entering the five-digit image address. Then the LIST key will open the keypad and the first data word number as well as the directory identification - by the operator retrieved. When this information is entered in the keypad, the Release button pressed, transferring to memory. The display device switches to the feedback information (RTN) and shows the operator the carried out transfer. Then the next picture can be used for compilation to get voted.

The data word count (ITM) is set automatically by the computer control system increased by 1, so that subsequent compilations can be easily entered with the image address by pressing the LIST key and then the release key will. The EOL key must follow the last ITtI number of a compilation pressed before the release button. Shall look at a picture before putting it together the image address is entered and the release key in front of the LIST key pressed. The following listing of the picture is made in the sense described above. If the suspended image is an off-line image, it can be in the Directory can be saved but not viewed. From the stored in memory Directory, a sequence can be put together, which is explained in more detail below is described.

Recordings can be deleted in the record / delete mode Permanent information tracks carried out and added sequences as well as occupied Permanent information tracks are deleted. It is still possible in this Operating mode of transferring single images of collated sequences. Of the normal process of recording an image is such that the letter des Video channel over which the recorded video information is to be monitored, the two-digit address (1 to 64) for the batch in which the image was recorded should be, as well as three liullen entered in place of a track address because the image is to be recorded in the next available track.

When the shutter button is pressed, the computer system 92 searches for it automatically the next available deleted track in the addressed stack, followed by a signal authenticity test a recording is carried out. The search process is carried out in the state memory of the computer system so that it can be found a deleted track does not require stepping through the tracks is. After the recording, the feedback display device is displayed by the computer system Updated to report the five-digit address where the Image was recorded. If a recording process is not possible, this will be the case displayed by the operator. Used to make a recording on a next available Opur an off-line stack is brought into a drive unit, a search process for all tracks in batch identification mode is first required, to bring their state into the memory of the computer system. As long as the pile remains connected directly to the computer system (is on-line) is for subsequent Records on the next available tracks a repetition of the initial one Viewing process not required.

If an image is to be recorded on a certain track, it must the operator reads the video channel letter before pressing the trigger button and enter the five-digit address. Is a recorded one on the specific track If there is an image, the recording is not carried out, which is clear to the operator is indicated by a display that this track is occupied.

In order to delete an image, its five-digit address must be entered the deletion process by actuation of the key switch and then simultaneously pressing the delete / edit control key and the Trigger button is triggered. However, if the trigger key is before the delete / edit control key is pressed, the video information of the track can be viewed. After viewing the information can be deleted by pressing the delete / edit control key at the same time and the trigger button are triggered again. So a visual inspection is one Before it is deleted.

To all or part of a compiled sequence of images of the sequence to delete the last frame of that sequence, the ITM number of the first image to be deleted in the sequence is entered in place of the normal track address. The cooputerystem automatically recognizes that the entered number is a working track and no fixed information track is defined and triggers the deletion of the sequence. After actuating the key switch, the delete / redigLer control button and the trigger button pressed simultaneously to trigger the deletion. The deletion process is completed after the data word identified as EOL has been deleted.

Is supposed to be a quick edit for a fully compiled Sequence, so it is possible to put together in this operating mode To transfer images by adding a working track through their five-digit address addressed and at the same time the delete / edit control key and the release key be pressed. It should be noted that the dubbing option, as already mentioned only for the working tracks, but not possible for the fixed information tracks is.

To assemble a sequence of images, the SEQ ASSY button pressed. In this operating mode, a Sequence of data words automatically compiled in a defined batch in a sequence directory. To compose the sequence, the two-digit address of the relevant Stack and then the first ITM number in the sequence and the LIST letter entered. When the release button is pressed, the computer system automatically displays the on-line images on the working lanes of the addressed stack. Occurs during the compilation operation an off-line image, an off-line status display appears on the display device. When the on-line data word compilation is completed, everyone will Off-line batch containing directory data words on the display device identified. To add an Offllne-Blld to the compilation, a another compilation operation triggered if the previous offline image is on-line. It is necessary to put the sequence together as often as different ones Off-line batch addresses are included in the sequence directory. For each compilation operation the previously compiled images are not disturbed. In every stack of discs A working track is assigned to each data word number, which means that in each stack a maximum sequence length is guaranteed.

Since each data word is arranged in a sequence in a working track it is recorded with an occupied status indicator. This prevents that a data word of another sequence is inserted into the same working track.

In sequence playback mode (SEQ PLAY) there is access to the composite Images in the working track of a stack via the corresponding sequence data word numbers possible.

To play a sequence, the video channel letter must be the two-digit batch address and the original ITM number must be entered. Will the trigger button pressed so is an access to the one with this ITM number designated image possible. The feedback display (RTN) is then on brought up to date so that it has the address of the selected picture, the Contains video channel letters and ITM number. The keypad ITM number is also added automatically increased by 1, so that successive data words can be entered into a. Sequence directory are easily accessible in that the release key without entering new data is pressed. To skip the next data word in a directory, the +1 "button in the matrix on the right is pressed, which causes the keypad ITM number is increased by 2. Correspondingly, a decrease is made by pressing the n ~ 1 "button the number of data words by 1. If the last data word in a sequence is reproduced the end of the directory (EOL) is displayed. Will the trigger button is pressed after the last data word has been reproduced, the reproduction remains are at this data word. With an auxiliary input device, images saved in the working traces of stacks of discs of two disc drives are stored, can be made available for a sequence playback operation. With the one described here Device, the auxiliary input device only needs two buttons, namely a release button and having an auxiliary input device selection button. An input device is structured like this and works with the auxiliary input device in such a way that the function keys of the Input device can be used to enter the data pertaining to the operations, which are to be carried out by the auxiliary input device.

Are the conditions for a sequence playback operation for the The input device and the auxiliary input device are set, so are images of the stacking of slices on the disk drive controlled by the auxiliary input device by pressing the Release button of this auxiliary input device accessible while images of the stack of discs on the disk drive controlled by the input device by pressing the release button this Input device are accessible. The display in the auxiliary input device as well as the display on the display device 82 of the associated input device are mentioned above Updated senses to the operator about the condition of the sequence playback operation.

Purely electronic operation (E-E operation) is activated by pressing the E-E button in the left-hand matrix of the device's own input device. This means that there is a video display in one channel, bypassing the stack of panes possible regardless of the recording and playback process. The digital video input signal for a drive unit is then put directly into the video playback channel, In this mode it is possible to select individual video channels for the signal path. To perform this operation, the video channel letter and disk drive number are used entered and the release button pressed, the video information being purely electronic is available for review. Pressing the trigger button will do the System returned to playback mode, viewing disc video information can be. Purely electronic operation (E-E operation) is used to carry out Investigation and maintenance tests for the definition of operational characteristics useful.

To initiate the batch identification mode, the PACK IDENT key pressed. This operating mode is a way of reducing the on all data tracks of a stack of discs from the memory of the Computer system to read or to write in this memory. When choosing this Operating mode and input of the video channel letter and the disk drive number is after pressing the trigger button in each Track in the stack of discs an examination carried out. The number of errors found in this test Batch addresses is displayed.

The batch definition mode, which can be selected by pressing the PACK DEFINE key is triggered, facilitates the introduction of new batches into the database. One of the disk drive units, for example, disk drive unit No. 1 is set as the defining disk drive unit so that each stack on this disk drive unit automatically when this operating mode is triggered becomes a new pile. This operating mode is activated by entering the new two-digit Stack address, by actuating the key switch 86, and by following Simultaneous pressing of the delete / edit control key and the trigger key triggered.

The data tracks of the stack are included in the data drive unit new identification data, with an erasure indicator recorded on each track will. The completion of the definition operation is indicated by a ready information signaled by the display device.

In batch replication mode, which can be accessed by pressing the PACK DUPE button is triggered, can be an exact duplicate of the whole on a stack of discs recorded digital video information. In this company becomes one of the disk drive units, e.g. unit No. 1, as the source and another disk drive unit as a receiver for the duplicating operation Are defined. To start the batch replication operation, the operator gives Enter the two-digit stack address, operate the key switch 86 and press then the delete / edit control key and the release key at the same time. The device automatically transfers the content of the stack tracks of the source to the corresponding ones traces in the stack on the receiver disk drive unit. the Receiver batch number becomes the batch number which is relevant to the selection of the duplicator was entered as follows. The termination of the duplication process is through a ready information signaled on the display device.

It should be noted that the buttons in the left-hand matrix 85, which define the operating modes to be carried out, expediently as Illuminated keys are designed so that when they are actuated a visual display given is. For example, if the playback mode is activated by pressing the playback button is selected, this button lights up until the device is no longer in this Operating mode is operated.

Flow charts of the program for the computer system 92 to be carried out the functions described above based on the operation of the input devices shown in Figures 63A through 63VV.

ComauterreRel ßvstem The computer control system shown in block form in FIG. 4 92 is shown in greater detail in the block diagram of FIG.

This computer system 92 includes a central processing unit (CPU) 106 with associated program memory 107, which with various interface circuits work together to carry out the regulation for the various units of the device. Used to transfer both address and data information between the CPU 106, memory 107 and interface circuits is a single main bus 105 provided, with the transmission of the address and data information on this Bus 105 is time-multiplexed. To connect the CPU 106 of the Operators operated input devices to carry out the various Functions of the sowing device is an interruption abus formed by several lines 143 provided. When an input device requires the CPU 106, it initiates the transmission an interrupt command via an interface circuit 115 for a remote input device via a line of the bus 143 to the CPU. The CPU then interrupts its operation and operates the calling device. For connecting the device units, the interface circuits and the input device is for the transmission of control, timing and status information a control bus 144 formed by a plurality of control lines is also provided. Interpreted under the influence of the control program stored in memory 107 the CPU 106 issues a set of instructions as a result of actuation of an input device is received, and works the necessary programs and arithmetic functions so that the computer system 92 can perform the necessary functional operations, which should be executed by the device. The way in which the control program the instructions received for performing the various functional operations in the device through the CPU 106 executes is through the flowcharts indicated in accordance with FIGS. 63A to 63W. That described by these flow charts maintenance program can be processed with a CPU developed by Digital Equipment Corporation is manufactured.

The CPU 106 and the Memory 107 over the main bus 105 with a central processor interface circuit 108 coupled, which contains an address decoding unit 113. This address decoding unit 113 identifies that device unit which is either used to receive information is selected by the CPU 106 or for the transmission of information to the CPU 106.

For the CPU manufactured by Digital Equipment Corporation a 16-bit address is used to identify the selected device unit. the three most significant bits of the 16 bit address determine whether a peripheral device or one or more storage locations in memory 107 for connection to the CPU 106 should be selected. The next 13 bits of the address form the address word to identify the specific address location for the selected device unit. In the CPU manufactured by Digital Equipment Corporation, a byte-organized Address scheme used, where the least significant bit of the address word determines whether an odd or an even byte address was received.

The CPU 106 operates asynchronously with the others making up the device Units. However, the other units operate synchronously with respect to a system clock. The time coordination of the asynchronously operated CPU 106 and the other synchronously operated System units will be in address time during the address / data multiplex cycle on the main bus 104 by one supplied by the CPU 106 in the addressing time Bus synchronization signal carried out via one of the control lines 144 to the CPU interface circuit 108 is transmitted. The CPU interface circuit 108 generates as a function of the bus <: ynchronsignals the corresponding through the address word in the addressing time certain selection signal, whereby the selected device unit can communicate with the CPU 106.

In the case of the device in question, several peripheral devices are used Perform various functional operations. When the three most significant bits of the 16-bit address specify that a peripheral device is used Has been called in cooperation with the CPU 106, the address decoding unit decodes 113 under control by the CPU the 13-bit address word and specifies which of the 21 separate selection lines are to be activated in order to establish the connection between the CPU and the called peripheral device. Six of the selection lines serve to activate either a teletype interface circuit 109 for connecting to an external teleprinter 110, a paper tape reader 111 or a read only memory 112 to receive information from the CPU 106 or to transfer to this. The 15 separate selection lines shown in Fig. 8 running to the right in the form of a group of lines 114 are used for activation other peripheral devices to connect to the CPU 106. From the CPU 106 control signals sent out via the control lines 144 to called peripheral devices determine according to the functional operations to be performed by the device, whether the called peripheral device receives information from the CPU 106 or to this transmits. For the interface circuit 115 for the remote input device CPU interface circuit 108 generates a UART timing signal on one line 1121 when a connection with the CPU 106 is to be established.

With regard to the peripheral devices connected to the selection lines 114 the remote input device interface circuit 115 couples the remote input devices 76, an auxiliary input device 116 or the device's own input device 78 with the bus 105, which requires four selection lines. A disk drive interface circuit 118 couples the bus to the disk drive circuits of three disk drive units, for which three selection lines are required. A signal system interface circuit 119 provides the coupling for the recording and playback processing circuits of the signal system, which also requires three selection lines. Data track interface circuits 120 provide the connection to the data track areas of three wedge drive units and the associated circuits provided in these as well as the signal system, This also requires three selection lines. A computer interface circuit 121 establishes the connection between the bus 105 and the CPU 106 with an automation computer which has the functions of an entire television studio including others Video recorders and similar devices. For this connection between The automation computer and the CPU 106 have two selection lines available.

In the computer control system provided for the device according to the invention 92 at least two select lines are used to select each peripheral device. Typically, a line is activated when data is transferred to the CPU 106 should, while another line is activated when receiving data from the CPU should be. Some peripheral devices associated with the interface circuits however, require more data from the CPU 106 to perform the various functional operations in the device than in the 16-bit binary word system by the CPU of the company Digital Equipment Corporation can. However, the 16 bit binary word organization and thus the use of a To be able to retain a CPU of the type mentioned becomes the main bus containing 16 lines 105 for the transmission of all data to such interface circuits in the form of 16 bit binary words are used, with additional selection lines being provided are when the interface circuit requires more data than in a 16-bit binary word can be accommodated. The plurality of selection lines will selectively so activated that certain data are transmitted over the 16 lines of the main bus 105 when one of the select lines is activated and that other data is about these lines of the main bus are transmitted when other select lines to be activated. A maximum of two selection lines are used in the device described here used for such interface circuits which receive more data from the CPU 106 than can be accommodated in a 16-bit binary word.

A microcomputer system is preferably used for the computer system of the type LSI-II from Digital Equipment Corporation of Maynard, Massachusetts for use. Specifically, the device according to the invention contains as the CPU, a KD II-F microcomputer model of the type LSI-11 which has a microprocessor and includes a 4K semiconductor-based read / write memory. The structure and the How such a system works is described in the LSI-11 Users Manual, No. EK-LSI 11-TM-002, Described in 1975. A block diagram of the central processor interface circuit 108 is shown in Fig.

29 shown. More detailed circuit diagrams are shown in Figs.

58A through 58D. The interface circuit 115 for remote input devices is shown in block diagram form in FIG. 30, while more detailed Circuit diagrams are shown in Figs. 55A to 55D. Detailed circuit diagrams for the disk drive interface circuit in fig. 35A to 35B. The first part of the data track interface circuit is as a block diagram in FIGS. 33A and 33B and as a detailed circuit diagram in FIG the fig.

57A and 57B. The second part of the data track interface circuit is correspondingly shown as a detailed circuit diagram in Figures 34A through 34H. Detailed electrical Circuit diagrams of the signal system interface circuit are shown in Figs. 32A and 32B shown. These aforementioned interface circuits will be described in more detail below described.

VideosiRnalsa, first opposite the above explanation of the signal flow paths for both recording and playback operations is the signal processing system far more complex for the composite television signal than the signal flow circuits 6 and 7 show. The video signal system is described below with reference to Block diagrams according to FIGS. 9A and 9B are described in more detail. As far as possible, be For functions that correspond to themselves, the reference symbols already selected above are also used used. The block diagrams of Figures 9A and 9B also include more lines to display the video data flow through the signal system and other connecting lines, which are used to control the timing and synchronization of the various Blocks given circuit are necessary. The connection of the signal system with the computer control system explained (with the aid of the block diagram of FIG. 8) also shown.

The corresponding input and output lines for the various Blocks in Figures 9A and 9B which lead to computer control system 92 are included marked by an asterisk.

The device according to the invention is used here in connection with the I1TSC system described, in which a television picture has 525 lines and the horizontal sync pulses occur with a repetition frequency of about 15.734 Hz, i.e. the period between successive horizontal sync pulses is approximately 63.5 microseconds. Furthermore, the vertical blanking frequency in the NTSC system is 60 Hz, with the chrominance information is modulated onto a subcarrier at a frequency of about 3.58 MHz. The subcarrier frequency from 3.58 Kiz is also referred to simply as SC in the following, by which the simple subcarrier frequency is meant, with others usually necessary Clock frequencies in the device are designated accordingly with 1/2 So, 3 SC and 6 So. The triple subcarrier frequency (3 SC) often occurs because during the Keying of the analog composite television signal for digitization a sampling frequency equal to three times the subcarrier frequency, i.e. one frequency of 10.7 MHz is used.

Before a detailed description of the block diagram According to FIG. 9A, some basic explanations of the overall function of the illustrated Signal system can be made. That fed into the video input circuit 93A The video input signal is initially an analog signal that is used for further processing in the analog-digital converter 95 is fed. The output of this converter contains the video information in digital format, being the digitized data further processed and recorded in a digital format on a stack of discs will. In this form, the signal is also reproduced by the disk stack, with regard to corrected the time base and performed a separation of the chroma component, where the processing takes place in digital technology. The return to an analog signal does not occur until the final signal processing steps are performed are, in which case the digital-to-analog converter and circuits for inserting Sync signals and burst signals the analog composite video output signal deliver.

In the analog-to-digital converter 96, the analog composite video signal is converted three times per subcarrier basic period, i.e. with a sampling frequency of 3 SO (10.7 MHz), whereby each sample value is digitally quantized into an 8-bit digital word will. A tactile clock signal with a triple Frequency or each odd multiples of the NTSC subcarrier frequency is necessarily odd Multiples of half the horizontal line frequency. Is such a tactile clock signal phase continuously from line to line, its phase changes successively at the beginning Lines. If such tactile clock signals, which are phase-continuous from line to line, are used, so the instantaneous amplitude of the analog signal becomes during successive Lines relative to the beginning of the successive lines at different points in time groped. For this reason, the quantized samples are from line to line shifted vertically. A vertical alignment of the sample values from line to line is desirable to facilitate the use of a digital comb filter that for obtaining a separated chrominance component of a television signal thereby serves that quantized sample values of three successive lines of a television field (only odd or only even fields) can be combined with one another. These three consecutive lines can be marked with T (for the upper edge of the picture), M (for the center of the picture) and B (for the lower edge of the picture), where the following relationships apply: (Chrominance) C I M - 1/2 (T + B) (lAaiinance) Y - M + 1/2 (T + B) Are the keyings of the NTSC television signal carried out with an even multiple of the subcarrier frequency, comb filter technology is ideal, since the phase of the key clock signal does not change changes from line to line. The digital code words or the quantized sample values then describe the instantaneous amplitudes of each line of the analog signal in equal terms Points in time relative to the beginning of each line, with all sample values in consecutive Lines aligned vertically from the upper screen across the center of the screen to the lower edge of the screen are.

The lack of vertical alignment of the samples consecutively Lines when using a key clock signal which is phase-continuous from line to line a frequency of 3 SO can be explained with the aid of the signal diagram according to FIG. 9C (1) are represented by multiple periods of the subcarrier in a television line 1 are, which by the positive jump of a duty cycle signal with a frequency can be keyed by 3 SO (Fig. 9C (3)). The positive jump is through an arrow marked with an X in the tactile dot. The tactile points of the auxiliary carrier for the TV line 1 are also indicated by the X (Fig. 9C (1)). In each Period of the subcarrier there are three tactile points. During a television line 2, i.e. during the next line, the subcarrier according to Fig. 9C (2) and accordingly also the key clock signal with the frequency 3 SO opposite phase (Fig. 9C (4)) relative to the phase in line 1 (Fig. 9C (1), 9C (3)) so that the Sampling values during television line 2 in points marked by X on the subcarrier (Fig. 9C (2)) occur with positive jumps. The sample values marked by X are from line 1 to line 2 in relation to the subcarrier basic frequency around 600 shifted, whereby the operation of the comb filter is adversely affected, by taking the instantaneous amplitude of the analog signal according to the equations given above is used for the correct extraction of the chrominance information. So it is to be noted that all sample values in odd lines and all sample values in even lines vertically are aligned with each other, but the sample values in even lines are relative to the sample values in odd lines around 600 with respect to the subcarrier fundamental frequency are shifted.

To do this by keying with an odd multiple of the subcarrier frequency, i.e. with the frequency of 3 SO im to avoid device according to the invention, the vertical alignments of the sample values in all lines are changed by changing the phase of the key clock signal reached in every other line. In the in Fig. 9C, Fig. 9C (5) shows the duty cycle signal with the frequency 3 SO for the television line 2, whose phase compared to the tactile clock signal for the TV line 2 is inverted as shown in Fig. 9C (4). By feeling for positive jumps In the tactile points denoted by 11011, tactile points "O" result on the auxiliary support for line 2 of FIG. 9C (2). This means that the touch points in the subcarrier are for the television line 1 ("i") relative to the tactile dots (@wo ") vertical to each other aligned. This results from the keying with a changed phase of the keying clock signal according to FIG. 9C (5) instead of the keying with the signal according to FIG. 9C (4). This technique is commonly referred to as PAL coding (Phase Alternate Line coding). in the This abbreviation or the term phase inversion or phase inversion is used below used.

Although a comb filter technology with a Key frequency of 3 SO or 10.7 spleen used, so that a PAL key pulse is required is. The phase reversal is not necessary if a key frequency of 4 SO is used will. Such a sampling frequency of 4 SO can be used for the case in the device according to the invention it can be provided that the frequency characteristics of the recording media, i. the disk stack on the disk drive units for operation with a Frequency of 4 SO or 14.3 Siz is sufficient. In this regard, it should also be noted that that standard disk drive units in data processing are usually in Work area of about 6 1/2 megabits and that recording at a repetition rate of 10.7 megabits, a sufficient increase in the packing density of the disk stacks ensure yourself.

The use of phase inversion as shown in Fig. 9C has another important aspect in the operation of the device according to the invention result. By Change in phase of the key clock signal in each subsequent line necessarily occurs a phase discontinuity with respect to the subcarrier. However, Ls is during the channel coding of the signal for the subsequent recording, the digitally quantized sample values with respect to a continuous phase clock code so that there are no line-to-line phase discontinuities. For this reason, the PAL data are sent out at the output of the analog-digital converter the channel encoder clocked out with a clock that is continuous from line to line (i.e. without discontinuities) 3 SC phase. By clocking the Encoder with a clock signal which is continuous in phase from line to line however, the data in every other line by half a period of three times the subcarrier frequency shifted in time, which is due to the keying being timed from line to line the keying with a PAL clock bothers. Since the ear oma processing circuit when reproducing requires the sample values of the data in a vertically aligned sequence from line to line (That is the reason why a PAL key clock signal in the analog-to-digital converter is used), it is necessary to use the data from the continuous phase clock to clock back into the PAL clock, so that the sampling time disturbance is eliminated and that Ohroma processing comb filter which can process data without errors. The analog-to-digital converter samples the analog signal using a PAL clock with phase discontinuities from line to line. The channel encoder encodes the PAL data for recording with a phase clock that is continuous from line to line, which is the case with playback and Post-decoding a reverse clocking of the NRZ information into a PAL clock for use makes necessary in the otomy processing circuit. This reverse cycle will but not carried out in transfer mode if the storage is on a disk stored data and for recording on another disk memory be transferred. In these cases, the line-to-line approach remains continuous Phase clock of the reproduced video data is obtained, with the data without interference of the data clock can be recorded again.

The above explanations are given below with reference to FIG. 9C explains where the PAL data for lines 1 and 2 is shown in Figures 9C (6) and 9C (7), respectively are. The bits A1 to E7 are consecutive bit cells which form the in line 1, instantaneous sample values, denoted by X, of the analog video signal according to FIG. 9C (1) represent. Each bit cell lasts for a full clock cycle of the third SC clock as shown in Fig. 9C (3). Correspondingly, the bit cells represent A2 to E2 of line 2 data representing the sample values "O" in FIG. 9C (2) using of the PAL key clock signal used for television line 2 in Fig. 9C (5) is shown. For the timing of the PAL data with a continuous from line to line 3 SC phase clocks are the clock points among the bit cells according to FIGS. 9C (6) and 9C (7) of the phase cycle continuous from line to line represented by arrows, where this clock the shifted bit cells according to the relation of FIGS. 9C (8) and 9C (9) generated. The start of each bit cell is at the time of the clock, the level being the Cell is continuous in the bit cell interval, so that the bit cells have their identity retained during clocking.

To get the data from the phase clock which is continuous from line to line back-clocking into the PAL clock, so that the bit cells (sample values) are in the intended sense are aligned vertically to each other (A2 is aligned vertically to Al, B2 is aligned vertically to B1, etc.), the reverse cycle must from the continuous phase clock in the PAL clock can be carried out correctly so no misalignment of the ditzella occurs. Therefore, the reverse cycle must be complementary take place, i.e. a LIi cell, which when clocking back from I>! 'I' to continuous Phase was clocked in the right part, must to ensure correct reproduction when clocking back from continuous phase to P / L in the left part. With data clocked continuously from line to line in the Iins according to FIG. 9C (and 9C (9)) therefore give the solid arrows the correct complementary Clocking for the two television lines again, with the back clocking of the data in the PAL clock with vertically aligned cells A1 and A2 according to Fig. 9C (10) and 90 (11). Right-clocked bit cells, which from PAL to I'ontiiiuierliche phase are clocked back, are clocked counterclockwise, what from (ler consideration of the bit cells (for example the Bitzel1e A1) with their corresponding clock apples, according to FIG. 9C ((>) and C (8)) results in the complementary Clocking not carried out, the bit cells are not correctly aligned with one another, as indicated by dashed arrows according to Fig. 9C (8) and Fig. 9C (9) is indicated. This omits that shown in FIGS. 90 12) and 9f: (13) Connection. The clocking either from PAL to continuous phase or from continuous phase to PAL is carried out at various points in the system, which is explained in more detail below.

It should be noted that the NTSC communication is not a special one define the relationship between the horizontal sync pulse occurring in each line and the phase angle of the intermediate carrier signal. Only the phase of the Hilisträger changes by 180 ° from line to line. In other words, the phase angle can be of the auxiliaries relative to the horizontal sync signal of Change video source to video source so that the horizontal sync signal in the device is not suitable for regulation. In the device in Rdc here, the lillfstrdger of the input signal, as represented by the color sync signal component is used as the basic timing reference for the system, with a new one on the horizontal sync signal related signal is defined, which in place of the Ilorizontl sync signal is used for timing purposes. The new on the horizontal synchronous pulse The related signal is chosen so that it has a frequency equal to half the nominal horizontal line frequency because it has an integer number of periods of subcarrier frequency, i.e. two represents complete horizontal lines of the current frequency or 455 periods. In addition, the signal related to the horizontal sync pulse has a defined relationship to the auxiliary carrier, i.e. it is in relation to the phase angle of the subcarrier synchronized. In the recording part of the signal system, in every second television line of the video signal to a sync word in the video signal a point used, which is approximately the point of the horizontal sync pulse corresponds to where a phase coherence with respect to a certain phase angle of the subcarrier generated from the burst signal component of the video signal is guaranteed. The new signal related to the horizontal sync pulse is present at the beginning of each image and is maintained for the duration of the image to im Video signal to ensure a signal related to the horizontal arychronic pulse, which is precisely related to the phase of the subcarrier of the video signal.

For len reproduction part of the signal system like a H / 2 bezelchlletes generates a signal related to the Elorlzontal sync pulse that is coherent with a certain phase angle of the input reference subcarrier, this Ph.-i angle 1 can be selected by the phase control in the playback system.

The signal H / 2 related to the horizontal sync pulse serves as basic reference timing signal for the system in playback operations.

By using the one related to the liorizontal sync pulse Signal as a reference llorizontal - ', synchronous signal for the system is the signal processing for recording, playback and other operations of the system facilitated because a fixed time relationship between the subcarrier of the video signal and the on the signal related to the IlorLzontal sync pulse is guaranteed.

By using internal reference horizontal and auxiliary beams, which are temporally variable relative to the reference sync signal of the television station, a timing control is also possible, based on which the television signal at the right time after the usual propagation delays at one removed can arrive lying position.

According to the block diagrams of FIGS. 9A and 9P, the analog Video input signal fed to the input of a video input circuit 93A, in which it is subjected to various processing operations before entering the Analog-digital converter 95 is fed. Specifically done in the video input circuit 93A an amplification of the analog video signal, a readjustment of the DC voltage level, a separation of the synchronous components contained in the video signal for generation of timing signals for the Signalsyst-m, a determination of the peak value of the Horizontal sync pulse and a subsequent limitation of the} Jori zoIl ta l sync pulse. I) In addition, the horizontal synchronous pulse is made by a precision synchronous tufe separated in order to generate a regenerated; synchronous pulse can. The circuit continues to generate a regenerated Subcarrier signal that from Color sync signal in the input video signal or in the absence of the color sync signal from the actual / 2 reference signal, which is generated from the input horizontal sync pulse, is derived.

It should be noted that the video input circuit 93A as well as one Reference signal input circuit 93B in the lower left part of the block diagram perform similar functions of Fig. 9A, with the video input circuit primarily for the signal recording part of the signal system and the reference signal input circuit is primarily intended for the playback part of the signal system. For convenience Identical circuits are therefore used in manufacture and maintenance. However take the input circuits only those input signals, which are necessary for implementation the corresponding functions are required. Although both circuits are the same Generate signals, not all signals are used by every circuit. The reference input signal for the reference signal input circuit is determined by the station reference black signal formed that all components of a color television signal with the exception of the active one Contains part of the video that is at black level. Therefore, in the lingengssignal for the reference signal input circuit 93B as well as the input signal for the video input circuit 93A the burst signal, the horizontal burst signal and corresponding signals contain. In addition, in the reference signal input circuit 93B, there is an H. phase adjustment circuit provided, which H-position control signals, for example, from a dial to Adjustment of the H-phase position of the regenerated H-sync signal for the playback part of the signaling system.

Part of the output signals of the input circuits 93 and 93B become fed into reference logic circuits 125A and 125B, which of the corresponding Initial circuit are assigned. The reference logic circuit> 125A processed while of the recording mode signals from the video input circuit 93A, the analog-to-digital converter 95 and the computer control system 92 and generated a number of recording clock signals via precision phase locked loop circuits with frequencies of 6 SO, 3 SO and 1/2 SO as well as a PAL error indicator signal. From the PAL error flag signal and the 3 SC signal, becomes in the reference logic circuit 125A generates a 3 SC-PAL key clock signal whose phase for each line of the video signal is set by the PAL error flag signal having a frequency of H / 2 owns. The PAL error flag signal changes value at this frequency. This change occurs asymmetrically, i.e. the two values of the PAL error flag signal have unequal time intervals. The asymmetry is chosen so that the touch-tect phase for the color sync signal part of the video signal with the phase of the subcarrier constant is and that only the part of the television line has a key phase thereafter, which is changed in consecutive lines. This PAL clock signal is on the Analog-to-digital converter 95 coupled and provides the duty cycle signal for generation of the sample values with a frequency of 3 SO or 10.7 MHz.

The reference logic circuit 125B generates from signals from the reference signal input circuit 93B and the computer control system 92, a clock reference signal having a frequency of the subcarrier (SC) and various other timing control signals. These signals are in others Operating modes of the device (non-recording of video input signals) are used.

In the recording and reproducing operations, the reference logic circuits generate continue to provide servo sync signals for the disk drive units in order to convert them to the correct phase to operate.

Apart from recording video input signals, a Reference clock generator 98 during playback and other modes of operation Clock signals as well as additional clock control signals which are used for the various Parts of the signaling system are required in these modes of operation.

The reference clock generator generates from input signals from the reference signal input circuit 93B from the reference logic circuit 125B (reproducing part of the signal system) and a control switch actuatable by an operator clock signals with frequencies of 6 SO, 3 SO, SO and 1/2 SC as well as various other timing control signals. the Reference logic circuits 125A and 125B and reference clock generator 98 form together the clock generator 94 according to FIG. 6, which the timing control signals for the system delivers.

The clamped analog video input signal, from which also the horizontal sync signal is separated from the output of the video input circuit in the analog-to-digital converter 95, which converts it into an eight bit binary coded signal in PAL-NRZ format convicted. This coded signal is then fed into a coding switch 126. The analog-to-digital converter 95 will not be described in detail since it is a known type is, for example, in one marketed by the applicant Device with the type designation TBO-800 is included. Circuit diagrams for the analog-digital converter 95 can be found, for example, in a catalog with the number 7896382-02 from October 1975.

Such an analog-to-digital converter is special, for example Circuit diagram No. 1374256 on page 3-31 / 32 and circuit diagram No. 1374259 on page 3-37 / 38 can be found in the catalog.

The coding switch that receives the output signal of the analog-digital converter 126 contains switching circuits, which either the digitized video data with eight Bit from converter or from a data transfer circuit 129. As will be explained below, the data transfer circuit 129 enables transferring the video information from one disk drive unit to another Disc drive unit, as mentioned above with respect to the operation of the device below Exploitation of the remote input devices or the device's own input device became. The digitized information is transferred from the disk drive unit in transfer mode read out, decoded into digital NRZ format, corrected in the time base and then on the coding switch, which is the sources for the digitized video information for encoder 96 can select. Since the on the disk drive units 73 recorded coded data is clocked with a continuous phase clock, the NRZ data received by the data transfer circuit 129 are also related clocked to the rhythm of the continuous phase. Usually the data transfer circuit receives 129 a PAL error flag signal used to reverse clock the digital NRZ data with respect to a PAL clock signal, so that the comb filter and chroma inverter circuit 101 is in the correct PAL format. During the transfer operation this counterclocking is not necessary. The coding switch 126 contains a circle to interrupt the coupling of the PAL error indicator signal to the data transfer circuit 129, whereby the clocking back of the NRZ data with respect to the PAL clock during the Data transfer operation is prevented.

The code switch 126 is controlled by the computer control system 92, to clock the video data from either the video or the transfer path. He switches continue between the video and reference timing signals with 6 So and 1/2 SO um, as the reference timing signals during the data transfer operation and the video timing signals can be used during the recording operation. The coding switch serves furthermore for generating a signal that generates a flashing cross in the TV picture, which a visual indication is that the picture location or address for a picture are free and therefore available for recording. In addition, the Coding switch signals for performing examination functions.

The eight bit data from encoder switch 126 is then fed into the encoder 96 is fed in, which first generates a parity bit and the PAL data into a encoded square Miller channel code format, which is a self-clocking, DC-free NRZ code. While fed into the encoder PAL data the encoder output signal is a 9-bit data sequence (with inserted parity bit), which is 3 SO phase continuity with respect to the frequency owns. Continuously phased data is easier to process, what applies in particular to decoding processes. Are in a DC-free code do not contain any DC voltage components, which due to the dominance of a logic state could occur over a period of time, causing the data in the Playback pro.

could be disturbed. It is in this context on one See parallel application (Serial No. of U.S. Patent Application 668,679).

As already stated, the code format can be used as a DC voltage-free, self-clocking NRZ format. It is suitable for the transmission of Binary data via an information channel with limited bandwidth and limited signal-to-noise ratio, tn which the data in a co-voltage.

free self-clocking format.

In information channels of limited bandwidth, which do not have DC voltage transmitted, binary signals experience distortion at zero crossing, which cannot be eliminated by linear compensation networks. These Distortion is commonly referred to as baseline deviation and reducing it the effective signal-to-noise ratio, where the zero crossings of the signals are modified and thus the bit accuracy of the decoded signals are adversely affected. Fin common transmission format or a channel data code that is used in recording and playback systems is described in U.S. Patent No. 3,110,261. In the Miller code, logical ones are created by signal jumps at a certain point, i.e. in the middle of the cell and logical zeros through signal jumps at a certain earlier position, i.e. in the area of the leading edge of the bit cell. in the Miller code will follow hops at the beginning of an interval for a 1-bit an interval containing a jump in its center is suppressed.

Asymmetries of the signal generated according to these rules can lead to a DC voltage component lead in the coded signal, the so-called quadratic Miller code, which is used in the device according to the present invention, the DC voltage content of the original Miller code effectively eliminated without either a large memory or a repetition frequency change in the coding and Decoding are required.

The encoder 96 also generates a unique sync word in Form of a seven-digit binary number and adds this sync word to every second Line at a precise point, which is determined by the clock signals with a frequency are determined by 6 SO and 1/2 SO. In the recording mode, the synchronous components of the video input signal generated by reference logic circuit 125A fed through the coding switch 126 into the encoder 96, through which the Syndiron word arises, which is inserted at a point, such as the one Place corresponds to at which the horizontal sync pulse of the video signal before was present. In other modes of operation, the clock signals are with a frequency of 6 CC and 1/2 SO by the cooperation of the reference logic circuit 125B and des Reference clock generator 98 from the synchronous components of the station reference black video signal generated. The encoder scans the sync word related to the horizontal sync pulse in every second television line in the data sequence at the right time relative to regenerated subcarrier phase.

Before the recording is also carried out on the data track of the disk drive units 73 recorded data track information is encoded. The data track information is through the computer control system 92 is provided via the data track interface circuit 120.

As shown in Fig. 9B, the ten data sequences become the output of the encoder 96 encoded digital data occurring in an electronic data interface circuit 89 is fed, which is only a signal separation and buffer circuit. This circuit couples the encoded data to the three disk drive units 73 for recording them on a data stack 75. Each disk drive unit contains a data interface circuit 151 for this disk drive unit, which receives the data from the electronic data interface circuit 89 and through a recording amplifier 153 and a head switch 97 for recording leads to an associated stack of discs 75.

The interface circuit 151 continues to take reproduced data through the head switch 97 and a playback amplifier 155 and supplies them a data selection switch 128. In addition, the data interface circuit 151 for the disk drive unit a multiplex servo reference signal from the electronic Data interface circuit 98 and transmits it to a timing generator (Fig. 39) of the disk drive control circuit. This signal is generated by the computer control system 92 taken from either reference logic circuit 125A or 125B. In the timing generator the multiplex servo reference signal is used for such a timing of the Disk drive unit that recording and reproducing operations as well as the Speed of the disk stack 75 in the disk drive unit 73 with a suitable e-system timing reference signal are synchronized.

The disk drive control circuit carries out pre-recorded timing and data timing signals through the interface circuit 151 for the disk drive unit back to the electronic data interface circuit 89. With the one in question here standing special embodiment of the device according to the invention are only two fields of the four-field NTSC color television signal color code sequence recorded, with the two fields in separate revolutions of the disk stack 75 can be recorded. Immediately before the recording of the two fields of the video data, the pre-recorded timing signal is generated and converted into the electronic Data interface circuit 89 fed. This interface circuit transmits the prerecorded timing signal to encoder 96 to generate an interval, which represents two field data equivalent to the color black, this being Interval is defined digitally by logical zeros. These data are processed via the Interface circuits fed back to the disk stack in a track location to be recorded, which is used for the recording of video data and their Data track information has been selected. The record of the mentioned Black data occurs immediately during two revolutions of the disk stack 75 before the two revolutions during which the two fields of the video data are recorded This is the track location for the following transfer of video data and Data track information prepared. Because the dubbing of previously recorded Digital data with new digital data to obscure the previously recorded one Digital data can be carried out, with a recorded signal being sufficient Quality guaranteed for reproduction with an acceptable signal-to-noise ratio is, the pre-recording cycle can be omitted, so that the recording of the two Fields of video data and the associated data track information in only two revolutions of the disk stack 75 can take place.

The data clock signal is sent to the electronic data interface circuit 89 fed back to the generation and recording of the data map information to clock in the second or last field of the two fields of video data. The signal is a pulse which follows the vertical sync pulse of the two fields the video data begins and ends at the end of the second field. During this Interval, the data track information on the data track of the disk stack 75 becomes recorded. The electronic data interface circuit 89 couples the fed back Data timing element on the data track. Interface circuit 120 of the computer control system 92 to identify the system's data track recording interval. The computer control system 92 consequently performs functions relating to the recording of the data track information which is, among other things, the data track information of the recording of video data on a specified track of the selected data stack. The encoder 96 receives the data track information and processes it as described Senses for transmission to the disk drive unit 73 and for simultaneous recording with the last field of the video data.

The recording and reproducing amplifiers 153 and 155, the head switch 97 and the disk drive control circuit of the device are assigned to one another in such a way that that the playback amplifier 155 and the head switch 97 for data playback from associated disk stack 75 at all times except when a recording operation is being carried out are effectively switched.

Except during recording, data played back will be always received by the interface circuit 151 for the disk drive unit, which in turn couples the reproduced data to the data selection switch 128. When recording, a recording command is received from the disk drive control circuit coupled to recording and playback amplifiers 153 and 155 to the recording amplifier 153 to be activated and the playback amplifier 155 to be blocked. The disk drive control circuit continues to provide a head switching signal of 30 Hz for during recording operations the head switch 97, causing it to run the data sequences during the first field of the two consecutive field data to be recorded to a set of Heads and couples to the second set of heads during the second field. This 30 Hz head switching signal is continuously available and is used in playback operations to control the head switch 97 to set the playback amplifier 155 for playback of two fields of a desired video data signal between the two headers to switch.

In reproducing operations, the reference signal input circuits generate 93B and the reference logic circuit 125B according to FIG. 9A show the regenerated subcarrier frequency for feeding into the reference clock generator 98, its output signals with frequencies of 6 SO, 1/2 SO and H / 2 the basic timing signals for playback operations form. The output signals of the reference clock generator are converted into the decoding and Time base correction circuit 100, the data transfer circuit 129, the comb filter and a chroma inverter circuit 101 and a video playback output circuit 127 fed, which inserts the output signal, performs a selective bit lock and a selected monochrome video signal as output for the signal systems supplies, if the heads, which a disk drive unit coupled to the playback channel are assigned to be moved between the track locations. The digital information with eight bits is then fed into the digital-to-analog converter 102 and the processing amplifier 103 fed, which uses sync signals and the color sync signal. at The reference clock generator 98 supplies the basic transfer and examination processes Timing signals for encoder 96 via encoder switch 126.

When played back, the one played by a stack of disks becomes parallel 10-bit data sequence, which includes 8-bit video data, the parity bit and data track information includes, amplified by circuits according to FIGS. 24 to 28, 53 and 54, equalized and detected and then via the interface circuit 151 for the disk drive unit fed to the data selection switch 128, which is the output of the three Can couple disk drive units on one or more of three channels. The data selection switch can thus read the information from the disk drive unit Switch No. 1 into channel A or into two channels while simultaneously a data sequence is switched to another channel by another disk drive unit.

While information from two disk drive units does not simultaneously can be switched into a single channel, however, the reverse is possible. The data select switch 128 includes conventional switch circuitry, which is shown here not be described in detail.

The captured data sequences with 9 bits of video data and a parity data are then switched by the data selection switch 128 into nine individual data decoders and time base correction stages fed into circuit 100 which decodes the data and then the nine Data sequences independent of one another in relation to a common H / 2 reference signal corrected in the time base, the latter signal with respect to the phase of the regenerated reference subcarrier is set to avoid timing errors in the nine Eliminate data sequences.

All sync words are aligned with one another so that each 9-bit parallel bytes contains the correct 9-bit data. The data track information is only activated by the data selection switch on the decoding part of the circuit 100 out, the decoded data track information for transmission to the CPU 106 is coupled to the data track interface circuit 120. The time base correction is performed using a continuous phase clock. The data however, through the data transfer circuit 129 with respect to a PAL clock clocked back, i.e.

the phase of the signal is clocked back in each horizontal line changed so that the data sequence coming from the data transfer circuit arrives again is true PAL signal.

The data transfer circuit 129 also performs a parity check the data coming from the disk drive units. This is done through Error coverage of individually occurring byte errors by means of substitution by the most similar, previously occurring byte in place of the byte that was identified as an error was established. The substituted byte is the third preceding one Byte that is equal to the earliest sample value, which is phase-related was won on the subcarrier.

The output signal of the data transfer circuit is for the case in the comb filter and ear domain inverter circuit 101 is fed when the video information should be displayed visually. There is no recording to another Disc drive unit (transfer). For a transfer, the data from the Data transfer circuit 129 coupled to coding switch 126. The comb filter and chroma inverter circuit 101 separates using a comb filter technique removes the chrome information from the luminance information and inverts the chrome information in every other frame to form a composite NTSC signal with four Fields, which are then fed to the video playback output circuit 127 will. In this circuit, a reference black level becomes during the blanking period and gray level signals during the interval between the display of successive images inserted. If necessary, this circuit also locks bits. By this bit blocking is all bits or certain bits of an 8 bit television signal blocked by suppressing the data bit sequence, whereby ix resulting television signal special visual effects such as enhanced color tones, ghosting and the like are achievable. The output of the video playback output circuit 127 is then fed into the digital-to-analog converter 103. This digital to analog converter receives clock signals from the video playback output circuit 127 and transfers the data in their analog form, with synchronous and color synchronous components at the same time of the signal can be used to produce a full composite analog television signal to create.

In the foregoing, the signal system of the invention Device generally described in its overall function. Special descriptions of the blocks 9A and 9B are either in the following using separate block diagrams or given on the basis of detailed circuit diagrams. For the block diagrams for Explanation of the individual blocks according to Fig.

9A and 9B, detailed individual circuit diagrams are also given.

Video and reference signal input circuit The video input circuit 93A and the reference signal input circuit 93B, which are generally indicated in Fig. 9A are constructed in the same way, but with different input signals and all available output signals are not used. During recording operations feeds the composite video input signal to be recorded into the video input circuit 93A, which is used to generate a regenerated subcarrier signal as well different on the repetition frequency of the vertical and horizontal sync pulses related signals is used. These signals are used in the device to perform recording operations exploited.

The video input circuit also provides an amplified and filtered video signal for feeding into the analog-digital converter 95. During playback operations a reference black video signal is fed to the reference signal input circuit 93B, which provides similar signals for performing playback operations.

According to the block diagram for the video input circuit and the The reference signal input circuit of Fig. 10 is the video signal on a line 200 fed into a video amplifier 201, which amplifies the signal and the DC voltage component is reversed via a clamping stage 202. The clamping step 202 samples the output of the amplifier on a line 203 and generates a DC voltage component on a line 204, which is fed back to the amplifier 201 is. The clamped video signal on line 203 is then passed through a low pass filter 205, whose output signal is on a line 206 in a video variable gain amplifier 207 is fed. This amplifier 207 is associated with another video amplifier 208 coupled, being ensured by a second clamping stage 209 that the blanking level of the signal has reference potential (ground level). this takes place by feeding in a DC voltage control signal via a line 210 into video amplifier 208. The output of video amplifier 208 is via a line 211 and a line 218 are fed into the key input of the clamping stage 209. The line 211 also leads to a keyed synchronizing signal limiter stage 212 as well as a precision sync signal separator 213. In the video input circuit 93A continues a remote gain control signal on line 217 in a Comparison stage 216 fed to the control amplifier 207 from another point to regulate out. The output of a synchronous peak detector 214 that is still may contain a ripple, is in an input of the precision sync signal separation stage 213 fed, the other input via line 218 to the output of the Video amplifier 208 is coupled. The two input signals of the precision sync signal separator 213 can also have a ripple, the feed being carried out in such a way that the separation stage generates a ripple-free synchronous signal on a line 220, the different eynchronstufe 221 as well as an input of a horizontal synchronous phase detector 222 is performed. Line 218 continues from the output of video amplifier 208 to a less precise sync signal separator 219, which is a less provides an accurate sync signal. This signal is fed into a pulse generator 223, the output of which is fed via a line 224 to both the clamping stages 202 and 209 and the synchronous peak detector 214 is coupled. When a horizontal sync signal is detected and disconnected, the key pulse generator 223 delivers a key signal, that the clamping steps as well as the synchronous peak detector at the right time during of the horizontal blanking interval closes.

The clamp stage 209 is not during the burst signal time in an arbitrary period but closed for an integer number of periods, so that the blanking level of the video signal is accurately obtained by an integration technique can be. This function is described in more detail below. The color burst occurs on both line 210 and line '225 which occurs a color sync signal limiter stage 226 is performed.

This stage 226 is in turn coupled to an amplifier 227, which complementary output signals from the limited input color burst supplies. The output of limiter stage 226 is a burst signal detector 228 coupled, one output of which via a line 229 to a precision key generator 230 and a further output via a line 260 to a phase detector 231 is coupled. If the presence of a color sync signal is determined, so the precision tactile generator 230 delivers a precision color synchronous tactile signal, which activates the amplifier 227, whereby the middle three periods of the color sync signal are coupled to the phase detector 231. As a result, the phase detector delivers an error signal for a lock-controlled oscillator 232, which is a measure for the phase difference between the output of this oscillator and the phase of the burst signal periods supplied by the amplifier 227.

The phase detector thus controls the oscillator 232 in order to avoid longer-lasting Correct for changes in the phase of the three periods of the burst signal, which are used as subcarrier reference in every line. The output signal of the oscillator 232 is coupled to a line 233 via a buffer 234. That The oscillator's output signal is a continuous regenerated subcarrier signal the frequency SC (3.58 MHz) that is present in the phase on the. Color subcarrier signal is related. However, if the burst signal detector 228 does not produce a burst signal fixed, so the phase detector 231 compares the phase of an H / 2 signal with that of the regenerated one Subcarrier output of oscillator 232, the H / 2 signal via a Synchronous generator 235 is generated by an oscillator 236, which is generated by the horizontal synchronous phase detector 222 is controlled.

In the reference signal input circuit 93B, one is indicated generally at 237 designated horizontal phase control is provided, which is used to adjust the Horizontal position of the regenerated synchronizing signal is used. For example via a operator-operated dial becomes an 8-bit binary number in Hold stages 238 loaded to preset a counter 239 which is preceded by a clock signal coming from oscillator 236 is clocked at 400 Hz. When the counter reaches its final count value, it triggers a sawtooth generator 240 with an output 241, which to a second input of the horizontal synchronous phase detector 222 is led. By setting the hold levels, you can enter the feedback loop can be set on line 241 up to plus or minus 20 microseconds, wherein the phase of the regenerated sync signal for horizontal adjustment of the Can be adjusted during playback. There is a delay in the feedback loop means that the regenerated sync signal is advanced, the horizontal position control can the image to compensate for transmission delays of a signal over cable be moved forward accordingly in a television station. As in the following based on a detailed description of the reference clock generator 98 operates this horizontal phase position control together with a subcarrier phase control, whereby the delay can be regulated in small increments. At the in This is the embodiment of the device according to the invention in question by values of about + 0.8 nanoseconds.

The output of oscillator 236 controls that for television signal processing conventionally designed synchronous generator 235 in the sense of generating various signals related to the vertical and horizontal synchronizing signal repetition frequencies according to FIG. 10. These signals related to the synchronous signal repetition frequency become with respect to the phase of the precisely regenerated horizontal sync signal from the phase detector 222 are generated so that they are always related to the phase of the input signal.

An important aspect of the circuit of FIG. 10 is that the horizontal sync signal of the video signal is exactly half its value limited and the value of the blanking signal clamped exactly to reference potential (ground) will. The regenerated subcarrier is related to the phase of the color sync signal, wherein a precision horizontal sync signal by the precision sync separator is won. This signal is used in the synchronous generator 235 to generate a Reset pulse (picture index pulse with 30 Hz) to reset one of the following line identification or synchronous word insertion circuit to be described.

Since the clamp stage 209 has a mean zero level of the video signal during the burst time using a clamp pulse to determine which lasts exactly for an integer number of periods of the color sync signal is none Low-pass filtering of the video signal and switching off the color sync signal before the Clamping process required. This arises from the fact that the resulting Integration of the burst signal is zero, and that by the integration a signal that does not contain complete periods of the burst color signal, no H / 2 ripple is generated.

The block diagram according to FIG. 10 describes the functional mode of operation of the input circuits. Special circuits to carry out of these functions are shown in FIGS show the complete circuit diagram of the input circuits.

With regard to the mode of operation of the clamping stage 209 (see Fig. 42C) the voltage at the output of amplifier 208 is on lines 211 and 218, the latter of which is led to the base of an emitter follower transistor 244 is at which a voltage drops. The blanking level is under equilibrium conditions of the video signal on line 218 to reference potential (ground). This signal becomes negative due to the voltage drop at the emitter follower 244 by 0.7 volts postponed. A matching emitter-follower transistor 245, the emitter of which has a Line 247 coupled to the inverting input of a differential amplifier 246 is, shifts the comparison level (ground) into the negative just like the transistor 244. The emitter of transistor 244 is connected to the non-inverting input of the differential amplifier 246 coupled when a transmission gate or a switch 248 during a integer number of periods of the burst signal by a signal on the line 224 is closed by the key pulse generator shown in Fig. 42D 223 is generated. During the color sync signal time, switch 248 is closed, whereby a capacitor 249 is charged to the mean value of the burst signal will. The switch is closed for an integer number of periods of the subcarrier. This eliminates the need for low-pass filtering of the video signal in order to achieve the Turn off the color sync signal before the clamping process, which in a known manner for Elimination of the H / 2 modulation of the clamping level takes place. The charging of the capacitor 249 reproduces the exact mean value of the burst signal, with the output signal of the differential amplifier 246 represents an error signal which is transmitted via a line 251, a transistor 252 and the line 210 which is connected to the emitter of the Transistor 252 is coupled to the video amplifier 208. The blanking level of the signal on line 211 is therefore due to the high DC voltage gain of the differential amplifier 246 approximately at reference potential (ground held the clamping step 202 shown in FIGS. 42A and 42B corresponds to the mode of operation the Klemistufe 209.

42C, when the switch is closed, the burst signal becomes 248 gated into the capacitor 249 and fed into the line 225, which from The left part of the circuit according to FIG. 42C is routed to the circuit according to FIG. 42A and coupled to the emitter of a transistor 254 so that the burst signal from its collector via a line 255 to the color sync signal limiter 226 is performed.

If the color sync signal is present, the color sync signal detector delivers 228 a limited burst color signal on line 229 which the precision key generator 230 clocks. This key generator is designed as a counter, which periods of the limited burst counts and during the middle three periods of 9 to 11 periods of the burst signal interval is a precision burst signal key signal generated, which is coupled via a line 256 to the amplifier 227 to this to switch effectively.

Except for the three middle periods of the burst signal the amplifier 227 is controlled by the output of the burst signal detector 228 blocked. If the color sync signal is present, a diode detector delivers 257 and a subsequent hold circuit 258 of the detector 228 have a more negative value on a line 260 which leads to a switching transistor 259 (Fig. 42B) of the phase detector 231 leads. When the color sync signal is present, the switching transistor 259 is blocked and a further switching transistor 261 of the detector 231 is turned on. Is the transistor 261 is switched through, the three periods of the Color sync signal from amplifier 227 via a driver stage 277 to a transformer 262 of the detector 231 coupled.

The driver stage is coupled to a phase comparison stage 231a, the phase of the color sync signal with the phase of the output signal of the oscillator 232 from 3.58 MHz (SC) to compare, with the latter signal on the line 233 stands. If the detector 228 does not detect a burst, the transistor will turn off 259 switched through, whereby the H / 2 signal on the other input of the driver stage 277 is coupled, which is also connected to the transformer 262, then the phase of the oscillator output signal on line 233 with the Phase of the H / 2 signal is compared.

The circuit part for separating the horizontal sync signal according to Figure 42C includes the decrease of the sync signal from amplifier 208 on the line 218 through a low-pass filter 264, the output of which is sent to the base of a transistor 265 is coupled. The emitter of this transistor 265 is connected to a transmission gate or a switch 266 coupled, which during the presence of the sync signal is closed via the control line 224. The value of the sync signal is above the charging of a capacitor 267 (Fig.

42D) found which on an amplifier 268 with the gain 1 is coupled, with half the DC voltage level of the peak of the sync signal along with the full value of the ripple present in the signal across the line 215 is coupled to one input of the comparison stage 213, the other input of which is fed via a line 269 coming from the emitter follower transistor 265. That The output signal on line 220 is therefore a separated synchronous signal, its Timing is not affected by the ripple on the video signal as this Ripple occurs at both inputs of the comparison stage 213 and because of the Common mode operation no longer appears at the exit. The sync signal generated on line 220 represents a precision sync signal that is used in other parts of the signaling system is used to generate synchronous signals related to the horizontal lines, which are fixed with respect to a certain phase of the subcarrier signal. These Signals serve as timing reference signals in the signal system for processing the video signals. Has the synchronous signal related to the horizontal lines used in the system a repetition rate of 1/2 H, since for every two horizontal lines (227.5 x 2 I 455) there is an integer number of subcarrier periods.

This fact is for the mode of operation of the invention Device is important, as will be explained in more detail below.

A less accurate split sync signal will continue to do so generated that the sync signal from the low-pass filter 264 via a line 270 on the less accurate synchronizing signal separator 249 is performed, the output signal is passed via a line 271 to the pulse generator 223, which one contains as a synchronous detector 276 acting monostable multivibrator. One in general with 272 designated upper circuit part generates a key signal for the switch 266 to close it while the sync signal is present, while a circle 273 generates a porch touch signal and a circle 274 a color synchronous touch signal redefined in relation to the SC phase. With regard to the detector 223 it should be noted that that the synchronous detector 276 in the absence of a synchronous signal, then that too not on the line originating from the less accurate sync signal detector 219 271 occurs, both the switch 248 in the clamping stage 209 via the circuit 274 as also a corresponding switch 275 in the clamping stage 202 closes, so that all clamping stages are on a DC voltage feedback loop and not work on an open loop. If the synchronous signal is not available, it is the level on line 224 is high until the sync signal reappears and is detected will. In the event that the precision key generator 230 does not provide the necessary number of burst signal periods to it after triggering its counting cycle to touch its final value is provided as a safety measure that the detector 276 is switched through via the circuit 274 in order to activate the color synchronous key signal to couple the precision key generator 230, thereby terminating the counting cycle and the precision color sync key signal is supplied. This ensures that the precision key generator 230 always responds correctly to each input burst signal appeals to.

In order to ensure an image index signal in the coding switch 126 that precisely related in phase to the vertical sync signal of the input video signal is, the output of the precision sync separator 213 and an output of a vertical synchronous detector 278 (Fig. 42B) to a NOR gate 279 (Fig. 42D) which provides the desired image index signal.

Reference Logic Circuits The reference logic circuits 125A and 125B receiving various signals from the input circuits according to the block diagram of FIG. 9A 93A and 93B, respectively, which respond to the horizontal and vertical sync signals, the regenerated Subcarriers and other corresponding signals are related and generate a number of clock and timing control signals for the device according to the invention. Continues to deliver the computer control system 92 control signals to both logic circuit 125A and 125A for the logic circuit t25B, which are used to generate servo sync signals. These signals regulate the functional phases of the disk drive units in the various Operating modes, for example for recording, playback, transfer and others operations performed by the device. The reference logic circuits are duplicated present, so that such a circuit for the video input circuit 93A and a further is provided for the reference signal input circuit 93B, the function of the reference logic circuits during said various operations of the Device works slightly differently. Since the logic circuits 125A and 125B are different Performing functions, they receive different input signals, with all available output signals are not used.

The operation of the reference logic circuits is shown below Hand of a block diagram according to Fig. 11A explained in more detail. One through the The middle of this block diagram is separated by a horizontal dashed line different functions. The upper part of the circuit is only used when recording exploited while the lower part of the circuit when recording, playback and other operations of the signaling system is used. The upper Part of the circuit is used to generate various phase-locked clock signals for Recording processes using the regenerated sub-carrier, which is in the above from the video input circuit 93A from the burst signal is produced. The circuit also generates a single-ended PAL error flag signal with a frequency of H / 2, which for the reasons mentioned above leads to phase reversal of the key clock signal in the analog-digital converter in successive horizontal lines is exploited. This PAL error flag signal is also available as an output signal the reference logic circuit 125B is available to, in other parts of the signal system, primarily used in the parts that are used to process the playback signals to become. The circuit also generates a driver sync signal for control the servo control of the disc drive motors, which are a set of three Impulses with a repetition frequency of 15 Hz, which together with the horizontal synchronous signal is used several times to control the servo control.

Further timing control signals are explained in more detail below generated by reference logic circuit 125B, to be described.

In the upper part of the circuit of Fig. 11A, the subcarrier signal (SC) either from video input circuit 93A to the reference logic circuit 125A or from the reference signal input circuit 93B for the reference logic circuit 125B fed in on a line 300 and fed to a phase comparison stage 302, the output signal of which is fed into a summation node 304 on a line 303 whose second input signal is from an integrator 306 via a line 305 is delivered. A digital precision color synchronous phase decoder 307 takes the digitized video data from the output of the analog-to-digital converter 95 above a line 308 and determines whether the samples with the correct phase of the Color sync signal can be obtained. This decoder generates a plus or minus error signal for the integrator 306 on a line 309, thereby changing the phase of the duty cycle signal adjusted so that the video signal is always keyed correctly. The output signal of the cummation node 304 is connected via a line 310 to a loop amplifier and filter stage 311 out, which via a line 313 to a voltage-controlled Oscillator 312 is coupled. Line 313 is still on one of two driver stages 314 led for fault indicator lamps. The output of oscillator 312 occurs on a line 315 at a frequency of 6 SO and is switched to one through 6 dividing counter 316 and a dividing by 2 counter 317 led, with on a line 318 generates a PAL clock output signal at a frequency of 3 50 will. The dividing by 6 counter supplies an output signal on a line 319 with a frequency of 1 SO which is divided into a divide by 2 counter 320 as well as in the other input of the phase comparison stage 302 is fed. The output signal of the divide by 2 counter 320 is a signal of frequency 1/2 SO on one Line 321, which is led to a pulse shaper 322, to divide by 2 To set and reset counter 317 in every other line. The control takes place via a line 323 at a frequency of H / 2, this signal being transmitted by a PAL error code generator 324 is supplied, which will be explained in more detail below is explained.

The operation of the upper part of the circuit is used to generate a signal with the frequency 6 So at the output of the voltage-controlled oscillator 312, which is regulated so precisely that the one carried out in the analog-to-digital converter 95 Keying at all times with exactly the same phase of the Color burst he follows. This is important considering the fact that the phase of the The keyed video signal ultimately determines the color produced by the device. The phase comparator 312, one input of which via the line 319 with the divided Output signal of the voltage controlled oscillator 312 is applied, forms a phase-locked loop, which keeps the phase of the output signal relatively accurate the phase of the video or reference subcarrier signal on line 300 defines that is fed into the other input of the phase comparison stage 302.

The divided output of the voltage controlled oscillator 312 generates a signal with the frequency SO via the phase-locked loop, which is generally is within about 100.

The digitized video output signal from the analog-to-digital converter 95 is, however, also via line 308 into the digital precision color synchronous phase detector 307 fed in, which by the precision color sync key signal on a Line 307 is activated to generate an error signal during of the color sync interval of the video signal. This error signal is through integrates the integrator 306 to feed one into the summation node 304 Generate mean. This means that the voltage value at the output of the loop amplifier and filter stage 311, which controls the voltage controlled oscillator 312, see above adjusts that changes in the sample times the video signal caused by the the color synchronous sample values supplied to the decoder 307 are represented, corrected will. The color synchronous sample values represent the same values for all lines, if there is no change in the sampling times. By monitoring the exit The gated data occurring in the analog-digital converter can be precisely defined whether the sample values were obtained with the correct phase. In this way supplies the output signal of the voltage controlled oscillator on line 315 which is fed to divide by 2 counter 317 PAL clock signal of frequency 3 SC on line 318 through which the analog-to-digital converter 95 is controlled to keep the keying in phase. The digital one Precision color synchronous phase decoder 307 corrects errors that occur due to a Temperature drift and the like arise and in the range of 50 to 100 lie. In this regard, represents the phase of the video (or reference) sub-carrier on line 300 the basic definition for the voltage controlled oscillator 312, with the precision correction on line 305 in the reference logic circuit 125B changes the phase a few degrees, i.e. up to about 20 °.

In the lower part of the block diagram of FIG. 11A, the PAL error code generator generates 324 a PAL error flag signal with the frequency H / 2 for switching a switch 325, which pulses with the frequency 1/2 SO into the set or reset input of the by 2 dividing counter 317, which feeds the PAL clock signal on the line 318 delivers. The PAL error identification signal changes its state in every line, as will be explained below with reference to Fig. 11B. The PAL error flag signal is unbalanced, so that the phase of the PAL clock signal with the Freqltenz 3 SC during of the sync interval of the video signal is never reversed while it is during the active video signal phase. is reversed every other line. m essential it follows that only the part of the line after the burst signal is sampled with a clock signal whose phase is reversed in every other line i.e. it is an unbalanced signal.

As shown in Fig. 11A, the PAL error flag generator 324 takes inputs from video input circuit 93A or the reference signal input circuit 93B, which is an H drive signal on line 326, a picture index pulse on line 327 and a color sync error flag signal on line 328 acts. The color sync error flag signal prevents the PAL error flag generator a PAL error flag signal is generated on line 323 until the burst signal occurred because the keying phase of the color sync signal for the function of the color sync phase detector 307 in the upper part of FIG. 11A need not be changed.

The PAL error label generator continues to generate on one line 324a a transfer reset pulse with the frequency H / 1/2 for the coding switch 126, which is used in data transfer operations to generate a signal which is used in encoder 96 to reset the sync word insertion circuit.

The H drive signal and the picture index signal are fed into a drive servo synchronous generator 330 fed, the output of which via a line 332 to a driver synchronous switch 331 is coupled. This driver sync switch 331 provides the basic Driver sync signals on line 334 for disk drive units 73, it is controlled by the computer control system 92 via a control line 333.

The sync signals are necessary for all operations in which the information is transferred between a disk stack 75 and the signaling system will. The computer control system 92 determines whether a record or a playback operation is desirable. The synchronous information is on the disk drive units leading lines 334 in the form of a multiplex sync signal, which is a set of three consecutive wide pulses with a rate of 15 Hz for indexing the first recorded or played back Field as well as horizontal sync pulses (with H-repetition frequency) contains and for Control of the spindle servomotor is used. For controlling the servo drive as well as for Generation of control signals during playback operations by the reference clock generator color image-related synchronous signals are still generated. These signals are generated by a color image generator 301 which generates the image index pulse at a frequency of 30 Hz via a line 327 and uses it to generate a color image signal divides by 2 at 15 Hz. This color image signal is fed via a line 329 to the Disk drive units 73 and sent to the reference clock generator 98.

A special circuit for performing the operations in the block diagram 11A is shown in FIGS. 43h to 43D, which together form a circuit diagram the reference logic circuits shows. Because the mode of action of those shown in these figures The circuit generally proceeds in the manner described above with reference to Fig. 11A, this circuit will not be described in detail. Regarding of the digital precision color synchronous phase detector shown in the upper part of FIG. 43A 307, however, it should be noted that the digitized video information is in the form of 8 bits input from the output of analog-to-digital converter 95 over lines 308 which are coupled to arithmetic logic stages 335, which in turn with Shift registers 336 are coupled. These shift registers 336 are through a generally designated with 337 logic, which is clocked by the precision color synchronous touch signal on line 307A and along with the arithmetic logic stages 335 for determining the sign of the phase of the digitized color sync signal perform the necessary arithmetic steps on line 309. The mistake from Sample values is determined by the quadrature component of the sample values investigates which one is equal to zero when the sample values are in the correct phase of the subcarrier signal were obtained. Specifically, the quadrature component is proportional for the function X1 - 1/2 (X2 + X3), in which sample values Y1, X2 and X3 are 1200 apart. The logic 337 executes the sequence that the arithmetic stages 336 to carry out the arithmetic calculation, activate either Plus or a minus signal generated on line 309, causing an error in the Phase of the actual sampling values is displayed.

The circuit of FIG. 43A further includes a circuit 324 for Generation of the PAL error flag signal on line 323, the H driver signal inverted by an inverter 342 and via a line 338 into the clock input a flip-flop 339 is fed, which is on an output line 340 through 2 split signal generated. This signal is fed into the input of a second flip-flop 341 fed by the color sync error flag signal on the line 328 is clocked. The line 340 and the output line 344 of the flip-flop 341 lead to a NAND gate 343.

The operation of the PAL error code generator 324 is described in the explained below with reference to the signal diagrams according to FIG. 11B. 11B shows (1) the high drive signal (line 326), Fig. 11B (2) the signal on line 340, Figure 11B (3) shows the signal on line 344; Figure 11B (4) shows the color sync error flag signal on line 328 and FIG. 11B (5) the output of the NAND gate on the Line 345. The PAL error flag signal on line 323 is due to the Effect of inverter 346 is the inverted signal on line 345. The PAL error flag signal occurs at a frequency of H / 2, which Fig. 11B (5) shows that it is is an unbalanced signal because that on the line 344 appearing and fed into the NAND gate 343 output signal of the flip-flop 341 is delayed with respect to the signal of the first flip-flop 339. This is stirring hence that the flip-flop 341 is not driven by the H drive signal, but by the Color synchronous error indicator signal is clocked.

Reference Clock Generator The reference clock generator 98 generates the basic Clock signals for the device for playback, data transfer, examination and other operations during which video input signals are not recorded, and uses the regenerated SC signal (3.58 MHz) transmitted by input circuit 93B is generated and passed through reference logic circuit 125B will. A phase shift option is provided in the reference clock generator, to shift the phase of the whole system, being a phase-locked loop as well as associated counters and logic circuits are provided to the timing signals with the desired system phase. It also generates control signals for the decoding and time base correction circuit 100 and the comb filter and ear domain inverter circuit 101.

The operation of the reference clock generator 98 is described below explained in more detail with reference to the block diagram according to FIG. 12A. The top half of this Circuit generates various timebase signals including multiple clock signals, while the lower half utilizing reference sync information, for example the color image sync information from the reference logic circuit 125B as well as image index and Horizontal drive signals from the reference signal input circuit 93B are the control signals generated for the comb filter and chroma inverter circuit. The signal becomes special SO fed into the reference clock generator 98 via a line 340 ', from which this Clock signals of the frequencies 1/2 SO, SO, 3 SO and 6 SC as well as various pulse-shaped Correction time base signals are generated as indicated on the right hand side of Figure 12A is. The reference clock generator 98 contains a circuit part which is generated by an operator, for example can be controlled by means of a dial 349, so that the phase of the output signals relative to the phase of the regenerated SC signal Adjustments can be made at the input by different amounts of phase shift introduced into the circuit and thus set the system phase during playback can be. Using that introduced in the reference signal input circuit 93B An operator can control the horizontal synchronous position control signal and the SC phase control signal the delay introduced into the playback signal channel in a wide range set and control in small increments.

The regenerated signal is used to control the phase of the SC signal SO divided at the entrance on line 340 by means of a divider 343 'which divides by 2, the output signal of which is carried on at two points on a line 344 '. This is once a programmable counter 345 'and further by a divider 346 'which divides by 2 and which is fed via a line 347 to a phase comparison stage 348 is coupled. A 10-bit BCD number is displayed on dial 349 a range from 0 to 399 is entered in the programmable counter 345 ', whereby the phase of the subcarrier in a range from 0 ° to 399 ° in increments of 1 ° is variable. The output of the programmable counter that is is a periodic signal, the pulse period of which in increments of exactly 1/720 of its basic period can be varied by dial 349, is converted into a Current switch 351a fed, which the current from a power source 351 two matched current sources 351 and 353 modulated. This modulated current is turned into a Low pass filter 354a fed one to the pulse period of the signal on the line 354 supplies proportional DC voltage.

A circle with identical DC voltage characteristics, which the further adapted current source 353, a current switch 353a and a low-pass filter 355a is generated a DC voltage on a line 355, which is proportional to the pulse period of the output signal of the phase comparison stage 348 is. The voltages on lines 354 and 355 are fed into a differential amplifier 356, the output signal of which is fed into the control input via a line 357 a voltage controlled oscillator 358 which is at a nominal frequency of 6 So swings. A number of divider levels 360 (division factor 6), 363 (division factor 2) and 365 (division factor 2) work sequentially on the output signal of the oscillator 358, whereby on a line 342 'a signal with a nominal frequency of 1/4 SO which is fed into the second input of the phase comparison stage 348 so that the pulse period of the signal at the output of the phase comparison stage varies with the phase angle between the input signals. In stationary conditions becomes the pulse period of the signal on line 352 due to the exact match of the current sources 351 and 353 and the DC voltage impedances of the filters 354a and 354b in a very small margin of error equal to that of the signal on the line 350 made.

A change in the pulse period of the signal at the output of the phase comparison stage 348 of 1/720 of the fundamental period requires a phase change of 0.25 ° between the input signals, which have a frequency of 1/4 SO. This in turn does a change of 10 is required between lines 340 'and 361 on which the frequency is equal to 1 SO. By changing the value by 1 through the dial 349, a phase change of 10 of the SC signal on line 361 is generated. The total range of the phase comparison stage 348 (1800 at 1/4 SC) corresponds to 7200 at 1 SO.

For convenience, the dial is limited to 3990, however, this gives a sufficiently wide range of possibilities in terms of the necessary 3600 is ensured.

The voltage controlled oscillator 358 provides on its output line 341 'the phase-continuous clock signal with a frequency of 6 SO and in combination with the divider chain 359, 360 and 363 phase-continuous clock signals with frequencies of 3 SO, SO and 1/2 SC at the outputs shown in Fig. 12A. The dividers deliver furthermore clock signals with frequencies of 3 SO and SO for a logic circuit 362, which for the time base correction circuit 525 control signals in the form of a continuous phase Write / read clock with the frequency SC, a write control clock, a demultiplex clock and a multiplex clock. The circuit diagrams according to FIGS. 44A to 44D as well as the Signal diagram according to FIG. 12B explain the mode of operation of an embodiment of FIG Logic circuit 362 for generating continuous phase time base correction clock signals with the necessary temporal context.

In the lower part of the circuit of the block diagram of FIG. 12A a signal of frequency H / 2 related to the horizontal synchronizing signal is generated, which is synchronous with the continuous phase signal 3 SC passed through the upper Part of the circuit is generated. This puts a person in the right position relative to the Reference horizontal sync signal generated. As shown in the following from the description of a clock back circuit 367, which the H / 2 signal in relation to to the SC signal requires maintaining the N / 2 signal in one fixed position with respect to the horizontal synchronizing signal and the setting of this Signals that it is in the first line of the first field of each sequence of two Fields (which corresponds to the insertion of the sync word in the video signal), a frame rate phase inversion of the clocking circuit 367 controlling Clock signal with subcarrier frequency, related to the / 2 signal to redefine the phase of the SC signal. By the subsequent reverse cycle of the newly defined H / 2 signal with respect to the phase continuous 3 SC clock signal in circuit 367 and the use of the H / 2 signal thus obtained in the time base correction circuit 525 for correcting a repeatedly reproduced color video signal consisting of only is composed of two television fields, a picture-picture motion of 46 Nanoseconds (half period of the 3 SC signal) of the H / 2 signal relative to the reference horizontal sync signal newly generated. This movement arises because the clocked back and redefined H / 2 signal incorrectly positioned relative to the correct horizontal synchronous position in every second image which causes the time base correction circuit 525 to use the sync word in every other image by a corresponding amount of half a period of the 3 SC signals incorrectly positioned. As can be seen from the following description of the sync word insertion circuit part of the encoder 96 results, the sync word with the frequency H / 2 in every second Image of the video signal inserted at a point which is half a period of the SC signal is shifted from the point which the reference horizontal sync signal is equivalent to. This is because the sync word insertion circuit for each Reset the picture and insert the sync word in the first line of each picture it should be noted that the first line of consecutive images is a Contains anti-phase SC signal. The time base correction circuit eliminates this Offset except for the aforementioned half period of the 3 SC signal. A following Image delay detector 368 generates an image delay switching signal for use of the digital-to-analog converter contained in the circuit 102 for correcting a such movement. It is also undesirable to have a positive jump of the not newly defined H / 2 signal exactly with a jump of the Subcarrier in the back-clocking circuit 367 coincides, because then a time ambiguous newly defined H / 2 signal for the time base correction circuit 525 is generated, which leads to errors in the time base correction.

To one with respect to the phase of the phase-adjusted, phase continuous To generate a defined H / 2 signal, the subcarrier signal is generated by the divider 360 supplied SC signal coupled to an input of a phase inverter 399, which is formed by an exclusive OR catter. The other input of the phase inverter is coupled to an input line 396a via a NAND gate 397, via which a pulse-shaped color image signal of 15 Hz is input.

The level of the pulsed color image signal at the input of the phase inverter 393 sets the phase of the SC signal at the output of the inverter, with a high Level is inverted and a lower level is not inverted. The inversion of the phase of the SC signal is necessary because it is phase-coherent with the horizontal sync signal H / 2 signal is required. (In the recorded video signal, for all images of the video signal in the same lines a sync word used, whereby it in the present device around the odd-numbered lines of an NTSC television signal forming 525 lines.) Without reversing the phase of the SC signal, the Phase of the newly defined H / 2 signal with a frequency of 15 Hz with respect to change the horizontal sync signal by half a period of the SC signal. Such a thing H / 2 signal is not suitable as a reference for processing reproduced Video signals in playback operations.

The 30 signal at the output of the phase inverter 393 is fed into the clock back circuit 397 and together with the reference horizontal '? Friction signal on a Line 396 and the Image index signal on line 395 for Used to generate the H / 2 signal defined with respect to the phase of the SC signal. The back-clocking circuit 367 contains logic that ensures that a temporally ambiguous H / 2 signal is generated, which with respect to the phase of the SC signal is defined.

The output of the clock back circuit 367 is fed into the frame delay detector 368 fed, which on a line 369 the image delay switching signal that determines the first or second playback of a reproduced image. This picture is composed of two television fields or one full picture, so that the clock generator circuit for the digital-to-analog converter detects whether a additional half period of the 3 SC signal offset against the clock of the digital-to-analog converter to correct the above-mentioned image-image movement of the H / 2 signal of 46 nsnoseconds is required.

The newly defined H / 2 signal generated by the clock back circuit 367 appears as a pulse-shaped signal on a line 368, which is via AND gates 370 and 371 on line 372 is clocked to be used as a reference signal in the basic Time base circuit to be fed. A control signal is then sent on a line 373 fed from the control signals from the computer control system 92 via the coding switch 126 is delivered. During playback operations, a appears on line 373 Signal high, the playback H / 2 signal on line 386 being the AND gate circuit 370 turns on and thus appears on line 372.

For other operations, for example purely electronic operations and transfer operations in which video signals in a playback channel are processed will be through the clock back circuit 367 generated H / 2 signal not used. In purely electronic operations is continuous Time base correction not required as the video signal does not have any recording and is subjected to reproduction process. To switch off the phase reversal of the SC signal is therefore the one from the control signals of the computer control system 92 through the coding switch 126 generated E / E or P-B command via a line 398 into the reference clock generator 98 which is assigned to the selected playback channel. The phase inversion is switched off via a NAND gate circuit 397, which a signal with provides a low level for the second input of the phase inverter 393. Farther the E / E or P-B command is coupled to a logic circuit 399, which provides a corrected I / O shutdown signal that enables the Time base correction circuit 525 will operate for about 10 lines at the beginning of each color image can and thus the correct time base correction for each color image or every 15 Hz generated. The time base correction is necessary because the synchronous word generator during the sync word insertion process for E / E operations on every two fields, i.e. it is reset for every picture. This leads to a discontinuity of one half period of the SC signal in the position of the sync word for every second picture or for each 15 Hz.

When performing a transfer operation through a playback channel is in line 373 of the reference clock generator assigned to the playback channel 98 a low level signal is input. The AND gate circuit 374 feed a transfer H / 2 signal on line 375 into an OR gate 371, which couples the transfer H / 2 signal onto output line 372. This transfer H / 2 signal will derived from the sync word insertion part of the encoder 96.

An output pulse from encoder 96 which coincides with the sync word or the line identification serves as the time base correction reference signal. This Pulse is fed into a shift register delay stage 377 via line 376 fed in, which puts him in the right position. The transfer H / 2 signal becomes positioned so that that which is input to decoder 96 during a transfer operation digitized video signal a properly identified location for the onset of a owns new sync word. A special circuit to perform the operations of the block diagram of Fig. 12h is shown in Figs. 44A to 44D.

The operation of this particular circuit is not detailed as it performs the operations already described with reference to Fig. 12A. For the generation of the H / 2 signal, without any ambiguity in relation to the SC signal is redefined, the clock back circuit 367 includes an H / 2 signal generator 378 with a counter dividing by two and a subsequent pulse shaper, which by an edge-triggered flip-flop or a subsequent self-resetting Flip-flop can be formed. The counter takes H driver signals at its clock input from input line 396 and provides an H / 2 signal at its output. This The H / 2 signal is generated by the pulse shaper of the H / 2 generator with every positive jump converted into a series of negative impulses. The picture index signal is set at 30 Hz the counter of generator 378 at the beginning of the first field of each television picture back so that the phase of the H / 2 signal at the time of the first line of the first Field of every television picture is the same.

The SC signal provided by the phase inverter 393 continues to be converted into a train of negative pulses by a pulse shaper 393a. A Pulse coincidence detector 378a, which is followed by a AND gate and a following D flip-flop is formed represents a coincidence of the Related to jumps of the SC signal pulses of the pulse shaper 393a and the Jumps of the H / 2 signal related pulses from a timing selection circuit 379 as Function of each negative pulse determined by the pulse shaper of the generator 378 is delivered. If there is a positive jump to the one supplied by the generator 378 H / 2 signals too close in time to a positive jump in the SC signal, so overlap the aforementioned pulses in the coincidence detector 378a in time, resulting in a Tilting the D flip-flop of the detector results. By tilting the flip-flop, the Level at the input of an exclusive OR gate 379a in the time selection circuit 379 changed, making this between its inverting and non-inverting operation is switched. The time selection circuit 379 includes a self-resetting one Edge-triggered flip-flop 379b, whose clock input is connected to the output of the exclusive 0DER gate 379a is coupled. By selectively inverting or not inverting the negative pulses supplied to the H / 2 signal generator 378 becomes the positive edge of the pulsed output signal of the exclusive OR gate relative to the SC signal pushed. The time selection circuit 379 works with the coincidence detector 378a together to the positive edge of the output pulse of the exclusive OR gate 379a so that there is always a redefinition of the H / 2 signal without ambiguities results.

The H / 2 signal is redefined by clocking back the edge-triggered Flip-flops 376a, the reset input of which is connected to an output of the time selection circuit 379 and its clock input to the phase inverter 393 for receiving the SC signal is coupled. Everyone on a jump of the H / 2- Signal related Pulse resets flip-flop 367a, with the immediately following positive Jump of the SC signal at the clock input changes the switching state of this flip-flop, whereby the newly defined} i / 2 jump is generated. A following flip-flop 367b couples the newly defined H / 2 signal to a delay circuit 391 which passes through a counter and a subsequent shift register is formed, which the Correctly timed H / 2 signal on line 380 into the frame delay detector 368 feeds. The newly defined H / 2 signal at the output of the flip-flop 367b is used to reset the delay circuit 391 while an SC signal is on a line 392, which is in phase opposition with respect to the signal used for the clock back circuit 367 is, the delay circuit clocks to the newly defined H / 2 signal for the Detector 368 to generate.

The image delay switching signal appearing on line 369 of Fig. 44D, the level of which changes every other picture is used in the video playback output circuit 127 for adjusting half the period of the 3 SC signal in the above sense. The operation of this part of the circuit will now be described with reference to FIG. 12C explained.

The signal on line 380 is a pulsed signal of frequency H / 2, the one with no ambiguity as to the phase of the regenerated SC signal was redefined.

The regenerated SC signal is in turn in every other picture inverted to ensure that the newly defined H / 2 signal is stationary with respect to to the H sync reference signal. This newly defined H / 2 pulse is through a continuous 3 SC signal on line 394 into the shift register 381 clocked in and appears on the first output line 385 delayed and on the 3 SC signal is synchronized. Since the continuous 3 SC phase clock is an odd one A multiple of half the frame rate is different his Phase with respect to the H sync reference signal during the first frame around 1800 of its phase at the same time during the next picture so that it is also differs from picture to picture with regard to the newly defined H / 2 pulses around 1800. Due to this 1800 phase difference, the positive jump of the 3 SC clock signal shifts half a period from picture to picture relative to the newly defined H / 2 pulse, whereby the timing of the shift register 381 relative to the occurrence of the stationary H / 2 pulse changes from picture to picture by half a period of the 3 SC clock signal. To the Relationship between the newly defined H / 2 signal and the continuous phase 3 SC clock signal is determined from the positive jump of the newly defined H / 2 signal generates a stationary pulse and is used by the D flip-flop 368a for determination determine the phase of the 3 SC clock signal at the beginning of every other frame and the phase-indicating image delay switching signal on line 369 according to FIG. 12C to generate. Specifically, the pulse shaping circuit generated by a Inverter 382, resistor 386, capacitor 387 and NAND gate 389 is formed, from the leading edge of the H / 2 pulse on a stationary pulse the line 380 at the input of the shift register 381. The stationary pulse has an interval of 3/4 of a period of the 3 SC signal, with its leading edge (likewise like that of the H2 pulse) the positive jump of the newly defined H / 2 signal is equivalent to. Since the shift register 381 by the phase-locked 3 SC clock signal is clocked, the pulse appears on an output line 385 of the shift register at different times relative to the occurrence on input line 380 what depends on the phase relationship of the newly defined H / 2 signal and the 3 SC signal. When the signals are in phase, the H / 2 pulse appears on line 385 one period of the 3 SC signal after its presence on the input line 380

If the signals are not in phase, the H / 2 pulse appears on the Line 385 earlier by half a period of the 3 SC signal. The signal level on the Line 385 is triggered by the positive jump of the stationary pulse on the line 384 is keyed into the D flip-flop 368a, the pulse on line 384 being a 3/4 period of the 3 SC signal after the occurrence of the newly defined H / 2 pulse occurs at the input of the shift register. The output of flip-flop 368 on line 369 indicates whether the H / 2 pulse on line 385 is after a delay of 3/4 period, which determines whether the time delay between the positive signal jumps on lines 394 and 385 half a period or is a period of the 3 SC signal.

This signal on line 369 in turn leads to the digital-to-analog converter clock influencing offset of half a period of the 3 SC signal, thereby reducing the above-mentioned image-image movement of 46 nanoseconds of the newly defined H / 2 signal is compensated.

The frame delay switching signal appearing on line 356a in Figure 44D is a signal that changes its level in every second image and is used in the comb filter and chroma inverter circuit 101 for inverting the reproduced video signal chrominance component contained in alternate reproductions of the color video signal is used with two fields. The playback burst is through the data transfer circuit 129 is provided on output lines 361a and through the Exclusive OR gate 362a in phase with the continuous phase SC signal compared.

The SC signal and the playback burst signal alternate between alternate reproductions of the color video signal with two fields between the States in phase and out of phase, reducing the level at the output of the exclusive OR gate 362a with the Color burst occurring change is changed with a frequency of 15 Hz. The picture phase inverter switching signal is activated by clocking the output of the exclusive OR gate 362a through a Flip-flop 363a with the correct timing for each color sync error flag signal clocked.

The flip-flop 364a takes at its D input that through the reference signal input circuit 93b supplied color sync error flag signal and is made by the phase continuous 50 signal, which is fed into its clock input by the divider 360. Whenever a color sync error flag signal is on input line 360a is present, the flip-flop 364a supplies a pulse to the flip-flop 363a, the with respect to the phase of the SC signal. This pulse is used for clocking of the level at the input of the flip-flop 363a to its output. Because the level at the input of the flip-flop 363a with alternating reproductions of the color sync signal changes two fields, the level at the output of the flip-flop 363a also changes with alternating reproductions to the picture phase inverter switching signal with 15 Hz on line 356a which determines whether the chrominance component should be inverted in the comb filter and chroma inverter circuit 101 or not.

Coding switch The one described with reference to the block diagram according to FIG. 9A Coding switch 126 is connected to the computer control system 92 and performs when receiving of the corresponding command signals a basic selection function, with either in the case of recording operations, the data sequences from the analog-to-digital converter 95 or in the case of transfer operations, the data sequences coming from the data transfer circuit 129 to be selected. In transfer operations, the image is taken from a disk drive unit transmitted to another so that the video information passes the comb filter and chroma inverter circuit 101 does not go through. Instead, it is led to the coding switch 126, to then be encoded and recorded on another disk drive unit will. The coding switch 126 also switches between the corresponding clock signals, i.e. between the 6 SC and 1/2 SC signals. It switches the through the reference logic circuit 125A generated clock signals which are used when the video information from the Analog-to-digital converter 95 is recorded. Switches during transfer operations he the 6 SC and 1/2 SC signals supplied by the reference clock generator 98, which are used as basic reference clock signals during recording of the transferred Video signal can be used. These functions are from the block diagram according to 9A can be seen.

In addition to the switching functions of the correct reference signals the code switch also provides other functions, which depends on whether regular recording operations or transfer operations are carried out. There are circuits for generation a blinking cross image display signal available, one of which is a diagonal line through one field and the other diagonal line is supplied by the second field. This makes it possible to display that the track is deleted and is available for taking a picture at this particular location. The coding switch further includes a circuit which generates a PAL switching signal. This signal ends the phase reversal during the transfer process, whereby it is applied to the data transfer circuit 129 is transmitted, which is normally the one for the comb filter and chroma inverter circuit 101 led th signals reversed in phase. The phase reversal by the transfer circuit is stopped because the sample values are not aligned during a transfer operation line to line is required. The coding switch also contains a circuit to carry out examination operations, which selectively a repetitive Frequency of data information and an optional word for use in one generated such an examination process.

13A to 13D, which together are a circuit diagram of the coding switch 126 show, the data bits occur on sets of input lines 400 or 401, there are eight lines for each set representing the eight bits in the data stream from the analog-to-digital converter 95 or from the data transfer circuit 129 correspond. Lines 400 comprise the eight data lines from converter 95, while the Lines 401 collectively the 8 bits of video information from the data transfer circuit 129 represent. The input lines are to multiple multiplex switches 402 coupled, which are controlled by signals on lines 403 and the information from the lines 400 or 401 to an output line 404. The multiplex switch 402 also lead with a corresponding command those forming the Bllnkkreuzsignai Bits or those bits which define the data for investigation purposes.

For deleting information in a track on a stack of discs the blinker cross signal is in the lane above the to information to be deleted recorded. At the output of the coding switch 96 either the blinker cross signal, Examination data or the transfer or originally digitized video information delivered.

As Figure 13B shows, this is from reference logic circuit 125A delivered 6 50 signal is available on a line 405, whereby from the reference clock generator 94 a corresponding reference-related 6 50 signal is supplied on a line 406 will. The 1/2 SC signals from reference logic circuit 125A are on one line 407 are available, while the reference-related 1/2 SC signals from the reference clock generator 98 can be fed in on a line 408. For selective switching of the 6 SC and 1/2 S5 signals from either reference logic circuit 125A or the reference clock generator 98 a number of uND gates 409 are provided on the output lines 410 and 411, the 1/2 SC and 6 SC signals in encoder 96 being used. In recording mode a reference selection signal activates the AND gates 409, which the 6 SC and 1/2 SC signals on lines 405 and 407 from reference logic circuit 125A obtain. During other operations, i.e. when deleting data, during investigation operations and during data transfer, the reference selection signal activates AND gates 409, which the 6 SC and 1/2 SC signals over lines 406 and 408 from the reference clock generator 98 received.

Referring to Fig. 13C, reset pulses become from the video input circuit 93A and reference logic circuit 125B on lines 412 and 413, where one of these lines can be switched through by AND gate 414 to generate a reset pulse on a line 415 to generate. The line is doing this as a function of the in one Flip-flop 446 clocked reference selection signal switched through. The reset pulse serves for resetting the synchronous word generator circuit in the encoder 96. The through the Video input circuit 93A as well as the input image signal provided by the reference logic circuit Transfer ID reset signals supplied to 125B are used as reset pulses. Accordingly, V-drive pulses Wr. 2 and no. 1, which by the synchronous generator circuit the video input circuit 93A and the reference signal input circuit 93B, respectively are placed on input lines 416 and 417, one of these lines being over AND gate 418 switched through to line 419 by the clocked reference select signal to be used in the sync word generator circuit in encoder 96. The V drive pulses continue to be placed on line 435 to generate of the lane blinking signal by circuit 420. These in the following Circuit 420 to be described is shown in dashed lines in FIGS. 13C and 13D.

Several connections designated by 421 in FIG. 13D are used for coupling to an external input, a generator 427 for generating a repetitive Data word or a generator 429 for generating an optional location, where the control is carried out by the synchronous word switching signal that is generated by the in the encoder 96 contained synchronous word generator circuit is supplied on a line 429A.

Data select signals provided by computer control system 92 on input lines 422 form a two-digit command which is used to set the multiplex switch via the lines 403 in the correct state for the type of operation of the device serves. A tactile control signal also coming from the computer control system on a Line 448 samples a pair of flip-flops 449 to put the two-digit command on to bring the lines 403 leading to the multiplex switches 402. The groped command is also fed into a NAND gate 423, which is on a line 424 Provides a signal that determines whether the device is in a transfer operation or in normal recording operation works. In the case of a transfer operation, a delivers NAND gate 425 (Fig. 13D) the PAL switching signal for switching off the phase switching in the transfer circuit 129. The other input of the NAND gate 425 is from to reference logic circuit 125B on line 426, a PAL error flag signal fed in.

The circuit 420 for generating the lane blinker signal is in following with reference to the block diagram of FIG. 13E and the view of two Fields of a television picture shown in Fig. 13F explained. Fig. 13F represents a visual representation of the deleted data signal. A horizontal counter 430 counts down from a pre-counted value as a function of an 80 H cycle, which, for example, from the synchronous generator circuit of the reference signal input circuit 93B is supplied and fed in via a line 431. The freedom of the 80 H-beat is equal to 80 times the frequency of the reference horizontal sync signal. The horizontal counter 430 is preset by an H driver signal during each horizontal line, received from reference signal input circuit 93B over line 428 (Fig. 13D) and is input to the counter via line 432 as an input. A Vertical counter 433 counts up and down as a function of the H driver signal, that via the gate circuit 434a (FIG. 13C) via the input line 434 in this Meter is fed. The vertical counter 433 is after every other field preset by a preset command which is transmitted via line 447 and a dividing by two flip-flop 436 is fed. The preset command is generated from the V drive signals transmitted by the reference signal input circuit 93B can be supplied via line 417. The V-driver signals run from one the AND gate 418, which is effective by the flip-flop 446 in the sense described above is switched (Fig. 13C and 13D) to line 435, which is at the input of the flip-flop 436 leads.

To create a favorable geometric shape for the blinker cross is at the input of the vertical counter 433 a divider stage 438 dividing by 4 coupled, so that 4 H driver signals are required to read the count of the To change the vertical counter. The divider stage 438 dividing by 4 is expedient formed so that the output of the vertical counter 433 by two bit positions is shifted, the output value of which changes both in the upward and in the Down counting changes every fourth H drive signal.

The horizontal counter 430 and the vertical counter 433 are digital Comparison stage 437 coupled. A line width generator is attached to this comparison stage 439 coupled, its digital output signal in the above mentioned multiplex switch 402 is fed.

Referring to Fig. 13F, the television picture is divided into an X and Y matrix. For example, the horizontal direction is divided into 80 counts, while the vertical direction is divided into a number of counts which are those contained in one field Lines corresponds. When the horizontal counter and the vertical counter have the same counts assume, the comparison stage 437 determines and generates a coincidence point a "?" output pulse, which corresponds to a white level. Will not be a coincidence detected, the comparison stage generates an "on" or a black level. The two counters 430 and 433 are set via their respective preset inputs in front, whereby in these inputs the H-driver signal resp.

the V-driver signal can be fed. The latter signal will divided by a factor of 2, so that the vertical counter 433 every other field is preset.

The horizontal counter is in the first television line of the first field 430 clocked by the 80 H cycle from 0 to 80. The divisor level dividing by 4 438 as well as the vertical counter 433 are indicated by the first line 1 Clock pulse of the H driver signal is incremented, with coincidence between the output signals the counter occurs when the horizontal counter clocks the first clock pulse.

This defines point 1-1, which is in the upper left corner of the grid of horizontal lines forming the displayed field.

The line width generator 439 includes a counter 443 which is a given number counts in order to put a logical "1 n" on the data bit lines, which corresponds to the white level. This creates a short line segment from the starting point the coincidence at 440 in Fig. 13F. As the input signal of the vertical counter divided by 4, there are 4 H drive pulses to be incremented further this counter required after this counter by the first H-drive pulse is clocked from its preset counting state. Hence, there will be four television lines scanned at the same output pulse of the vertical counter 433, with the lines 1 to 4 coincide with the first clock pulse of the 80 H clock if the duration the television line is counted. Therefore, in four adjacent television lines become four short side-by-side line segments 440 are generated. When receiving the the fifth H drive pulse, the vertical counter 433 is incremented by one count, with short for the next four H clock pulses for a further four horizontal lines Line segments are generated, but in the counting cycle of the horizontal counter 430 occur one count later.

This leads to the creation of a diagonal sequence of diamonds, which define a diagonal line 441. To every fourth horizontal line the H driver signal increments the output signal of the vertical counter by one Count (to count 2, etc., for the interval of the next four television lines). The 80 H clock increments the horizontal counter 430, with coincidence in the point 2 occurs during lines 5 to 8, in point 3 during lines 9 to 12, and so on. The process continues with the point of coincidence moving along the diagonal, until the diagonal line 441 with the television lines 261 to 262 in the lower right Corner of field 1 ends. No output signals are generated at this point, since this is the time period corresponding to the vertical interval.

The opposite diagonal line appears in the second field 442 corresponding data is inserted into the signal. The diagonal lines 441 and 442 are drawn through alternating fields in order to be easily visible when played back Generate blinking signal with 30 Hz and a display of the recorded blinking cross signal to ensure.

For this purpose, the vertical counter 433 is at the end of the first field held at its count. Due to the timing of the flip-flop 436 by a another V drive signal on line 435 switches at the end of the first field the catter circuit 434a the high drive pulses on the other input line 434 for the divider stage 438 dividing by 4 and the vertical counter 433 (FIGS. 13C and 13D). The vertical counter 433 now counts back from its coincidence point count. For the second field this corresponds to the upper right corner (corresponding to the lower right corner of field 1) what is displayed on a monitor. There the scanning of the field raster always at the top of the displayed raster of horizontal lines begins and the lines are scanned sequentially to the bottom is the first full scanned Horizontal line the top of the displayed grid of forming field 2 of Fig. 13F Lines.

The horizontal counter 430 is unaffected by the V drive signal and continues to count the received 80 H signal.

The divider stage 438 dividing by 4 and the counter 433 are not increments until the horizontal drive pulse is at the beginning of the fourth full line is received, which corresponds to line 267 in the second field. During this Line counter 430 counts until it reaches a count of 79, whereby Coincidence with the vertical counter 433 occurs. The comparison stage then generates 437 a logical "1" bit, which is entered into all data bit lines via the multiplex switch 402 is entered (white level). The line segment length is determined by the line width generator 439 established.

The rhombs are drawn along the opposite diagonal in the picture, whereby the diagonal line 442 running from right to left arises, since the Vertical counter counts down, making each subsequent coincidence earlier than the previous one Coincidence occurs. Since the vertical counter 433 does not appear until the fourth full line is incremented, the diagonal line 442 is slightly from the true diagonal shifted to the left. However, this slight shift is for the purpose of the flashing cross insignificant and not detectable for an observer if the Ad is not viewed very closely.

The divider stage 438 dividing by 4 as well as the line width generator 439 are used to determine the angle of the diagonals and to form the rhombuses, which form a thicker more symmetrical line. The aforementioned conditions result from the available limited input signals such as the 80 H signal. For example, if a 262 H signal is available, this results in one Matrix of 262 to 262 grid points, with the horizontal and vertical counters 430 or 443 can be designed so that a common incrementing takes place, while the diagonal lines 441 and 442 are drawn from one corner to the other, without a mathematical compensation, for example by dividing by 4 Divider 438 is required.

The display with fields lying one below the other facilitates understanding the creation of diagonal line 442 of field 2 upon creation a display from top to bottom and from right to left. The fields are however actually interleaved on the same television display device so that the diagonals are superimposed from field to field to form the blinker cross are.

The output of the line width generator 439 is fed into the multiplex switch 402 according to FIGS. 13A and 13B, which generate a digital erase data word, that in the device in question corresponds to a timed sequence of the white level 1 "bit. An output line 444 of the row width generator 439 is used for a parallel pass through the switches 402 to the output lines 404 selected, what by the two-digit command signals via the flip-flop control lines 403 takes place in the sense described above. The erase word on lines 404 forms an input signal to the video recording system and is used to record like the video signal coming from the analog-to-digital converter 95 over the lines 400 or 401 processed. The flashing cross signal is recorded on a track, if a previous one Record is erased and provides a visual indicator for one to be taken of a video signal to be recorded. Becomes a playback request initiated by a track identified in this way, the erase signal and so that the blinker is queried and displayed in the same way as a picture of the stored video signal.

The various components 430 to 439 and 444 of the block diagram 13E are shown in the circuit diagrams according to FIGS. 13h to D, with the same Reference symbols denote corresponding components. The horizontal counter and the Vertical counters 430 and 433 are formed by two 4-bit counters, with the output signals of the vertical counter 433 are shifted by two bit positions to achieve the divider function by the factor 4 in accordance with block 438 of FIG. 13C. The digital Comparison stage 437 supplies the counter when a coincidence point is determined 430 and 433 a carry pulse, while the line width generator 439 via the Line 444 provides the white level output for a selected period of time, which corresponds to the preset count value of the counter 433. This period corresponds to the desired length of the short line segments 440 (Fig. 1dz), which the rhombuses of diagonal lines 441 and 442 form. The digital (8 bit) delete word is in the above described sense via the (8) output lines 404 of the multiplex switch 402 delivered.

The circuit 420 described above can be used in place of a flashing cross also generate other geometric shapes or images for the erasure data signal, where part of the display can be generated in one field while the remaining Part in the other field is generated with an easily visible flashing signal a frequency of 30 Hz.

The entire display can also be generated in one field, if a blinking effect is not desired. However, the coding of the erasure data signal makes it easier in the sense of generating a visible blink signal, generating a defined one Erasure trail signal, as displays of visual information typically do not flicker. For a video image storage device, the blinking effect is expediently achieved by splitting of the parts of the erasure data signal in generated the two television images, which are recorded in the cpur of deleted data. To reduce the Repetition frequency of the deletion data signal and for generating the blinking effect can also other techniques may be used, for example one of the two television fields can be coded with the complete cross, while the other field is information-free is.

In addition to a visual display, other types of display can also be used are provided. For example in a video storage system in which audio signals Recorded in video tracks, the playback data erase signal can be heard as audible Be displayed. In a computer-oriented data storage system with a Sequence of deleted data areas, the computer can be designed so that it interrogates the erased data signals recorded in the erased tracks and establishes, with an electronically detectable display provided if necessary is.

In the system described here, the indication is visual, with the deleted data word is queried during playback.

Encoder The encoder shown in the block diagram of Figure 9A 96 of the video signal system contains circuits which, in addition to the coding of the digitized Data of the 8 video data bit lines, the parity bit and the data track sequence additional Functions. One of these additional functions is a parity generator used to perform a parity check to determine that the data are correct on all 8 data bit lines. The parity bit is optional and required an additional data bit line, which is available in the device described here stands. The encoder 96 also generates the sync word (also as a line identification labeled) and causes its insertion. This sync word is in the form of a seven-digit binary number, which is generally there in alternating television lines is introduced where the horizontal sync pulse was previously. Be it noted here again that the horizontal sync pulse through the video input circuit 93 was separated from the composite video signal. The sync word is in a range of 1 SO that previously occupied by the horizontal sync pulse Place used, the encoder 96 the sync word in each of the 8 video data lines, the parity bit line and the data trace line are used before the encoding is performed so that the output of encoder 96 fed into the disk drive interface circuit 98 is fed, the sync word in each of the recorded on a disk stack 95 contains ten data sequences. (During purely electronic operations, this output signal is input to playback channel 91.) How the encoder works 96 is explained below with reference to the block diagram of FIG. 14 and the circuit diagrams 45A to D described. NRZ-L data from coding switch 126 are transmitted via an input line 450 is entered and can be removed from an output line 451, after firstly a parity check has been carried out, secondly the synchronous word was inserted in every second (odd) line and, thirdly, an encoding in A format was implemented that was used for recording and playback of digital Information in connection with one of the disk stacks 75 is suitable. The input data on each data bit line are applied to one input of a data input AND gate 452, which is connected to a channel encoder 453. This channel encoder can be switched between two coding formats, which will be discussed below to be discribed. In the circuit diagrams according to Fig.

45A through D are identical channel encoders for two video data bit lines shown in its entirety. Below this shown in its entirety Coders are further identical channel coders for the other video data lines, the parity data line and the data lane line in dashed borders shown. A sync word input AND gate 454 on each of the ten bit lines is used for the correct timing of the synchronization word in the encoder, this AND gates are also used to insert a test signal into the ten bit lines, this test signal, if necessary, by a suitable test signal source, for example a digital test grid generator is provided over line 450a (Figures 45A and 45B) will. A first clock generator 455, which receives input signals 6 SO and 1/2 SO receives, provides output signals SO and in the manner shown 3 SO. Two of the three SC output signals are fed into one via lines 472 and 473 second clock generator 456 fed in, which offset two times against each other 3 SC clock signals on two lines 474 and 475 for clocking of Channel encoder 453 provides. The clock signal on line 475 is a 1 clock, the offset by half a period of 3 50 from the clock signal on line 474 which represents a p 2 clock. Bci recording operations are these Time-shifted clock signals from the 6 SO and 1/2 SC signals with continuous Phase derived which is generated by reference logic circuit 125A and over the coding switch 126 can be given to the encoder 96. In other operations, For example, the reference clock generator delivers when the cross-blinking clear signal is recorded 98 these clock signals. These 1- and 2-3 SO clock signals are used to control the Channel encoder 453 in the sense that on the output line 451 a continuous channel-coded digital signal is generated without phase discontinuities.

The clock generator 455 supplies an SC clock signal on an output line 471a for controlling a divider 457 dividing by 455, which by a a line 463 supplied by the coding switch 126 reset pulse with a frequency can be reset from 30 Hz. This divider 457 sets a flip-flop 458 via a start line 464 and resets this flip-flop 458 via a pulse on a stop line 465. The start and stop impulses define a window in which one of the output of a Single seven-digit binary synchronous word supplied by the synchronous word generator 459 can be inserted into all data bit lines at the same time.

During the vertical blanking interval, a pulse becomes monostable Given flip-flop 460. This monostable multivibrator is for a period of about 10 lines of the vertical blanking interval are active, whereby the value set by the coding switch 126 Vertical blanking pulse supplied via line 466 to an input of a gate 461 (an OR gate in the present block diagram) is given, the other Input with the output of the window flip-flop 458 fed will. The output signal of the OR gate 461 is sent to the other input of the AND gate 454 and via an inverter 462 also to an input of the AND gate 452 given.

In operation of the encoder 96, the data sequence for each bit should be an input, for example the input line 450, which is a represents the 8 separate data input lines, these lines at each have an encoder 453 and the associated AND gates 452 and 454 and the Inverter 462 are coupled. There is also a data output line for each data bit 451 is present so that the data sequences can be correctly encoded and the sync word can be used. Because the sync word is very close to the point of the previously existing horizontal sync pulse is to be used and there If no interference is to occur with the data of the data sequence, the channel encoder 453 leading data bit lines during the insertion of the sync word in the windows generated by divider 457 and flip-flop 458 through the data input gates 452 switched off. Specifically, the divider 457 provides a start pulse for setting of flip-flop 458, whereby one input of each AND gate 454 is activated while each AND gate 452 is disabled, thereby disabling data entry is blocked via the lines 450. Twelve data bit intervals after creation of the start pulse, the divider 457 supplies a pulse for the sync word generator 459, which then generates a seven-digit binary word that goes into the upper input of all AND gate 454 is fed, which were previously activated. These AND gates 454 give the sync word to the channel encoder 453, in which it is in the Data sequences is encoded. 29 data bits after generating the sync word the divider 457 a stop pulse to reset the flip-flop 458, eliminating all AND gate 454 disabled and all AND gates 452 at the same time be activated so that the data on lines 450 in the channel encoder be fed in. It should be noted that the data is continuously on the lines 450 are pending and that by blocking the AND gate 452 only their continuation blocked. During the insertion of the sync word, the information becomes deleted in a certain sense. However, since the synchro word takes the place of the previous existing horizontal sync pulse is inserted, there is no active video information lost.

The monostable multivibrator delivers during the vertical blanking interval 460 an output signal for the OR gate 461, which for an interval of about 10 Lines is present.

Thus, the data input AND catter 452 becomes during an interval locked by 10 lines of the blanking period, so that the channel encoder during this No information received at intervals. The only data or logical 1 "bits, which during the interval of 10 lines of the vertical blanking interval to the Output lines 451 occur are those in the sync words which as already described above in every second line and the sync word catter 454 pass through. This ensures that the decoding and time base correction circuit 100 does not respond to an arbitrarily occurring sync word bit pattern during playback, but is set to the actual synchronous word. A random one Synchronous word bit patterns can be found in the active video information during the data flow to be available.

Another aspect of the operation of encoder 96 is discussed below described with reference to FIGS. 9t and 9B. The electronic data interface circuit 89, the data interface circuit 151 for the disk drive units and the data selection switch 128 couples the encoder 96, the disk drive units 73 and the decoding and time base correction circuit tOO. During a search, when the heads in the disk drive units 73 are running between the tracks it is desirable to avoid interference in the signal system. Usually delivers the recording signal processing system 88 at the output of its encoder 96 as well digitized data in the absence of an input video signal. That’s what it’s about noise information, the digital signal processing electronics of the However, there is no difference between digitized noise and digitized video information can distinguish. This fact is exploited when the device carries out a search operation performs. During the search operation, the transducer heads generate noise signals which with the digital data code format normally present in the signal system are compliant. Can such noise signals get into the playback channel 91, so become the phase locked loops of the decoder and the time base correction circuit 100 disturbed.

In order to avoid such interference, the data interface circuit 151 for the disk drive units (as well as in purely electronic operation) switched so that the output of the encoder 96 to the decoding and time base correction circuit 100 is returned. In this way, the decoding and time base correction circuit is obtained 100 encoded digital signals that form the corresponding phase-locked loops in keep this circuit 100 in its normal operating range. When the heads of the Disk drive units 73 are properly positioned and playback data in the Supply channel 91, so is the decoding and time base correction circuit 100 prepared to have the decoded and timebase at its output corrected To deliver signals.

The encoder 96 also serves to generate black level data for use in the sense described above when recording on the disk surfaces during the first two revolutions of the disk stack 75 prior to recording the video signal information in the subsequent two revolutions of the disk stack. A pre-recording line originating from the electronic data interface circuit 89 443 (Fig. 45A) is provided by the data interface circuit 151 for the Disc drive units activated signals supplied, creating a NAND gate 461 blocks any logical 1 present on the input lines 450, whereby the black level signal at the input of the channel encoder 453 is generated. The encoder 96 also inserts the sync word into the black level signal.

The NRZ-L data on data bit lines 450 are processed by the channel encoder 453 selectively encoded in the DC voltage-free, self-clocked channel code, the for example in a US parallel application (file number 668 679) or in the U.S. Patent No. 3,108,261. As will be described below, a code selector switch 480 with two positions selects between the two Channel codes off. In both codes, the NRZ-L data bit sequence is on a data bit routing divided into discrete bit times, commonly referred to as data bit cell times will. Run for the channel code described in U.S. Patent No. 3,108,261 the code rules for logical first bits, for example one logical each "1", which is generated by signal jumps at a certain point in the corresponding bit cells, specifically in the middle of the cell, as well as to logical second bits or to a logical "O" in each case, which is triggered by signal jumps at a certain earlier place in the corresponding places, especially at the beginning or are represented on the leading edge of each flitzelle. Everyone at the beginning of one Signal jump occurring at a bit interval, which occurs on a jump in its middle containing interval is suppressed.

In the case of the US parallel application mentioned above (file number 668 679) described channel code, the ring input data sequence in each data bit line can be viewed as a cascade of variable length sequences according to three types. The first type is sequences of the form 1111 --- 111 with any number of logical ones without logical zeros.

The second type is sequences of the form 0111 --- 1110 with any odd number of consecutive ones or without ones and one Zero in the first and the last digit. The third type is sequences of the form 0111 --- 111 with an even number of consecutive ones, those preceded by a zero. A sequence is of the third type only if that first bit of the next following sequence is a zero. Sequences of the first and second Type are coded according to the code rules of US Pat. No. 3,108,261. One Sequence of the third type is performed according to the rules of US Pat. No. 3,108,261 coded in such a way that all bits with the exception of the last one are equal to a logical one, the jump is simply suppressed for this logical one. on in this way a sequence of the third type appears in itself as one Sequence of the second type, i.e. the last logical one appears as a logical zero.

By definition, a sequence of the third type follows immediately a logical zero at the beginning of the next sequence.

A separation of a sequence of the third type from the following logical Zero by jumping is not possible.

Hence, this particular encoding is distinctive for decoding purposes. The decoder only needs to recognize that a logical one and a logical Zero must be output if two on a normally coded logical one Bit intervals follow without jumps. Other jump sequences are made according to the rules of the Miller code is decoded.

The coding process for this code requires that since the last preceding zero, which is not the end bit of a sequence of the second Type was, a modulo-2 count of the number of logical ones in the output signal of the encoder is maintained. If the count is 1 (odd number of Ones) and the next two bits to be coded are a one and a zero in this order, no jumps appear at the output during the next both bit intervals. If the next following bit is another zero, this becomes from its predecessor in the usual manner according to the teaching of U.S. Patent 3 108 261 separated by a jump. This code is suitable for the transmission of Data in binary form via an information channel such as a magnetic one Recording and playback system that does not transmit any DC voltage components can. The information is transmitted in a self-clocking manner.

In the code, it makes no difference which binary level is considered logical One and which binary level is considered a logical zero. With the one here in The facts in question are usually represented by jumps in the middle of the cell marked level is considered as a logical one, while normally by jumps the level marked at the cell edge can be regarded as a logical zero.

The channel encoders 453 shown in Figs. 45A to 45D operate according to the code rules explained above. Fig.

45E shows a timing diagram for explaining the operation of the in a data bit line 450 contained channel encoder 453. If the switch 480 in the position shown in FIG. 45B, the channel encoders 453 encode the data according to the code rules according to the above-mentioned US parallel application, while the data in the other wave of the switch according to the code rules above U.S. Patent No. 3,108,261 referenced.

The channel coder is described in the following in connection with the in Fig. 45B, the position of the code selection switch 480 shown, the channel coding one of the data bit sequences according to the code rules according to the above-mentioned US parallel application (File number 668 679) is encoded. An explanation of the differences in the mode of action of the encoder when the switch 480 is in the other position, whereby an encoding the data bit sequence according to the code rules according to the above-mentioned US patent 3 108 261 is given below.

As already stated, it is for following the rules according to the said US parallel application encoded data required two consecutive encoding Examine data bits when counting the modulo-2 of previously encoded logical Ones is odd. To this end, each channel encoder 453 includes a pair of series-connected input flip-flops 481 and 482, which are indicated by the positive Clocked trailing edge of the 2-3 SC clock signal (Fig. 45E- (2)) on line 474a The latter line is connected to line 474 via an inverter 483 is coupled. The two input flip-flops cause between the input of the Flip-flops 481 and the output of flip-flop 482 have a delay of 2 bit cells. With every positive The trailing edge of the 2-stroke becomes the existing one Data level of the bit sequence at the input of the flip-flop 481 through-connected to its output (Fig. 45E- (3)), where the previous data level contained in flip-flop 481 is the Data sequence from the input of the flip-flop 482 to its output is clocked (Fig. 45E- (2), (3) and (4)). Therefore, the output signals of the flip-flops 481 and 481 482 represent the data bits to be ccd for two successive bit cells, the The outputs of the flip-flops 481 and 482 are connected to the inputs of three NANGattern 486, 487 and 488 led to logical ones and logical zeros in the data bit sequence forward corresponding impulses separately. NAND gate 486 receives three inputs. This is the output signal of the flip-flop 481, the output signal of the flip-flop 482 as well as the 1-clock pulses (Fig. 45 - (1) on the line 475a, the provided by inverter 484 from output line 475 of clock generator 456 will.

This NAND catter is activated to always have an output pulse 489 (Fig. 45E- (6)) when recording a 1-clock signal to be supplied when to the other Inputs are at a lower level. This is only the case when consecutive received data bits are logical zeros. The NAND gate 486 therefore delivers a logic zero related pulse generated by jumps in the coded format of the data sequence are marked at the output of the channel encoder 453. A zero bit that is immediately on a one bit follows, the NAND gate cannot go through because the flip-flop 482 is high when, for example, a 1 clock pulse 490 (Fig. 45F- (1)) occurs. Of the Channel encoder 453 thus operates in accordance with the code rules of the above-mentioned US patent 3 108 261 for consecutive zero data bits.

On the other hand, the HAND gate 487 has two inputs and is used for all logical zero data bits when receiving a 1-clock signal to deliver a Output pulse (Fig.

45E- (5)) activated. Because the output of the flip-flop 282 the NAND gate 487 activates, a data cell after clocking in of the data in the Xanal encoder 453 generates logic zero related pulses.

NAND gate 488 has three inputs and when one is picked up, it will be 2 clock signal for all logical one data bits by the inverted output signal of the flip-flop 482 for generating an output pulse (Fig. 45r- (7)) is activated, if it is not due to a high level bit suppression pulse 491 (Fig. 45- (10)) on a line coming from a bit suppression NAND gate 493 492 is blocked. The NAND gate 488 generates the 2 clock signal during the interval impulses related to the logical one. This is the case before the flip-flop 482 is clocked by the positive trailing edge of the 2-clock signal. The one on the logical One related pulses are made by the NAND catter 488 one data cell after the Clocking the data into the channel encoder 453 via the flip-flop 481 supplied.

Fin two-input OR gate 494 takes the logic one Zero related pulses 489 (Fig. 45r- (6)) which are generated by NAND gate 486 can be generated according to the code rules of US Pat. No. 3,108,261. Farther this OR gate takes the logic one-related pulses 515 (Fig. 45E- (7)) which are provided by NAND gate 488. The output signal of the ODE gate 494 appearing on output line 451 is therefore a train of pulses (Fig. 45E- (14)), which according to the Code rules for the channel coder be generated. The NAND gates 486 and 488 serve in conjunction with the OR gate 494 to encode the incoming, stored by the flip-flops 481 and 482 l'RZ-L data in the selected channel code format. The NAND gate 487 works with one in the following to be described bit suppression logic together to the selective Suppression of the jump related to the one data bit into the channel-coded Control data. By blocking the bit suppression logic 500 due to a switchover of switch 480 from the position shown in FIG. 45C encode the NADJD gates 486 and 488 the data according to the teaching of U.S. Patent No. 3,108,261.

For coding the data bit sequence according to the teaching of the above In U.S. patent application bit suppression logic 500 includes two modulo-2 counters 495 and 496 for counting the coded logical ones and zeros, in cooperation the bit suppression command on line 492 is generated with gate circuits is the selective one-bit related jumps in those appearing on line 491 channel-coded data suppressed. The modulo-2 counter 495 counts the logical Zero related pulses which are sent through the NAND gate 487 to its clock input be coupled. The ones supplied by NAND gate 488, related to the logical one Pulses are entered into the clock input of the todulo 2 counter 496 for counting.

The counter 495 recognizes the beginning of each sequence by toggling it as a function of logic zero related pulses each time a logic zero is encoded being released each time a logical one related Jump is suppressed. As can be seen from the code rules explained above, counter 495 toggles twice during a sequence of the second type and never during a sequence of the first type so that he before the The beginning of each sequence is in its released state. The bit suppression logic 500 must recognize the end of a sequence of the third type. The modulo 2 counter 496 when performing this function is used to tilt as a function of the logical One related pulse every time a logical one is encoded, he in coding a logical zero as a function of those related to the logical zero Impulse is released.

The signal trains (8) and (9) according to FIG. 45E explain the corresponding ones Operations of the modulo-2 counters 495 and 496 if their outputs are not in a OR connection 501 are combined. The signal train (13) according to FIG. 45E gives the actual conditions at the OR connection 501 again. From the above Explanations it follows that the counter 495 is in its enabled state is when the counter 496 is not in its enabled state. The existing bit to be coded is a logical one and the next one Bit is a logical zero, the bit suppression command through the NANO gate 493 is provided on line 492 to disable NAND gate 488, where the coding of the existing logical one bit is suppressed.

In connection with the gate circuits to control the release of the two modulo-2 counters 495 and 496 is the set input of the counter 496 to the NAND gate 487 so that its output is high every time a the logic zero-related pulse is output from the NO gate 487 as an output signal will.

The set input of the counter 495 is connected to the output of a NAND gate 497 coupled so that its output is high every time a the logical one-related jump in the channel coding of the data bit sequence is suppressed will. As can be seen from the following still results is into the output circuits of the modulo-2 counter 495 and the NAND gate 493 a pair of capacitances 498 and 499 switched on to the occurring at the OR connection 501 logic set level of the counter 495 to delay and the bit suppression command from NAND gate 488.

The bit suppression command is generated by NAND gate 493, which is the first bit of consecutive data bits to be encoded, which is inverted Form is present at the output of the flip-flop 482, the next bit to be coded successive data bits that are present at the output of flip-flop 481, as well as the counter readings of the Kodulo 2 counters 495 and 496 examined. Is one of the If the counter outputs on the OR connection 501 are high, the NAND gate is blocked. However, if the beginning of a sequence of the third type occurs, both counters are located 495 and 496 low, so that at the input of the NtND gate 493 an effective switching Signal arises. Are the next two bits to be coded one of a logical? A logical one followed by a zero will put the bit suppression command 491 on the line 492 when the 2-clock pulse 502 occurs (Fig.

45E- (2)) is generated immediately before the 1 clock pulse 490, whereby the Formation of the pulse related to the logic one via the NAND gate 483 causes will. If the 1 clock pulse 490 (Fig. 45E- (2)) occurs on line 474, whereby the NAND gate 488 generates a logic one related pulse, so will the NAND gate 488 disabled by the bit suppression command on line 492, so that the pulse related to the logic one is suppressed.

This is shown in dashed lines in the signal train (14) according to FIG. 45E Pulses 512 indicated. The bit suppression command is activated when the counter is set 495 finished. The set pulse 505 (Fig. 45E- (12)) is passed through the NPND gate 497 as Function of the bit suppression command 491 (Fig. 45v- (10)) on the line 510 and the above 1-clock pulse 490 generated, which is half a period of the frequency 3 SO occurs after the 2-stroke pulse or about 47 nanoseconds later. To ensure, that the counter 495 is not set and the bit suppression command is not removed until the 1 clock pulse 490 is finished, the delay capacitances are 498 and 499 provided to return counter 495 to its high power level to delay, thereby holding NAND gate 493 off, and to return of the NAND gate 493 to its low-lying shutdown level, thereby the duration of the bit suppress command 491 is extended. The effect of this delay is from the course of signal curves 508 and 509 in the signal trains (10) and (13) can be seen according to FIG. 45E.

To switch off the bit suppression logic 500, the switch 480 switched to the source in which a signal with a high level (ground in the channel encoder 453 of this device) is generated on the set line 510 for the counter 495. Through this the counter is permanently set to its set state, whereby the input of the NAND gate 493 receives a high level shutdown signal from the ODFR connection.

Therefore, bit suppression commands 491 cannot be generated, so that no bits are suppressed either.

Typically, self-clocking data code formats contain data and timing information as specially placed jumps between two signal levels. If such coded Data is transmitted over a transmission channel, the non-linear occurs Characteristic of most transmission channels on a certain timing distortion. If this timing distortion is significant, errors can occur because of the Decoder does not determine the correct position of the transmitted jumps determine can. In addition, timing distortion can occur with large data densities such as occur in the device in question here, to unacceptable errors in the transferred data lead. This is especially the case when opposing directions Jumps in data and timing information lead, as is the case with the codes for this one Device occurs. Non-linear transmission channels change the positive and negative Jumps in a non-linear manner with respect to time. Hence, at the end of a The transmission channel is usually level-sensitive data detectors used to detect the to process the transmitted data so that they have correctly positioned jumps. The positive and negative jumps are positioned differently.

The different positioning occurs because a positive one Jump with considerable timing distortion to determine the presence level selected by jumps is reached at a point in time according to its nominal position.

This level differs from the level which is used for a correspondingly distorted negative jump is required.

To the reliability of the transmission of the coded data in which jumps in opposite directions that carry data and clock information, improve each channel encoder 453 encodes the data bit sequence at its input by generating it of pulses according to the rules of the selected code at jump points of the coded Formats. In the channel encoder used specifically for this device logic one related pulses 515 (Figs. 45E- (7)) and (14) at the data cell boundaries generated to define logical one related jumps which are in the encoded data occur. Logical zero related pulses 589 (Fig. 45E- (6)) and (14) are generated in the center of a data cell to be related to the logical zero Define jumps, which appear in the encoded data. The jump-related pulses are generated by the clock generator 456 to be precise to get defined edges, whereby the trailing edge is selected. This second one Clock generator 456 contains two monostable multivibrators 456 which are caused by the antiphase, 3 SC clock signals supplied by the first clock generator 468 via lines 472 and 473 be clocked. Since the leading edges of the monostable flip-flops 456 generated positive impulses by quickly switching the flip-flops from their stable state are defined in their quasi-stable state (there are no ins Weight falling components determining the time constant), is each The leading edge is identical to all others and occurs following an exact point in time on the occurrence of the positive jump of the clock signal. The two tilt stages 456 therefore deliver 1 and 2 clock pulse sequences, which in the present exemplary embodiment have a pulse width of about 17 nanoseconds, with the leading edges being the Pulse trains in relation to each other and in relation to the impulses of the other Pulse sequence are precisely defined. As already stated above, the 1-clock pulses on line 475 clocked as pulses through NAND gate 488, which on in logical ones contained in the encoded data are related. The one on the line 474 delivered 2-clock pulses are sent as jump-related pulses by the NAND gate 486 clocked, with these jump-related pulses occurring in the encoded data Zeros are related. Because the NAND gates 488 and 486 are activated at times in which the 01 and 2 clock signals for transmission as jump-related pulses are received (Fig. 45E- (4), (7) and (14) for one-bit pulses and Fig. 45E- (3), (4), (5), (6) and (14) for zero-bit pulses), become their respective leading edges not noticeably influenced by the transmission via the NAND gates. Since the transmission channel, above which the impulses are transmitted, has the same effect on identical impulse edges the exact positions of the jump-related positive pulse edges and thus the data signal jumps even due to distortion which the pulses through the action of the transmission channel can suffer, not lost.

The encoded jump-related pulses at the output of the encoder 96 on lines 451 are through the electronic data interface circuit 98 transmitted to the transmission line 152, which to the disk drive units 73 associated data interface circuits 151 for the disk drive units leads. The interface circuit 89 includes conventional logic converters, which convert TTL logic levels on lines 451 into ECL logic levels. In this way, pulses with complementary levels are obtained on two lines in such a way that that they can be used in different places on the device. The interface circuit 151 of the disk drive unit selected for recording lists the data the recording amplifier and head switch circuit (Figs. 54A and 54B) of the selected ones Disc drive unit. One contained in each data bit line and dividing by two JK flip-flop 1070, which receives the jump-related pulses, speaks to the Leading edges of the transmitted pulses to quickly become stable between its two Switching states to be switched. This means that the transmitted pulse shape becomes the encoded data for recording in the form of jumps between two signal states transferred to the level jump form. Before this reshaping by the JK flip-flop 1070 the transmitted pulses pass through a differential amplifier line receiver in each data bit line 2020 '(Fig. 60t.) In the data interface circuit for the disk drive units. This is a level as it is based on of the decoder 525 (Fig. 46A) in the decoding and time base correction circuit 100 became. The transmitted impulses are thereby after passing through the associated Transmission line of the transmission line bus 152 with precisely defined leading edges regenerated.

Decoding and Time Base Correction Circuit The ten data bit strings of the encoded data, which eight video data bit sequences, a parity bit sequence (if a parity bit is present) and comprise a data track bit string and via a Transmission line bus 154 is transmitted to a disk drive unit (Fig. 9B) are selected by one or more of the data selection switch 128 Playback channels 91 (Fig. 4) added. Be at the input of each playback channel the ten transmitted data bit sequences by a separate decoding and Timebase correction circuit 100 added to decode the encoded data in the tsFZ-L form of the digital code. Then there is a time base correction The iF: Z-L data carried out time shift errors in the received data sequences in the channels or between the channels. Such bit time shift errors result from the effect of the data transmission channel on the transmitted data, where symbol interference and reflections due to impedance discontinuities occur in the transmission channel. This makes the timing of the transmitted in the channel Data disturbed. In a data transmission channel of a video recording device bit time shift errors usually arise due to changes in the Dimensions of the recording medium, which in turn are influenced by environmental conditions, by differences in the relative speeds between the head and the recording medium during recording and playback and due to mechanical differences from device to Device resulting from geometric differences between the heads and the recording medium result, caused. In the case of video devices with rigid, disk-shaped recording media, as they are given by the disk stack 73 in the present device, usually occur no large time shift errors in the transmitted data. This is particular About data densities, as is the case with analog recording devices with disk-shaped Recording media are in use today. The ones used in such devices rigid recording media are dimensionally stable, with servo mechanisms the relative speeds between the heads and the rigid recording media can keep within sufficient tolerances, so that time shift errors are small being held. In certain applications of recording devices with disk-shaped The time shift errors on recording media are so small that they are negligible are. In such cases a time base correction is not necessary.

In the present device with time base correction circuit, however, uses (with minor modifications) very reliable disk drive units, which are specially developed and manufactured for computer data processing. These Oomputer disk drive units, however, keep the relative speeds between Head and disk not stable enough to prevent impermissible bit time shift errors to avoid in the data bit sequences if such disk drive units in the present device can be used to process video data. That's because that the disk stack spindle in the drive unit is not servo-controlled, but driven by an ordinary three-phase AC motor for which a relatively unstable mains voltage is used as a reference. The rotation position of the stack of slices cannot be regulated relative to an external reference. the resulting positional errors and bit time shift errors are particular disadvantageous in the case of high data bit densities, for example in the range of 10.7 MHz.

Such frequencies are on the other hand for transmitter quality the Video data required in order to achieve a reduction in the quality of the video information turn off. To take advantage of the mechanical reliability of existing computer disk drive units to exploit, is in the device in question here is a position servo system for the AC motor and a time base correction circuit are provided to avoid impermissible Eliminate time shift errors in the data bit sequences. There is then one No change in the reliable design of the computer disk drive units necessary.

As already described above, the encoded data bit sequences before performing a time base correction to its original NF'.Z-L digital form decoded back. To this end, the decoding and time base correction circuit is included 100, as shown in FIGS. 46A and 46B, a channel decoding circuit 525 having a pair of Inputs 526 which are coupled to data select switch 128 (FIGS. 9A and 9B) are. The coded data is fed in here, as already described in the form of coded jump-related pulses such as pulses 515 and 489 of Figs. 45E- (14) are present. The input pair 526 is to the differential amplifier line receiver 527 coupled, which is connected so that unidirectional noise in the pair is eliminated by complementary jump-related pulses, with serving pulses after passing through the data selection switch 128 (FIG. 9B) via the in the transmission line bus 154 transmission line pair contained are supplied. The differential amplifier line receiver 527 also generates complementary jump-related ones from each transmitted pair Pulses a single jump-related pulse, so that the regenerated pulse is a has precisely defined leading edge, which according to the code rules for the originally coded video NRZ-L data is correctly positioned.

Specifically, the differential amplifier line receiver 527 provides one only regenerated jump impulse, the leading and trailing edge of which occurs when the levels of the edges of the received complementary pulses are the same. By such an examination of the edges of the transmitted complementary pulses the leading edges of all regenerated pulses are correct according to the code rules positioned because they have the same direction, i.e. positive and negative edges of each pair of complementary pulses defining the occurrence of the leading edge each regenerated jump-related impulse serve. Because the transmission channel, through which the jump-related pulses are transmitted to the decoding circuit 525 are identical With the same influence on pulse edges, time distortions of the pulse edges do not have any Influence on the regeneration of the jump-related impulses.

After the jump-related impulses have been regenerated, they are over a line 528 is used for clocking a monostable multivibrator 529, this Clocking each time a regenerated pulse occurs through its defined Leading edge takes place. The monostable multivibrator 529 quickly becomes stable from its Switching state switched to its auasi-stable switching state to the precisely defined Define the leading edge of the jump-related impulses. One of the outputs of the monostable Trigger stage 529 is via a line 530a to the clock input of a dividing by 2 Flip-flops 531 led. When each regenerated jump-related pulse occurs the flip-flop 531 quickly switches between its two stable switching states the leading edges of the regenerated pulses are switched because of the pulse shape the channel-coded data is converted into the level form in order to generate a subsequent To be able to decode the data into the original NRZ-L digital form. This The facts are described in more detail below.

The monostable multivibrator 529 provides complementary output signals of the channel-coded data on the line 530a and a line 530b. The complementary Output signals are coupled to a 6 SO clock generator 532, which is on output lines 533 and 534 provide complementary 6 SC clock signals which are used by the data decoding circuit 100 can be used to decode the received data. The clock generator contains a voltage-controlled oscillator 537 oscillating at the frequency 6 SO, which through a phase detector 535 to the phase of that contained in the channel encoded data Data clock is set. The complementary jump-related data pulses am Output of the monostable multivibrator 529 on lines 530a and 530b are on coupled to the input of the phase detector 535, the output of which via a line 536 is fed to the control input of the voltage controlled oscillator 537. The phase detector 535 examines the phase of the 6 SC clock signal supplied by the oscillator 537 with respect to the received and regenerated jump-related data pulses and provides an error correction signal to the oscillator via a phase error smoothing capacitance St. 538. A change in the phase of the received data is effected via the phase detector 535 a change in the mean voltage value at the capacitance 538 by a corresponding one Amount, whereby the phase of the supplied by the voltage controlled oscillator 537 6 SC clock signal is adjusted to the clock in the channel-coded data.

The phase detection process is performed by a pair of matched current sources 540 and 541 carried out, each via an output line 542 and 543, respectively the line 536 connected to the phase error smoothing capacitance 538 is coupled are. In the absence of a jump-related data pulse, that of the monostable is Flip-flop 529 outgoing line 530b high, whereby the current source 541 is activated will. Since the bases of transistors of a current switch 545 forming a differential pair are grounded at the output of the current source 541, it is divided by the current source 541 supplied current in two identical current paths defined by the current switch 545 on. The current in the path that passes through the coupled to output line 543 Current switch 545 flows on line 536 to provide the phase error smoothing capacitance 538 to a voltage value that allows the generation of a 6 SC clock signal with nominal frequency and nominal phase caused by the voltage controlled oscillator 537, when the decoder circuit 525 does not receive a data sequence. So it will also be in absence a data bit sequence at the input of the decoding circuit 525 with a 6 SC clock signal Nominal frequency generated. This will speed up the synchronization of the oscillator 537 facilitates the data clock when a data bit sequence is received, whereby the correct decoding of the Karal-coded data takes place.

If a jump-related data pulse is received on input line 526, the monostable multivibrator delivers a high level signal on the line 530a and a low signal on line 530b in an interval that is is determined by a time constant circle 529a. In the present decoding circuit this interval is about 17 nanoseconds. The low level signal on the Line 530b turns off current source 541, thereby charging the phase error smoothing capacitance 538 is terminated via the current source 545. The high level signal on the line 530a, however, activates the other current source 540, which is the phase error smoothing capacitance 538 in accordance with the relative conduction periods of two halves 544a and 544b of a power switch 544 charged by as Differential pair switched transistors is formed. The two halves 544a and 544b of the Current switch forming transistors are with their bases on the line 533 delivered 6 SC-TaRt coupled. If the clock is at a low level, then the transistor 5fi4a is switched off. However, the other transistor 544b conducts because an RC circuit 547 with a large time constant the voltage at its base on a Holds mean value, which is more positive than the value of the low level 6 SC clock is. Therefore, all of the current supplied by the current source 540 flows through the one turned on transistor 544b to the output line 542 of the current source 5L0.

When the 6 SC clock goes high, the base of the Transistor 544a more positive than the base of transistor 544b. Hence the transistor 544a is turned on and transistor 544b is turned off. The current flow to the phase error smoothing capacitance 538 is thus interrupted. Is the jump-related received from the power source 540 Data pulse timed to the 6 Sr clock supplied by power switch 544 so positioned that jumps from low to high level in the 6 SC clock in the middle of the Jump-related data pulses occur, the transistors 544a and 544b of the power switch is switched through for equal intervals, with the voltage on of phase error smoothing capacitance 538 is maintained at an average value that corresponds to a 6 C cycle with correct phase. Any change in the data bit rate of the received channel-coded data bit sequence changes the position of the jump-related Impulse at the input of the current source 540 relative to the jumps from low to high Level of the 6 SC clock at the input of the current switch 544. If this is the case, then one of the transistors of current source 544 during the period in which the current source 544 (through the jump-related Pulse) is activated, turned on for a longer interval than the other transistor, this being Switching one of the transistors through for a longer interval depends on whether the data bit frequency is increasing or decreasing. This causes a corresponding change of the current flowing into the phase error smoothing capacitance 538 and a corresponding one corrective change in the mean voltage value on this capacitance. A change the spa.natural value on the capacity causes a change in the phase and the joy of the voltage controlled oscillator 537 until the jump-related pulses are related to the change from low to high level in that supplied by the current source 540 6 Sr clock are centered. Is the change from low to high level in the 6 SC cycle centered with respect to the duration of the jump-related impulses, the two deliver Halves 544a and 544b of the "Tromschelters" flow individually for equal intervals of the current source 540. The mean voltage at the capacitance 538 is therefore on the Value, which is used to determine the frequency and phase of the 6 SC oscillator 537 to the data clock frequency of the received channel-coded data is required is.

The voltage controlled oscillator 537 performs the phase determination does not affect the received data or is saved by one of the decoders in the in tent base correction circuits included in the 10 bit lines of a playback channel 100 does not receive any data, a signal leading to the reference clock generator 98 is used Output line 550 provided a frequency unlock signal. All lines 550 of the 10 decoders and time base correction circuits of the playback channel in the reference clock generator 98 are ORed in order to issue a frequency unlocking command via the signal system interface circuit in the event 119 (Fig. 8, 32 and 3? B) to couple to the computer control system 92 that in the how delivery channel one or more frequency unlocking signals are generated. The computer control system 92 responds to the frequency unlocking command in such a way that it has the Signal system interface circuit sends a video mute command to the video playback output circuit (Figs. 51A and 51B) indicates which data is to be sent to the requesting party Station blocked. In the decoder 525, the frequency unlock signal is through Detection of the failure of the decoder when generating a data bit for 16 Periods of the 6 SC signal generated. The frequency unlocking signal is activated by a supplied by 2 dividing circuit 546, whose clock input then a clock pulse each time on line 548 when the decoder receives 525 for an interval of 4 periods of the 3 SC signal and thus no data bit for 8 periods of the 6 signal. A second clock pulse appears on line 548 before the divide by 2 Circle 546 is reset by the riAtiD-Catter 549, then the one with 2 dividing circuit 546 the frequency unlock signal on line 550. The NAND gate 549 resets the divide by 2 circle 5fi6 every time there is a coincidence between a low level of the 6 SC clock supplied by the oscillator 537 and a low occurs on line 530b, which is the case when a jump-related data pulse is received at input 526 of the decoder.

After the divide-by-2 flip-flop 531 outputs the encoded data the jump-related pulse form has been converted into the channel-coded IZ-L form the data on line 531a to a pair of flip-flops 551 and 552 at the input coupled to a decoding circuit 525a. This decoding circuit can according to the code rules according to US Pat. No. 3,108,261 and the aforementioned US patent application Data (Fig.

46v- (1) or 46v- (2)) decode. The flip flops are through 1- and 2-3 SC clock signals, which are clocked by the generated by the oscillator 537 6 SC clock can be derived.

The 6 SC clock on line 534 is on one input of NAND gates 553a and 553b coupled. The other input of these NAND gates receives complementary ones 3 SC square-wave signals, which are generated by a dividing by 2 flip-flop 536a from the 6 SC clock on line 534 can be generated. The NAND gates are activated when their inputs are low, the positive 1 clock pulses (Fig. 46E- (4)) to Clocking of the flip-flop 552 and the positive 2-clock pulses (Fig.

46E- (3)) for clocking the flip-flop 551. The 1- and 2-stroke pulses are shifted against each other in time by half a period of the 3 SC signal. Therefore is the point in time when the level of the encoded NRZ-L data on line 531a clocked by flip-flop 551 against half a period of the 3 SC signal shifted the point in time at which the level is clocked by the flip-flop 552 (Fig.

46- (5) and (6)). Both flip-flops are connected to the two inputs of one Docked Exclusive-OR Gate £ 554a. This exclusive OR gate is used to determine the occurrence of a change in the level of the channel-coded NRZ-L data at the input the flip-flops 551 and 552 between the times they go through against each other offset 1 and 2 clock pulses (Fig. 46t- (7)) are clocked. To realize, whether the change in the state at the input of the flip-flops represents a logical one bit, is the output of the exclusive OD, P gate 554a to an input of a NAND gate 555 coupled. The other input of this NEID catter receives 1-3 SC clock pulses through an inverter 55a from the NAND gate 533a. Represents the change in level a logical one bit at the input of the flip-flops, then the output of the exclusive 0DER gate is 554a when an inverted 1-3 S clock pulse occurs low. The NAND gate 545 is switched through, causing a high level at its output arises. To ensure that the detected logical I? Ins bit pulse is clocked reliably To ensure at the output of the NttD-Catter 555, a delay circuit is at its input 556 coupled, which receives the inverted 1-clock pulse, so that the output of the IYTAI; D gate is held high for an interval that is longer than the 1-3 SC clock pulse (Fig. 46E- (8)). This makes it possible to do one of the following Flip-flop 557 with the positive trailing edge of the 1-3 SC clock to clock the to turn on delayed high signal from NAND gate 555 (Fig. 46E- (9)).

Is the input data according to the code rules of the US patent 3 108 261 encoded, the output signal of the flip-flop 557 represents the decoded NRZ-L data.

This is shown by dashed lines in the timing diagram of FIG. 46E. In the decoder shown in Figs. 46t and 463, however, there is an additional one Flip-flop 558 required in order to be able to decode data, which according to the code rules are encoded in accordance with the aforementioned US patent application. When coding according to the rules of US Pat. No. 3,108,261 delay this additional flip-flop 558 only reduces the decoded output data by one period of the 3 SC signal.

If data is in accordance with the code rules of the US petition filing above are coded, special jumps related to a logical one-bit are suppressed. If such a jump related to a logical one-bit has been suppressed, so for an interval greater than 1.5 periods of the 3 SC signal there are none Data jumps exist. This is determined by a modulo-4 counter 559, whose clock input receives 0 clock pulses supplied by a NAND gate 553b and its reset input to the output of the Exclusive-OR gate 554a is coupled. The exclusive OR gate 554a provides a reset pulse, to enable the counter 559 every time a jump in the encoded data occurs (Figs. 46E-t10)). The output of the modulo-4 counter 559 is connected to an input coupled to an AND gate 560 which receives 0 clock pulses at its other input. Both inputs are low for half a period of the 3 SC signal after the Modulo-4 counter has counted four 1-3 SC clock pulses without resetting, which is the lack of it of data jumps for an interval of 2.5 periods of the 3 signal (Fig. 46F- (11), (12) and (13)).

This usually indicates that there is a logical One bit is suppressed. To ensure that there are no errors in the data sequence were introduced, a following NAND gate 561 examines an output of the Flip-flops 558 at the time when the AND gate 560 is suppressed supplies a logic one-bit representing signal with a low level. Is the If the output of the flip-flop 558 is low, it is verified that a logical one bit has been suppressed, with output pulses being supplied on a line 562 (Fig. 468- (14)), which is ORed with the output of the flip-flop 557, the curve (14) of Fig. 46E represents the state of the NAND gate 561 when it is not would be ORed with the output of the flip-flop 557. A second from NAND gate 561 Delivered pulse 563 occurs at the time of the 1-3 SC clock pulse and is through this clocked into the flip-flop 558. This prevents the output of the Flip-flops 558 can return to a low level, thereby suppressing the logic fins bits are introduced into the decoded NRZ-L data on line 566 becomes (Fig. 45 [- (15)). In the data track bit line, the decoded data is over line 566 is fed to data track interface circuit 120 (Fig. 8). Of the decoded data clock supplied by flip-flop 543a on line 573 and that provided by a first shift register and sync word detector circuit 572 The sync word on the tenth line is also fed into the data track interface circuit entered.

Is the phase of the 3 SO decoding clock provided by flip-flop 543a incorrect, a monostable multivibrator 534b becomes due to the coincidence of the 6 eC cycle on line 534 and a pulse on line 564 activated. This pulse will be three periods of the 3 SC signal before the first detection Line identification generated by the sync word detector portion of circuit 572.

If the level of the decoded data is low at this point in time, then there is an error. A counter 590 (Figs. 15A and h6C) takes the decoded 3 SC data clock and delivers a in a manner to be described below an H / 2 frequency pulse on a line indicating an advanced end-of-count 591. Due to the known data bit pattern of the sync word interval, which is usually occurs when the pulse indicating an advanced counting end is generated, the decoded data level in the shift register portion of circuit 572 can be examined to see if the decoding was done correctly. A gate circuit 592 provides a pulse on line 564 when the examined decoded data level is low, whereby the monostable multivibrator 534b is effectively switched to for a period of the 6 SC signal is a switch-off signal in the clock input of the flip-flop 534a to be fed. This leads to a shift in the phases of the 1 and 2 clock pulses by half a period of the 3 SC signal, bringing the correct phase to the correct To ensure decoding of the channel-coded NRZ-L data.

In playback operations, each sequence contains decoded NRZ-L data on output line 566 of decoder circuit 525 time base errors in the form of Bit time shift errors in the sense described above. In addition, in the nine data bit sequences, which are eight parallel bits with digitized video information and, if present, carry a parity bit, errors from bit line to bit line or skew time shift error present. About this bit time shift error from the NRZ-L data is a time base correction circuit for each data bit sequence 565 is provided, which corrects such errors by adding a variable delay, which is passed through by the NRZ-L data is adjusted electronically. Any time base correction circuit contains circles which process the received data in such a way that the data bit frequencies in all video data and parity bit lines frequency and phase coherent in relation to that supplied for the playback channel 91 by the reference clock generator 98 3 are the SC reference signal. In addition, the time base correction circuits set up 565 also the data bits in the data bit lines with respect to a common H / 2nd reference signal provided by the playback channel reference clock generator 98. By combining these functions, relative timing errors between the data bits in the nine bit lines, skew errors and bit time shift errors eliminated in a switched bit line.

The operation of the time base correction circuit included in each data bit line 565 is described below with reference to the block diagram of FIG. 15A and with reference to FIG Signal diagrams according to FIGS. 15B and C explained. Special circuits for implementation of the operations of the time base correction circuit are shown in Figs. 46B, 46C and 46D shown.

The decoded data on each bit line that travels over the line 566 are received by the decoder 525 independent of the other eight data bit lines using all of the data bit lines common, periodically occurring time reference signal corrected in frequency and in the phase to a higher frequency used in the coding of the data Clock signal is related. In the case of the video recording and recording in question here Reproduction device are H / 2 signals related to horizontal lines, which are transmitted by the periodically occurring sync signals are derived, which in turn in the above described sense in the horizontal blanking interval synchronously in each data bit sequence be inserted, in the Freauenz and in the phase on the higher frequency color subcarrier component (455 x H / 2) and the 3 SC data clock signal (1365 x H / 2). These on horizontal lines Related H / 2 signals are available as a periodically occurring reference time cycle.

To perform the time base correction of the reproduced decoded data, the data in all data bit lines are fed into a phase setting circuit 567 re-timed to a common 3 SO reference clock signal. In the In the illustrated embodiment, a multiple register 568 performs the downclocking, the writing of data takes place in addresses which are generated by a write address generator 569. This write address generator 569 is decoded by the 3 SC data clock, which is supplied by the channel decoder 525 via the line 573 will. The data are controlled by means of a read address generator 570, clocked by the 3 SO reference clock signal on line 571 from the register 568 read out. Since all read address generators of the phase setting circuit in the nine data bit lines are clocked by the same 3 SC-T2ktsignal the data in all data bit lines on the stable 3 SC Reference clock clocked back, which has a frequency of 10.7 Hz for an NTSC television standard.

The write and read address generators 569 and 570 are through a first shift register and sync word detector stage 572 each time their start addresses are set or

reset when a sync word is decoded in the received Data is established. The start write address advances by four addresses the start reading address.

The decoded data enter a contained in the stage 572 7 bit shift registers and are examined by logic circuits which define the Form synchronous word detector part of stage 572. After passing through the shift register the data is clocked into multiple register 568. Register 568 has has a capacity of 8 bits and is initially activated after four periods of the 3rd SC clock to read an address following the writing of data in the address. Since the write address generator 569 by the 3 SO data clock and the read address generator 570 is clocked by the 3 SC reference clock, data bit shift errors change in the received data the time at which an address was written, relative to the time at which the address is read. This change in time between writing data into an address and reading data out of it this address leads to a new time definition of the received data to the stable 3 SO reference signal. In addition, the phase adjustment circuit provides 567 the received data search for the stable 3 SO reference signal a new time, if the synchronous word is not detected by the first synchronous word detector stage 572 will. In any case, this applies as long as there are no too large time shift errors occur which exceed the storage capacity of the register 568.

The first synchronous word detector stage 572 and a second synchronous word detector stage 575 are used to determine the synchronous word by a synchronous word switching pulse generator 600 switched effective. The generator 600 provides the establishment of a synchronous word effective switching pulse on a line 601 (Fig. 15B- (3)), which by a advanced EOC pulse (Fig. 15B- (2)) from counter 590 three counts before Occurrence of a sync word in the detector stage 572 is supplied (Fig. 15B- (6)). When a synchronous word is determined by the detector stage 575, the Pulse on line 601 terminated when counter 590 after a count of 15 reset by an EOC reset pulse on line 602 is. The effective switching pulse is switched off by counting value 15 in counter 590, if a synchronous word is not detected by the detector stage 575 (Fig. 15B- (7)).

A shift register 604 and a pulse generator 605 enable that the detection of the synchronous word effective switching pulse temporal Changes in the occurrence of consecutive synchronic words with an amount of + can follow a period of the 3 ÇC cycle. If the derived from a sync word Reset control pulse occurs one count before the EOO reset pulse the counter 590 is not reset (Figs. 15B- (4) and (8)). Becomes the reset control pulse a count is supplied before the occurrence of the EOO reset pulse, the Counter 590 also not reset. Becomes a synchronous word in the interval of the synchronous word control pulse not determined, the counter 590 and the generator 600 operate as one Memory to record when the sync word control pulses are delivered should until a sync word by resetting the counter via the shift register 604 and line 610 is asserted (Fig. 15ES- (5)). If there is no coincidence with the positive key signal of the generator 605 is present (Fig. 15B- (4)), so a gate 612 is activated, around the synchro word for to bring the reset of the counter 590 to a line 613.

The vertical blanking signal on line 606 (Fig. 15B- (1)) becomes coupled to the sync word control pulse generator 500 to this for an interval of 10 horizontal lines to be activated, with a clock signal to the generator 600 coupling gate 611 is blocked. This becomes the recording time base correction circuit effectively switched to the synchronous word detector stages 571 and 575 at the synchronous word time to switch effective and the phase adjustment circuit 567 and the error gate 582 correct to let work.

The data is read from the multiple register 568 by the 3 SO reference clock into the shift register of the second shift register and synchronous word detector stage 575 is clocked in. Three output lines of this shift register are connected to the Data input of a serial parallel converter 577 coupled. One from the reference clock generator 98 multiplex clock with the frequency SO supplied via a line 578 clocks the Data in blocks of three. Data bit cells from the shift register of stage 575 into the converter 577 for an interval of one period of the SC signal. Three Output lines 580 of the converter 577 are at the input of a read-write memory 579 led. The final time base correction is made in this read / write memory 579, the write address generator 614 of which is clocked with the SC reference signal is, the read / write memory operates at the frequency SO, while the decoded Data are clocked with the frequency 3 SO. A read address generator 615 is also clocked with the SO reference signal to read out the memory addresses perform. Read / write signals and write control signals from the reference clock generator 44A-D control reading and writing to the Addresses of the read / write memory, so that a read cycle during part of a subcarrier period occurs and a write cycle occurs in a part of the sync word period other than occurs in the record synchronous forward detector.

This causes a 3.58 MHz counter to count 616 Sfl signals, which are obtained from the 3 SC reference signals via a divider 583 which divides by 3 will. This count continues until the H / 2 reference signal is applied to the SC reference signals to counter 616 through error gate 582 terminated.

Receives the H / 2 reference signal on line 581 and the error gate 582 is closed, a delay and pulse shaper stage 621 turns on Pulse generated by which the error count in the read error address generator 616 is terminated. The blocking pulse then becomes a reset pulse for resetting of the divide by 3 counter 583 and the read error address generator 616 are generated. The counter sets the read address as a function of the time difference between the H / 2 reference signal and the synchronous word determined by the second synchronous word detector stage 575 measured in periods of the 3 SC signal divided by 3 and subtracts this value to generate the correct read address from the write address. Because the mistake representing clock signals are divided by 3, the read / write memory adjusts Errors in whole numbers of subcarrier periods. A 3 bit shift register 617, an error switching stage 618 and gates 619 correct residual errors after the data has passed through the read / write memory 579 in fractions of a Period of the 3 SC signal. A parallel-serial converter 620 at the output of the read-write memory takes a demultiplex clock from reference clock generator 98 and feeds the data at the input of the shift register 617 back to the data clock frequency of 3 SO. Fig. 150 shows a typical correction performed by phase adjustment circuit 567 with subsequent time base correction by the read / write memory 579 and the Shift register 617.

Data transfer circuit After the data is reproduced by the Decoding and time base correction circuit 100 and decodes with respect to the time base are corrected, the 8 bit lines with video data and the additional only one Parity bit line (if any) to the data transfer circuit 129 according to the Block diagram outlined in FIG. 9A. The output signals of this data transfer circuit are used for normal playback on the comb filter and ear domain inverter circuit 101 or when transferring the data in transfer mode to another disk drive unit given to the coding switch 126.

The data transfer circuit carries out a parity check of the Time base correction circuits passing data through and solves an error mask in the event that errors are found during the parity check. the Data occurs at a 3 SC repetition rate, each with the third sample the NRZ data represents approximately the same video information. The error masking part the circuit clocks the data sequence through a series of flip-flops, which one Form 3 bit memory, so that if an error is detected by the parity check the third preceding data word is newly inserted in the position in which the error was detected. The replacement of the third preceding data word masks the error assuming that the third earlier data word is the video information more accurately than the data word containing the error. Every third sample value is reinserted in the place of the detected error sample because (for example) the zero degree sample from the previous period of the 3 SC subsequent frequency is likely more accurate than is the duty cycle, which is either 1200 or 2400 is taken. The prerequisite is that the level of the keyed Signals contains chrominance information which is for a period of several sample values remains approximately constant.

The data transfer circuit also clocks the data from the input to the output, using a 3 SC-PAL clock to vertically shift the sample values into the gexinschten to bring aligned positions, which in the analog-digital converter 95 by the original phase reversal process were obtained during keying. In the Channel coding of the signal, the alignment is changed due to the fact that a line to line phase-continuous 3 tC clock for channel coding the NRZ data was used. The data coming from the time base correction circuit are therefore aligned in the same way as the encoded data at the output of the encoder 96. The data transfer circuit therefore performs a new one Phase reversal of the data by means of the sample values in the with reference to FIGS. 9C- (10) and 9C- (11) explained way to align with each other again.

According to the block diagram of the data transfer circuit 129 according to FIG. 16, the decoding and time base correction circuit 100 via 9 bit lines, i.e. 8 bit lines containing video information and one parity line are provided, time base corrected data in 9 input lines of the data transfer circuit fed in. Line 625 in Figure 16 represents the line for the most significant Bit, which is representative of the 9 input lines, which is for the individual Bit sequences are provided. The data is generated using a 3 SO-PAL clock signal on lines 628 and 629 into a flip-flop 626 and a flip flop 627 keyed in. The PAL clock signal is generated by a PAL clock generator in the lower Part of the block diagram of a 6 qC signal, a 1/2 vC signal and a PAL error indicator signal educated. The 6 SC signal and the 1/2 SC signal come via lines 630 and 631 from reference clock generator 98, while the PAL error flag signal from the reference logic circuit 125B via the coding switch 126 on a line 632 is delivered. The PAL error flag signal is output through an inverter 633 and a line 634 is fed to an input of an AND gate 635 '. The administration 634 also leads to a second inverter 636, the output of which is via a line 638 is led to an input of a further .UND gate 637. The 1/2 SC signal on line 631 runs through a pulse shaper 639 and clocks a dividing by 2 Flip-flop 640, which on output lines 641 and 642 3 SC output signals with opposite directions Phase supplies. These signals are sent to the other inputs of AND gates 635 and 637 '. The outputs of the AND gates are coupled to a line 643, which leads to a complementary dual output buffer 645. This buffer 645 clocks flip-floos 626 and 627. The PAL error flag signal on the line 632 is a signal with two levels which change with an H / 2nd repetition frequency. By changing the level, the AND gate 635 is alternately blocked and the AND gate 637 is enabled to activate one of the three SC signals on the lines 641 and 642 to the output line 643 to couple. This changes the PAL error flag signal in effect, the phase of the 3 SC signal that is used to clock the data alternates serves on line 625 through flip-flops 626 and 627 so that successive Horizontal lines of the video data are clocked with 3 SC signals of opposite phase. This changes the video data bits from the continuous phase clock into the PAL clock back in time so that the vertical alignment of the sample values consecutive New lines generated for the subsequent earoma detachment and processing will.

As stated above, the video data bits are used in transfer operations not reoriented in terms of time. To prevent this time reorientation, the code switch 126 blocks the coupling of the PAL error flag signal from of the reference logic circuit 125B to the data transfer circuit 129, where instead of a signal of low level on the line 632 is given. So it gets an input of the AND gate 635 is a signal that activates this gate and an input of the AND gate 637 a signal blocking this gate, one of Line to line phase-continuous 3 S ^ clock signal via AND gate 635 line 643 is supplied.

The data at the output of the flip-flop 627 are transmitted via a line 648 given to a W5D gate 647, the output line 649 of which to a first flip-flop of three flip-flops 651, 652 and 653 is coupled. Slide these three flip flops the serial bits on the output of the last flip-flop, which is on a line 654 is performed. This line 654 is also at an input of a further AND gate 655.

A parity error detector 656 receives the data bits of the 9 bit strings in a manner to be described below, with two output lines 657 and 658 are led to the AND gate 655 or the AND gate 647. Will be a mistake is detected, the AND gate 647 is disabled to the containing the error Bit to block while the AND gate 655 is activated, so that the Output data on line 654 is clocked through AND gate 655 onto line 649 can be. This will get the wrong bit, which is the third preceding one Bit in the data sequence is replaced, whereby the error is masked by the bit is approximate for the reasons mentioned above correct is.

Five bits, i.e. bits 2 through 6 or the next most significant Bits up to the sixth most significant bit are using a resistor network Matched resistance values are sent to an analog form of digital information which is an approximation of the digitally encoded analog information and used to determine whether the chroma phase needs to be inverted. That The output of this resistor network on a line 660 is sent to the reference clock generator 98 out and with the phase of the burst signal of the station reference video signal compared to see if the chromium phase needs to be inverted. The one in the Data transfer circuit made digital-to-analog conversion is clocked so that With the exception of the Fsrbynchronsignal all components are eliminated, whereby an imprecise but sufficiently precise determination of the color synchronous signal phase for use in the reference clock generator is possible.

A special circuit for performing the functions of the block diagram 16 is shown in FIGS. 47A and 47B. Since the way this The circuit is the same as that in the block diagram, it is not described in detail, 47A, the parity error detector 656 includes a number of exclusive-OR gates 661, which are assigned to the eight data bit lines carrying the video information and are connected to them. The outputs of these exclusive-OR gates are 661 coupled to one input of another exclusive ODFR gate 662, the other of which Input receives the parity bit in channel 9.

This exclusive OR gate 662 controls a flip-flop 663, its Output lines 657 and 658 drive the AND gates described above to either those on the input lines 625 received video data bits to continue or an incorrect byte with 8 bits through the third preceding byte to be replaced with 8 bits. The remainder of the circuit of Figures 470 and 47B is the same its mode of operation corresponds to the block diagram according to FIG. 16.

Chroma Separation and Processing A television picture with a saturated Color area which is delimited on its underside by an area without color, defines a vertical color jump along the horizontal border or color edge. For three consecutive television lines A, B and C of a field in which the Lines in the saturated color area are directly above the color edge a conventional comb filter the vectors representing the chrominance according to FIG the context - 1/4 A + 1/2 B - 1/4 C.

However, the color subcarrier of an NTSO television signal has between the alternating lines A, B and C have a phase shift of 180 °. For example an inversion of 180 ° of lines A and C and a subsequent summation of the vectors + 1/4 A + 1/2 B + 1/4 C leads to the generation of a full ear dominance vector, which is referred to here as 1 B or simply + B, which is the chrominance in line B. If this chrominance vector + B from the broadband final (which also contains the chrominance vector + B) is subtracted, they cancel each other out the chrominance vectors. The comb filter thus has a complete chrominance and luminance separation is performed, i.e.

all of the chrominance is in the ear coin channel.

If, however, in a second case, lines A and B are saturated Color range, where line C is in the range without color, the line delivers A is a chrominance vector which is equal to B in the negative direction, and the line B is a vector which is equal to B in the positive direction.

Line C, however, provides a zero ear dominance vector since it has Im Area without color. Will the vectors according to the above Combined, then - 1 / ££ of the vector A is inverted and the value + 1/2 of the vector B is added, the result is a sum of + 3/4 of a full vector B. If the chrominance becomes + 3/4 B from the broadband signal, i.e. from the line If B is subtracted, a remainder of + 1/4 of the chrominance vector remains in the luminance channel, while only + 3/4 of the ear dominance vector is separated into the chrominance channel will.

In a third case, only line A is in the saturated color range, while lines B and C are in the area with no color. This third case is the same the second case explained above, but the signs are reversed.

The second (and third) case discussed above in which the line C (or B and C) is in the area of no color is disadvantageous when a composite DiTSC television signal is reconstructed from a single stored color field shall be. In a manner known per se, when playing the composite Video signal from a single stored field in a field the chrominance added back directly to the previously separated luminance, while in the second field the chrominance component is first inverted and then added to the luminance component will.

In the second case explained above, in which the line C in a Area is without color, therefore becomes the + 1/4 chrominance vector in the non-inverted Field that remains in the luminance channel due to the incomplete separation, to the separated + 3/4 chrominance vector which was separated into the chrominance channel, added. Therefore the full vector B, i.e. the full chrominance signal, is recovered, around define a properly reconstructed color television signal for the non-inverted image. In the reconstruction of the second half-frame of the color video signal from the only one stored field, however, the chrominance component (+ 3/4 B) is initially inverted, whereby a -3 / 4-Ohroirinanzvektor arises, so that with the following addition to the + 1/4 vector in the luminance channel for the inverted field only a - 1/2 ~ chrominance vector arises. In the non-inverted field, therefore, the chrominance becomes fully saturated reproduced, while in the other inverted field the chrominance with half Saturation is reproduced. The color saturation, which is the color edge between the The area with full color and the area without color defined, therefore flickers with it a repetition rate of 15 Hz between half saturation and full saturation. This visible flicker is when playing back the color-coded with four fields NTSC television signal disadvantageous.

The chrominance separation and processing system includes several Embodiments of digital circuits that perform the inversion process digitally in combination with a digital comb filter and a digital bandpass filter perform, generating a chrominance signal that is digitally recombined the detrimental flicker to form the composite NTSO color television signal with a frequency of 15 Hz in the vertical transitions completely extinguishes or at least keep it as small as possible.

The following is specifically the use of a PAL encoding with three times the subcarrier frequency (10.7 MHz) in connection with a POM coding of the NTSO video signal. However, other coding methods can also be used, Keying methods, frequencies, etc. can be used. Furthermore are the individual lines, which are the inputs and outputs of the components of the block diagram indicate, representative of digital words with predetermined bit numbers, as shown in the each is shown in FIGS. 48, 49 and 50.

Fig. 17 shows a digital chrominance separation and processing circuit; in which a PAL-POD'1 color video signal with a frequency of 10.7 OEz via an input line 700 is fed into a digital comb filter 701. This comb filter 701 is in itself typical of digital comb filters as used today in various television signal processing systems be used. In the present context, however, it is used in conjunction with a special clock to be described in the following for the separation of the Chrominance component from the broadband digital color signal. The output signals of the comb filter 701 are delayed by one horizontal line broadband Signal on a line 702 and by a separated chrominance signal (with still existing low-frequency components) formed on a line 703a. The term separated defines in the present context that which is routed into a chrominance channel Chrominance signal, regardless of whether the separation is complete or is incomplete in the sense described above according to case 2 (and 3).

The separated chrominance signal is fed into a bandpass filter 704, eliminates the vertical resolution error caused by the comb filter in that only the frequency band occupied by the chrominance information is allowed to pass will. This bandpass filter 704 has a center frequency of 3.58 MHz (NTSC subcarrier frequency) and a bandwidth of, for example, 1.5 MHz.

The resulting filtered chrominance signal is transmitted over a line 703b fed into a digital circuit to its phase in alternating Invert fields at frame rate. In the circuit of FIG. 17 contains the inverting circle is a digital transversal filter 705 with odd symmetry, in the present context as a modified digital "Hilbert" transformer can be designated. It should be noted that the transversal filter 705 has a shape performs the inversion. The function basically corresponds to the known one Hilbert transformation. However, it is a special form of house management a trensversal filter with odd symmetry, not an analog one, but a digital inversion takes place. The special transversal filter has the property all frequencies of a certain frequency range, here specifically a frequency range from e.g. 2 to 4 MHz to rotate 90 ° in phase.

In the present context, the term inversion denotes a Circuit and a method for digital processing of the chrominance component with frame rate (or field rate, - if a field is used to create the color-coded NTSC color television signal in four fields) through phase shift, Phase rotation, phase inversion or other treatment of the phase. Farther are successive displays of either a single stored field or image in the present context as "alternately repeated reproductions" designated.

The chrominance signal is still fed into a negative input Addition (subtraction) stage 706 fed. That delayed one horizontal line broadband video signal on line 702 is fed into the positive input of the adder 706 fed in. The transversal filter 705 has one over a line 707 controlled control input, via which the processing of the ear dominance signal phase is determined. According to one embodiment, the transversal filter can for example alternately repeated the chrominance component with respect to the luminance signal in FIG Reverse phase renditions by + 900 and then by - 900.

The chrominance and luminance signals then become digital Adding stage 708 adds to an output 728 the composite color television signal to create.

The control stage 709 takes various time base and clock input signals which are related, for example, to the total time cycle of the device and therefore come from outside.

This control stage 709 generates special control signals for the comb filter 701 for the control input of the transversal filter on line 707, for the bandpass filter 704, etc., including a PtL clock signal, a signal for a delay is a horizontal line and 4 phase clock signals. The tax bracket 709 and the various inputs and outputs are shown in detail in Figs.

48A, 48B, 49A, B and C shown and are not shown here in detail explained in more detail.

In short, the comb filter 701 in the circuit of FIG. 17 the three above-mentioned adjacent television lines A, B and C. It contains a Pair of digital delay lines 710 and 711 with a delay of each a horizontal line and a pair of addition stages 712 and 713. The PA.L video signal with a frequency of 10.7 FGHz is fed into both delay line 710 and also fed into the addition stage 712. That delayed one horizontal line Signal is fed into delay line 711 and delayed by one horizontal line in the Addition stage 713 fed in. That by two horizontal lines delayed signal is fed into another input of adder 712, its output signal in turn into the negative input of the addition stage (subtraction stage) 713 is fed in.

The digital comb filter 701 and the digital bandpass filter 704 according to FIG the block diagram generate (8 bit) digital words corresponding to the separated Chrominance component and broadband signals delayed by one horizontal line. These filters are shown in the circuit diagrams of FIGS.

50k and 50B shown in more detail.

The filtered chrominance signal is used in the digital addition stage 706 subtracted from the broadband video signal delayed by one horizontal line, wherein the resulting filtered luminance signal is fed to the digital addition stage 708 is fed in.

18 shows the digital transversal filter 705 in which the digital filtered chrominance signal in a sequence of delay stages delayed by one duty cycle 714A to 714c and fed into the positive input of an addition stage 715b will. The negative input of the adder 715b is connected to the output of the last Delay stage 714c coupled. The positive and the negative input of one Addition stage 715a are connected to the input or the output of the delay stage 714b coupled. The outputs of the addition stages 715a and 715b are programmable Read-only memories 716a and 716b coupled to an addition stage 717. This stage 717 is in turn connected to the above-mentioned addition stage via an inverter stage 718 708 coupled, the filtered luminance signal from the adder 706 also is coupled to the addition stage 708, around the compound Generate color television signal. The control line 707 is to the inverter stage 718 coupled.

The transversal filter 705 forms digital circuits for processing the Phase of the ear dominance signal with respect to the luminance signal, i.e. for generation the digital representation of the phase inversion of the chrominance component in alternating Color images. For this purpose, the broadband is delayed by one horizontal line Signal and the chrominance signal via lines 702 and 703b into the adder 706, after which the resulting luminance signal is fed into the addition stage 708 is fed in. The chrominance signal is in each of the delay stages 714e to 714c delayed by one duty cycle (e.g. 93 nanoseconds), where the undelayed chrominance signal and the chrominance signal delayed by three sampling periods are fed into the addition stage 715b. By one key period and by two Duty cycle delayed chrominance signals are fed to adder 715a. The delay stages 714a to 714c can be through a single stage of a shift register are formed. The addition stages 715a and 715b provide signals for the programmable Read-only memories 716a and 716b, which are a multiplication of the corresponding signals with the factor 0.575 or 0.096 in a digital approximation according to a conventional one Perform folding operation. The resulting signals are then passed through the Addition stage 717 added, the sum signal in all of its frequency components with respect to the luminance signal is advanced by 90 ° to the above-mentioned conditioned Define chrominance signal. The output signal of the addition stage 717 is via the inverter stage 718 is fed into the addition stage 708. During a picture receives the inverter stage 718 via the control line 707 from the Control stage 709 a high signal or

a 1 ", whereby the (8) bits of the output word remain unchanged for the addition stage 708. In alternating video color images lies on the control line 707 e.n low (0 ") inversion control signal (see Fig. 49).

In this arrangement, data is in the sign-two's complement negative system represented by negative digits having a tal1 "in the sign bit position and the magnitude is the two's complement of its absolute value. Hence amounts to the inversion to a change in sign and the formation of the two's complement via the 0 inversion control signal on line 707. The conditioned chrominance signal (which is rotated by + 900) is added directly to the luminance signal in an image and inverted in the other image and then added to the luminance signal to produce the composite color television signal at output 728. On the other hand, it can Chroma signal by reversing the input signals of the addition stages 715a and b first rotated by - 906 in each image and then added directly in one image and rotated by 1800 in the next and then added.

According to a further embodiment, the transversal filter 705 be implemented, the phase of the chrominance signal during a color image advanced by 900 while the other color image is delayed by 900 to in effect an inversion around 1860 of the frequency components between the images realize.

Figs. 48A to C, SOA to B and 49A to B show detailed embodiments the circuits according to FIGS. 17 and 18 with the digital transversal filter 705 with odd symmetry. Figs. 48A to C show an embodiment of digital comb filter 701 and part of the control stage 709 according to FIG. 17. The Figs. 50 through B show an embodiment. of the digital band pass filter 704. The 49A to B show an embodiment of the digital transversal filter 705, of addition stages 706 and 708 and the remaining circuits of control stage 709. In all figures, the components according to FIGS. 17 and 18 have the same reference numerals Mistake.

According to Fig. 48A, the P; L video signal 21 of 10.7 MHz is applied via the input 700 fed into digital comb filter 701.

The separated chrominance signal is at the output 703a and at the output 702 supplied the broadband signal delayed by one horizontal line (FIG. 4au). The wingangssignele at inputs 719 and 725 are generated by control signals of a group z and a group B and formed by a symmetrical PAL clock, which in the corresponding part of the control stage 709 according to FIG. 49B (see below) can be generated. The inputs 719 and 725 are connected to a 4 phase clock generator 720 of the control stage 709 coupled according to FIG. 48A. The clock generator 720 forms part of the timing circuits for clocking the ochiehere registers, which delay the one horizontal line Delay lines 710 and 711 include. The delay lines 710 and 711, the addition stages 712 and 713 and the lines 702 and 703a are Uber registers 712a, 713a and 721, which are the corresponding digital signals of the preceding Temporarily store shift registers, addition stages, etc. in a conventional manner. The line 703a forms the input for the digital bandpass filter 704 according to FIG. 50t to B, while line 702 is the input for addition stage 706 according to FIG Fig. 49B forms.

The delay lines 710 and 711 also contain a sequence of two-phase shift registers 750 and 751 with a 2-phase cycle, wherein the register stages in groups 750A and 750B of the delay line 710 and 751t and 751B of the delay line 711 are arranged. Shift register stage selection circuits 752A and 752B select parts of the digital word according to the particular clock phases of groups t and B for delay line 710, during shift register stage select circuits 753A and 753B do this for delay line 711. Broadband inl selection circles 754 and 755 of delay lines 710 and 711 then provide a selection of the Digital words corresponding to around a horizontal line and around two horizontal lines delayed broadband signals.

The broadband video signal word is split up and the 4 Phase clock signals in 4 bit stages of the shift register 750 and 750B clocked, whereby the 4 phase clock signals are in effect 4 phases of the symmetrical PAL clock. Of the Level Selector 752A receives and loads the pairs of 4 bits as a function of the PAL clock alternately from different pairs of stages of the shift register 750A. The stage select circuit 752B performs the same function for the stages of the shift register 78OB through. As a function of the PAL clock signals, the stage selection circuit 752A discharges into a (4 bit) broadband signal selection circuit 754, while the stage selection circuits Unload 752B into the other (4-bit) selection circuit 754. At given times the selection circles of group B are clocked, whereby the combined register of groups A and B deliver a total of 680 bits per television line. An NTSC horizontal television line, which is sampled at three times the subcarrier frequency, contains 682.5 samples. However, as will be described in more detail below, the clock signals for the shift register is generated and fed into these registers so that the total of the bits per television line at the output of the register is the same for each bit line one are an integer number of sample values. In the examples described here 680 sample values per television line are clocked through the registers. The clocking of the Register is chosen so that the cleared interval of 2.5 sampling intervals during the siorizontal blanking interval outside of the active video information part the television line is.

The control stages 720 of FIG. 48A, which the 4 phase clock signals for the shift registers 750A, 750B and 751k, 751B and which provide a symmetrical Record PAL clock are more detailed in the block diagram and in the signal diagrams of the combined control stage 709 according to FIG.

49P through D, one embodiment being represented by the circuit diagrams 48A and 49A-E is given.

50h-B show the bandpass filter 704 with the incoming separated chrominance signal from the comb filter 701 leading line 703A according to FIG. 48B. The filtered ear dominance signal from band pass filter 704 is over the line 703b according to FIG. 50B, which is the input line for the transversal filter 705 with odd symmetry according to FIGS. 49k-B. Just before the line 703b is a ttdditions / switching stage 756 in which the switching stages can be clocked via a line 757 by a chroma inverter control signal. at the embodiment (FIGS. 17, 18, 49) containing the transversal filter 705 switches the chroma inverter control signal does not have the enable input of the switching stages, whereby the signal fed into the addition / switching stage 7; 6 appears on line 703b. The PAL clock signal on line 725 couples the various inverters (Fig. 50B) in such a way that a plurality of clock signals len for the bandpass filter 704 forming addition and Switching stages is generated. The switching steps are therefore clocked by the PAL clock signal to the digital output signal of the preceding logical processor components (the addition stages) to the following ones to deliver logical processor components (as well as addition stages).

The addition / switching stage 756 of the bandpass filter 704 provides the filtered Chrominance signal.

To carry out the comb filter process for the separation of the ear dominance signal from a broadband signal are delay lines delaying one horizontal line necessary. The delay lines and thus the comb filter 701 must be synchronous work with the timing of the overall system, this timing among other things is formed by the input PAL error flag signal. As already based on of the video signal system of FIG. 9A and the reference logic circuit 125B of FIG 11A has been explained in detail, the PAL error flag signal is unbalanced, i.e. it has one phase for a longer period of time while the other phase occurs for a shorter period of time. The phase of the PAL clock signal changes coherently with the single-ended PAL error flag signal. For those in talk standing circuit for separating and processing the chrominance component However, a symmetrical PAL clock signal is provided, i.e. it is a Clock signal in which different phases occur for the same period of time.

A problem with the recovery of the composite color television signal from a single stored color half-image or color image is justified in this, that each line of a field has a duration of 227.5 periods of the subcarrier frequency fso owns. In other words, this duration is equal to an integer number of periods plus half a period of the pilot's time. Will the around a horizontal line delaying delay lines through shift registers such as the Shift register formed in the comb filter 701, one condition is that an integer number of samples per television line and thus a delay of one Horizontal line is present.

According to the invention, a control stage 709 is therefore provided which including the symmetrical PAL clock signal from the asymmetrical PAL error indicator signal of the entire device and which one during the horizontal blanking period deletes an integer number of subcarrier periods plus half a subcarrier period, to a phase shift with respect to the preceding sample values with line frequency from 1800 to effect. The PAL clock signal therefore has the correct phase relationship with respect to the subcarrier frequency, as is the case for the regression of that for the color coding of the television signal necessary four fields is required, with the correct timing connection with the overall device is given.

49C shows a block diagram of the digital control stage 709, their circuit configuration in Figs.

48k-B and 49A-B is shown. Fig. 49D shows a signal diagram for timing signals at various points in the circuit of both FIG. 49 and also according to FIGS. 48A to B and 49A to B. Input signals from the overall system include the single-ended PAL error flag signal, a six-fold continuous phase Subcarrier frequency (6 fSC), half a phase-continuous subcarrier frequency (1/2 fSc) and an image index pulse on respective lines 758, 759, 760 and 761. The signals are incorporated into a PAL clock generator, generally designated 762 fed, which in turn is sent to the 4 phase clock generator 720 as part of the Control stage 709 according to Fig.

48A is coupled. The last-mentioned clock generator delivers in im the following way to be described the fi phase clock of the shift register 750A to B and 751A to B.

The PAL clock generator 762 receives the PAL error flag signal via an input 758 and feeds it into an exclusive-OR gate 763. This Gate is coupled to a D flip-flop 764 which also has the 1/2 fsc clock from a Receives input 760. The exclusive 0DER gate 763 and flip-flop 764 form a gated phase detector. A D-type flip-flop 765 is coupled to the flip-flop 764, this via a line 766 by a correction pulse in accordance with the control signal of group A (719) is clocked.

This fact is described in more detail below. A JK flip-flop 767 is coupled to flip-flop 765 by a terminal K, wherein the flip-flop 767 is clocked by the 6 fsc clock at an input 759. The flip-flop 767 is connected to a U} JD gate 768 and to the enable connection of the flip-flop 765 coupled. The flip-flops 765 and 767 and the AND gate 768 together form a clocked phase correction circuit. The AND gate 768, which also has the 6 fSc clock is to a divide by 2 JK flip-flop 769 as well as to a coupled by counter 770 dividing 1365. The picture index pulse via a Counter 770 receiving input 761 is on via a reset pulse generator 771 coupled to the dividing by 2 flip-flop 769. As shown in Fig. 49B, the picture index pulse becomes first clocked back to the inverted 2 is signal via a flip-flop stage. The counter 770 is also coupled to a counting decoder 772, which is at the input 719 the control signals of group A and the group B generated. That Group A control signal forms the correction pulse on line 766, which the flip-flop 765 clocks.

The output of the divide by 2 flip-flop 769 forms the symmetrical PAL clock, which is sent to a second input of the exclusive OR gate 763 is fed back, creating a closed loop in the PAL clock generator 762 is formed. The PAL clock is still sent to the 4 phase clock generator via line 725 720 according to FIGS. 48A to B and 49C, which as shown only generates the 4 phase clock signals of group A.

49C and 49D, when the counter 770 is turned on, it is the The circuit for separating and processing the chrominance component is incorrect set so that it is reset via the clocked back picture index pulse. This Impulse has a repetition frequency of 30 Hz and appears in a predetermined Field in which the sync pulses coincide with the vertical interval. To after resetting the PAL clock generator starts generating an initial PAL clock, which forms the true PAL clock. During the active part of a television line however, the PAL clock must be in phase with the device's PAL error flag signal be.

In other words, the rising edge of the 1/2 fcc signal coincides with the rising edge of the PAL clock when the PAL error flag signal is high. Otherwise, the opposite is true. The (initial) PAL measure, which can have the waveform according to FIG. 49D- (17) or (18), when switching fin fed back to the exclusive OR gate 763 along with the PAL error flag signal. When the PAL error flag signal is high, the output of the Exclusive 0DER gate is deep, even if the PAL clock is low. If the PAL error flag signal is low, so the output of the exclusive OR gate is low when the PAL clock is high.

This uses the PAL clock to form the 3 fSc signal from the PAL form regressed, the 3 fSc signal together with the 1/2 fsc signal in the flip-flop 764 is fed in. This flip-flop 764 compares the reconstructed from the PAL form Signal and the 1/2 fSc signal (S4gnaldcharts shown in Figs. 49D- (16), (17) and (18)). When the flip-flop 764 receives the data, the PAL clock is with the PAL error flag signal not in 'phase or vice versa. This leads to the exclusive 0DER gate and the flip-flop 764 the clocked phase determination.

If the PAL clock does not have the correct phase, it is canceled the flip-flops 765 and 767 and the AND gate 768 formed clocked phase correction circuit a period of the 6 fsc clock to shift the phase by 1800 and the PAL clock to bring into the correct phase position relative to the PAL error indicator signal. During the active part of the television line in which the phase is known to be the is the same, the correction pulse on line 766 delays the time in which the determination and correction is carried out. Because the phase reversal process the keying carried out in the video signal in accordance with the explanations given above with regard to FIGS. 9 and 11 does not occur during the horizontal interval, the determination can be made the correct phase of the symmetrical PAL clock during the horizontal interval do not occur. However, the correct phase of the symmetrical PAL clock is once detected, the phase of the PAL clock changes thereafter during the horizontal blanking interval.

The counter 770 counts 1365 count values corresponding to one television line of the 6 fSc signal (Fig. 49D- (1)) and provides on a leading edge of the 2 fs signals (Fig. 49D- (2)) a carry (Fig. 49D- (3)) for the reset pulse generator 771. This generator contains a sequence of D flip-flops, which provide 6 counts after the carry has taken a low level. This creates a sequence of high levels as shown in Figures 49D- (4) through (8).

The inverse output signals corresponding to the signal trains according to Fig. 49D- (6), (8) form the beginning and the end of a low level for the through 2 dividing JK flip-flop 769 (Fig. 49D- (9)), which in turn creates the syrmetric PAL clock of frequency 3 fSC (Fig. 49D- (10)) on line 725 is generated.

As can be seen from comparing the signals of Figs. 49D- (10) and (11) is, the phase of the PAL clock is shifted by 180 ° that 2.5 periods of the continuous phase 3 fSc signal can be deleted. Has the input signal of the divide by 2 flip-flop 769 assumes a low level, then remains the rising edge of the PAL clock corresponding to the next rising edge of the 6 fSc signal at a low level. This also applies to the following two rising edges of the PAL clock. Has the input signal of the flip-flop 769 Assuming a high level, the PAL clock takes on the following rising Edge of the 6 fsc signal goes high, but relative to the phase during a phase shift of 1800 takes place in the preceding line (Fig. 49D- (11)). This erases half the period of the subcarrier frequency of each television line guaranteed.

The counter decoder 772 coupled to the counter 770 generates after a specified counter value the control signals of group A and B, which are transmitted via the input 719 can be fed into the 4-phase pulse generator 720. The group's control signal A. is, as explained above, into the clocked phase correction circuit via line 766 fed in.

The 4-phase clock generator 720 ensures a predetermined timing control the comb filter shift register 750A to B and 751A to B, with at the outputs an integer number of sample values per television line (e.g. 680 sample values) below Use of the symmetrical PAL-3 fSc clock is guaranteed. This becomes a Another problem avoided by the integer number of subcarrier periods plus half a subcarrier period per line, with half the line being a prevents correct keying from line to line and therefore deleted or otherwise must be compensated.

For this purpose, the 4 phase clock generator 720 contains an Uber the line 725 coupled to the PAL clock and divided by 4 binary counter 773, which in turn is coupled to a 1 out of 4 bin ground decoder 774. Then is the connection to the shift register stage selection circuit 752A (and the selection circuit 753h) according to FIGS. 48A to B in the sense described above. The input data of binary decoder 774 are high with selected output signals at a low level and unselected output signals at a high level lie. Shift register stage selection circuits 752A and 752B are connected to the broadband selection stage 754 (Fig. 48A) which digital words from the sliders of the group Select A or B as a function of the group A and B control signals from the 772 counting decoder. The binary decoder 774 is connected to 4 D flip-flops 776a to d via a switching stage 775 coupled. The switching stage 775, whose output signal follows the input signal, is coupled to the PAL clock, and the flip-flops 776a to d also have a Inverter 777 are coupled to this PAL clock.

Clock signals 1, 2, 3 and 4 are both fed into the shift register 750A (and 750B) and into the shift registers 751 (and 751B) of the comb filter stages 710 and 711 (Figs. 48 to B). The video input signal is over the line 700 fed into the shift register.

The overlapping 4 phase clock signals 1 to 4 (of the order of magnitude of 150 nanoseconds) are transferred to the multi-stage 2-phase shift register 750A (750B) to clock consecutive 4 bit pairs in alternating stages, whereby the required clock rate is guaranteed. This clock rate cannot be processed by the shift register without 4 phase clocking takes place in the alternating stages. To ensure the exact delay by one horizontal line, the 4 phase clock signals as shown in FIGS. 49D- (12) to (15) switched off during the 2 1/2 periods of the PAl cycle according to FIG. 49D- <10). Since the shift registers provide a capacity of 512 bits, they can accommodate 680 Provide bit corresponding to the delay by one horizontal line.

In Fig. 490, only the group A shift registers 750h are shown as well the necessary timing controls of the delayed by one horizontal line Delay line 710 shown. The PAL clock (725) of the group's control signal However, B (719) also goes into the shift register of group B of the delay line 710 (Fig. 48A).

Furthermore, the delay line 711 (Fig. 48B) is the same as the delay line 710, whereby the PAL clock and the control signals of group A and B are also used Find.

Figures 49k-B show a digital embodiment of the control stage 709 according to FIG. 49C and the transversal filter 705 with odd symmetry according to FIG Fig. 18, in this Transversal filter over the lines 703b and 702 the filtered chrominance signal and the one delayed by one horizontal line Broadband signals are fed in.

The schematically illustrated components 714 to 718 of the filter 705 are used to rotate the phase of the chrominance signal by + 900, with the inverter 718 converts the signal as a function of the inversion control signal on line 707 1800 inverted. A phase change by - 900 can be achieved by changing the sign accordingly be generated.

The addition stages 715a and 715b are activated by input signals clocked, the sign of which is opposite to that of the illustration according to FIG. 18 are chosen. The inverter stage 718 is made up of several exclusive ODSR gates formed, which carry out the phase inversion around 1800.

The bandpass filter has a gain of 27/32, so that the gain of the broadband signal must be adapted to this gain. To this end, will 49A to B show the broadband signal delayed by one horizontal line coupled to a programmable read only memory 722 which stores the broadband signal multiplied by a factor of 27/32 to give an overall gain of 1.

The broadband signal is then passed through an (eight-stage) delay circuit 723, which shows the delays in the broadband channel in terms of delays in the chrominance channel due to the bandpass filter 704. Then the broadband signal coupled to the addition stage 706. Between the addition stages 706 and 708 are Register 724 is provided, which temporarily stores the intermediate signal, while the luminance signal is clocked by the adder 706. At the exit 728 becomes the composite color television signal through the adder 708 49B, with repeated reproductions of the stored Video signal can be combined.

A circuit diagram of the PAL clock generator shown in block form in FIG. 490 762 is shown in FIGS. 49A-B, while the 4 phase clock generator 720 49r is shown in detail in FIGS. 48A-B. Because the mode of action of the generators 762 and 720 has already been explained with reference to FIG. 49C the circuit diagrams according to FIGS. 49A to B are not explained in more detail. In the corresponding In the figures, the same components are provided with the same reference symbols.

According to FIG. 49t, there is an input 778 for receiving chroma and picture switching signals These signals are provided by the computer control system 92 via the video / low gate output circuit 127 and the reference clock generator 94 are supplied. The image switching signal represents represents an ear dominance inversion control signal which is to be inverted and not Specifies the color image to be inverted. The image switching signal generates the inversion control signal at the input 707 for the transversal filter 705, this inversion control signal at input 757 according to FIGS. 49B and 50A also fed into stage 756 (FIG. 50B) will. As has already been explained with reference to FIG. 18, the inversion control signal is present high during a color image to keep the input signal unchanged through the exclusive ODEP. gate 718 to direct. In the next picture, the inversion control signal is low to reduce the To change the sign and the two's complement to invert the chrominance component to build. The chroma switching signal at input 778 couples over the picture switching signal an AND gate 779, which prevents inversions from the image switching signal, when the device is not receiving signals from a disk drive unit. The device then works in a purely electronic one Operation in which a Chrominance inversion is not required.

49A-B, the PAL clock generator supplies the PAL clock also via lines 781 and 782 to the inversion input of the dividing by 2 JK flip-flop 769 and to the inverters 780. The PAL clock is used to clock the addition stages 715a and b of the multiplying programmable read-only memories 716a and b, the delay stages 714a, b and c, which delay a sample value, and the delay stage 723

19 shows a further embodiment of the circuit arrangement for the separation and processing of the chrominance component, with identical components as in Fig. 17 are provided with the same reference numerals. The transversal filter 705 17, 18 and 49 is replaced by a digital inverter stage 705a, which is selectively activated via a control line 707a. In one picture the Inverterstuoe leaves the incoming signal from the bandpass filter 704 unchanged while the line 707a in the other picture is an inversion control signal for the inverter stage supplies the bits of the incoming digital word before being fed in to move 1800 to the addition stage 708. That from adder 706 derived luminance signal is fed into the addition stage 708, which in the the composite color television signal at output 728 is generated in the sense described above.

FIG. 20 shows a modification of the embodiment according to FIG. 17, in which the addition stage 706 is missing and the inverter stage 705a by an inverter stage 705b is replaced.

In Fig. 20, corresponding components are also given the same reference numerals Mistake. The inverter stage 705b is through a digital, with 2 multiplying stage 75usa formed, which is sent to the bandpass filter 704 and to Performing a subtraction process on a negative input of an addition stage 708a is coupled. The broadband signal delayed by one horizontal line of line 702 is fed into the positive input of adder 708a.

The stage 756a multiplying by 2 is controlled via a control line 707b controlled by the chroma inverter control signal, the stage in a picture supplies an output signal 0, so the addition stage 708a the composite TV signal only from the broadband signal delayed by one horizontal line generated. The chroma inverter control signal (line 707b) from stage 756a, multiplying by 2, in order to pass the digital Signal to the negative input of adder 708a, while simultaneously the broadband signal comes from the comb filter 701. The multiplication process with the Factor 2 is done by shifting the lines by one bit, with the subtraction of the doubled chrominance signal from the broadband signal by the addition stage 708a alternate reproductions summed to form the composite color television signal to form at output 728.

The circuit of Fig. 20 is simplified in that the addition stage 706 is missing. In either case, the circuits of Figures 19 and 20 provide less Degree of conditioning of the chrominance signal in the case of repeated reproductions in comparison for the circuit according to FIGS. 17, 18 and 49. The circuits according to FIGS. 19 and 20 provide full saturation of the chrominance signal in the non-inverted picture, while in the inverted one Image is on the order of half saturation. The by the total digital Improved stability achieved in the process In connection with the inversion process, however, the colored edges correspond accordingly.

49E to F show a circuit diagram of the inversion circuit with associated control for the digital circuit for separation and processing the chrominance component according to FIG. 20. The broadband signal delayed by one horizontal line is supplied from comb filter 701 (Fig. 48B) via line 702, the filtered The chrominance output of band pass filter 704 from line 703b of FIG. 50B via the addition / control stage 756a (which is part of the inversion circuit forms) is delivered. For reasons of clarity, this is part of the inverter stage 705b, which corresponds to the addition control stage 756 according to FIG. 503, in FIG.

49E is represented by a dashed block 756a after line 753b. The control line 707b for the Zhromainverter control signal corresponds to the input 757. This control signal switches the enable input of the registers of stage 756a effective in a non-inverted image to prevent the passage of the signal and to in effect the input signal 0 from the bandpass filter for the adder 708a to build. In the inverted image, the chroma inverter control signal switches the enable input the registers of stage 756a to pass the chrominance signal. The multiplication process with a factor of 2 is carried out by sliding the line connections to the Doubling the chrominance signal shifts the digital forward by one bit to ensure.

The broadband signal delayed by one horizontal line is converted into a the delay circuit 723a corresponding to the delay circuit 723 according to FIG. 49A (FIG. 49E), which the delays in the broadband signal to the delay in the chrominance signal caused by the bandwetting filter 706 adapts. The broadband signal is then fed into a 27/32 multiplier 722a (Fig. 49E to F), which performs a gain adjustment. The broadband signal from the multiplier 722a along with the output of the addition / control stage 756a fed into the addition stage 708a. The composite video signal becomes at the output 728 by the addition stage 708a in the case of alternately repeated reproductions obtained by a subtraction process in alternating images.

Just like the circuit according to FIG. 49; through B contains the circuit 49E to F the control stage 709 with inputs 758, 759, 760 and 761, a PAL clock generator 762, a counting decoder 772, the input 719 for the control signals of group A and B as well as the input 725 for the PAL clock.

As mentioned above, the chroma inverter control signal is via an input 757 is fed to the addition / control stage 756a. The PAL clock will Supplied via inverter 780 by JK flip-flop 769 and via lines 781 and 782 into the various stages of delay circuit 732a, the 27/32 multiplier 722a and the addition stage 708a fed to the digital signals in a known per se Way from the preceding logical processor component into the following logical Clock processor component. The various logical elements of the circuit 49E to F therefore corresponds to the elements of the circuit according to FIG Fig. 49t to B.

Fig. 21 shows a block diagram of a digital circuit for isolation and processing the chrominance component, generally like those already described Circuits works. This circuit generates the composite color television signal However by repeatedly rendering a single stored color field. As in Components that correspond to those of the preceding figures are similar here as well Provided with reference numerals. The chrominance signal is made from the color video wideband signal separated via the comb filter 701 and via the input 703a into the bandpass filter 704 fed in. This is delayed by one horizontal line via line 702 Broadband signal fed into adder 706. The filtered chrominance signal is via line 703b into an inverter stage 705c and especially into the transversal filter 705 with odd symmetry according to FIGS. 17, 18 and 49, a third input an electronic switch 737 and a first input of a further electronic Switch 738 fed. The number of inputs of the switches corresponds to the number of the reproductions of the single field for the regression of the four fields of the composite color television signal. The output of the transversal filter 705 is to a second input of switch 737 and a fourth input of the switch 738 coupled. The output of switch 737 is to one of the inverter 705b in accordance with FIGS. 20 and 49E to F (or the inverter 705a according to FIG.

19) corresponding inverter is coupled, which in turn is connected to the second and third input of switch 738 is coupled. The outcome of this Switch is coupled to an input of adder 708, while the output of the addition stage 706 coupled to the other input of this addition stage 708 is. The control stage 709 supplies switching signals via a control line 707c to to switch the switch stages 737 and 738 with half-frame frequency through their inputs, to activate the transversal filter 705 and the inverter stage 705c and around the filters 701 and 704, the addition stages 706 and 708, etc.

to control in the sense described above.

As is known, there is a phase rotation of 900 between the fields required because a whole number of periods of the subcarrier in a field plus 3/4 of a period of the subcarrier is present. To the regression of the four The inverter stage 705c effects fields of the composite color television signal shifting the single stored field by 900 in each of the four successive renditions. For this purpose, a first playback of the stored field of the switch 738 switched to the first input, around the filtered chrominance signal from bandpass filter 704 via switch 738 with the incoming luminance signal from the addition stage 706 directly to the addition stage 708 to give. The first field is therefore with a phase shift of 0 ° supplied to output 728.

The second time the stored field is played back, the Switches 737 and 738 switched to the second inputs, the chrominance signal via the transversal filter 705, the switch 737, the inverter stage 705b and the second input of the switch 738 is given to the addition stage 708. The transversal filter 705 causes a phase shift of, for example, + 900 and the inverter stage 705c a phase shift of 1800 to the frequency components of the chrominance signal turn + 2700 CLOSED.

On the third display of the field, the switches 737 and 738 switched to the third inputs, whereby the chrominance signal via the Shoulder 737 the inverter stage 705c and the third input of the switch 738 Edition level 708 is given. The chrominance signal is thus rotated by + 1800.

On the fourth playback, switch 738 is set to fourth Input switched, which means that the chrominance signal only passes through the transversal filter 705 is applied to the addition stage 708 in order to achieve a phase rotation of + 900 cause. The four fields are displayed in successive displays over the Summer 708 combines to produce the composite color television signal at the output 728 to generate.

The sign of the phase shift can be changed, where the circuit connections and the clock signals are adapted accordingly, whereby on the second display of the field, the transversal filter 705 removes the chrominance component turns by - 900, after which it is coupled to the adder 708. The third Playback, the inverter stage 705c rotates the chrominance component by -1800 while in the fourth playback the trenaversal filter 705 a rotation of -90 ° and the Inverter stage 705c causes a rotation through - 180 °, resulting in a combined shift of the chrominance component by - 270 ° results. This becomes the phase shift of 906 guaranteed between plays.

The control stage 709 supplies the PAL clock, the 4 phase clock signals, the ear domain inverter control signal, etc., for the various components of the inverter stage 705c, the filters 701 and 704 and the addition stages 706 and 708 in the above-described Senses.

As is known, the horizontal sync pulses at successive Playbacks without a delay of half a horizontal line in alternating Fields out of alignment when a composite color television signal is recovered from a single field. Although the circuit of FIG not right for this Problem is designed and the desired A sequence of fields supplies are additional components for detection when they are used of the vertical interval and the delay of half a line as a function of this Determination required. Such measures are known per se.

Instead of a 3 f50 key sequence frequency in the sense described above other cycle rates can also be used. For example, can Key sequence frequencies of 4 f50, 16/5 fS> etc. are used. A cycle rate, which supplies an integer number of sample values per television line is advantageous, because then the PAL clock is not required and the PAL clock generator 762 is omitted The PAL clock per se is therefore not required for the separation and processing of the ear dominance component. When using a band pass filter with the reinforcement 1 can also include components such as the 27/32 multiplier and programmable multiplier read-only memories are no longer required.

Video playback output circuit Die by the video playback output circuit The functions carried out consist primarily of one during the blanking period Insert black level, and during the time in which a still picture is reproduced and another has been addressed for reproduction, a gray level to insert. The head movement in the disk drive units can be a period of time have from one to four fields, the radial movement the greater is, The greater the time it takes to change from one image to another. Is about a track has been played on the outside of a stack of discs and lies that next addressed image on an inner track of the same disk stack, see above is a time of almost four full for the heads to move to the new position Fields required. As it is convenient for aesthetic reasons while To have no black picture during this time period, a gray level is inserted. the Circuit continues to perform bit erasure operations in which one or more the sample values defining the bits of a field are set to the logic zero level in order to be able to realize special effects during playback. In the Circuitry shown as block 127 in Figure 9A generated from a PhL error flag signal a PAL-3 SC clock signal for the digital to analog converter 103. Furthermore, it generates a continuous sinusoidal subcarrier signal derived from the continuous phase 6 SC and 1/2 SC square wave signals can be phase-adjusted. These signals are for the circuit provided by the reference clock generator 98. It also serves the circuit for adjusting the values present during the display of an image half period of the 3 S ^ signal, which in the sense described above in the reference clock generator 98 was established. After all, the Circuit 127 on a line 874 the chroma inverter control signal, which the circuit 101 for separation and processing the chroma component effectively switches to the phase of the chroma component in alternating frames of the received television signal in playback operations to invert.

The operation of the circuit 127 for level introduction in the blanking interval as well as bit masking is described below with reference to the block diagram according to Fig. 22 explained. The image delay signal from the reference clock generator is generated via a Line 857 fed to an input of an exclusive ODFR gate 872, the other input on line 878 the PAL error flag signal from the reference logic circuit 125B received. The output signal of the gate 872 runs over a line 878 ' a control logic 876.

The image delay signal is used to invert the PAL error flag signal with frame rate, which shifts the PAL clock from frame to frame half period of the 6 SC clock is impressed, creating the final output video signal is reset.

To ensure reliable keying of the video data in the digital-to-analog converter 102 to ensure by the PAL clock for the digital-to-analog converter, the the latter clock by the dild delay switching signal via the exclusive OR gate 872 is modified, the video data itself becomes selective by half a clock period delayed so that the keying of the data does not occur during a transition between bits he follows.

This function is provided by the upper part of the circuit according to Fig. ? 2 carried out as follows. The video data from the chroma processing circuit 101 are fed in on a line 850, which on an 8 bit register 851, whose output signal on lines 852 to a further register 853 and to a data multiplexer 854 (4: 1 x 8 bit). The registers 851 and 853 are connected to one line by the phase-continuous 6 SC clock 855, the output of the 8-bit register 853 also via lines 856 is led to the multiplexer 854. The registers clock the data from the lines 850 with a delay of half a period of the 3 SC signal through, so that the data appearing on line 852 by half a period of the 3 SC signal are delayed while the data on lines 856 is clocked through the two registers have a delay of one full period of the 3 SC signal. Since the same data are sent to the multiplexer 854 via the lines 852 and 856 the data on lines 856 is relative to the data on lines 852 delayed by half a period of the 3 SC signal.

The frame delay signal from reference clock generator 98 on the line 857 is also given to an address control logic generally designated 858, which controls the multiplexer 854 via lines 859. While alternating pictures the frame delay signal controls the address control logic to alternate data from lines 852 and lines 856 are continued to the offset by half a period of the 3 SC signal, which occurs on the second reproduction of the first Field is present in the sense described above to correct.

If the black fade command or the gray fade command, which from the computer control system 92 via the signal system interface circuit 119 be on lines 860 and 861 are fed in, so will they are keyed into a register 862 by the V driver signal (key signal 1).

The V drive signal is input through the reference signal input circuit 93B fed in via a line 862 '. Register 862 controls the address control logic 858 as a function of the stored command so that the logic on lines 859 provides the corresponding levels to black level or gray level digital information to be introduced via lines 863 and 864. In the one delivered via output lines 865 Therefore, the black level or the gray level is inserted into the video data sequence. The black level and the gray level are set by a black level switch 866 and a gray level switch, respectively 867 is generated, the corresponding 8-bit word being the black level or the gray level digitally defined. If the corresponding bits are to be masked out, bit masking control lines are used 868 coupled to the multiplexer via lines 869, provided that that gate 870 is effective by a bit masking switching signal on a line 871 are switched. The bit masking switching signal is generated by the address control logic 858 delivered. During the blanking interval, bit masking is blocked in order to not to change the pedestal level of the video information. The blocking takes place by the gated H and V blanking signals that are generated by the digital-to-analog converter 102 is provided over line 858 'to address control logic 858.

For the generation of the PAL-SC signal, the phase continuous 1/2 So and 6 SC input signal on lines 873 and 855 used, whereby the 1/2 SC signal is given to a pulse shaper 875, which converts the 1/2 SC pulses accordingly forms. and feeds into a control logic 876 via a line 877. One on one The PAL flag signal on line 878 controls either the 1/2 SC pulses on a set input 879 or a reset input 880 of a divider that divides by 2 881, which is clocked by the 6 SO signal on line 855. The output signal is a 3 50 signal on line 882 whose phase is determined by the control logic 876 processed 1/2 50 pulses as a function of the level of the PAL error flag signal on line 878 is changed.

The 6 SC and 1/2 50 signals are fed into a color synchronous phase coarse control stage 884, the output signal of which is fed into a 6-bit shift register via a line 885 886 is fed in. This Si ieberegister is clocked by the 6 C signal and has six lines for taking up the color response phase after every 600. The shift register is connected to a voltage controlled capacitance network via a line 887 888 out which a fine control of the color synchronous phase via a line 889 enables. The output signal is a 50 square-wave signal on a line 890, which is fed into a limiter and filter stage 891 in order to be on an output line 892 to generate a continuous sinusoidal SC signal, which in turn is used for Generation of the burst signal for the composite analog television signal is exploited.

A circuit for performing the functions of the block diagram 22 is shown in detail in FIGS. 51 and 7B. Since those in these FIGS. 51A and 51B as well as the circuit of the block diagram 22, it will not be described in detail here.

Regarding address control logic 858, however, it should be noted that they corresponding command signals on the lines 859, 871 and 874 supplies to drive the video playback output circuit 127 so that data as a function of the control input signals on lines 860, 861, 862 'and 874' fed into the following digital-to-analog converter 102. That through the coding switch 126 supplied via a line 874 from control signals of the computer control system 92 The EE / PB signal is entered into the register by the V drive signal on line 862 ' 862 keyed in. When performing playback operations, the register returns 862 a chrominverter switching command via a line 874 for activation two circuits. One of these circuits is the isolation circuit 101 and processing of the chroma component. The other circuit is through a NAND gate 857a is formed in the image delay line 857. This NAND gate 857a is through the command is activated to the image delay signal for the above Purpose to couple to address control logic 858.

In purely electronic operations, the ear dominance component becomes of the video signal is not inverted, with the above-mentioned image flickering at 46 nanoseconds does not occur in the video signal processed by the reproduction system 91 because a continuous television signal, color-coded in four fields, into the electronics of the playback system 91 is fed in. The EE / PB signal keyed into a register 862 blocks the NAND gate 857a and switches the chroma inverter switching command from the Line 874 off.

Address control logic 858 includes NAND gates 883a, 883b and 883c and a multiplexer 858a around those provided by NMjD gates 883a and 883b To carry command signals onto the multiplexer control lines 859. The NAND gate For the reasons mentioned above, 883c blocks bit masking while of the blanking interval, which has three inputs which carry the blanking signal via line 858 'and the black and gray fade out commands from the register 862 record. If one of these three functions becomes effective, the inputs become of NAND gate 883c is brought low, causing line 858 to go high Level comes and the bit masking circuit is switched off. The NAND gate 883c thus supplies a bit masking control signal on line 871, this signal However, not in the blanking intervals and in gray and black fade out operations is available.

The inputs of NAND gates 883a and 883b are connected so that the NAND gate 883b has a low output during normal playback operations Level and the NAND gate 883a provides an output signal with a high level. The multiplexer 858a switches these output signals on the two lines 859 in each frame as Function of the frame delay signal on line 857 so that the multiplexer 854, in the sense described above, alternate data from the two registers 852 and 856 leads.

If there is a gray masking command on line 861, the register delivers 862 a low-lying lock signal to one of the inputs of the NAND gate 883c, whereby the bit fade control signal on line 871 is turned off. A Inverter 861a, however, inverts the low level supplied by register 862, thereby driving the output of NAND gate 883a low will. Multiplexer 858a activates lines 859 so that multiplexer 854 the digital gray level information from lines 864 onto the data output lines 865 couples.

Black level fade operations are selected by having a Switch 860a is switched so that the black fade command at the output of the Register 862 is fed to an input of NAND gates 883a, b and c. This Fade-out command causes these gates to deliver high-level signals. Therefore, the bit blanking control signal from line 871 is turned off. The multiplexer 858a activates lines 859 so that multiplexer 854 receives the digital black level information from lines 863 to data output lines 865.

DIrital-i'naloconverter and color sunchronsjRnal.- and synchronsinal insert Do in the final rendering functions performed in the block diagram of Figure 9A it is a question of converting the digital video signals into a final log signal as well as the generation and insertion of the burst signal and the composite Sync signals. The functions carried out are based on the block diagram according to Fig.

23 described in which the digital video information on 8 bit lines 900 is fed from the video playback output circuit 127 into register 901, that aligns the bits on the bit lines so that the digital-to-analog conversion can be carried out. One through the video playback output circuit 127 The 3 SC-PAL clock signal generated is fed in via a line 902 and clocked both the registers 901 and a second register 903 as well as a back-keying gate 904. The digital video information appearing at the outputs of the registers 901 is fed via output lines 905 in the current switch 906 to which reference current generators are coupled. The power switches 906 are connected to a resistor network via lines 907 908 coupled, the one weighted analog value of each of the 8 bits of the digital word supplies, so that an analog value with 256 possible levels is created.

The analog output signal of the resistor network is via a Line 209 in two paths, namely an upper path 910 and a lower path 911 nuffed. The upper path 910 represents the normal path over which the video information is fed into a switch 912. The lower path 911 leads to a blanking filter 913, which during the Blanking time is switched to the blanking pulse to shape so that it has flanks with the correct slope.

If the blanking filter is not available, the rapid transition can take place from the video information to the blanking signal to oscillation in television receivers to lead. The output of filter 913 is fed into the switch via line 914 912, which is controlled via a line 915 coming from the pegister 903 will. Register 903, in turn, is activated by the 3 SC-PAL clock on the line 902 clocked. The analog signal on line 909 travels over both paths 910 and 910 911, with the exception of the blanking period via the switch in its top Switch position is performed. During the blanking interval, the switch is on its lower switch position is switched, i.e. it takes it through the blanking filter 913 filtered signal.

The signal is passed from switch 912 via line 916 to the reset gate 904, which shows the signal level immediately before a level jump in a Point in which all transitions from a previous jump disappear are. For example, in the digital word with 8 bits, a change in the value in up to 7 or 8 changes between logic levels, i.e. from 1 to 0, are made each change creates a transition condition in the switch.

The backspace gate 904 performs a key and hold function, whereby the junctions are blocked so that they stand on line 917 Do not influence analog information. Line 917 is on a buffer and Low-pass filter stage 918 out.

This buffer and low-pass filter stage is on a line 920 an amplifier and equalizer stage 919 led, which is a sine and performs attenuation compensation, after which the signal is reduced to a black limiter stage 921, which cuts off all luminance components of the video signal, which are below the black level. An output line 922 of the amplifier and Equalizer stage 919 also forms part of a DC voltage recovery loop containing a switch 923 and a loop amplifier 924 and generates a feedback signal fed to the buffer and low-pass filter stage 918, the switch being controlled by a clamping pulse on line 925; The DC voltage level of the video signal is thus reduced on line 922. The clamping pulse is in that supplied from the reference signal input circuit 93B Blanking signals and composite sync signals are present on a line 933.

The output signal of the black limiter stage 921 is via a line 927 fed into a synchronous and color synchronous addition stage 928, which the Color sync signal on line 929 and the sync signals on line 930 receives, so that on a line 931 leading to output amplifiers 932 complete composite analog television signal is produced. The sync signal is generated by a synchronizing shaper stage 934, which one in the mistast signals and the sync pulse contained in the composite syrichron signals on line 933 processed and the correct rise time of 140 nanoseconds as well as a correct one Pulse shape guaranteed. The burst signal is made of a burst signal error flag signal generated by reference signal input circuit 93B on line 935 is delivered. Because of this The signal becomes a color synchronous envelope detector 936 controlled, the output line 937 of which is routed to a multiplier 938, which modulates a sinusoidal signal of frequency SO on a line 939. That The latter signal is, as already stated, in the video playback output circuit 127 generated. The output signal on line 929 contains the color synchronous envelope with 9 to 11 periods of the chrominance signal. This composite signal becomes the analog Video signal on line 927 added.

An embodiment of a special circuit for performing the Operations of the block diagram of Fig. 23 are shown in Figs. 52A to 52D. This circuit operates in the same way as the block diagram of Fig. 23 and is therefore not explained here in detail. Referring to Figs. 52A and 52B, a blanking signal becomes fed into a line 950 which is carried to the register 903. This register provides an output signal for several switching transistors on lines 915 953, which together with two transistors 954 and 955 form the switch 912, which is either the signal in upper path 910 or lower path 911 from the filter 913 selects. During the scan, the trensistors 953 block the transistor 954, while the transistor 955 is switched through. At all other times the switching behavior is reversed.

Regarding the reset gate 904, a becomes on the line 902 led clock signal led to several inverters 957 and 958, which have a low Cause the propagation delay of the signal, so that the line 902 on Clock signal carried by transistors 961 and 959 is shifted from one another, making a positive leap on the primary side of a transformer 960 is created. The secondary of this transformer is connected to a diode bridge 904 coupled, which blocks the signal flow during the period of the pulse, to a passage of jumps or spikes during the switching of the switches 906 of the digital-to-analog converter.

power supplies and recording and reproducing amplifiers Fig. 24 shows part of the equalizer and data detector circuit 99 of the recording and playback channel including a playback head coupled to a preamplifier 1009 1008, the combination of elements 1008 and 1009 being combined to form a block 1001 are. The magnetic flux patterns recorded on a disk surface are picked up by playback head 1008 and by preamplifier 109 reinforced. Due to the known differentiating effect of the playback head the output signal of the block 1001 at a terminal 1006 is represented by a voltage which is equal to the time derivative of the recorded flow.

The transfer function of block 1001 is symbolic in the conventional one Representation of the Laplace transformation given by the following relationship: G1 = k1s (1) where: G1 is a complex transfer function, k1 is a gain constant, and the complex Laplace variable.

In the following, the aforementioned symbols G, k and s are retained, where for indexing the special circuits to which the designations refer refer, only the indices are changed. Denote in the following equations Symbols R and C with the corresponding indices corresponding resistance and capacitance values of corresponding switching elements. These switching elements are in the figures also by identical reference symbols and corresponding indices marked.

The output of block 1001 of Fig. 24 is fed into an equalization circuit 1000 fed in, which in idealized form for the theoretical explanation of the Equalizer function is shown. The input of the equalizer circuit 1000 is on the connection 1006 of the block 1001 is coupled.

In particular, an input of an integration stage is connected to the connection 1006 1002 and an input of a differentiation stage 1003 are coupled. The transfer function of the integration level is equal to: G2 ak2 / s (2) The transfer function of the differentiation level is equal to: G3 tk38 (3) There is a variable gain control branch in the differentiation signal path 1004, which caused a linear change in the values caused by the differentiation stage 1003 Hochfreouenzrerstärkung allows, which will be explained in more detail below. The difference between the output signals of the integration stage and the differentiation stage is formed in a subtraction stage 1005. The resulting difference signal at an output 1007 of the equalization circuit 100 forms the required amplitude and phase equalized signal from the input signal at terminal 1006.

The resulting recording and playback channel has one flat overall gain characteristic and a linear phase characteristic for all transmitted signal frequencies, which is also explained in more detail below will.

The overall transfer function of the recording and playback channel according to FIG. 24 with the block 1001 and the equalizer circuit 1000 is given by the following relationship: = C1 (G, = G1 (4) By substituting the quantities G1, G2 and G3 from equations (1) , (2) and (3) result: If s = jw is set, the result is: The total phase shift through the portion of the playback and recording channel shown in Fig. 24 is given by the following relationship: phase of G (jw) = arctan Im G tSwi (7) Since the expression on the right-hand side of equation (6) is a real number (the imaginary part is zero), the total phase shift given by equation (7) is zero. With a phase shift of zero, the condition of a linear phase characteristic is met for all transmitted frequencies in the channel.

It is essential for the equalization circuit, instead of a sum of the corresponding output signals of the integration stage and the Differentiation stage to form a difference signal at output 1007. The latter Levels cause an equal phase shift of 900 in opposite directions, with the The integration stage lags the phase and the differentiation stage leads the phase leaves. The corresponding output signals of stages 1002 and 1003 according to FIG. 24 are therefore exactly 180 ° apart in phase, so that a difference signal leads to a resulting signal combination for which the corresponding signal amplitudes not subtracted, but added.

In addition, the phase shift of -900 leads through the integration stage and the phase shift of + 900 due to the differentiating effect of the Playback head leads to a total phase shift of 00. On the other hand, the Phase shift of + 900 of the differential stage together with the phase shift from + 900 due to the differentiating effect of the playback head to a total phase shift of 1800, so it is just an inversion. Whether the resulting Total phase shift of recording and playback channel is 0o or 100, i.e. whether the output signal at output 107 with respect to the polarity of the recorded The flow is in phase or inverted depends on the direction of the 90 ° phase shift by the equalizer circuit 1000, which will be explained in more detail below.

In addition to the linear phase characteristic for all transmitted through the channel Frequencies, the equalization circuit also compensates for non-constant amplitude-frequency characteristics of the playback head, which can also be seen from the following remarks. The output voltage of the playback head 1008 increases in a manner known per se and the preamplifier 1009 according to FIG. 24 at low frequencies with an amount of 6 dB per octave, while in the range of the center frequency there is a Reversal of direction and then a drop at high frequencies. Such an amplitude characteristic is shown in the form of a curve GR in FIG. Should therefore be a flat Overall amplitude characteristic of the recording and playback channel realized it is necessary that the equalization circuit adjusts the amplitude both at low frequencies as well as at high frequencies. This equalization characteristic is in the The circuit of Fig. 24 is implemented in the following manner.

In the diagram of FIG. 28, the gain G2 is the integration stage 1002 and the gain G3 of the differentiation stage 1003 in dB as a function of Frequency plotted, with a logarithmic scale selected for the frequency values is. The curve G2 falls at an amount of 6 dB per octave, while the curve G3 increases with the frequency accordingly. Also in Fig. 28 are curves for two further transfer functions G3 and G3 of the differentiation stage are shown, which a linear change in these functions with the output signal of the gain control branch 1004 represent. A curve GE represents a resulting transfer function of the equalization circuit 1000, which is created by adding the linear quantities G2 and G3. It can be seen that the transfer characteristic GE of the equalization circuit 1000 is complementary to the transfer characteristic GR of the playback head. By combining the two Characteristics GR and G [performed by the circuit of FIG. 24] the equalizer characteristic compensates deviations from a straight course the characteristic Gp of the playback head at both low and high Frequencies, so that overall a flat overall amplitude characteristic results.

The equalizer circuit in question has a further advantage, there is a linear change in the amount of high-frequency boost due to the differentiation stage can be carried out. For this purpose, the variable is in the differentiation signal path Gain control branch 1004 according to FIG. 24 is provided. By adjusting the gain of the differentiation signal branch through branch 1004 can be the frequency at which the high frequency increase of the equalizer amplitude characteristic begins, changed will. For this purpose, a variable resistor or

a potentiometer can be provided. On the other hand, however, an amplifier can also be provided in the differentiation signal branch, the gain of which is changed in a manner known per se. This is explained in more detail with reference to the embodiment according to FIG. The group of curves GD, G3 and G3 according to FIG. 28 is obtained for three different gain values of the differentiation stage 1003 according to FIG. 24, the setting being made via the variable gain control branch 1004. The gain setting only affects the gain constant k3 in the transfer function (3) given above. Specifically, only the frequency value at which the high-frequency boost takes place is changed. The mentioned frequency value is given by the following relationship: If this frequency value increases, the amount of the signal amplitude increase decreases linearly, since the curves obtained shift from G3 via G3 to G3 and so on. A linear magnification of the amplitude increase at the high-frequency end of the equalization characteristic is an essential aspect because it enables compensation, for example, of changes in the relative speed between the head and the recording medium. Such a change in the relative speed can result, for example, from changes in the track length on a magnetic disk. When digital signals are recorded on a magnetic disc, this also enables compensation for the higher density of recorded bits that is present on the inner tracks of the disc. This effect is also known as pulse compression.

Examples of practical embodiments of the above-described idealized form of the equalizer circuit according to FIG. 24 are shown as block diagrams in FIGS. The same elements are provided with the same reference symbols in each case. With regard to the relatively low signal level at the output of the playback amplifier 1009, it is necessary for practical reasons to amplify the signal both in the integration signal branch and in the differentiation signal branch. According to FIG. 25, the integration stage according to FIG. 24 is formed by an inverting integration amplifier 1002 which contains an inverting operational amplifier 1010, a negative feedback capacitance C1 and a series input resistor R1. The differentiation stage according to FIG. 24, on the other hand, is formed by an inverting differentiation amplifier 1003 which contains an inverting operational amplifier 1011, a variable negative feedback resistor R2 and a series input capacitance C2. The variable resistor R2 enables variable gain control of the differentiation signal branch. The transfer function of the integration amplifier 1002 according to FIG. 25 is given by the following relationship: Comparing formulas (9) and (2) results in: The transfer function of the differentiation amplifier 1003 according to FIG. 26 is given by the following relationship: C3 A --- R2C2s (11) Comparing equations (11) and (3) gives: k3 - R2C2 (12) The subtraction stage in the circuit according to FIG. 24 is formed by a differential amplifier 1005 in the circuit according to FIG. The output of the inverting integration stage 1002 is coupled to an inverting input of the differential amplifier 1005, while the output of the inverting differentiation stage 1003 is coupled to a non-inverting input of the differential amplifier 1005. The output signal at output 1007 is the difference signal which represents the equalized signal of the recording and playback channel. The resulting equalized signal has a phase difference of 00 with respect to the signal recorded on the magnetic medium, ie it is in phase with this signal. When using the equalization circuit 1000, the phase characteristic of the overall channel is therefore linear.

The circuit according to FIG. 25 is, however, still idealized in that an exact realization of the transfer functions (9) and (11) mentioned above requires unlimited gain in the integration amplifier 102 at low frequencies and in the differentiation amplifier 1003 at high frequencies. In practical embodiments, these extreme requirements are avoided, for example, by introducing a shunt resistor R "for the capacitance CI and a series resistance R 'for the capacitance C2 in FIG. 25, whereby the corresponding integration and differentiation approximations are cut off at given frequencies below and above the frequency range of interest If the resistors R 'and R "are taken into account in the circuit according to FIG. 25, the corresponding transfer functions G2 and G3 result as follows: Here R1, R2, R ', R ", C1 and C2 mean the values of the corresponding switching elements.

If one takes into account the following conditions for equation (13): so it results: This expression is identical to the transfer function according to equation (2).

Consider the following for formula (14). Conditions: this results in: G3 # - k3s (18) This expression is identical to the transfer function according to equation (3).

From the above statements it follows that the corresponding transfer functions of the integration and differentiation stages of the equalization circuit 1000 according to FIG. 25 correspond to an ideal integration and an ideal differentiation in the following frequency range when ss jw are substituted: Fig. 26 shows a further practical embodiment of the equalizer circuit. The equalizer circuit buttocks Pig. 24 is formed here by a passive integration network 1002 with a series resistor RA and a parallel capacitance CA, which is followed by a non-inverting amplifier 1012, which ensures the necessary amplification in the integration signal branch. Correspondingly, the differentiation stage according to FIG. 24 in FIG. 26 is formed by a passive differentiation network 1003 with a series capacitance CB and a parallel resistor RB, which is followed by a non-inverting amplifier 1013 which ensures the necessary amplification ii differentiation signal branch. As in the circuit according to FIG. 25, the subtraction stage is formed by a differential amplifier 1005. In the circuit of FIG. 26, the integrated and subsequently amplified signal at the output of amplifier 1012 is fed into a non-inverting input of differential amplifier 1005, while the differentiated and subsequently amplified signal at the output of amplifier 1013 is fed into an inverting input of amplifier 1005 will.

The output signal at output 1007 of the circuit according to FIG.

26 is the resulting difference signal which is the equalized signal of the recording and playback channel. The resulting equalized Signal has a phase difference of Oo with respect to that on the magnetic Disc recorded signal. Therefore leads through the described equalization circuit caused phase difference to no non-linearities in the phase character of the overall channel; rather, the result is a linear overall phase characteristic.

The corresponding transfer functions of the integration and differentiation stage in the circuit according to FIG. 26 are given by the following functions: Here, A2 is the gain of amplifier 1012 and A3 is the gain of amplifier 1013.

A comparison of equations (20) and (2) gives for A comparison of formulas (21) and (3) results in k3 A3 BCB (23) A potentiometer 1014, which is coupled to the amplifier 1013 1 differentiation signal branch in the circuit according to FIG. 26, forms a variable gain control branch.

By adjusting the gain A3 of amplifier 1013, the Gain constant k3 according to equation (23) and the frequency value at which the amplitude increase changes, adjustable according to equation (8).

A detailed circuit diagram of an embodiment of the equalizer and data detector circuit 99 is shown in Figures 53A and 53B. Ii video image memory recording and playback system, a color television picture is encoded and recorded in digital form recorded on a magnetic disk. The digital code is free of DC voltage self-clocking channel code as described in the above-mentioned US patent application (File number 668 679) is described. When played back, the digital data is through reproduced by a reproducing head and amplified by a reproducing amplifier (Playback head and amplifier are shown in Fig. 54B).

53A and 53B show two identical equalizer and Data detector circuits for ten separate data sequences which are transmitted by the data interface circuit 151 come for the disk drive units. However, it becomes just one of those circuits described. In the circuit of FIGS. 53A and 53B, the pre-amplified Reproduction data in the channel code format according to, for example, the above United States patent application equalized by an equalizer circuit 1000, which the above described Equalizer circuits according to FIGS. 24 to 26 corresponds. The equalized signal is filtered in a low pass filter 1018 and then amplified and in amplitude limited to a square wave pulse sequence in an amplifier limiter circuit 1019 to generate.

The pulse sequence from the limiter is created by a pulse shaper 1020 sent, which forms output pulses for each detected signal jump. The pulses from pulse shaper 1020 are passed through the decoding and time base correction circuitry 100, which performs decoding and time base filters from the playback data eliminated from which the original color television signal is recovered.

As shown in Figs. 53A and 53B, the data is from the preamplifier fed into inputs 1021 and 1022 of a differential amplifier 1033 which, for example can be formed by a type CA 3004 manufactured by RCA.

This type of amplifier contains output transistors with open collector, which are coupled to outputs 1034 and 1035. A resistor 1036 forms the Load resistance for the non-inverting output 1034. The gain of the amplifier 1033 for the output 1034 is constant in the frequency range of interest. That non-inverted signal is buffered by an emitter follower 1037 and then fed into a differentiating network 1003, which is fed by a capacity 1038 and a resistor 1039 is formed. This network 1003 differs Signal frequencies below 60 MHz. Its transfer function is through the following relationship given: G3 # ################# (22) For w <############ results: G3. (1039) (1038) s (23) Equation (23) corresponds to Equation (3) discussed above for the block diagram of FIG. 24 with k3. (1039) (1038).

As the signals of interest in this particular embodiment only have frequencies up to about 10 MHz, this network 1003 can be considered real Differentiation stage are considered. The output signal of the differentiation stage 1003 is fed into an input 1040 of a differential amplifier multiplier 1041, which is formed, for example, by a type MC1496 sold by Motorola can be. The inputs 1040 and 1042 of the amplifier multiplier 1041 are differential inputs, which are biased by a voltage of + 7.5 volts. The amplifier multiplier 1041 receives a second input signal at differential inputs 1043 and 1044, where at an output 1045 an output current can be tapped, which is proportional to the negative product of the input signals at inputs 1040, 1042 and 1043, 1044 is. In the present embodiment, input 1043 is a. Amplification rule equation ichapennen is fed in while input 1044 is grounded. The control voltage at input 1043 corresponds to an output voltage of one at a different point provided variable gain control branch (not in Fig. 53 shown), for example in connection with branch 1014 according to FIG. 26 has been described. In the embodiment of the frequency equalizer in question here becomes the gain of circuit 1041 in the differentiation signal path by a digital-to-analog converter automatically regulated by another body, depending on the changes of the recording track length on the magnetic disk, the desired gain changes to realize. A special number of lanes (corresponding to a special lane length), special data from which are reproduced are stored in a digital decoder decoded and converted into a DC voltage value in the digital-to-analog converter, which is then fed into input 1043 of stage 1041 as a gain control signal will. As already stated above, the variable gain control is used in the differentiation signal branch to compensate for the higher pulse density on inner tracks of the disc, while the linearity of the high frequency boost of the equalized signal throughout the transmitted Frequency band is retained.

The magnitude of the current at the output 1045 of the amplifier multiplier 1041 is proportional to the input signal at input 1040 and to that caused by the control voltage gain value set at input 1043. The output current at output 1045 of stage 1041 is operated as an input current to the emitter of a base circuit Transistor amplifier fed, which as a subtraction stage 1005 in the sense of Fig. 24, 25 and 26 acts. This input current is generated at the collector of the amplifier an output voltage that corresponds to both the input current and the resistance value a collector load resistor 1047 is proportional. The aforementioned part of the Output voltage of transistor 1005 is proportional to the negative, signal amplified by the amplifier multiplier 1041.

The inverting output 1035 of the differential amplifier 1033 is connected to a load resistor 1048 and a parallel load capacitance 1049. The DC voltage gain of the amplifier 1033 is greater than the gain at the non-inverting output by the ratio of the corresponding load resistors 1048/1036, ie by a factor of about 3 1034. For signal frequencies above 80 kHz, the gain at output 1035 is determined by the capacitance 1049 and is inversely proportional to the frequency. The output circuit 1048, 1049 at the output 1035 therefore acts as an integrating network for frequencies above 80 kHz in the frequency range of interest, which ranges from approximately 0.3 MHz to 10 MHz. The transfer function of amplifier 1033 at output 1035 is given by the following relationship: A1033 means the gain of the differential amplifier 1033 at the output 1034.

For where (1048) (1049) we get: This equation (25) corresponds to the above-discussed equation (2) for the block diagram according to FIG The inverted and subsequently integrated signal from the output 1035 of the amplifier 1033 is fed into a transistor 1005 connected as an emitter follower. This transistor 1005 inverts this input signal and multiplies it by the ratio of the collector and emitter load resistances 1047/1050. The transistor 1005 operates in the integration signal branch as an emitter follower and in the differentiation signal branch as an amplifier operated in a base circuit.

The resulting output signal at the collector of transistor 1005 is equal to the sum of the two input signal contributions, one contribution being proportional to the integral of the playback signal from the playback head and preamplifier is and where the other contribution is proportional to the negative derivative of the playback signal is. The resulting output signal at the collector of transistor 1005 corresponds to therefore a difference signal corresponding to the output signal at output 1007 of the the above-described embodiments of the equalizer circuit according to FIGS. 24, 25 and 26. The output of equalizer circuit 1000 of Figures 53A and 53B is the same the equalized signal of the playback recording channel according to those described above Embodiments according to FIGS. 24, 25 and 26.

The following now describes the remaining part of the circuit after the Figs. 53A and 53B will be described. The equalization circuit 1000 transfers the voltage peaks the playback signal supplied by the playback preamplifier 1009 (Fig. 54B), that corresponds to the zero crossings of the recorded flow, into correct ones Zero crossings at the output of the equalizer circuit back. This equalized output signal stands at the collector of transistor 1005 of the equalizer circuit and is through a Filtered low pass filter 1018, after which it is filtered through a first buffer amplifier 1051 (for example the type MC10116P) of the amplifier-limiter circuit 1019 will. The output of the buffer amplifier is through a Sequence of five amplitude limiting amplifiers sent, which one is preferred are of the same type as the buffer amplifier. The one at the output of the amplifier-limiter circuit 1019 delivered equalized playback signal is in channel-coded form, with the signal jumps are correct. The amplitude limit of the playback signal is used to recover the rectangular shape of the playback data signal transmitted by the recording and playback processes became distorted. In addition, the Amplifier-limiter circuit 10.19 for the formation of antiphase forms of the regressed Data signal which is used to generate a pulse for each jump of the rectangular Channel-coded playback data signal are used. As above using the channel coding of the data signals by the decoder 96 and the subsequent recording thereof Signals has been described, the jump-related pulses are generated so that a precisely defined edge (in the exemplary embodiment the leading edge) through a transmission channel can be transmitted without causing errors in the data, although the data signal can be distorted by the channel. As already stated above, can in the data sequences with high bit density, as provided by the device in question processed due to the transmission characteristics of transmission lines, as used for the transmission of channel coded data between the disk drive units and the signal system are used, errors are generated.

To get one such pulse for every jump in the playback data signal to generate that only the positive leading edges identify the data signal peaks, the amplifier limiter circuit 1019 provides two anti-phase pulse trains of the data signal. Au output 1052 of the last amplifier 1053 of the Sequence of amplitude-limiting Amplifiers will be a square-wave pulse sequence with non-inverted polarity while at the output 1054 of the same amplifier 1053 an identical Pulse sequence is supplied with inverted polarity. These pulse frequencies are in one of two identical monostable multivibrators 1055 and 1056 (for example type MC10131L) of the pulse forcher 1020. Any multivibrator supplies for a positive jump of the playback data signal recorded at its clock input a positive impulse. The the non-inverted form of the playback data signal The receiving monostable multivibrator 1055 delivers with every positive jump of the Data signal a positive pulse. On the other hand, it provides the inverted form of the playback data signal, the monostable multivibrator 1056 receives a pulse at the point of every negative jump in the data signal. Since the leading edges of the through the multivibrators 1055 and 1056 generated positive pulses through a rapid Switching of the multivibrators from their stable switching state to their quasi stable switching state are defined (important, a time constant determining components are absent), each leading edge is with all others identical. These leading edges occur following a precisely defined point in time on the occurrence of the positive clock jump of the playback data signal. Since the Transmission channel via which Cie pulses are transmitted on identical pulse edges acts the same, go the positions of the jump-related positive pulse flanks and thus the jumps in the data signal itself are not lost due to distortion, which can arise in the impulses due to the effect of the transmission channel. If required, an amplitude value can be applied to the output of the transmission channel responsive detector can be coupled, for example at the entrance of the Decoding part the decoding and time base correction circuit 100 described above is provided is to precisely recreate the relative positions of the jumps in the playback data signal defix.

For the transmission of the jump-related impulses to the signal system the output pulses of the two monostable multivibrators 1055 and 1056 in separate Inputs of a positive OR gate 1057 fed in for each input pulse provides an output pulse. The output pulse.

This OR gate 1057 is entered in the interface circuit 151 for the disk drive units (Fig. 9B) for transmission over the lines 154 fed to the data selection switch 158, which the transmitted pulses on the input of the data decoding part of the decoding and time base correction circuit 100 of the selected playback channel 91 couples to a decoding of the reproduced Data and subsequent processing to recover the original color television signal perform.

54A and 54B show successive parts of a circuit diagram from recording driver. and playback preamplifiers for four identical recording and playback channels 1058, 1059, 1060 and 1061 which are stored in the video image memory recording and playback system can be used.

Ftn fifth channel 1062 contains a servo track which is constantly with is coupled to a servo playback preamplifier and also in a data track recorder. and playback channel is included. In the video image storage recording and playback system five additional recording and playback channels (not shown) are included, which with the aforementioned recording and playback channels according to FIGS. 54A and 54B are identical.

A relay 1063 in channel 1058 couples one of the heads 1064 and 1065 for a recording process, if via a line in the sense described above 1066, a recording command from the control circuit for the disk drive unit Will be received. In the absence of a recording command, relay 1063 is in the Playback position. In this position the contacts of relay 1063 are switched. The heads 1064 and 1065 are used for both recording and playback and are switched alternately for odd and even television fields. Switching these heads 1064 and 1065 is controlled by a head switching signal of 30 Hz, that via line 1067 continuously through the record timing circuit 38A, which is provided in the electronics of the disk drive units is included. The playback data received from heads 1064 and 1065 alternately of the corresponding channels 1058, 1059, 1060 and 1061 are in the corresponding Decoding and time base correction circuits assigned to playback channels according to FIG Figures 53A and 53B. Those in the video image storage recording and playback system The recording and reproducing heads used are conventional heads like them for example by the companies Applied Magnetic Corporation or Information Magnetics Corporation for digital recording on stacks of disks of the subject Device has been delivered.

Central processor interface circuit Ii following are the various interface circuits for the computer control system 92 according to Fig. 8, starting with the central processor interface circuit 108 which is the various parts, namely the teletype interface circuit 109, the paper strip reader 111, the read-only memory 112 and the address decoders 113 includes. Various facilities can be selected via these components and to be brought into communication with the address and data bus 105.

In the central processor interface circuit shown in FIG is shown as a block diagram, there are 13 lines of the address and data bus 105 1 upper part provided, which run to the CPU 106. These 13 cables lead an address word with 13 bits on a register 1100. This register is still controlled by a bus line selection signal and a bus synchronization signal. That s bus sync signal is used by the CPU ii address time of the address data multiplex period supplied via one of the control lines 144 to the address word and the bus line output signal, which identifies the peripheral device to be coupled to the CPU 106. A decoder demultiplexer 1101 does not use the address word stored in register 1100 as well as the bus line selection signal which is also stored in this register and decodes the address to one of the 21 device select lines 114 as a function to activate the address information. The decoder desultiplexer 1101 decodes the address and activates the corresponding device selection line as a function of the Bus line selection signal that is sent by the CPU 106 via one of the control lines 144 is supplied when the three most significant bits of the address one Identify peripheral request. A device selection line is created by switching activated from a high to a low level, with the associated selected Device is connected to the main bus 105 to transfer data to the CPU 106. As As stated above, 15 of the 21 control selection lines 114 lead to the peripheral ones Interface add-ons 115, 118, 119, 120 and 121, while the six remaining Device select lines to logic circuit represented by block 1102 lead to the interface circuits for the teletype 109, the paper tape reader 111 and the read-only memory 112 to control.

The control program is made using a paper tape reader 111 loaded into memory 107, with 8 data bit lines coupled via AND gate 1104 1103 are provided.

The outputs of the AND gates are via lines 1105 on 8 lines of the data bus 105 coupled. The loading of the memory 107 is carried out by actuation of a switch 1125 triggered, which upon pressing a command for the CPU 106 supplies, so that this corresponding device addressing and control signals via the Main bus 105 and control lines 144 supplies to that from the paper tape reader 111 to clock the control program on bus 105. The CPU 106 initially delivers Device addressing. and control signals which correspond to device selection lines 114 to activate a coding stage 1126 so that the read-only memory 112 supplies a load command sequence to the CPU.

After capturing the load command sequence, the CPU 106 executes the necessary Routines and arithmetic functions made up by the microprogram of the computer are set to the loading of the control program from the paper tape reader 111 characters for characters to perform. Specifically, the loading instruction sequence becomes in the form of a sequence of 6 characters with a subsequent loading command character through the Read-only memory 112 generated, each character being formed by a 7-bit word. Each 7-bit character of the sequence is under control by read-only memory 112 encoded by the coding stage 1126 and sent individually to the CPU 106 by clicking on the main bus 105 is clocked after a status command indicating the availability which shows data in read-only memory has been sent to the CPU.

Each character is coupled to bus 105 via AND gate 1127, whereby these AND gates are activated by clock signals which are activated by logic circuit 1102 can be provided over lines 1128 and 1130. After the Command by pressing switch 1125 (as well as sending the 7-bit characters the load command sequence) has been supplied, the demultiplexer 1101 receives a Address signal and control signals from the CPU 106 and activates a line F. the device select lines 114. The logic circuit 1102 responds to the signal on the activated device selection line as well as a bus data input control signal supplied by the CPU 106 to deliver a status command to one of the inputs of AND gates 1127. A status command which indicates the availability of data in the read-only memory, is sent to the CPU 106 by the AND gate 1127 through one of the logic circuit 1102 the status clock signal supplied to its second input is activated is, the status command from output 1129 of AND gate 1127 via the line 1105 is coupled to the main bus 105. When receiving the status command, which indicates the availability of data in read-only memory, the CPU 106 sends the corresponding address and control signals to the interface circuit 108 to enable the The next 7-bit character of the load command sequence can be traced back to the CPU. Of the Demultiplexer 1101 activates a line C of the device selection lines 114, where the logic circuit 1102 supplies the clock signal on line 1128, which activates AND gate 1127 when CPU 106 receives the bus data input signal via line 113 to the interface circuit. The effectively switched AND gate 1127 brings this through read-only memory 112 and coding stage 1126 generated character word with 7 bits over the lines 1105 on the main bus 105 for the purpose Transmission to CPU 106. In the manner described above, the coding stage 1126 deliver and read only memory 112 is a sequence of 6 7-bit characters and one thereon The following load command with 7 bits to the CPU 106. For the device in question here the coding stage 1126 and the read-only memory 112 generate a load command sequence with 7-bit characters in the ASCI code language, which is usually used on a teleprinter Is used.

After recording the load command, the load command sequence with 7 characters the CPU 106 provides the device addressing and control signals for activating the corresponding device selection lines, with the control program from the paper tape reader 111 is loaded into the memory 107 via the logic circuit 1102. The demultiplexer 1101 first receives an address from the CPU, creating one line M of the device select lines 114 is activated for the paper tape reader. Then the CPU 106 provides one Command via one of the lines of the main bus 105. When a bus data output control signal occurs on line 1114 over one of lines 1103 a strip reader advance signal is applied sent to strip reader 111. The strip reader 111 delivers over one of the lines 1103 returns a signal to the interface circuit 108 when the requested data to interface circuit 108 are sent. The logic circuit 1102 responds the returned signal and a bus data input Control signal at, where the AND gate 1143 is a command indicating the availability of data indicates to the CPU 106 sends. The command indicating the availability of data will be brought to main bus 105 via line 1105 and sent to CPU 106. To The CPU 106 delivers the command indicating the availability of data the address and control signals to interface circuitry 108, including the paper tape readers available data to memory 107 to send. The demultiplexer 1101 activates one Line L of device selection lines 114, whereby logic circuit 1102 controls the AND gates 1104 can switch effectively while a clock signal is brought to line 1106, when a bus data input is put on line 1113 from the CPU. The AND catters 1104, which are activated, bring the received from the paper tape reader Data via line 1103 to main bus 105 for transmission to memory 107. The CPU 106, the central processor interface circuit 108 and the paper tape reader 111 continue to work in the aforementioned manner until the stored on the paper strip Control program is loaded into memory 107.

Becomes a teleprinter 110 containing serial data by the CPU 106 is addressed, the data is clocked by AND gate 1108 onto bus 105, these AND gates are effective via line 1109 through logic circuit 1102 are switched after the serial data on line 1107 by a universal asynchronous Eipflnger.Übtranser 1110 converted into parallel 8 Llt data have been.

Conversely, if the CPU sends data to the teletype, the parallel ones run 8 bit data on lines 1105 to a universal asynchronous receiver-transmitter 1111, which converts the parallel data into serial data. These dates to run via a line 1112 to the teleprinter. It should be noted here that the blocks 1110 and 1111 identified receiver universal asynchronous transmitters are typically designed as a unit, which perform both functions.

The logic circuit 1102 receives a bus data input command via the line 1113 and a bus data output command is supplied via line 1114. These two commands are provided by the CPU 106 over one of the control lines 144 if either Data can be received over the main bus 105 or sent over the main bus 105 should. Correspondingly, the CPU 106 sends a bus trigger signal on a line 1115 is supplied to a number of flip-flops in the logic circuit during a Start-up sequence or equivalent operating sequences in a known switching state to put.

The logic circuit 1102 continues to make one through an OR gate 1132 bus response signal supplied with multiple inputs on a line 1116 available, which leads to the CPU 106. This can be used to inform the CPU that the addressed device is coupled, i.e. data is available for transmission or that data has been received when the CPU is sending data. Receives the CPU 106 no bus response signal on line 1116 within 10 microseconds, so it no longer waits for a signal, but switches off.

The timing signals for the universal asynchronous receiver-transmitter and the interface circuit 115 for remote input devices are provided by an oscillator 1118, which provides a 3 SC signal on line 1119. This signal is coupled to a divide-by-11 counter 1120, the output of which as Clock signal over a line 1121 both on a counter 1122 and is coupled to the interface circuit 115. The counter 1122 divides continues the already divided 3 So signal at the output of the counter dividing by 11 and provides an output signal on a line 1123 as a clock signal for the universal asynchronous receiver-transmitter with a frequency which corresponds to the mode of operation the teletype is compatible. This is a frequency of about 1758 Hz.

One embodiment of a special circuit for implementing the Functions of the block diagram of Fig. 59 are shown in Figs. 58A to 58D, which show a total of a single connected circuit. The mode of action 58A to 58D, with the exception of parts which have hitherto been used have not yet been described, not further explained. Regarding the circuit to activate the device selection lines, register 1100 is activated by the bus sync signal, which is supplied by the CPU 106 at the address time of the bus multiplex period, activated to the address word with 13 bits and the bus line selection signal to clock the input of a first decoder, which has several exclusive OR gates 1098 and an AND gate 1099 contains. The AND gate 1099 has two inputs, from one of which is the bus line output signal and the other is the ORed output signals the exclusive OR gate 1098 receives which of the seven most significant bits plus the least significant bit of the address word with 13 bits. Are both the bus line output signal and the ORed output signals of the exclusive OR gate in the correct state for a request to a peripheral device, the AND gate delivers 1099 a control signal to the decoder demultiplexer 1101, which then connects the device selection lines 114 as a function of States of the remaining five bits of the address word switches effectively. The 15 device selection lines shown in the block diagram of FIG 114 extend from the right-hand side in the circuit part according to FIG. 58D. The ones in the central processor interface circuit 108 internally used six device selection lines are labeled C, D, E, F, L and M designated.

With regard to the mode of operation of the paper strip reader 111 is to note that the data readout is relatively slow compared to the speed of operation of the computer system 92 takes place. According to FIG. 58B, a circuit part is therefore provided, to notify the CPU 106 when the tape reader has data on the lines 1105 and to reduce the operating speed of the reader to one Input of the data into the CPU 106 to regulate appropriate value. Becomes the paper tape reader 111 is selected by actuating switch 1125, a switch register delivers 1124 via lines 1150 and 1151 two commands to the CPU 106, the CPU then sending a Processes the microprogram, which enables it to work on input data from the paper tape reader 111 to wait. The switch register 1124 continues to clear a shift register 1117 of the coding stage 1126 and then sets a delay stage 1133 the shift register for generating a logic "O" in the first output bit position as well as for generating a logical 1 "in the further seven output bit positions. Thus, the shift register 1117 can generate the load instruction sequence with seven Trigger characters through the read-only memory 112, which leads to the transmission of the control program leads into the memory 107. After the shift register 1117 has been set, the Delay stage 1133 is also provided by the CPU 106 The administration 1150 by setting the flip-flop of the switch register 1124 in front so that it can respond to further actuation of switch 1125.

To switch between identically encoded data from the paper tape reader and to differentiate between teletype and incorrect transmission of data to avoid the CPU 106, the delay stage 1133 switches when the Switch 1125 an AND gate 1159, which is a data available from the teletype indicating status signal generated.

If the shift register 1117 is set in the sense described above, so supplies its eighth Bft8tute a control signal via a line 1153, which the generation of the status signal on line 1130 that is available in the read-only memory Indicates data, effected via a flip-flop and a following AND gate 1154 '. Farther becomes an input of a two-input AND gate 1175 for the eventual Generation of the keystones on line 1128 enabled the AND gate 1127 effective for sending the read-only memory load command sequence to the CPU 106 to switch when the device selection line C is activated and a bus data input signal is received in the sense described above. The one formed by AND and OR gates Gate circuit lot56, which signals the cerZte selection signals and the bulk data input and picks up output signals, sets the various status and data gates in the corresponding switch positions to the desired information transfer between the CPU, the central processor interface circuit and the various interface circuits for peripheral devices.

Every time data characters are activated by activating the data AND gate 1127 are transferred to the CPU 106, delivers the AND gate 1155 on the flip-flop of circuit 1154 for the purpose of switching off the status AND gate 1127 to delete. In addition, this signal clocks a monostable multivibrator 1157, which then sends a pulse to shift register 1117 to determine the bit position the logical | O ". The monostable multivibrator 1157 clocks that too Flip-flop of circuit 1154, when reset, to the logic level the eighth bit position of the shift register 1117 in the following AND gate.

As long as the eighth bit position of the shift register 1117 is a signal supplies in the form of a logical "1", the status AND gate 1127 receives it effective switching signal from circuit 1154 when clocking by the monostable multivibrator 1157 takes place.

When the logic "O" is the eighth bit position of the shift register 1117 reached, the line 1153 couples a signal level equivalent to the logic "O" to the data input of the flip-flop of circuit 1154 and to one of the inputs of AND gate 1155. So if the flip-flop of circuit 1154 by the monostable Multivibrator 1157 is clocked, the status AND gate 1127 is not effective switched, with the AND gate 1155 not having an effective switching clock signal for the data AND gate 1127 supplies. The CPU 106 interprets the first six characters the loading sequence as the address of the paper tape reader and stores it for use for the transfer of the control program into the memory 107, the seventh Character serves as a command to trigger the loading of the control program.

One of the lines from the paper tape reader 111, namely the line 1141 leads a clock signal to a flip-flop 1142, taking for each perforation hole of the read paper strip a clock pulse is generated. If a clock signal for the flip-flop 1142 appears on the line 1141, then supplies the output of which is a signal that indicates the availability of data. This signal is clocked by a NAND gate 1143 onto one of the lines 1105, this NAND gate is enabled by a command on line 1144. Will When data is read, a pulse on line 1145 is passed through AND gate 1146 clocked to delay a monostable multivibrator 1147.

This monostable multivibrator 1147 in turn activates a monostable Multivibrator 1148, the output pulse of which is sent via a line 1149 to the paper tape reader is fed back, whereby the advance of the paper strip is controlled. the Delay of the monostable multivibrator 1147 thus sets the operating speed in effect of the paper strip reader, preferably at a speed of about 300 characters per minute is set to avoid the possibility of destroying the paper strip to keep it as small as possible due to too high a speed.

For example, to carry out an investigation program in the case of the present device a teletype machine is used, whereby the examination program for example by the paper tape reader 111 in accordance with the loading of the control program is loaded into memory 107. When carrying out the examination program data from the telex to the CPU 106 and from the CPU 106 to the telex transfer.

In the part of the central processor interface circuit 108 for transmission of data between the CPU 106 and the teletype becomes data from the teletype either through the teletype keypad or the tape reader to the CPU 106 transferred. The programmed CPU defines when data from Paper tape reader are to be sent. Get data from the teletype keypad is required by the CPU 106, the demultiplexer 1101 is addressed to the line F of the device selection lines 114 to activate. Then the gate circuit operates 1156 the transmission of a status command indicating the availability of data through status AND gate 1127 to the CPU when the required data is received from the teletype are included. The teletype sends a character over the line 1107 8 bits to central processor interface circuit 108. The 8 bits go serial and transmitted by clock signals on line 1123 in the universal asynchronous Receiver-transmitter 1110 clocked. If this universal asynchronous receiver-transmitter 1110 the serial data transmitted by the teletype over line 1107 has received and assembled with 8 bits, it uses the AND gate 1159 the generation of an effective switching gate signal on line H for the Input of the AND gate 1127. The AND gate 1159 is controlled by the shift register 1117 delivered via line J, a measure of the low speed of the The status signal representing the paper strip reader is activated. When occurring either a bus data input control signal or a bus data output control signal on the line 1113 or 1114, the gate circuit 1156 causes the transmission of the the availability of the data indicating status command from AND gate 1127 to the CPU 106. The CPU responds by sending an address signal to the demultiplexer 1101, to cause line C of device select lines 114 to be activated. if CPU 106 then provides a bus data input control signal on line 1113 so the gate circuit 1156 sends a data transfer command over the line 1 to the universal asynchronous receiver-transmitter 1110 as well as to a effective switched AND gate 1159 '. This will indicate the availability of data Error identifier data of the universal asynchronous receiver-transmitter reset, and AND gate 11592 effectively switches NAND gates 1108 to the associated Coupling data on lines 1105 to main bus 105 and transferring it to CPU 106. After receiving the transmitted data, the CPU 106 causes an activation again the line F of the device selection lines 114 through the demultiplexer 1101 to the Prepare to receive further data from the teletype.

When the last data to teletype has been received by the CPU the teletype program is terminated.

If data from the teleprinter strip reader is required, then corresponds to the operation of the central processor interface circuit 108 the operation when transferring data from the teletype ur CPU 106 in the above, yourself senses relating to the teletype keypad operation. However, it will be additional line F of device select lines 114 through one from CPU 106 to the demultiplexer 1101 is activated, the CPU supplies a paper strip advance status signal to the interface circuit 108 via the to "bit line of the main bus 105. Upon occurrence either a bus data input control signal or a bus data output control signal on the line 1113 or the line 1114 the gate circuit 1156 delivers effective switching signal on line K, whereby an AND gate circuit 1139 ' the register 1139 clocks. The clocked register 1139 supplies over the line 1140 a feed command for the teleprinter tape reader to a teleprinter reader relay, whereby the feed of the strip reader takes place. Register 1139 will cleared to allow the counter to generate the next feed command 1138 ready to make. The counter delivers after receiving the eighth clock signal the t gate 1136 a clear signal for the register 1139, the AND gate 1136 effective by the start bit of the serial data sent by the teleprinter is switched. During each interval of the messages sent by the teletype Bits become 16 clock signals for the universal asynchronous receiver-transmitter delivered.

If the CPU 106 sends data to the teleprinter 110, it addresses the demultiplexer 1101 to activate the device selection line D. When the data buffer is empty in the universal asynchronous receiver-transmitter 1111, a will take effect Switching status signal with a high level is supplied on line A, which together with the signal on the activated device selection line D the transmission of a die Availability of status signal indicating data from the teletype through the gate circuit to the CPU 106. This status command is activated when either a bus data input signal occurs or a bus data output signal on line 1113 or 1114 through an AND gate 1152 delivered. When the occurrence of the availability of data from the teletype indicating the status command, the CPU 106 addresses the demultiplexer 1101 to the Activate the device selection line E zd. The gate circuit thus delivers 1156 a command on line C, which is the universal asynchronous receiver-transmitter 1111 causes the parallel data with 8 bits, which its input through the CPU 106 via the main bus 105 and the lines 1105 are offered to load. The load command is sent by the gate circuit upon receipt of a bus data input signal or a bus data Output signal via line 1113 or Delivered in 1114.

After loading the data from the CPU to the universal asynchronous Receiver-transmitter 1111 clocks the clock signal on line 1123 the data serially on line 1112 for transmission to the teletype. After the CPU 106 transmit the data to the universal asynchronous receiver-transmitter 1111 it activates the device selection line D again to wait for the teletypewriter is ready to record further data. When the last data from the CPU 106 are sent to the teletype, this teletype program is ended.

To generate an interrupt command for the CPU 106 and they to restart their work process is a restart control switch 1148 provided with an associated register circuit. By pressing this switch 1148 the interrupt is triggered, after which the CPU 106 after returning the switch starts again in its basic position. A Leuf / Halt control switch 1148 'with associated Circuitry is used to halt the operation of the CPU 106 when, for example, a system failure occurs occurs.

If this control switch 1148 'is reset to its running position, the associated run / stop circuit generates the bus trigger control signal on line 1115 through CPU 106 to the central processor interface circuit 108 to control in the sense described above.

Interface circuit for remote input devices During operation of the in The device in question, it is also necessary that the device's own input device, the auxiliary input device and the seven remote input devices with the central processor communicate. To this end, the interface circuit for remote input devices couples the input devices with the address and data bus, so that communication between the central processing unit and the input devices is possible. The interface circuit 115 for remote input devices, which are already in connection with the computer control system 92 was explained with reference to the block diagram according to FIG. 8, will be explained below with reference to of the block diagram according to FIG. In this block diagram, the address and data bus 105 in both the upper right corner and the lower left corner Corner shown. It should be noted that each input device 76, 78 and 116 have a has associated interface circuit, the block diagram of Fig. 30 an interface circuit representative of the various input devices shows with common, not repeated wiring. A dashed Enclosed block 1160 in the upper left part contains the typical for each device Interface circuit, which is also contained in a dashed block 1161 for that The circuit in the lower part of the circuit diagram applies. A circuit diagram according to FIG. 55A through 55D shows an embodiment of a circuit which can be used to carry out the Operations of the interface circuit 115 according to the block diagram of FIG. 30 is suitable.

The communication between the interface circuit 115 for remote input devices and the input devices are carried out by serial transmission over two pairs of lines of wire sets 1162 and 1270, while the address and data bus 105 Includes 16 lines. For communication between the input devices and the bus It is therefore necessary to convert serial data into parallel data. When a certain input device sends data to the CPU 106, this data is available from the input device on the device lines 1162 in the upper left part of the circuit diagram and are given to a line receiver 1163, the output of which is via a line 1164 on the receiver part of a universal asynchronous receiver-transmitter 1165 is performed. This receiver transmitter 1165 is triggered by a clock signal the line 1121 clocked by the central processor interface circuit 108, to convert the serial information into parallel information on lines 1166, to which all the universal asynchronous receiver-transmitters for the interface circuits the input devices are coupled. Lines 166 comprise a data line, a line for false indicators and a data standby line. There are three error flag signals, namely a parity error signal, an image error signal and an overdrive signal, the latter signal being indicates that a second character has been sopiangcn before the first character is out has been read from the buffer of the universal asynchronous recipient transfer. if Data are to be transferred from the CPU 106 to a specific input device, so the parallel data received via the bus 105 are transferred to the transmitter section of the universal asynchronous receiver-transmitter provided for the special station 1165 Input via an input gate circuit 1203 and lines 1204. The above clock signal provided on line 1121 from the central processor interface circuit 108 clocks the universal asynchronous receiver-transmitter 1165 to the parallel Data to serial data on lines 1270 leading to the selected Input device to lead. A 1 in 16 decoder 1186 sets the special universal asynchronous receiver-transmitter by activating a device selection line 1187 leading to it.

The device in question here also has an input allocation control keypad 140 of FIG. 61, through which playback channels and disk drive units in certain permissible combinations for exclusive use by a remote input device or assign a device-specific input device. A pair of leads 1162a of the Set of input lines 1162 and a pair of lines 1270a of the set of Output lines 1270 connect the keypad 140 to the interface circuit 115 for remote input devices. These wire pairs transfer data between the CPU 106 and the keypad 140 via the interface circuit 115 to set the desired Assign the channel and the desired disk drive unit to the input devices.

If data is sent from an input device to the CPU 106, a Binary identification number with 4 bits sent by the device and on lines 1181 brought at the entrance of a 4 x 2 switch 1182. This switch 1182 is in set in a manner still to be described below, us the via the lines 1181 to bring the received identification number on output lines 1187a, which to the Input of the decoder 1186 lead. The 1186 decoder activates one of nine possible Decoder device selection output lines which identify the device sending the data. By activating the device selection output line, the universal asynchronous Receiver-transmitter activated in order to transfer the received data to the address and data bus 105 bring.

If data is sent from the CPU 106 to one of the input devices, a binary identification number with 4 bits is assigned to the station by the CPU Interface circuit 115 transmitted. This is called the RAS TX ID signal The signal is sent to the input of the 4 x 2 switch 1182 via lines 1184. The switch is set to the identification number received on lines 1184 to the output lines 1187a leading to the decoder 1186.

The decoder responds in the sense described above to the device selection output line to activate which is sent to the universal asynchronous receiver-transmitter 1165 associated line 1187 is coupled for the selected input device. Activation the device selection line 1187 enables the loading of the ones received by the CPU 106 Data in the transmitting putter of the universal asynchronous receiver-transmitter.

The transfer of data between the CPU 106 and one of the input devices is effected by control signals and input device address signals sent by the CPU 106 are delivered.

As described with reference to Fig. 29, the device effect address signals the activation of the device select lines 114 by the demultiplexer 1101 of FIG Central processor interface circuit 108, with device selection signals applied to the Lines 114 are given. The through the CPU 106 on the control line bus 144 Given device selection signals as well as the control signals are sent to the interface circuit 115 coupled to the transfer of data between the CPU and the selected To effect input device through the logic of the interface circuit.

For the transfer of data from an input device to the CPU 106 must the operation of the CPU is initially interrupted and an interrupt routine of the Control program can be skipped. This interruption is caused by an input device received data triggered, with a bus interrupt request on a line 1222, which is coupled to the interrupt bus 143 leading to the CPU 106 is. The corresponding input device sends its data over its set of input lines 1162 to the associated line receiver 1163. This line receiver 1163 gives the data via a line 1167 for clocking to an associated input register 1168, in order to generate a first effective switching signal on a line 1169, which leads to an input of a subsequent NAND gate 1170. In the case, that the CPU 106 is not servicing any further device interruption requests the interruption-enabling flip-flop 1171 in a switching state in which a second effective switching signal via a line 1172 to the other input each NAND gate 1170 for the various input devices that are coupled to the CPU are given. Since only the NAND gate assigned to the sending input device 1170 receives the first effective switching signal, this gate is activated, an output signal on one leading to an input of an OR gate 1220 Loitung 1177 to deliver. This OR gate supplies a signal for clocking a Flip-flops 1221, causing this to be a bus interrupt request over a line 1222 supplies to CPU 106.

In addition to generating the bus interrupt request, the output of register 1168 clocked by NAND gate 1170 via a Line 1177 on one Priority encoder 1167 given which one supplies a binary identification number with 4 bits for the station from which the Outgoing interrupt request. This identification number is used by the decoder 1186 decoded to activate the device selection line 1187, which is the control input of the corresponding universal asynchronous receiver-transmitter 1165 leads. the The identification number is sent to an input of a register 1179 via lines 1180 given. This register 1179 is activated by a pulse for receiving the identification number clocked, this pulse as a function of one received over line 1233 Low level signal through a monostable multi brator 1234 over a line 1235 is supplied when the flip-flop 1221 is clocked by the OR gate 1220 will.

The identification number then appears on the 4 x 2 switch 1182 leading line 1181 and will continue to use this line on output gate 1183 given, which clock the information on the address and data bus 105, when a line 1194 is high. A second output signal of the monostable multivibrator 1234 on a line 1236 clocks the flip-flop 1171, whereby on the line 1172 leading to the NAND gates 1170 a signal with a low level. With this the gates are blocked, whereby the transmission further interrupt requests to CPU 106 are prevented until the flip-flop 1171 when receiving a RASRST device selection signal from the central processor interface circuit 108 is reset via the interface circuit 115 for remote input devices, which is explained in more detail below.

The CPU 106 acknowledges the bus interrupt request by issuing it a bus interruption acknowledgment command (BIAKI) on one line 1224, which via an OR gate 1226 to the clock input of a flip-flop 1223 is clocked.

This is done by the flip-flop 1221 as a function of the previously received Interrupt request put a high signal on line 1222 and clocked onto an output line 1228, with an output line 1229 a low level signal appears. The high level signal on the line 1228, along with the inverted BIAKI signal on line 1224, enables interrupt vector gates 1239 to put a vector address on bus 105 which is the transition on causes the interrupt routine of the control program in the CPU 106. Simultaneously the flip-flop 1223 causes a bus feedback signal to be fed into a line 1245, which is based on an OR gate 1246 with multiple inputs (see Figs. 55B and 55D) leads. This OR gate supplies the bus feedback signal via a line 1247 to the CPU 106.

Furthermore, the CPU then receives a bus feedback signal each time the OR gate 1246 when a device select line through the central processor interface circuit 108 is activated and the corresponding control signal supplied by the CPU 106 is received by the interface circuit 115. As in the following in more detail are to the device selection lines and to the control signal lines of the CPU gate circuits 1178, 1193, 1202 and 1218, which inter alia the generation trigger the bus feedback signals through OR gate 1246. That through the interface circuit 115 bus feedback signal is used on the basis of the central processor interface circuit 108 is the purpose already described, i.e. it reports to the CPU 106 that communication took place with the addressed device.

Since the signal is low on the outgoing from flip-flop 1223 Line 1229 appears at one of two inputs of a NAND gate 1188 the BIAKI signal received at the other input of this NAND gate 1188 is blocked and therefore not transferred to a BIAKO line 1195. The BIAKO line 1195 runs to the BIAKI inputs of all interface circuits in the device for systems which Cause interruptions. This line is used to transmit the through the CPU 106 sent out BIAKI signal only to the interface circuit, which is assigned to a device triggering the interrupt request.

The signal with deep. Level on line 1229 is still through an OR gate 1230 coupled to a line 1231, which leads to the flip-flop 1221 leads to reset it to accommodate subsequent interrupt requests.

The CPU 106 continues to respond to the bus interrupt request to return RASRCV device selection signals and bus data input control signals (BDIN signals) to the interface circuit 115 for remote input devices. These signals are input to an AND gate 1193 via lines 1195 and 1200. This AND gate 1193 supplies an output signal when the signals mentioned are fed in to delete a flip-flop 1211. An output of the flip-flop 1211 is via a Line 1212 is routed to the control input of the 4 x 2 switch 1218. If the flip-flop 1211 is cleared, its output coupled to line 1212 becomes a Switching state in which the switch 1218 connects the lines 1181 to the input lines 1187a of the 1 out of 16 decoder 1186.

Therefore, the identification number generated by the priority encoder 1176 becomes of the requesting input device coupled to the decoder 1186 to the device selection line 1187, which is assigned to the control input of the requesting device universal asynchronous receiver-transmitter 1165 is coupled. This becomes the Receiver part of this universal asynchronous receiver-transmitter effectively switched, to couple the assembled data to lines 1166.

AND gate 1193 is still on lines 1194 to a NAND gate 1192 and coupled to output gate 1183. Has the universal asynchronous Receiver-Transmitter 1165 a complete 8-bit character from the sending one If the input device is received and assembled, a data ready signal is transmitted one of the lines 1166 is sent to the output gates 1183. The output gates respond to the receipt of the data ready signal, the signal with high through AND gate 1193 by coupling the data in the universal asynchronous Receiver-transmitter is put on bus 105 on line 1194.

The NAND gate 1192 coupled to the device selection line 1187 switches the OR gate 1190. The output of this OR gate is set to the Line 1191 carried to the reset input of register 1168 is given.

This register 1168 is reset by the OR gate 1190, in order to switch off the first effective switching signal from its output, which is via line 1169 is coupled to associated AND gate 1170. The first BDIN control signal, after receipt of the bus interruption request by the bPU 106 to the remote input device is also used to switch off the activation signal on line 1228 leading to interrupt vector gates 1239. For this purpose is the BDIN line 1200 of the CPU control line bus 144 to the OR gates 1226 coupled, which sends the clock signal on line 1228 to the flip-flop 1223, at which point a low level signal is on the line 1222 and at the input of the flip-flop 1223 is present.

After the universal asynchronous receiver-transmitter 1165 When data sent has been received by the CPU 106, RASRST selection signals become and bus data output control signals (BDOUT signals) at inputs of an AND gate 1178 fed back to the interface circuit 115.

The BDOUT control signal and the RASRST device selection signal are coupled via a line 1198 or 1199 to the inputs of the AND gate 1178. This AND gate 1178 is therefore turned on and provides an effective switching Signal on line 1175 to an input of a NAND gate tut96 and a Input of an OR gate 1174. That coupled to the activated RAS selection line 1187 NAND gate 1196 is switched through to over a line? 1197 a data ready reset signal (DRR signal) to the universal asynchronous receiver-transmitter 1165 to couple. OR gate t174 generates as a function of that provided by gate 1178 effectively holding a signal with a low level at its output that is on the interrupt control flip-flop 1171 is performed. This signal at a low level resets the flip-flop 1171, whereby the second effective switching signal is transmitted line 1172 is coupled to NAND gate 1170 so that these NAND gates can respond to a further interrupt request from an input device.

To transfer data from the CPU 106 to one of the input devices, causes the CPU to send out a RASTX device selection signal and the BDOUT control signal to the interface circuit 115 for remote input devices.

These signals are fed to an AND gate via lines 1201 and 1198 1202 given, whereby this AND gate is switched through. This will become the input gates 1203 activated to transfer data from the bus 105 to the interface circuit 115 transferred to. In addition to transferring the data to the selected input device The CPU 106 sends the station address or identification number (RAS TX ID) the bus 105, thereby identifying the input device, the transmitted data should receive. In addition, the CPU 106 sends switching control and transmission trigger signals. The latter signals switch the logic of the interface circuit for the Remote input device effective to transfer the data to the selected input device perform. The line of bus 105 passed through input gates 1203 is coupled to the flip-flop 1211, receives the switching signal through which the flip-flop 1211 is set. If this flip-flop 1211 is set, will be Output that is coupled to the control input of the 4 x 2 switch via line 1212 is switched to a switching state in which the switch 1218 the input lines 1187a of the decoder 1186 is coupled to the output lines 1184 of the input gate 1203. This switches the RAS TX ID data identifying the input device with 4 bits, to receive data from the CPU 106 and to couple it to the decoder 1186. The decoder switches as a function of the RAS TX ID device identification number that of the selected Device selection line 1187 assigned to the input device is effective. One of the entrances to the AND gates 1207 and 1213 thus receive an effective switching signal.

The AND gate 1207 initiates the transfer of the data from the CPU 106 to the selected input device via the universal asynchronous receiver-transmitter the end. However, the transfer does not take place until the universal asynchronous Receiver transmitter 1165 can process the data from CPU 106. The AND gate 1213 triggers the transmission of a status signal to the CPU 106, which indicates that the universal asynchronous receiver-transmitter receive, process data and can transfer.

For this purpose, the CPU 106 causes a RASTST device selection signal to be sent out and the BDIN control signal to interface circuit 115 for the remote input device. These signals are sent to an AND gate via a line 1188 or line 1200 1218 given and switch this AND gate through. This becomes an AND gate 1217 activated to the ready status signal of the universal asynchronous Receiver transmitter to the CPU 106 to send. If the data buffer is in the the selected Universal asynchronous receiver-transmitter 1165 assigned to the input device is empty and can receive data from the CP 106 is via an output line 1214 of the universal asynchronous receiver transmitter sends a signal to a second Input of the UND gate 1213 given to the activated device selection line 1187 is coupled. The AND gate 1213 outputs an effective switching signal an OR gate 1215 with several inputs, the corresponding signals from further, AND caterpillars 1213 assigned to other input devices. The effective switching Signal is coupled to AND gate 1217 via OR gate 1215, which the ready status signal of the universal asynchronous receiver-transmitter for the CPU 106 supplies.

The CPU 106 responds to the ready status signal and effects the feedback of the RASTX device selection signal and the BDOUT control signal to the Interface circuit for the remote input device, the data together with the transmission trigger signal are transmitted to the selected input device. The device selection signal and the BDOUT control signal switch the input gates 1203 effective in the sense described above. The transmission trigger signal is triggered by the Input gate 1203 coupled to a monostable multivibrator 1210 which A signal for all AND gates 1207 of the interface circuit via a line 1209 115 for remote input devices. The to the activated device selection line 1187 coupled AND gate 1207 is activated to generate a signal for the associated universal asynchronous receiver-transmitter 1165 to deliver, thereby reducing its buffer is loaded with parallel data supplied by the CPU 106 over the bus 105 and through input gates 1203 on input lines 1204 of the universal asynchronous Receiver-transmitter are given.

Clock signals sent to the loaded universal asynchronous receiver-transmitter are fed via a line 1121, cause the transmitter of the universal asynchronous receiver-transmitter transmits the data serially over lines 1270 to the selected Input device outputs.

Bsi the allocation of playback channels, as shown in FIG and disk drive units 73 for exclusive use by a remote input device 76 or

an on-board input device 78 communicates the input allocation control keypad 140 via its circuit shown in FIGS. 62A to 62C with the computer control system 92 via the interface circuit 115 in the manner in which it is based on the input devices 76, 78 and 116 described above. An operator gives over the Keypad 61 the desired input device, the desired Playback channel and the desired disk drive unit. A desired Allocation takes place by pressing a DRIVE, an IAS and a RAS button, the allocation being triggered by an enter key. Pressing the Enter key causes data to be sent to interface circuit 115 over a pair of Input lines 1162a, causing a bus interrupt request to be sent to CPU 106 and subsequent processing of the request is carried out. One requested Allocation is made by entering the identification of the allocated playback channels, Disk drive units and the input device in the memory 107 of the computer control system 92 guaranteed, the control program being used to prevent the allocated Playback channels and disk drive units through an input device assigned by the assigned one different input devices can be acted upon.

In the interface circuit 115 there is also a bus release line 1173 is provided, which connects it to the control signal bus 144 leading to the CPU 106. As already described with reference to the central processor interface circuit 108 CPU 106 provides a bus release control signal on line 1173 to convert the logic of the remote input device for start-up sequences or equivalent operating sequences to put in a previously known state.

The operation of the computer control system 92 in transmission of data between the CPU 106 and one of the input devices occurs as a function of the control program loaded into memory 107, which is shown in the flowcharts according to 63 is indicated.

Input device circuit The overall effects of the device in connection with input devices was explained above on the basis of the sequence of inputs, which must be done in the keypad in order to perform the desired operations. Furthermore, the interface circuit 115 for remote input devices (Fig. 8), which the communication of the address and data bus 105 and thus the CPU 106 guaranteed with the input devices. The following is now based on 31 shows the circuit associated with the input devices self described.

Should be on via the interface circuit 115 for remote input devices Command are sent to the CPU 106, an operator presses the appropriate Buttons and puncture keys on the keypad, for example the keypad 83 for the device's own input device, which is shown in FIG. 31 as block 1260 is. This keypad contains buttons and keys 84, 85, 86 and 104 according to FIG the perspective view of FIG. 3. A circuit for performing the Operations of the block diagram of Fig. 31 are shown in Figs. 56A to 56D. The buttons or function keys in the keypad 83 are connected to a transmission gate 1266 (Figures 56A and 56B), with some of these buttons and buttons still are also coupled to sliding and control lines 1269 and 1269a. Each transmission gate 1266 connects two lines corresponding to predetermined x and y coordinates, which along with status on X lines 1269 and 1269a through an encoder 1261 can be coded. Lines 1262, 1269 and 1269a encompass the entirety the lines that connect to the various buttons and the encoder 1261 manufacture. The keypad encoder 1261 contains a network which selects one of 99 possible combinations and a word with 7 bits on lines 1263 generated which to the transmitter of a universal asynchronous receiver-transmitter 1264 are coupled. This universal asynchronous receiver-transmitter transferred the parallel information into serial information on an output line 1265, which when keyed by a pulse from a monostable multivibrator 1267 via lines 1162 to the interface circuit for remote input devices is given. The monostable multivibrator 1267 is via a line 1268 coupled to the universal asynchronous receiver-transmitter 1264, which via a line 1325a clocked by a clock supplied by a clock counter 1325 will.

Are data from the interface circuit 115 for remote input devices are received on lines 1270, they pass through a line receiver 1271 in a universal asynchronous receiver-transmitter 1272 working as a receiver, which converts the serial data into parallel data under the control of the clock provided for it and this parallel data on 6 data lines 1273 and two branch lines 1274 and 1275 there. The universal asynchronous 11-catcher transformers 1272 and 1264 are combined in a single integrated circuit and occupy a single one Control and clock circuit for controlling the receiver and transmitter parts. The data- and branch lines carry the data to different places in the circuit, for example on a self-scanning display device 82 (also in FIGS 2) or lamps assigned to the keypad to illuminate certain Keys in the sense described above. The one occurring on branch lines 1274 and 1275 Information is inverted by respective inverters 1276 and 1277, whereby inverted signals on lines 1278 and 1279 arise. These lines are connected to inverters 1281 and 1282, the output signals of which are on lines 1283 and 1284 are given. A monostable multivibrator 1286 is made by a die Availability of a data indicating pulse on a 1287 line from the universal asynchronous receiver transmitter 1272 triggered and provides one the availability of data indicating reset pulse on line 1288. The high output signal this monostable multivibrator is connected to an AND gate via a line 1289 1291 and to another IIND catter 1292, with a key pulse for keying the information either on the display device 82 or on the keys assigned Lamps is generated.

With regard to the keying of the information on the lamps, the AND gate 1292 carries the information on lines 1283 and 1284 so that on one Output line 1294 of AND gate 1292 the key pulse when these input signals are present is available. The output of AND gate 1292 on line 1294 switches a register 1295 is effective, which the status of four lower order bits on the Takes over data lines 1273 and delivers a 4-bit address on lines 1297, which is given to a 1 out of 16 decoder 1293, whereby corresponding lamps 1299 can be switched on.

The data lines 1273 are still on a read-write memory 1301, the 5 bits of the lower order being fed to a counter 1302 become, which the Read / write memory 1301 via five address lines 1303 addressed. The memory 1301 has six leading to the display device 82 Output lines 1304. In the case of the display device with a display matrix in the form of 32 drawing points is one manufactured by the Borrows Corporation Type which indicates each character addressed by the memory. The counter 1302 becomes clocked through 32 addresses, the display device 82 being the alphanumeric character as a function of the data on lines 1304.

The counter counts the addresses as a function of a clock pulse a line 1305, this clock pulse being generated by an AND gate 1306, that by a pulse generated by the display device 82 on a line 1307 and a normally high signal on line t308 will. The counter is therefore successive due to the pulses supplied by the display device clocked by its addresses.

Should new data be written into the read / write memory 1301 the correct memory address must first be selected, after which the the following sequence occurs. Through the information at the input of a NAND gate 1309 as well as by a clock on a line 1310, which by the monostable Multivibrator 1286 is supplied via AND gate 1291, this becomes NAND gate 1309 activated to deliver a set pulse on a line 1311, which is performed both on the counter 1302 and on a flip-flop 1312. An exit line 1308 of this flip-flop 1312 blocks the AND gate 1306 and thus stops the clocking of counter 1302. At this point in time, the desired address to be rewritten is received given into the counter via lines 1273, so that the correct information is available when next key pulse a NAND gate 1313 activates the gives a write pulse on a line 1314. This write pulse causes the Writing of data present on the data lines 1273 into the memory 1301. Then the flip-flop 1312 changes its switching state, so that the AND gate 1306 is activated via the line 1308, the counter 1302 via the Line 1307 is clocked again. When the counter 1302 reaches its final count of 32 reached, its output line 1315 is through an OR gate 1316 and a Line 1318 coupled to a flip-flop 1317. An output line 1319 this Flip-flops 1317 is coupled to a further flip-flop 1320, which via a line 1321 couples a clear signal to the counter, so that this counter is cleared and through the addresses sent to the read / write memory 1301 can be clocked again. An outgoing line 1322 from the flip-flop 1320 leads both to the display device 82 as well as an AND gate 1323, whereby a reset signal for the display device is delivered by yourself. The AND gate 1323 blocks the display clock for about two Clock pulses so that a reset is possible. An oscillator 1324 as well as a Counters 1325 generate a clock signal at 15 kHz on a line 1326 for clocking the flip-flops 1317 and 1320 and for the display device 82 via the AND gate 1323. A power-on reset signal on line 1327 sets a flip-flop 1328 in front of it, its high and low output on lines 1329 and 1330 occurs, whereby the signal on line 1329 blocks the decoder 1298 and the Signal on line 1330, the display device 82 scans through a NAND gate 1331. The output of flip-flop 1312 on line 1308 also causes one Blanking of the display device if an address is sent when the counter 1302 is stopped will.

The circuit shown in the block diagram of FIG. 31 is in all input devices and remote input devices, whereby the on-board input device 78 (Fig. 8) a full complement of numeric Has keys and function keys for operating the entire device. The remote input devices 76 (Fig. 8) have fewer function keys, so that they have certain already described Cannot perform operations. Another control device, namely the auxiliary input device 116 (Fig. 8) is for use in conjunction with a remote input device for certain independent operations which are performed in the sequence playback mode from the working tracks 1 to 64 of a disk drive unit can be used. A keypad of a Auxiliary input device only has a release button and a selection button, which via lines 1262a to keypad transmission gates 1266 (Fig. 56A) are coupled, whereby a remote input device a disk drive unit and a neighboring auxiliary input device can use a second disk drive unit, separate playback channels are also used. By an alternating sequence control between the remote input device 78 and the auxiliary input device 116 can stand Alternately transmit images over a channel from two disk drive units , whereby fades of the resulting image are eliminated, so that a very quick, practically instantaneous transition from a still image can be generated to another. An auxiliary input device 116 includes a large one Part of the circuit shown in the block diagram of FIG. 31, also including a Display device with associated memory and associated circuitry is provided. However, there is no complete keypad in the sense described above. Both the remote input device and the auxiliary input device contain a flip Flop 1332, which receives information from the universal via lines 1274, 1275 and 1278 asynchronous receiver-transmitter 1272 receives. Furthermore, this flip-flop takes one Key pulse on line 1289 and a control signal on line 1334. The flip-flop provides an output signal on a line 1333 which is connected to the AND gate 1291 and the auxiliary input device. If the flip-flop 1332 has a signal controlled with a low level on line 1334, the AND gate 1291 is blocked, which then also AND gates 1309 and 1313 are blocked, so that data in the display device 82 of the remote input device to which the auxiliary input device is coupled has not changed can be. The low signal on line 1333 switches the auxiliary input device effective, so that its display device, its memory and its associated circuit take effect to transfer data on lines 1273 for use in the display device in to write its memory.

The circuit diagram of FIGS. 56A to 56D shows an embodiment a circuit for performing the functions of the block diagram according to FIG. 31, specifically according to FIG. 56A, a release button 1336 via a line 1335 is coupled to an inverter 1337, the output of which is connected to an AND gate 1338 as well as an AND gate 1339 is coupled.

A control key 1340 is via a line 1341 and an inverter 1342 coupled to AND gate 1338. A third line 1349 from a key switch 86 (see Fig.

3) is via an inverter 1343 both to an AND gate 1344 and also coupled to a further AND gate 1345.

The outputs of AND gates 1339, 1344 and 1345 are connected to transmission gates 1346, 1347 and 1348 coupled, each delivering a signal that, like Signals from other keys on the keypad are given to encoder 1261 will. The logic described allows certain operations to be carried out the input devices while other operations are prevented. Will the trigger button 1336, the UNOCatter 1339 is switched through, so that the associated Transmission gate 1346 takes effect.

Activate the trigger and control button 1336 and 1340 at the same time is pressed, the UNOCatter 1339 is blocked, while the AND gate 1345 is effective which then activates transmission gate 1348. This will make the Editing of a previously compiled sequence is possible.

By turning the key switch 86 to which only certain Operators have access by pressing the release button and the control button 1336 and 1340, the gate 1345 is blocked and the gate 1344 is activated, whereby the transmission gate 1347 is activated.

This means that every address becomes the deletion of a single standing address Image in information tracks or the deletion of a complete sequence in working tracks possible until an EOL indication occurs or until track No. 65 is reached. the Logic therefore prevents deletion operations from being carried out when the key switch is not used.

Input Allocation Control Keypad The input allocation control keypad 140 according to FIG.

61 can be used in the device in question here to create a or a plurality of selected disk drive units and one or more playback channels to be assigned exclusively to an input device if the device is used for broadcasting purposes or for other purposes Purposes with higher priority is used. For example, if the device is used at a News broadcast used in a commercial television station and assigns the operator operating the device a sequence of still images during the news broadcast, it would be annoying if through another remote input device an intervention in the broadcast by interrupting the representation of a standing one Image would occur if an image that does not fit into the context is displayed would or if the transmission was disturbed by another type of interruption process would. Since the device has up to seven remote input devices in different places one TV station can have, despite the common safety precautions improper use by unskilled personnel occurs in transmitter stations.

To prevent such improper or unauthorized use of the device to prevent personnel from using a remote input device when operating with If the priority is higher, the input allocation control keypad can be used be provided in the device to certain disk drive units and certain Playback channels exclusive to a remote input device or a device's own input device 76 or

78 to prevent interruptions. By assigning certain Combinations, for example the disk drive unit No. 1, remote input device no. 2 and playback channel B can be other input devices Do not use channel B or disk drive unit # 1 any more. However, it is possible that other input devices other playback channels and other available Take advantage of disk drive units for yourself. Although only an input device can control a channel or a disk drive unit at a time however, three or more disk drive units (if such a number in one special device is available) and one or more channels to a special input device be assigned. Furthermore, a disk drive unit can also be used at one point in time cannot be assigned to a specific finger device via more than one channel. However, one channel can have more than one disk drive unit at a time be assigned. Are all disk drive units or all channels assigned, so input devices that do not receive an assignment cannot work, as either the pulley drive units, the channels, or both the pulley drive units and the channels are not available for operations.

The input allocation control keypad shown in Figure 6e 140 is also connectable to the interface circuit 115 for remote input devices like the input devices. The keypad communicates with the CPU 106 of the computer control system 92 as well as an input device via the interface circuit 115 for remote input devices. The input allocation control keypad 140 has three horizontal lines as shown in FIG of pushbuttons, with the top line showing the assignment combinations for the playback channel A, the middle line the assignment combinations for playback channel B and the lower line shows the assignment combinations for channel C represents. Below the horizontal lines of push buttons is an enter key and above the horizontal lines a lamp indicating illegal operations intended. The push buttons in the rows are preferably mechanically locking Push-button switch (press to close the switch and press again to Opening the switch), which after pressing is mechanically opposite the open Switch position remain at a lower level. The switches are internal Lamps are provided so that they can be illuminated. As described below the switches can either be at full brightness or dimmed Intensity can be illuminated to choose between an existing assignment or a next assignment to distinguish.

In this regard, it should be noted that if one or more Drive units and one or more channels to a specific input device a lighting with full brightness of those push buttons is available, which represent the existing assignment. Should a next "assignment be carried out is a dimmed illumination of the push buttons for the next assignment useful in the mechanically pressed position. Are drive units and channels for the next assignment also available in the existing assignment, their mechanically pressed push buttons preferably brightly lit.

There are different illuminance levels for the keypad in question Exploited along with the mechanical levels of the push buttons, so is for one Operator a clear overview of both the existing assignments and Puch about the assignments to be carried out when changing the assignment.

The Enter key is used to enter an assignment as well to the Change the status of assignments from one existing assignment to the next Assignment. When the Enter key is pressed it will be a specific input device assigned drive units and channels with regard to a "next" assignment entered. In times when assignments are changed, the Illumination of the push buttons from dimmed brightness to full brightness, whereby the previously fully illuminated pushbuttons will be deleted, provided that they are not part of the new assignment entered. Once the assignment has been entered, so the associated pushbutton lamps remain on even when the pushbutton switch is pressed again as the existing assignment remains in the effect until the Enter key is pressed again. This is due to the fact that the lamps in the push buttons can be controlled by an independent circuit when the Assignment is entered once. A functional dependence on the position of the push button is not available. Should the assignment of a channel to a Input device, so it is necessary to use the special switch in to open the corresponding channel line, followed by the Enter key is to be pressed for the new assignment of the input device.

The input allocation control keypad 140 is as previously mentioned designed so that the three horizontal lines according to Fig. 61 the playback channels A, B and C represent. The top horizontal row of push buttons for the canal A contains three push buttons for the No.

1, 2 and 3, a push button for the device's own input device and seven push buttons for remote input devices No. 1 to 7. To assign an an input device too create, an operator pushes the corresponding push button for the lingab device together with the push buttons for the disk drive units, which this input device in the corresponding channel (Horizontal line) are to be assigned. Then the enter key is pressed, to carry out the selected assignment. For example, if an operator wants the device for a news broadcast and requires still images of the on the disc drive units 1 and 2 provided disc stacks, with them is located on the remote input device no. 2, to ensure the exclusive Utilizing the disk drive units 1 and 2, an assignment is made as follows will. There are the push buttons for the disk drive units 1 and 2 together with the push button for the remote input device 2 in the top line for the channel A is pressed and the Enter key is pressed. The aforementioned three snaps are then illuminated with full brightness when the assignment is carried out. at This assignment can be used by other operators at other input devices Do not use disk drive units 1 and 2 and channel A, so that only from input device no. 2 images of these disk drive units below Can be selected using channel A. The remote input device 2 can, however use other channels d other disk drive units when not through other input devices are used. Operators at other remote input devices or on the device's own input device, the disk drive unit no. 3 as well as use channels B and C to perform other operations.

The control program in the computer contains certain rules regarding the operation of the input control keypad. It acts it is u.n. around the rule that only one remote input device is a given Channel can be assigned. This ensures that the control of a Channel by one operator on one input device not by another Operator at another input device can be disturbed because the assignment excludes such multiple use. However, it is possible that one Input device can be assigned to more than one playback channel.

This enables predictive operations for the operation of the device possible, as is the case with transmitters as well as others, the simultaneous Operations requiring the use of still images is common. One other Feegel makes it possible to have one or more disk drive units Assign the input device via a special channel, since still images are on different Disc stacks may be present. It can also be used for a specific program a sequence may be required which is the preferred maximum of 64 for a stack of discs exceeds, so that more than one disk stack and thus more than one disk drive unit is required for this case. Another rule prevents the assignment of a certain disc drive unit via two or more channels for the reason that the input device controlling a certain channel to conflicting requirements Can give cause. So while two or three disk drive units one can be assigned to a special input device via a special channel However, each disk drive unit only has one channel at a time assigned to an input device will. Will at a time a disk drive unit associated with more than one channel in which an operator for example push button 1 for channel A and push button 1 for channel B is pressed, the lamp indicating illegal operations lights up immediately. as well This light comes on when more than one input device is on a given channel is assigned.

Multiple assignments can be made, provided that that disk drive units and channels are available for such assignments. In the above example for the assignment of the disk drive units 1 and 2 and the remote input device no. 2 via channel A can have a further assignment either channel B or channel C to # 3 disk drive unit will. The same applies to all other input devices, including for example the device's own input device. In this case, two separate assignments are simultaneous available. It should be noted that there are no disk drive units in either assignment for use by other operators on other remote input devices be available.

In the circuit for input allocation control keypad 140 62A, 62B and 62C, there are switches for each playback channel A, B and C intended for both the disk drive units and the input devices.

62A and 62D, channel A has three push-button switches 2210 for the assignment of disk drive units, three push-button switches for channel B. 2211 for disk drive unitsi below for channel C three push-button switches 2211 intended for common indulgence. The same applies to the Kanul A eight l) push button switch 2213 intended for input devices. Corresponding switches 2214 and 2215 are provided for channels B and C. the Switches 2213, 2214 and 2215 are on lines 2219, 2220 and 2221 to priority encoders 221 &, 2217 and 2218 are coupled, these priority encoders each being a provide a binary output signal with four bits, which the switched remote input device or the switched device's own input device is identified. The outputs of the encoder as well as the lines from the switches for the disk drive units are open an input of multiple NAND gates 2222, 2223 and 2224 for channels A, B and C, the output of the NAND gate via lines 2226 to a transmitter part a universal asynchronous receiver-transmitter 2230 is performed, which the Conversion of parallel information on lines 2226 into serial information, which is output on an output line 2231. This output line is 2231 to a driver 2232 with a blocking line 2233, so that the transmission the information on output lines 1162a to interface circuit 115 for Remote input devices can be blocked if an impermissible condition occurs, which contradicts the allocation rules explained above.

As will be explained below, the timing of the transmission is input from gates 2222, 2223 or 2224 via the other inputs of the NAND gates, the sequence of channels A, B and C being carried out so that the universal asynchronous receiver-transmitter transmits the data sequentially, which on the Mappings for each of the channels are related. A high level signal on one Line 2235 enables NAND gates 2222 while signals are on lines 2236 and 2237 activate the NAND gates 2223 and 2224, with the corresponding cables can be activated by the circuit of Fig. 62C, which will be explained below will. In the case of sequential transmission of the data from the channels, the lines are 2236 and 2237 coupled to inputs of NAND gates 2223a and 2224a to receive a signal to the universal asynchronous receiver-transmitter to deliver the transmission via channel B or C, but does not identify transmission via channel A. Line 2235 for channel A does not contain such a NAND gate, the universal asynchronous receiver-transmitter information about the beginning of the Contains sequence, thereby synchronizing the operations of the input allocation control keypad with the operations of the computer control system 92 is possible.

Inadmissible operations are displayed via lamp 2240, which via an inverter 2242 and a line 2233 through a lamp driver 2241 is controlled. Inverter 2242 and line 2233 are on the output of a NOR gate 2243 coupled to several input lines via which the lamp indicating illegal operations can be switched on. When switched on Lamp 2240 provides an inhibit signal on line 2233 which is directed to the driver 2232 and lamp driver 2241 is coupled.

The input lines of NOR gate 2243 are to those of a circuit associated lines coupled, which is an impermissible condition due to the Pressing a special push-button switch for the disk drive units, for example, is caused for more than one channel. Those mentioned, with 2245, 2246 and 2247 designated input lines come from majority gates 2248, 2249 and 2250, which indicate whether a specific disk drive unit for more than one channel has been selected. For example the majority gate 2248 has three inputs, which come from the push button switches for the disk drive unit # 3 coming in all channels. Will use more than one of these push button switches for disk drive unit # 3 is closed, majority gate provides 2248 a low level output on line 2247 so that the illegal Operation lamp lights up and line driver 2232 is disabled. Similarly, the majority gate 2249 is coupled to switches that control the channels for disk drive unit # 2, while the majority gate 2250 on input lines for the switches of the # 1 disk drive unit in Connection is coupled to all channels. Additional input lines for the NOR gates 2243, which are lines 2253, 2254, and 2255, go from comparison stages 2256, 2257 and 2258, whose positive inputs have a general Resistor network labeled 2260 with the push-button switches for the remote input devices is coupled via lines 2219, 2220 and 2221. Will be push button switch closed for the channels for more than one remote input device, the Resistor network coupled a threshold voltage, so that the resistor network Coupled comparison stage supplies an output signal to make the NOR gate 2243 effective to switch on, to turn on the lamp indicating illegal operations, and the Lock line driver 2232.

With regard to switching on the buttons assigned to the pushbutton switches themselves Lamps, for example with regard to the push button switch 2213 for channel A. the lines 2219 leading to the resistor network 2260 become when closing one of these push-button switches to an input of several negative AND gates 2261, the other input of which is via a line 2262 is fed. This line is coupled to an oscillator, which is preferably a chopped DC voltage signal to control the closed push-button switch associated lamp with sufficiently short period supplies to illuminate to be realized with reduced brightness. The output of AND gate 2261 is coupled to one input each of several OR gates 2262, which are the push-button switches Control assigned lamps. The other inputs of these OR gates 2262 are coupled to lines 2264 coming from the circuit part of FIG. 62C, where each line supplies a voltage which, if there is an assignment, can be switched on of the lamps to full brightness.

As shown in Fig. 62C, parallel data is received from the CPU 106 through the interface circuit 115 for remote input devices via lines 1270a, which are connected to a serial Input line 2270 of the receiver part of the universal asynchronous receiver-transmitter 2230 lie. The parallel data appearing on lines 2271 are indicated by circles 2272 inverted and via lines 2273 to three registers 2274, 2275 and 2276 with 8 bits are given, which are assigned to channels A, B and C. The data on lines 2273 set up commands to turn on the pushbutton lamps vnlle brightness as a function of the assignment made. These commands are as a function of activating a line 2278, 2279 or 2280 in one of the Register entered. For example, if the data is entered in register 2274, so they appear on output lines 2281, which are three lines for address control signals and four lines for binary coded information. This information will decoded in a binary-decimal converter 2283. The three lines from register 2274 and the eight lines 2264 from converter 2283 provide a signal with a predetermined voltage level for a particular negative OR gate 2262 according to 62A shows the pushbutton lamps as a function of the entered assignment or the to fully light up the assigned assignments.

In the lower part of the circuit of Fig. 62C is the enter key 2284 coupled via a line 2285 to an inverter 2286, which is connected to the universal asynchronous receiver-transmitter 2230 as well as to a shift register 2287 and a monostable multivibrator 2288 is coupled. That on the universal The signal given to the asynchronous receiver-transmitter represents the main reset signal for this stage, this stage being held in the corresponding switching state until the switch associated with the Enter key opens. Will enter released, the monostable multivibrator 2288 is triggered, with an output signal represents a load pulse that triggers the shift register on a line 2290, whereby output line 2235 for channel A is switched high while the output lines 2236 and 2237 for channels B and C initially be switched to a low level. If the shift register 2287 is through a When the signal is clocked on line 2295, the signal appears high sequentially on the three output lines, ao that the universal asynchronous receiver-transmitter can sequentially communicate with the CPU 106 for each channel. The exit of the shift register is via a line 2292 and an inverter 2294 and a line 2295 led to a monostable multivibrator 2293. Delivers that Shift register 2287 none Pulse on line 2292 so triggers the monostable multivibrator 2288 the monostable multivibrator 2293 with the rear flank of its output pulse, whereby a pulse for the universal asynchronous receiver-transmitter is supplied to a loading of the transmit buffer to trigger this universal asynchronous receiver-transmitter.

If information is to be sent from channel A to CPU 106, then triggers the monostable multivibrator 2288, the shift register 2287, with the signal high on line 2235, gates 2222 (FIG. 62A) for channel A. switches effectively. This is via the to the interface circuit 115 for remote input devices leading lines 1162a information about the transmitter part of the universal asynchronous Receiver transmitter 2230 sent to CPU 106. The CPU then sends over lines 1270a (Fig. 62C) returns information to the universal asynchronous receiver-transmitter, in order to fully illuminate pressed pushbuttons, which are assigned to channel A. permit. The information is provided by the receiver part of the universal asynchronous Receiver-transmitter 2230 received and on the register 2274 with eight bits of the Channel A because line 2235 of the shift register is the register for the Channel A switches effectively. This is achieved by keeping the signal on the line 2235 activates an input of an AND gate 2300, from whose output the Line 2278 goes off. Has the CPU information about the universal asynchronous receiver-transmitter sent back, it generates a signal indicating the availability of data, which indicates that the universal asynchronous receiver-transmitter is a character with 8 bits and has received it for loading into registers 2274, 2275 and 2276 which can give parallel output lines 2271.

The signal indicating the availability of data is on a Line 2301, which triggers a monostable multivibrator 2302 to be on a Output line 2303 to generate a signal that is transmitted via an inverter 2304 and a line 2305 is led to the AND gate 2300. This becomes the AND gate 2300 activated, which in turn registers 2274 for receiving the character is activated with 8 bits. The signal on line 2303 will continue to the shift register 2287, whereby this register on the information of channel B is clocked. The output line 2303 of the monostable multivibrator 2302 is also led to a further monostable multivibrator 2307 its output line 2308 a reset signal for the universal asynchronous Receiver-transmitter is delivered. The monostable multivibrator 2307 is over an output line 2309 is routed to a gate 2311 whose output signal is on a line 2312 triggers the monostable multivibrator 2293 to another Characters in the transmission buffer of the universal asynchronous receiver-transmitter to load. So once the Enter key 2284 triggers the sequence of operations and the monostable multivibrator 2288 triggers the shift register and the monostable Multivibrator 2293 for data transmission via channel A triggers, so it runs switching via channels B and C automatically continues when the operation is settled has started once. In the presence of the indicating the availability of data Signal at the input of the monostable multivibrator 2302 leads to the generation of a Signal on line 2303, which advances the shift register and the corresponding AND gate, for example the AND gate 2300 for channel A effectively switches, to selectively load registers 2274, 22-5 and 2276. In this way, the Information to be entered on the CPU 106 relating to the status of the assignments forwarded, where the programmed CPU the above Control works and when operating the associated disk drive units and Channels are prevented from being influenced by unassigned input devices. the Lights that light up show the operator both the existing assignments as well as the next assignments to be made when the Enter key is pressed will.

Interface circuit for the sensory system According to deo block circuit diagram of the computer control system of Figure 8 couples the signal system interface circuit 119 the CPU 106 with the signal system shown in the block diagram of FIG. 9A. The input signals marked with an asterisk in the block diagram of FIG. 9A represent commands which are sent by the computer control system via the interface circuit 119 can be delivered. The operation of the signal system interface circuit is explained below with reference to the circuit diagrams of FIGS. 32A and 32B.

The signal system interface circuit is used to transmit Data between the CPU 106 and the signal system, taking the fact into account the computer control system 92 is set to operate asynchronously. Should information respectively.

if data are to be sent from the CPU 106 to the signal system, see above there is a keying in registers and a transfer to further registers. These further registers are scanned by signal system control signals to initiate the transmission of information to synchronize the signal system, so that a synchronization takes place with the timing of the signal system. Are data or information from Signal system sent to CPU 106, gates on input lines through the CPU activated, whereby control signals for the transmission of the information to the CPU generated.

When information is transferred to the signaling system, nen appears Data from address and data bus 105 on lines 1350 and 1351. The data on lines 1350 are split into two registers 1352 and 1353 with 8 bits entered. Similarly, the data on input lines 1351 is split into two Paths split and on input registers 1354 and Given in 1355. Input registers 1352 and 1354 work in the same way as registers 1353 and 1355 as a pair. The data is passed through the central processor interface circuit 108 Device selection signals supplied on lines 1357 and 1362 as well as by the CPU 106 on a line 1366 supplied bus data output signals into one of the Pairs of input registers keyed. The signals on lines 1357 and 1366 an AND gate 1359 is activated, which is a monostable multivibrator 1360 triggers to generate a pulse on line 1361 leading to input of data is coupled to registers 1352 and 1354. On the other hand, signals switch an AND gate 1363 operates on lines 1362 and 1366, creating another monostable multivibrator 1364 is triggered to over an output line 1365 to control the register pair 1353 and 1355. The data on lines 1350 and So 1351 are entered into either one or the other pair of registers. Device select lines 1357 and 1362 are passed through the central processor interface circuit 108 activated as a function of an address signal supplied by the CPU 106 when the commands and the key signals at the output of the signal system interface circuit 119 can be changed as a function of the functions to be performed by the device.

After the data is entered into one of the pairs of input registers are, they are directly on the associated output lines 1367, 1368, 1369 and 1370 available.

Another set of registers 1371, 1372, 1373 and 1374 take data from lines 1367 to 1370 when the registers receive effective switching signals generated by the synchronizing signal circuit of the video input circuit 93A and key signals generated by the reference signal input circuit 93B of the signal system to be triggered.

These tactile signals (which are also known as V-driver signals) are continuously generated as 6Q Hz pulses, with the key signals 1 through the Reference signal input circuit 93B and the key signals 2 through the video input circuit 93A can be generated. Key signal lines coming from circuits 93A and 93B 1376 and 1377 are connected to controlling monostable multivibrators 1378 and 1379 according to Fig. 32B coupled. The one-shot multivibrator 1378 is controlled by the reference signal input circuit 93B via the line 1377 control signal 1 supplied and supplies an effective Switching pulse-shaped signal on a line 1380 for switching the Register 1371 and 1373. The pulse switches accordingly on an output line 1381 of the monostable multivibrator 1379 registers 1372 and 1374 are effective, see above that the data on the output lines of the registers with the correct timing of the signaling system are available. An OR gate 1383 is activated by either the key signal 1 on line 1377 or the key signal 2 on line 1376 switched through, this OR gate clocks flip-flops 1375, 1384, 4385 and 1386 to get the information to lead to their entrances.

The key signal 2 on the line 1376 goes through a delay stage 1387, resulting in a delayed key signal on a line 1390 that is a Represents input to NAND gates 1391, 1392, 1393 and 1394. Corresponding the key signal 1 on the line 1377 passes through a delay stage 1396, whereby a delayed key pulse is generated on a line 1397, which is sent to an input by NAND gates 1398, 1399, 1400 and 1401. The outputs of the NAND gates 1392 and 1399 are routed via an OR gate 1404, the output line 1405 triggers the monostable cultivator 1379. The flip-flop 1384 is activated by the via line 1376 or 1377 from OR gate 1383 clocked. However, the following NAND gates 1392 and 1399 are used to trigger the monostable Multivibrators 1379 with the correspondingly selected delayed key signal, da only one of the NAND gates is activated by the flip-flop 1384, the delayed key signal via line 1405 to the trigger input of the monostable Guide multivibrators. The activation of the NAND gate depends on the logic Level at the D input of the flip-flop 1384, which is clocked by a key signal.

The logic level is determined by the CPU for register 1355 delivered control input signal as well as by operating the monostable multivibrator 1364 via the output line coupled to the D input of the flip-flop 1384 of the register. The triggered monostable multivibrator 1379 delivers therefore an effective switching pulse on line 1381 to display the information from registers 1353 and 1355 with the correct timing of the signal system transfer the output lines of registers 1372 and 1374. The output signal of the OR gate 1404 on the line 1405 is still used as a coding strobe pulse. The outputs of NAND gates 1398 and 1391 are coupled to OR gate 1403, to a driver key signal on a line 1410 when the delayed key signal is received 3 to generate. The AND gates 1400 and 1393 have their outputs connected to an OR gate 1406 coupled to when the delayed key pulse is received on a line 1407 to generate a driver key signal 2. The outputs are similar the NAND gates 1401 and 1394 coupled to an OR gate 1408 for recording of the delayed key signal to generate a driver key signal 1 on a line 1409. The associated flip-flop only makes one of the NAND gates of each pair of NAND gates, which enable the generation of a driver key signal cause, activated. As already explained with reference to the flip-flop 1384, the logic levels at the output of the flip-flops 1375, 1385 and 1386 by the Control signals supplied to the CPU 106, which are to be used on the output lines of the Registers 1355 are present when these flip-flops are clocked by a key signal will. The driver state signals on lines 1407, 1409 and 1410 are on the reference logic circuit coupled to either the Rcterenzloglkßchaltung 125A or reference logic circuit 125B as the source of the drive sync signals for select the disk drive units.

The following describes the functions of the output lines with reference to Fig. 32B described in the signal system. A line is used in the lower part of the circuit diagram 1413 for feeding back a bus response signal to the CPU. This signal comes from an OR gate 1414 whose inputs are via the device selection input lines can be controlled by the central processor interface circuit. The bus reply signal informs the CPU 106 that the addressed device is coupled. Lines 1415 couple command signals to the coding switch 126 as a function of the selected type of operation, i.e. purely electronic operations, transfer operations, test operations or video input Ir for recording operations. A line 1116 couples commands to the code switch 126 to set either the reference or the video sync as the sync source use. Lines 1117 couple drive unit selection signals for selecting one of the three disk drive units for playback channel A, B or C, each of the three disk drive units can be coupled to one or more channels can. An automatic image level command for the video Playback output circuit 127 is supplied to in a search operation in which the playback heads are in the Move disk drive unit from one track to another, an average picture level into the channel carrying the playback signals. The one on line 1405 Coding pulse sent to coding switch 126 is used to select the type of operation of the coding switch, which determines whether this is in a test, erase, Transfer or record operation is working. If the key pulse is sent, so In other words, set the levels on the two input lines 422 of the coding switch (see Fig. 13C) represents a binary word of two bits which indicates the type of operation according to the truth table in the right part of Fig. 13B. Via lines 1419 a synchronous selection signal for the three disk drive units is supplied, while on lines 120 a black level command to the video playback output circuit 127 is supplied in the event that an error is detected during a test, then bringing the channel to a black level. The test error is thereby from the CPU 106 in the event of a mismatch between the requested track number and the number of the data track area on the disk stack upon playback. Via lines 1421 is a command to turn on the chroma inverter during normal playback operations the comb filter and chroma inverter circuit 101, while the chroma inverter is switched off in purely electronic operations, because such operations no playback is performed and therefore there is no need to perform a chrominversion as the full 4 picture sequence of the television signal is available. the Ohromainversion is required when making a fully color-coded sequence a reproduced signal is generated which has a smaller number of fields includes how to use them for a fully color-coded sequence necessary is. The NTSC television standard requires 4 fields, while the PAL television standard 8 fields are required. The other lines, which have no special function assigned are not used.

Should information or data be sent from the signal system to the CPU 106 are, the central processor interface circuit 108 activates the device selection line 1356. By the bus data input control signal provided on line 1358 by CPU 106 the AND gate 1411 is activated to activate the clock signal on one of the inputs of the AND gate 1412. In this way, the data received from the signal system over lines 122 directly onto the main bus 105 to be sent to the CPU 106.

First data track interface circuit that in Fig. 8 as a block diagram illustrated computer control system includes data track interface circuits 1 and 2, which are used to perform various functions and coupling operations between the CPU 106 and the data track disk surface for still images in a disk stack to serve. The data track disc area contains both the batch identification number as well as the track identification number for each of the 815 tracks of a stack of discs. Furthermore, the data track identifies whether a track is for recording a standing one Image is available or whether a recorded still image is retained target. The stack and track information contained in the data track is used for implementation a check after a head position change to make sure that have moved the heads to the correct position. Since the one on the data track area recorded information is in serial form, the data track interface circuit must convert this information into parallel data, which are transmitted via the address and data bus 105 can be sent to the CPU 106. Furthermore, the data track information recorded using the normal data rate of the signal system of 3 SO. This repetition frequency is much higher than those frequencies which from can be processed by the CPU. The data track interface circuit processes the data sent to and from the signaling system in such a way that, when coupled to the Address and data bus 105 are compatible with the clock frequency of the CPU.

The first data track interface circuit carries over the parallel ones Data to serial data for recording on the Data track areas the disk while other parts of the circuit transfer the serial data in parallel Transfer data when reproducing data from the data track areas. About that In addition, this first data track interface circuit performs level conversions, to carry out an adaptation between an EOL logic and a TTLd, ogik. the The operation of the first data track interface circuit is illustrated in the block diagrams 33A and 33B, which show the circuits for converting the serial Show data in parallel data and the parallel data in serial data.

According to FIG. 33A, from the data track of a disk stack read out serial flows through the data track disk area assigned Decoder and time base correction circuit 100 given on line 1700. the Data on line 1700 is inverted and over by inverter 1701 one, line, 1703 is input to a series-parallel shift register 1702. The administration 1703 is still led to a flip-elop 1704. One by the data decoding circuit Data clock signal given on a line 1705 with a subsequent frequency of 3 SO is inverted by an inverter 1706 and clocks the shift register 1702 -over a line 1708, which, furthermore, also to an input of a NAND gate 1709 is led. One from data track interface circuit 2 via line 1710 delivered start command is clocked into a l? ltp-Elop 1711, its output line 1712 with a low level signal on NAND gate 1709 and its output line 1714 is fed to a NOR gate 1715 with a high level signal. Will the NAND gate 1709 switched through, so clocks on one Output line 1717 standing clock a counter 1718 dividing by 12, which is coupled to a decoder 1719 via a line 1720. This decoder can Assume four different initial states, which are used to carry out different Operations in the circuit are used. The counter 1718 normally cycles through the Sequence from 1 to 12 and then returns to count 1. The count value reaches 0 he just by resetting.

The format used for data transmission includes a high level Start bit, 8 data bits, one parity bit and two deep stop bits. Will If serial data is entered, the start bit must be high to avoid that the counter is set to 0 by a signal on a line 1722. this happens by clocking the start bit via line 1703 and flip-flop 1704 into the NOR gate 1715, which sets the counter to 0 via line 1722 if the Start bit is incorrectly at a low level. The output lines of the decoder include a line 1724 for the state 0, which clears the flip-flop 1704 when the state 0 is reached. An input line 1727 for the state 1 clocks the flip-flop 1704, while a line 1728 for state 11 is on NOR gate 1730 is performed, which clears a flip-flop 1731, which in turn a signal indicating the availability of data on line 1732 in NAND gates 1734 and 1735 enters. When the decoder reaches state 12, it takes a line 1737 has a low level and supplies a signal that triggers the loading of data for a register 1738 which receives the data from the shift register 1702 via lines 1739 receives. Line 1738 for state 12 is still on a NOR gate 1740 out, the output signal of which is sent to the register via a line 1741 for clocking which loads data into register 1738. Will continue A clock pulse for the flip-flop via an inverter 1743 and a line 1744 1731, which indicates to the data track interface circuit 2 that Data is available.

Is on one coming from the data track interface circuit 2 If a stop command is present on line 1746, then the flip-flop 1711 is set, see above that it has the register 1738 and the counter 1718 via line 1714, the NOR gate 1715 and line 1722 clears. The data in register 1738 is transmitted via output lines 1750 coupled to the data track interface circuit 2. These lines are continue to be performed on a parity check circuit 1751, which via an output line 1752 supplies a clock signal for the NOR gate 17314, whereby a line 1753 given a parity error signal to the data track interface circuit 2 will. Correspondingly, artifacts are checked by NAND gate 1735, with over an input line 1754 a test of the start bit and via lines 1755 a The two stop bits are checked. If the stop bits are not at a low level or if the start bit is not high, line 1756 is on Image error signal generated.

The further part of the first data track interface circuit according to FIG 33B converts parallel data into serial data for the Record on the data track disc surface. Parallel data from the data track interface circuit 2 via 8 lines 1760 into a parallel series shift register 1761 and input to a parity generator 1762. The output signal of the parity generator on line 1763 is on at the next clock pulse a line 1765 is loaded into a flip-flop 1764. The clock pulse is thereby through a NOR gate 1766 generated from a reference clock signal on an input line 1767. The reference clock signal put on line 1767 by encoder switch 126 with a frequency of 3 SO is also input to a NAND gate 1768, the is activated via a line 1770 by a flip-flop 1769. The flip-flop 1769 blocks the NAND gate 1768 when it is triggered by a clear signal on a line 1772 provided by a flip-flop 1773 is cleared. Are parallel If data is present on lines 1760, it is indicated by the data track interface circuit 2, a signal is provided on line 1774 indicating the presence of data and applied to the flip-flop 1773 and an OR gate 1775. That the presence of data indicating signal continues to clock a flip-flop 1783 to put it in the switching state to switch for data that has not been transferred. The circuit also includes a through 12 dividing counter 1777, which is activated by the NAND gate 1768 via a line 1778 is clocked and from the data track interface circuit 2 via a reset line 1780 is reset to state 11. Via line 1780 and an inverter 1781 continues to be the F1ip-flop 1773 and a flip-flop 1783 via a NOR gate 1784 and a line in 1785. One to the counter 1777 via lines 1788 Coupled decoder 1787 supplies the various status signals on output lines 0,1, 10 and 11. When the counter is reset, the decoder responds to the status signal 11 switched, which after decoding a signal on a line 790 for a NAND gate 1791 and the OR gate 1775 supplies. The OR gate clears the Flip-flop 1773 and supplies the clock for the NAND gate 1768 via line 1772, the Fafp flap 1769 and the line 1770. The next time the reference clock jump, will a line 1792 carried to the NAND gate 1766 for the zero state signal is operative switched, the parity information from the parity generator 1762 in the flip-flop 1764 is clocked. In switching state 1, a line 1793 is activated and switched via the NOR gate 1784 to the flip-flop 1783, whereby this on its switching state is set for the data transfer, so that a display for the data trace interface circuit 2 that data is generated on the line 1760 are loaded into shift register 1761. Charging takes place over the line 1792, which on a load control input of the shift register and an AND gate 1795 is run. The input line 1792 for the AND gate 1795 is with the exception of the switching state 0 is normally at a high level, so that the AND gate 1795 after the occurrence of the start bit the serial data from shift register 1761 on a line 1798 to a line 1799 and then via a NOR gate 1800 and a line 1802 leads to a flip-flop 1801. After that the data is on a line 1803 clocked to be on the corresponding data track of the disk stack can be recorded on the selected disk drive unit. Are the switching states 10 and 11 are decoded, either line 1790 or line 1804 produces a high level on a line 1805 which is fed to the NOR gate 1800 is. This means that serial data are on line 1803 because gates 1795 and 1800 always received a start bit with a high level and two stop bits with a low level.

A special circuit for performing the operations of the block diagrams 33A and 33B is in the Figs. 57A and 57B are shown. This circuit according to FIG.

57A and 57B correspond in their mode of operation to the circuits according to 33A and 33B so that with one exception a detailed description is waived. According to Fig.

57A can handle the serial data on line 1700 as well as the Data clock signal on line 1705 coming from three separate channels. Corresponding may provide a serial line identification signal on line 1757 from the time base correction section the decoding and time base correction circuit 100 of three channels come. The line identification signal from the selected channel is applied to the data track interface circuit 2. Channel control lines 1560a, 1560b and 1560c control an input of NAND gates 1759a, 1759b and 1759c for the data, clock signal and line identification signal of channel A, B or C to OR gates 1776a, 1776b and 1776c. One of the Channel select lines 1560a, 1560b or 1560c are connected by a flip-flop 1542 (Fig.

34C) of the second data track interface circuit is activated.

Second data only interface circuit The second data track interface circuit performs three basic functions. First, it provides a storage facility for data received from the stack of slices.

Data track area are reproduced so that they are at the repetition frequency of the CPU clock can be sent to the CPU 106, which is less than the frequency of 10.7 MHz (3 SC) with which the data on the disk stack data track surface recorded and played back by it. Second, this interface circuit controls sending serial data from the interface circuit for recording. Third, it controls the receipt of serial data from the CPU for storage.

As will be described in more detail below, forms a read-write memory a storage facility for the data to be recorded or reproduced, which acts as a buffer between the disk drive unit and the CPU.

The read / write memory is made up of a memory with 64 addresses and 9 bits are formed so that it can process 64 bytes of information which are between him and the CPU and between him and the disk drive unit will. As will become clear from the following remarks, the transfer requires of data from the read / write memory to the disk drive unit compared to the Transfer of information from the disk drive unit to the read / write memory a different circuit, the circuit between these functions can distinguish between the different operations mentioned.

When recording, i.e. when transferring information from the read / write memory The data to be recorded are stored in 16 address locations on the disk surface Bring read-write memory, each address space containing 8 information bits. Therefore there are four information bytes in the first four places of the read / write memory stored and repeated a second, a third and a fourth time, whereby the 16 address positions of the read-write memory are filled. This information is then converted into serial information which is transmitted via the encoder 96 of the signal system for recording on the recording surface of each disk stack be sent in the disk drive unit in channel-coded form. There the four Bytes are repeated four times, filling a quarter of the read / write memory all 64 addresses are recorded on the data track area for each track. The reason for the redundancy of the four information bytes is to obtain one Comparison for an indication of whether the data received during playback is valid are. Each byte to be recorded is serially in the form of a start bit, 8 following Data bits, a parity bit and 2 final stop bits, which results in a total of 12 information bits result. A sync word gate is used during the recording process of encoder 96 to start recording the 64 bytes from memory, the 64 bytes supplied by the data track interface circuit 120 to the encoder 96 are coupled, which inserts a sync word into the data for the data track and encode them into the channel encoded format. Since every synchro word in every second TV line occurs, i.e. for every two lines If a sync word is available, the 64 bytes take up about two thirds of the total data track area of two lines a. In other words it takes the record of 64 bytes about two thirds of the time period between successive synchromes. Since the sync word occurs about 131 times per television field, the 64 bytes not 131 times but about 120 times recorded on the data track area because the Information is not recorded during the vertical blanking period.

When reading out the data track area, a logic circuit expects the Determination of the sync word by the decoding part of the decoding and time base correction circuit 100 and then reads out every 64 bytes of data from the disk area, followed by an operation completion signal which causes the CPU 106 to read the random access memory in the data track interface circuit 120 query. The data track interface circuit carries the serial information from the data track area into a parallel perforation and provides it to the data track interface circuit 2, in which they are stored in the read-write memory in the event that there are no errors be enrolled. An address counter of the read-write memory is updated after each Writing data in an address position. advanced. However, will during the transmission from the disk drive unit to the read-write memory during playback an image or parity error is detected, the operation is interrupted, so that the circuit waits for the next occurring sync word to complete the operation to repeat. This operation is repeated until all 64 bytes without parity or artifacts have been received, after which the CPU sends the operation completion signal supplies. Every time the circuit is not 64 consecutive. Bytes from the Disk drive unit reads, an error counter is incremented, which is a Provides an error indicator signal when a certain error count is reached. This makes the disorder one specific data channel used displayed.

34A to 34D show a logic circuit for control as a whole the flow of information over the address and data bus 105 between the CPU 106 and the random access memory of the data track interface circuit 120, wherein the Address and data bus lines 105 each at one end of the circuit diagram (Fig. 34A and 34D), indicating that the data is from the CPU 106 clocked in in the left part of the circuit (Fig. 34A) and in the right part of the Circuit (Fig. 34D) to be clocked out to the CPU. The 16 lines are via NAND gates 1500 clocked when a control line 1501 for the interface circuit through a manually operated switch is switched to a high level. This line is used to switch off the interface circuit when a test is carried out by a device part is carried out, which does not form a functional part of the overall device. The control line 1501 for the interface circuit is still on NAND gates 1502 and 1503 out, the line in normal operation is again at a high level and only is at a low level during a test process when the circuit is disconnected from the bus lines 105 should be switched off. NAND gates 1502 are on bus data input and Output control lines 1504 and 1505, which in turn are coupled to the control lines 144 of the CPU 106 (Fig. 8) are coupled. In this case, a line 1506 is a signal indicating no input of data and on lines 1506 and 1507, respectively generates a signal indicating no output of data. The other entrances to the NAND gates 1503 are coupled to device select lines 1510, 1511 and 1512, which in turn to device select lines 114 of the central processor interface circuit 108 (Fig. 8) are coupled, where on lines 1513, 1514 and 1515 output signals are generated which, together with the aforementioned signals clocked on lines 1506 and 1507 by a sequence of NAND catters 1516 to apply control signals on lines 1518, 1519, 1520, 1521, 1522 and 1523 produce. These lines carry the signals to other points in the circuit 34B to 34D to set logical conditions for carrying out certain still operations to be described.

The line 1518 is activated when the above signals is present on lines 1504 and 1510, which is the case when data is from of the disk drive unit into a random access memory 1533 of the above Type are to be registered. Line 1519 is activated when signals from the aforementioned type are present on lines 1504 and 1511, which is the case, when data are to be sent from the read / write memory to the CPU 106.

The line 1520 is activated when signals of the aforementioned Type is present on lines 1504 and 1512, which is the case when data, relating to the status of the interface circuit logic to the CPU 106 should be sent. Line 1521 is activated when signals from the aforementioned type are present on lines 1505 and 1510, which is the case, when data are to be sent from the CPU to the read / write memory 1533. the Line 1522 is activated when signals of the aforementioned type are on the lines 1505 and 1511 are present, which is the case when data is sent from the CPU 106 to the data track switching to be sent, which either the operation of the transmission from the disk drive unit for read-write memory or the transfer of data from read-write memory to Disc drive unit as well as the disk drive units to be used and identify channels. The line 1523 is led to a NOR gate 1525, to generate a reset pulse on a line 1525a, which is present, when the device selection line 1512 and the bus data output control line 1504 on Lead signal. The reset pulse sets both the logic circuitry in the data track interface circuit 1 as well as in the data track interface circuit 2 to an initial condition for performing the interface operations between the CPU 106 and the data track area. While a bus trip command is present, which is transmitted via line 1526 is provided by the CPU 106, a reset pulse continues to be generated.

As described above, the bus trigger command is used to set the logic in a certain switching state, for example during start-up.

Data from the CPU on the address and data bus lines 105 will be clocked by NAND gates 1500 on lines 1530, which on a sequence of NAND gates 1531 are performed, which in turn carry the data on input lines 1532 of the read / write memory 1533 clock when the line 1521 upon receipt of the corresponding Device selection signal and a bus data output control signal are activated will. Therefore, data from the CPU 106 can be written to the random access memory when gates 1531 are activated and a write command on a Line 1534 occurs. The line 1534 comes from a NAND gate 1535, whose input signals are supplied via line 1521 and lines 1536, the latter lines from a shift register comprising 4 flip-flops 1537 come, which by the reference clock signal coming via a line 1529 with the frequency 3 SC clocked by the data track interface circuit 1 will. The bad register 1537 also provides a bus response signal via a Line 1544 to CPU after the data has been written to read / write memory 1533 are. In addition to writing the data from the CPU to the read-write memory 1533 can data from the disk drive unit on lines 1750 into the read / write memory 1533 can be written when NAND; gate 1543 is activated. This is the case when the line 1527 is in operation for the transfer of data Disk drive unit is effectively switched to the read-write memory.

While only the lines of the group 1530 for the eight bit lower Order are routed to the NAND gate 1531, the entire group of 16 Blt lines is to the circuit parts according to FIGS. 34B and 34C, the lines for the 6 lower order bits are coupled to a pair of 1 out of 8 decoders 1540, while the lines for the higher order 8 bits are connected to a pair of registers 1541 and another pair of registers 1542 is coupled. There are also 6 of the bit lines are routed to NAND gates 1545 according to FIG. 34D, which are routed to address lines 1546 provide address information when line 1520 is enabled. Lines 1546 form the address lines for the address inputs of the read-write memory 1533.

In this way, know the data from the NAND gates 1531 into the Address positions of the Schrelb-Lesespelcher are written in, if on the line 1534 a Schrelbbefehl is available. The data in Schrelb read only memory 1533 are coupled to the disk drive unit via output lines 1548, the Lines 1548 leading to the data track interface circuit 1 according to FIG. 33B cables 1760 are coupled.

The decoders 1540 shown in Fig. 34C receive a through the 6 lower order binary number on lines 1530 if the Lines 1522 and 1536 are effectively switched, the outputs of these decoders are coupled to NAND gates 1550, 1551 and 1552. These gates provide output signals on lines 1553, 1554 and 1555. The line 1553 switches the registers 1541 to inscription of the addresses effective. Line 1554 activates Hegister 1542 and sets a flip-flop 1557 in front, whose output lines 1538 and 1539 the operation the data transfer from the read / write memory to the disk drive unit. Correspondingly, line 155f) activates registers 1542 and is activated Flip-flop 1558, whose output lines 1527 and 1528 operate for transmission of data from the disk drive unit to the random access memory. Output lines 1559a, 1559b and 1559c of flip-flop 1542 are on NAIID catter 1600 (Fig.

34E) and determine the corresponding disk drive unit, on which data should be recorded.

Output lines 1560a, 1560b and 1560c from further flip-flops 1542 are led to three NAND gates 1572, which define the channel A, B or C, which are used to process the reproduced data track information target.

The registers 1541 provide address information on lines 1562, which is clocked by NAND gate 1563 when line 1519 is activated, to address information to the address inputs of the read / write memory routed lines 1546 to lead. This becomes a command to read out the read / write memory 1533 which contains data from the disk drive unit. In addition to the coupling Lines 1546 are also on to the read / write memory NAND gate 1565 coupled, which are also activated by line 1519, whereby the address information is clocked onto the address and data bus lines 105 becomes effective when the associated output NAND gates 1556 via lines 1567 be switched.

t Lines 1567 are activated when either a signal is flowing Line 1519 or line 1520 (from the bus data input command and the corresponding Device selection signal generated) together with an interface circuit control signal is present on line 1568. The line 1568 generally carries a signal high level. This is only not the case when test operations are carried out a test device can be performed by an operator to a Cable connection 1569 is connected.

While the high order address bits are passed through NAND gates 1565 are clocked on the address and data bus 105, the Bltinformation becomes less Order on lines 1548 from the random access memory by a number of NAD gates 1750 clocked on bus 105, this MAND gate being effective via line 1519 are switched so that the eight data bits via lines 1571 to the bus 105 will be sent. The lines 1571 are still on the corridors of another Set of IAND gates 1572, which are the 8 information bits lower Order also supply, v-nn the IAND gates 1572 via the line 1520 effective are connected, so dali the status information relating to the interface circuit can be sent to the CPU.

For example, the status information relating to the operation of the Data track interface circuit 120 when sending data from read-write memory to the disc drive unit or when sending data from the disc drive unit to the read-write memory concerns, sent; are data from read to a disk drive unit or sent to a disk drive unit, so by the interface circuit shown in FIGS. 34E to 3411 a process flow signal on line 1528 is generated.

A read error status signal is detected by a read error detector 1654 (Fig. 34H) generated on a line 1547. From the interface circuit according to FIG. 34E through 34H, an operation completion signal is generated on line 1549.

Finally, a signal is also generated which indicates which Channel has been selected to display the information.

If the circuit is either information from the read / write memory to Disk drive unit or information from the disk drive unit to the read / write memory sends, an OR gate 1574 supplies an output signal on a line 1575, that activates a number of NAND gates 1576, which are on lines: 577 existing and generated by counters 1578 and 1579 address information clocks.

Illegal counters count under the control by counting increment signals, which silver lines 1639 or 1691 (Fig.

3411) on an input line 1582, through the 64 Addresses. The incremented counter selects the information from the read-write memory to the disk drive unit or from the disk drive unit to the read / write pelcher should be brought. The counter is controlled by a circuit according to FIGS. 34E to 3411 clears the signal generated on a line 1583. The exit signals Output lines 1577 are also clocked on to line 1580 Generate signals indicating that the address counter has a count of less than 63 owns. Furthermore, a signal is generated on line 1581 in the event that that the counter address counter is greater than or equal to 64. These Display signals are to be described in the following in the circuit of FIGS. 34E to 34H Wise exploited.

FIGS. 34E to 34H collectively show a circuit diagram of part of FIG second data track interface circuit, the entire circuit diagram being general can be divided into two parts, one part of which is the transfer of information from the read-write memory controls to the disk drive unit, with the parallel data from the read-write memory 1533 can be converted into serial data for recording on the data track area. The other part of the circuit controls the transfer of information from the disk drive unit to read-write memory, the serial information from the data track area of the disk drive unit is converted into parallel information and into the read-write memory 1533 is written.

In the circuit part according to FIG. 34E, that of the information transmission is assigned from the read / write memory to the disk drive unit, ss rd after Selecting one of the disk drive units 73 to select one of three NAND gates 1600 activated and supplies an OR gate 1601 at the corresponding output Through-switching signal when the other input of one of the NAND gates 1600 is activated becomes what is the case when recording is made. On one line 1602 creates a data timing pulse when recording on a disk drive unit is carried out. This pulse disappears when the recording is completed is. No data is recorded during the vertical blanking period the data track area of the disk drive unit. There is also a record only after the synchronization word has been inserted he wishes. The data timing pulse on line 1602 is therefore passed to a NAND gate 1603, the output signal of which indicates that an information transfer from the read / write memory to the disk drive unit takes place. This is the case when there is an input signal on line 1538 at Information transfer from the read / write memory to the disk drive unit is effective and when line 1605 receives a signal from the signaling system indicating that there is no vertical blanking.

The output signal of the NAND gate 1603 is thus via a line 1604 given to a NAND gate 1605, the other input of which is via a line 1606 receives a clock pulse after the synchronization word clocking has ended.

The sync word clock signal from encoder 96 is on a line 1607 given and clocked by a shift register containing flip-flop 1609, whereby this shift register puts a flip-flop 1610 in front of a NAND gate 1611, what a pulse occurs after stopping the sync word clock. The output signal of the NAND gate 1605 therefore starts the recording sequence at the end of a sync word. Line 1613 from NAND gate 1605 is on flip-flops 1614 included Shift registers, the outputs of which are fed to a NAND gate 1615, wherein an address counter erase pulse is generated on a line 1616, and via the Input line 1583 to address counters 1578 and 1579 according to FIGS.

34C and 34D is kept to these counters for the purpose of providing for clear the address count sequence with 64 counts. The shift register 1614 is further coupled to a NAND gate 1618, which after the generation of the address counter clear pulse clocks a signal on line 1619. This line 1619 is to a NOR gate 1620 coupled to a shift register containing flip-flops 1621 to clock, whereby a line 1622 indicates the presence of data Signal is generated, causing the parallel to serial converter in the data track interface circuit 1 receives information that for each address at the output of the read-write memory 1533 parallel data are available. An output appearing on line 1626 a shift register containing flip-flops 1625 switches an input of a NAND gate 1627 which performs a test to determine if the The address of the counter supplied to the input line 1580 according to FIG. 34D is less than 63 is.

If the address is less than 63, a flip-flop 1630 will have a Line 1629 is provided, the output signal of the flip-flop 1630 via a Line 1631 is applied to a NAND gate 1632 which has a signal on a line Expected in 1633. This through the flip-flops 1634 and an input signal on a Signal generated on line 1635 indicates that data is being passed through the parallel-to-serial converter have been taken over. The input on line 1635 indicates that data have not yet been adopted. If data have been accepted, the NAND gate becomes 1632 switched through and provides a signal on an output line 1637 for a Flip-flop 1638, which increments the address counter via a line 1639. One Another output line 1640 of the flip-flop 1638 is on another flip-flop 1641, the input line 1642 of which is fed back to the NOR gate 1620 which is the signal on line 1622 indicating the presence of data generated. This means that addresses 0 to 36 are clocked for recording until the data is clocked out in all addresses of the read / write memory 1533 are. If address 63 is reached, the switching condition for the NAND gate is established 1627 is not met, so that the circuit only responds to the next sync word clock signal waiting to start again. When the data timing pulse disappears, so will a NAND gate 1645 turned on after two clock pulses passed through a flip flop 1646 containing shift register are clocked. The output of the NAND gate 1645 provides a flip-flop 1647 to generate a signal indicating that an information transfer operation is being carried out from the read / write memory to the disk drive unit is completed.

In the following the circuit part will now be described, which at the transfer of information from a disk drive unit to the read-write memory is effective. On line 1527 is the information transfer from one Disc drive unit for read / write memory available, a flip-flop 1651 can be set to clear an error counter 1653 provides a signal on line 1652 as shown in FIGS. 34G and 34H. The error counter records how often a complete sequence with 64 bytes has been read due to the Presence of an image error or a parity error in the above Sense is interrupted. During the vertical blanking period, the data track area the disk drive unit to the read / write memory not to be transmitted written, with the signal on line 1605 indicating the absence of the Vertical blanking period is given to a NAND gate 1656, the other of which Input the line identification signal from the data track interface circuit 1 receives over a line 1657. The NAND gate 1656 blocks every sync word or Any line identification signal generated during the vertical blanking period appear.

If the NAND gate 1656 is turned on, which indicates that a serial line identification signal is present, it is via a line 1658 a flip-flop clocked 1659. This flip-flop forms part of a shift register, which further includes flip-flops 1660, 1661 and 1662. The flip-flops 1660 and 1662 are clocked by a clock signal on a line 1663, this clock signal is read from the disk drive unit. When the serial line identification signal occurs on line 1658, the shift register provides an address counter LtSsch command on a line 1664 and a start command for the series-parallel conversion a line 1665, which is also led to an input of a NAND gate 1666 is. The data is clocked in the serial parallel converter during 12 clock periods, where these are the 8 data bits, one start bit, two stop bits and one parity bit acts. The availability of data generated by a line 1667 signal indicating the NAND gate 1666 is turned on and generated on a Line 1669 a signal for a further NAND gate 1670, its further inputs activated by a shift register containing flip-flops 1671, after the pulse is clocked through. By that generated on a line 1672 The output of the NAND gate 1670 is tested for errors, if the available data are stored in the Swhrelb-Levespelcher. about the Line 1672 provides an input to a NAND gate 1673 which is on a line 1674 provides a no-fault signal when on lines 1675 and 1676 neither a parity error signal nor an image error signal is present are. The latter lines are led to an OR gate 1677, whose Output line 1678 is led to the NAND gate 1673.

If a parity error or a picture error occurs, the NAND gate is activated 1680 by the signal on line 1678 and the test pulse on line 1672 switched through, whereby a flip-flop 1681 is set in front, which in turn on a flip-flop 1682 is coupled. This is the error counter on a line 1683 1653 generates an incrementing signal, and in addition the flip-flop 1662 via an OR gate 1684 and a line 1685 is cleared.

The flip-flop 1662 then provides the operation on a line 1686 interrupting stop signal for the series-parallel conversion. The sequence begins then new as soon as another serial sync word appears on line 1658. If no error is found, a flip-flop containing 1688 and 1681 is generated Shift register placed in front of it, its output signals on NAND gates 1689 and 1690 be coupled. The NAND gate 1689 provides a write control pulse for the Read / write memory according to FIG. 34B, while a signal on a line 1691 from NAND gate 1690 increments the address counter to the next information byte from the disk drive unit and put it in the next address of the read / write memory to enroll.

Disk Drive Interface Circuit The disk drive interface circuit 118 according to the block diagram of the computer control system according to FIG. 8 for coupling of disk drive units with the address and data bus 105 is described below described with reference to a circuit diagram according to FIGS. 35A and 35B.

Data supplied by the CPU 106 via the address and data bus 105 are input to the circuit on the left side of the circuit diagram of Fig. 35A and loaded into registers 1140 and 1141 if a monostable multivibrator 1442 from the central processor interface circuit 108 on a device select line 1443 a command and from the CPU 106 on line 1444 a bus data output command receives. So that a NAND gate 1445 is activated to the monostable To trigger the multivibrator 1442 via a line 1446. The signal continues on line 1446 to a NOR gate 1447, which is an output line 1448, the bus response signal sent to the CPU 106 is generated.

The NOR gate 1447 is still activated by appropriate signals Lines 1449 and 1450 from other device selection lines are activated if the bus data input signal is present. The output signal of the monostable multivibrator 1442 controls the registers via lines 1452 in order to match them with the data and Address bus lines 105 to load occurring data. The stored information appears on output lines which lead to the circuit to be described below are performed according to Fig. 35B.

If a device selection line 1454 is activated, whereby indicates that the address is from a selected disk drive unit Lines 1451 along with a bus data input signal on line 1455 receive are to be, a NAND gate 1456 is switched through and provides a low output on that on NOR gate 1447 leading line 1459. The signal is inverted by inverter 1462 and converted into a Number of line receivers 1458 entered, which refer to a selected Contain address information relating to disk drive unit. Will accordingly another device selection line 1459 is activated, which indicates that that status information of the disk drive unit should be sent to the CPU 106, and when there is a bus data input signal on line 1455, it becomes a NAND gate 1460 is switched through and provides a signal with a low level on line 1450, thereby generating the bus response signal. The signal on line 1450 becomes inverted by inverter 1463 and onto another set of line receivers 1461, which contains status information from a selected disk drive unit obtain. The status information from the selected disk drive unit is sent to CPU 106 via output bus lines 105.

Certain output lines of registers 1440 and 1441 are on parity generators 1464 and 1465 which produce output signals on lines 1466 and 1467. These are marker and bus parity signals. Output lines 1470 transmit 8 bits of data to the bus lines in the disk drive units even, while lines 1471 carry 4-bit marker line information, which is a bus signal category for the disk drive unit for definition defined by their type of operation. Mark clock lines 1472 take effect switched, the disk drive unit receives the instruction to take over information.

To select a disk drive unit, use the marker lines The number 3 generated in 1471 indicates the number of the disk drive unit the bus lines 1470 are present, a selection line 1473 is activated and, as a final step, the marker clock line 1472 is activated be. To the selected disk drive unit in the selected conditions the selection line must remain active.

The disk drive interface circuit thus couples the 16 bus address lines 105 with the bus, marking and other lines of the disk drive circuit self.

Control of recording and playback by the disk drive units As already stated above, it concerns the device described here used disk drive units 73 preferably to unchanged standard units, so that their reliability, which has been achieved through development work over several years can be used to advantage.

The disk drive units are only changed as 8 bits of video data recorded simultaneously with a parity bit on 9 parallel surfaces are recorded and the associated information is also recorded on the data track area will. In a manual published by the applicant, part no. M 300211 for are a model DM 331 disk drive unit manufactured by the applicant Table 2-1 shows the command decodings for the bus within the disk drive unit and explains the marker lines that govern the operations that occur. In the named model DM 331, a marking line 11 relates to surgical and status functions, which are in connection with the device in question here specifically not applicable. Therefore some circuits of this device are modified or replaced by other circuits in order to have an application in the one at issue here Device to enable.

As when using the disk drive unit in the normal Computer data processing enables rapid switching between read and write operations within one revolution is required and because doing small sectors of the whole Disk circumference are used, many operations relate to the standard marking line 11 as well as status functions on this type of application. In which here The device in question is, however, with every revolution of the stack of disks single field of television information recorded or reproduced. For a a single full image therefore requires two rotations of the stack of slices, one field of video information on one set of 8 areas and the other Field of video information recorded on another set of 8 areas will.

Since switching between read and write operations is only at the end of full revolutions of the disc with respect to a defined point (specifically referred to as sector 000 or index) occurs, the switchover occurs during the vertical interval of the television signal, so that a very fast switching is not critical in the device in question here.

Record and playback operations for normal data processing occur at a data rate of about 6.5 megabits per second while the video information to be recorded on the disk stacking surfaces in the present device occurs at a repetition rate of about 10.7 megabits per second. Since the electronic Switching of the heads between the recording and the reproducing circuit at Standard disk drive units cause some impairment of the signal-to-noise ratio leads, the electronic switches have been replaced by relays, resulting in a Increase in the signal-to-noise ratio of the resultant, coming from the disk stack Signal by about 2 dB.

As the main part of the circuit associated with the disk drive unit remains unchanged, only additional or modified circuit parts are needed generally described, there them with the ones not shown Circuit parts must work together without interference.

37A and 37B show a circuit diagram of a recording and recording circuit Playback control circuit. In the left part of the circuit of Fig. 37A, there are bus output lines 1820 to 1826 (a bus line 1827 is shown in Fig. 37B), which can be switched on via NAND gate 1831 when an operation command is on a line 1832 is effective. This is the case when the marking line 11 is in the disk drive unit is raised to a high level and is tested and determined to be effective. The circuit of Fig. 37A stores instructions from the computer control system 92 which relate to cases where the relays controlling the head currents are in a recording position or are in a playback position. The purpose of this is to put information on a Disc stack 75 to record or play back and to receive commands about to couple additional circuits to a shaft servo unit, creating the correct one Rotation phase of the stack of slices relative to the reference vertical synchronization signal guarantee. These functions are performed as follows. When recording the servo reference signal coincides with the vertical sync pulse of the television signal. In playback transfer operations, the servo is referred to the vertical sync pulse of the television signal is advanced by one horizontal line period. When playing is the servo reference signal with respect to the vertical sync pulse of the television signal moved forward by two horizontal lines. The signals on the three upper bus lines 1820, 1821 and 1823 are inverted after passing through the NAND gates 1831 and given to a 1 out of 8 decoder 1834. Three exit lines 1835, 1836 and 1837 this decoder 1834 sets the phase in accordance with the input commands in the wave solitude fixed and are defined as permissible. All other decoded output signals are inverted in an OR gate 1838 ORed and fed into an OR gate ins40 via a line 1839, the generates a rejection order. This indicates that on the first three Lines 1820 to 1823 send an incorrect command.

The output of decoder 1834 on line 1835 is inverted and fed into a NAND gate 1842, which generally has a 1843 and having an output line 1844 sets.

A signal is supplied via this line 1844, by means of which the rotation phase of the disk stack is guided into the recording position via the shaft servo unit will. The signal on output line 1836, when inverted, becomes a NAND gate Fed in 1845 and in an OR gate 1847 with a power supply reset signal ORed on a line in 1846. The output signal of the OR gate 1847 is set the register 1843 over the line 1848 back, whereby also a general with 1850 designated register is set. This controls the wave feed unit in such a way that that a command for the display rotation phase is generated on line 1851. If the line 1837 of the decoder carries a signal, this signal is inverted and clocked by a NAND gate 1852, which resets the registers 1843 and 1850 and a register 1854 is set whereby on line 1855 an instruction for the playback transfer rotation phase is produced. Received the NAND gates 1842, 1845 and 1852 via a line 1856 a memory control command, the three permissible output signals define the Decoder has a playback transfer, recording or playback rotation phase.

The bus lines 1825 and 1826 alternately carry exclusive command signals, to switch the relays to the recording or playback position. Leads the bus line 1825 has a high signal and is of the effectiveness of the operation instruction indicating is present, the NAND gate 1831 sets a register 1857, the provides a high signal on line 1858, causing the relays in the recording position can be switched and a recording can be carried out, when the timing is right. The bus line clocked via the NAND gate 1831 1823 sets a register 1860 which supplies a head selection signal on a line 1861, that serves for maintenance purposes.

37B, a signal on bus line 1827 is combined with an operation command that activates the NAND gate 1831, a register 1862, provided that a NAND gate 1864 is active on a line 1863 Command is present. The output of the register 1862 represents a recording signal represents for the next picture, which in the recording timing circuit of Figs. 38A and 38B is used. As a further command, the circuit generates after the 37A and 37B show a signal on line 1865 indicating that the recording sequence is completed. This signal sent to CPU 106 resets register 1862.

Record timing circuit for disk drive unit The in The circuit shown in Figs. 38A and 38D provides the reference signal at 60 Hz for the shaft servo control system of the disk stack drive motor. Under use of the disk stack drive motor, the shaft servo unit regulates the rotation phase of the disk stack using a clock generator circuit to be described generated shifted color image signal as a servo reference signal.

As mentioned earlier, the television signal must be relative to its location be shifted by one or two television lines when recording, resulting in delays to compensate that in the circuit of the playback channel 91 during playback expected from video data. That in the recording timing circuit according to The shifted color image signal produced in Figs. 38A and 38B is relative to that required Correctly stored timing for recording, playback and transfer operations. The circuit shown in Fig. 38A provides a servo reference signal at 60 Hz, from the multiplex synchronous signal supplied by the signal system with a Frequency is derived from 2 H. For this purpose, the signal is with frequency 2 H divided by 525 to produce the basic 60 Hz reference signal, the due to the shifted color image signal from the clock generator in its phase position is regulated.

The recording timing circuit continues to generate drive signals for switching the relays in the recording or playback positions as well as via Driver control lines to be fed back to the CPU 106, whereby the CPU 106 receives information about the relay position. In the device in question a head shutdown signal is still generated, which the head stream locks for at least one revolution of the disk stack after the record / playback relay is switched between its two positions.

The recording timing circuit continues to generate the signal for Switching from one set of recording heads to another set to a Record field on one set of disk faces while the other video field recorded on another set as previously described. That Head switching is controlled by a basic 30 Hz signal.

In the circuit of Fig. 38A, a relay set line 1870 provides which when the relay is switched to the playback position at high level and at Switching the relay to the recording position is at low level, an input signal for a NAND gate 1871, the other inputs of which with a pulse via a line 1872, indicating that sector 000 (index) is on the The stack of disks passes the servo head, which occurs during normal operation during the Vertical interval takes place. If the relays are in the recording position and appears the pulse on line 1872, the NAND gate 1871 sets a register 1873, which is coupled to transistors 1874, which via a line 1875 a relay to a preamplifier circuit (Figs. 54A and 54B). The switching status of the Register 1873 also causes a signal to be generated on one to the circuit 38B lead line 1876, indicating that the relays in the playback position. Otherwise, on a circuit according to Fig. 38B leading line 1877 generates a signal indicating that the relay stand in the recording position.

To generate the reference signal for the servo unit, an as Multiplex sync signal denoted signal with frequency 2 H, its timing is determined by the signal system circuit is given on a line 1880, where it appears after inversion on a line 1881 that divides on one by 256 Counter 1882 is kept.

An output line 1883 of this counter clocks a dividing by 2 Flip-flop 1884, resulting in a line 1885 divided by 512 Signal is generated which sets a register 1886 via a NAND gate 1887. This Register 1886 is coupled to a shift register 1888 which is activated by the signal is clocked with the frequency 2 H on the line 1881. An exit line in 1890 of the shift register 1888 is coupled to a shift register 1892.

The pulse clocked by shift register 1892 onto line 1891 represents the count of 525 and clocks a flip-flop 1893. This flip-flop 1893 delivers a pulse on a line 1894, which via NOR gate 1895 on a line 1896 is clocked, thereby shifting registers 1892 and 1888 as well the counters 1882 and 1884 are cleared. So the final count of 525 sets the Counter and the shift register back. The frequency divided by 525 2 H drives to a signal with a frequency of 60 Hz on a line 1897, which Uber an inverter 1898 is coupled to a line 1899 and a NOR gate 1900, whereby the servo reference signal at 60 Hz is generated on line 1901. That The output of shift register 1888 on line 1897 continues to be in a dividing by 2 flip-flop 1902 is fed, whereby on a line 1903 a signal with a frequency of 30 Hz is generated, from which on a line 1904 the in-phase head switching control signal is generated.

If a color image signal is detected on line 1906, then a flip-flop 1907 set, which blocks the first NOR gate 1895, which also the deletion of the divider and shift register is locked, so that later on a shifted color image signal appearing on a line 1908 via the second NOR gate 1895 delivers the extinguishing pulse. Therefore, it is not the final count, but the shifted one Color image signal the shift register and the flip-flops back to 0. So that can Servo reference signal set correctly at 60 Hz relative to line feeds where the line shifts are required to accommodate the video information the correct one for playback and transfer operations in the sense described above Location owns.

That through the preamp circuit (Figs. 54A and 54B) for one revolution of the disk stack while the heads are switched from playback to recording via the transistor 1889 and the register 1878 on a line 1889 ' Head shutdown signal is clocked when the index pulse occurs on line 1872, when the register 1873 is in the record switch state.

The remaining part of the timing generator circuit shown in Fig. 38B is generated the timing commands used when performing the recording sequence will. The servo signal provided on line 1901 by the circuit of Figure 38A with 60 Hz switches on together with a synchronizing signal on a line 1953 NAND gate 1909 effective, its output signal with the shifted color image signal is ORed on a line 1936 by a NOR gate 1910, creating a register 1911 is set, which is an input signal for a shift register 1913 assigned NAND gate 1912 supplies. The NAND gate 1912 is switched through, when register 1911 is set together with shift register 1913, where the shift register 1913 carries a signal with a low level at all outputs. if If this is the case, the servo reference signal present on line 1897 is clocked with 60 Hz the shift register, with all output lines 1914 signals with high Lead level, which for the realization of the signal sequence required for a recording can be given to different logical gates.

Record ready signal present on line 1915 is generated when a NAND gate 1916 is switched through, which is the case when certain conditions are met. For this purpose the relays must be in the recording position stand, there must be a ready signal, a line for a control or Access deactivation reset must not be activated, the Disc stacks have the correct rotation phase and synchronization must be all right. When these conditions are met, the record ready signal becomes generated. Accordingly, a NAND gate 1917, which is a recording signal for the next image, a register 1918 is generated when certain conditions are met are. There must be a signal for correct synchronization, it a record command for the next picture must be supplied, the Relays are in the recording position, the timing from the shift register must be 1913 and there must be a signal for the correct setting of the stack of discs to be delivered. Register 1918 is set if these conditions are met and generates a recording sequence signal on line 1919. The registry 1918 is reset after passing four fields through the shift register 1913 are clocked and by resetting a recording sequence completion signal is generated on a line 1920. A pre-recording signal is made by a register 1922 generated on a line 1921 which has a duration of two fields. This Register 1922 becomes two fields earlier than the record sequence register Reset in 1918. During the pre-recording interval, the black level signal becomes recorded at the first two revolutions of the sequence of 4 revolutions, wherein the sequence of 4 revolutions in the present device as described above for recording is used by two fields of video data. It should be noted that the Register 1918 and 1922 can be set simultaneously. One generated on a line in 1923 Data timing pulse is exploited in the data track circuit when the record / playback relay is switched at the end of a recording frequency with 4 fields. This Pulse has a duration of one field and occurs during the last field the recording frequency of 4 fields. The data tracking provides a head shutdown signal to the preamplifier circuit (Fig.

54A and 54B) to block the head stream after the sequence if the record / playback relay is switched.

Timing generator for disk drive units in the circuit diagram The timing generator shown in FIG. 39 generates the signals for the timing functions the disk drive unit including the function of the servo system, so that the disk stack rotation during recording and playback in phase on the TV signal is obtained. The circuit uses the one supplied by the signal system Multiplex sync signal made up of narrow pulses with horizontal frequency as well a color image signal represented by three wide horizontal frequency pulses is formed for every fourth television field. This multiplex sync signal is used to generate an output signal with a horizontal frequency as well as a color image output signal, which is the basic impetus for the timing functions of the disk drive unit acts. The shifted color image signal produces the basic one among other functions Phasing of the servo reference signal, so that this servo reference signal when carried out a recording operation with the vertical sync of the one to be recorded Video signal coincides. However, if a reproducing operation is performed, so the servo reference signal is shifted so that the television signal is shifted by a period of time of two television lines is shifted by the delay of two television lines to compensate, which occur in the playback cells 91 of the device.

Specifically, the time base correction part effects the decoding and time base correction circuit 100 Each playback channel 91 has a delay of one television line during playback, wherein the ram filter and chroma inverter circuit 101 also tedes the playback channel causes a delay of one television line. When playing back the video information occurs at the output two lines later with respect to their target position, where the Position of the servo reference signal is set accordingly so that the video information is advanced by two lines during normal playback. However, it will be a transfer operation executed, i.e. a still information image is carried out from a stack of slices 75 is transferred to another stack of discs, the playback channel des Device only a delay of one TV line, because the information only the decoding and time base correction circuit 100, but not the comb filter and Chroma inverter circuit 101 passes through. Since in a transfer operation, the there is no delay caused by circuit 101, the situation becomes of the servo reference signal advanced by one television line so that it is with a vertical sync pulse recorded coincident with the sector 000 (index) on the other disk stack 75 will. The circuit assigned to the clock generator causes the shifting of the Color image so that the servo reference signal has the correct position.

Furthermore, the circuit generates a stable signal with horizontal frequency, due to significant noise levels or a possible lack of pulses is not noticeably affected in the multiplex sync signal.

In the circuit of Fig. 39, the multiplex sync signal is on an input line 1920 '. This signal has a horizontal frequency and contains the color image information in the form of three consecutive, at Broad pulses appear every fourth television picture. The multiplex sync signal is then converted from an ECL level to a TTL level by a converter 1921 ' and passes through an inverter 1922 ', the output line 1923' of which goes to a NOR gate 1924 '. The line 1923 'is still coupled to two AND gates, namely via an inverter 1925 to an AND gate 1926 and directly to another AND gate 1927. The lower signal path to the AND gates 1926 and 1927 is used for determination the presence or absence of information indicative of a color image.

The color image is generated by keying NAND gates via a monostable Multivibrator found in 1928, which gave a short pulse to activate the AND gate 1926 and 1927 supplies, so that the clocked pulses a counter Either increment or delete 1929. If there is a color picture, it doesn't AND gate 1927 performs three consecutive counts, creating a high Output signal is generated on two output lines 1930, which is stored in a shift register 1931 being loaded. If there is no color image, the three consecutive steps occur Pulses do not appear, so the AND gate 1926 due to the lack of either the second or the third pulse is switched through to clear the counter 1929. That Shift register 1931 is clocked by a 2 H signal on a line 1932, whereby the input signal is clocked through the shift register and onto lines In 1933, 1934 and 1935 successively high levels occur at 1 H intervals.

The timing of the signals on lines 1933, 1934 and 1935 causes the delays of one line, two lines, or three lines on a color image output line 1936 etnes Decoders 1937 (the delay of three lines is as an advance 0, the delay by one line as a shift forward by one line, and the delay defined by two lines as a shift forward by two lines). Two position selection control lines 1938 provide a binary input command to decode the signals on a of the input lines 1933, 1934 and 1935, being on the output line 1936 the basic shifted color image reference timing information for the recording timing circuit is produced.

The circuit continues to generate a stable horizontal frequency signal taking advantage of a phase locked loop with a voltage controlled oscillator in an integrated circuit 1940, which the sync signal from the NOR gate 1924 received via an inverter 1941, an AND gate 1942 and a line 1943. The output of the oscillator 1940 on a line 1944 is in a through 10 dividing counters divided in 1945, with a 2 H-Husgangssignal on one line in 1946 arises, which in turn in a counter dividing by 2 1947 to generate a 1 H signal leads on a line 1948, which is ultimately the output signal Horizontal frequency forms. The 1948 line is still on the phase comparator input of the circuit in 1940. The filtered error input signal for the voltage controlled The oscillator is carried on a line 1949 which is connected to a transmission gate Is docked in 1950. This gate always conducts when a multiplex sync signal is present on input line 1920. Via a line in 1951, a monostable multivibrator 1952 triggered, which for about three horizontal frequency Impulse goes high before flipping back. The high level is always present when the multiplex sync signal is present.

If the multiplex sync signal is not available and it also reverses does not return for three periods of the horizontal frequency, it takes an output line 1953 a deep one Level, which causes both the AND gate 1942 as well as the gate is closed in 1950. An inverter 1954 then becomes a another transmission gate 1955 activated, which is an artificial "error signal generated for the voltage controlled oscillator, which gives about the correct horizontal frequency is retained until the nultiplex sync signal is available again. One with its input is coupled to the phase comparator outputs of the circuit 1940 NOR gate 1956 generates a lockout indication signal which is a light emitting diode 1957 drives when the phase-locked loop is not locked to the correct phase is. A signal indicating the correct phase is generated on a line 1959. This is one of the conditions necessary for a recording operation.

The signal that indicates that the synchronization is OK, is generated when the servo system and the phase locked loop are on the right Function are specified.

These signals are applied to the inputs of a 1960 NAND gate.

Error checking logic circuit for disk drive unit The circuit diagram 40A and 40B shows error checking logic which in many respects the error checking logic of the existing disk drive circuit used for data processing purposes is equivalent to. In connection with the device described here, however, additional Error conditions occur so that the error checking logic can adapt to such Cases is modified. As described above, a Image of the video information requires two rotations of the disk stack. Therefore the position of the heads is changed when, as shown in FIG Management is given in 1975. However, since the change in the position of the heads of one Track leads to a discontinuity in the television picture, it is advisable to that the change in head position begins only during the vertical interval. Therefore, the search command is timed to relate to a specific location begins on the vertical frequency, which is fed in on a line in 1976. This means that a timed start search command appears on a line in 1977, which has the correct phase with respect to the vertical frequency. The vertical frequency signal is provided by the timing generator circuit shown in Fig. 39 and the recording timing circuit (Fig. 38A).

The part of the error checking logic according to Fig. 40B performs a check, to determine whether the recording stream has the intended behavior. if this current is turned on, it is checked to see if it is actually is switched on. After the shutdown, the circuit checks whether the shutdown also really happened.

If the specified condition does not occur, the can on the stack of discs existing data are at risk.

Specifically, a recording current test line 1978 is connected to a NAND gate 1979 and coupled to an inverter 1980, which has an input signal for a 1981 second NAND gate supplies. A recording sequence line 1982 is connected to the NAND gate 1979 and coupled to the NAND gate 1981 via an inverter 1983. Since the signal on the 1978 line actually indicates whether or not current is flowing Power is coming from the recording sources, the recording sequence line is said to be in 1982 carry a low level signal when current is flowing and a high level signal Lead level when the power is switched off. If a key signal occurs on a line 1984 on, one of the NAND gates in 1979 and 1981 delivers an activation signal on corresponding output lines 1986 and 1987, the corresponding flip-flops 1988 and 1989 sets. These flip-flops are coupled to a NOR gate 1990, the supplies a signal indicating unsafe conditions, whereby a statement is gained is that the data on the trail may be at risk. In this context shows the 1988 flip-flop indicates that current is flowing in the recording heads when it does not should be the case. The flip-flop 1989 provides an activating signal for the NOR gate 1990 when the recording head power is on but no power flows.

On a line 1992, a flip-flop 1993 clocking signal is included Horizontal frequency generated, said flip-flops having an output signal produce a 1994 line that samples the 1979 and 1981 NAND gates to determine that the recording current meets the target conditions. In other words is activated after switching off the recording power by pressing the Flip flops 1993 on the line 1994 one TV line later a signal with high level generated, which scans the NAND gate and determines whether the current behavior meets the target conditions is equivalent to. The key signal has the duration of a television line and begins one TV line after entering the command. The horizontal frequency signal becomes It is used because it ensures a reasonable amount of time to let the electricity flow can accept the new value after entering a command.

If an error condition occurs indicating that the heads have a misalignment so that they are not in the center of a recording track run, a signal on a line 2000 sets a flip-flop 2001, whereby a signal which activates a NOR gate 2002 is generated. This NOR gate then supplies a selection inhibit signal on line 2003, which the disk drive unit switches off because the data can be endangered by the existing conditions. The disk drive unit thus receives information that there is an error.

Disk drive interface circuit The in the block diagram according to 9B, data interface circuit 151 for the disk drive units serves to receive the video data from the encoder 96 as well as to the associated stack of discs 75 and for recording the video data read out from the associated stack of discs and to transfer the data to the selector switch 128.

For the transmission or reception of the ten data bits to or from two data interface circuits are provided from the disk stack 75, one of which only one is shown in FIGS. 60A and 60B. Data from encoder 96 becomes clocked from lines 2020 via AND gate 2021 to output lines 2022 and recorded on the disk stacking surfaces. The AND gates 2021 are replaced by a Recording sequence command activated on a line 2023, this Command generated by the recording sequence circuit shown in Figs. 38A and 38B will. Data taken from the stack of slices is passed over lines 2025 through AND gates 2026 clocked on lines 2027 when the AND gate 2026 has a signal with high level on a line 2028 are activated.

The signal on line 2028 is replaced by a high signal on line 2029, which is also generated by the recording timing circuit comes. If the line 2029 carries a signal with a low level, then a complementary one is generated Output buffer 2030 has a low level signal on line 2028 and a signal high on line 2031, thereby enabling NAND gate 2032 and a transmission of the data received from the encoder on the lines Enable 2027. This condition occurs with purely electronic ones and during search operations, with the signal passing through both the recording and playback electronics is processed and the recording step, however, is not performed. The data on lines 2020 are generated by an ECL logic with complementary levels transformed to level for a TTL logic before it is fed into the AND gate 2021 will. On the other hand, the data is on lines 2027 for transmission transferred from the level of a TTL logic to a level of an ECL logic.

Servo phase control for disk drive units In disk drive units for typical data processing equipment, for example in the above model DM 331 of the applicant, the motor drive for the disk shaft runs freely. To the to realize the desired servo control for the motor drive of the pulley shaft, the motor drive circuits are modified for use in the device described here.

The mode of operation of the motor driving the disk drive unit will now be described with reference to FIG. 36 which is a block diagram of a Circuit for controlling the drive motor for the disk drive unit shows with a phase control on the vertical sync signal in the sense of a correct one Adjustment to the clock is done so that recording, playback and transfer operations can be carried out with the correct timing.

The block diagram of Fig. 36 shows a circuit which serves to control the drive motor as well as for servo control. A detailed one Circuit diagram for the modified model DM 331 of the applicant for carrying out the Functions of the block diagram of Fig. 36 are shown in Figs. 41A and 41B. These figures show a phase lock circuit for the disk drive units. 59A and 59B show circuit diagrams of the logic and driver circuitry for the Disk drive motor, which is effective during the start-up of the disk drive motor is. According to Fig.

36 a three phase induction motor 2040 is running for the disk drive units via a three-phase alternating voltage from supply lines 2041, which via Relays 2042 are led to the motor and supply the motor with power until he ran up. After the Motor becomes the relay 2042, which is controlled by a motor run logic circuit 2244 via a winding 2043 , from lines 2041 to three-phase output lines of a switching inverter Switched in 2045. The inverter is generated from a DC voltage source via a line 2047 2046 is supplied with voltage, which is connected to lines 2041. The positional phase of the motor 2041 is derived from a servo read head 2049, which per revolution of the disk drive unit provides a signal to a preamplifier 250 whose Output signal is amplified by an amplifier 2051. A decoder circuit 2052 provides a pulse for sector 000 (index) of the disk, if it is once occurs per revolution. This pulse is fed to a phase detector via line 2053 Fed in in 2054.

The phase of the index pulse is increased with the vertical sync signal a line 2055 at the input of the detector 2054 compared, whereby on a line 2057 an error signal is generated which, in terms of phase, is determined by a phase compensation network 2058 compensated and then fed into a voltage controlled oscillator 2060 is to get the frequency and phase of its output signal as a function of the error signal to adjust. This output signal adjusted in terms of frequency and phase of the oscillator 2060 is fed into a logic circuit 2061 via a line 2087, which controls the three-phase switching inverter 2045. That way the engine can 2040 are servo-controlled in such a way that an associated index position for the driven Disk drive units is set to the vertical sync signal that is either from a station reference for playback or from a video input signal for recording is derived.

According to the circuit diagram specifically shown in FIG. 59B, after the turn on of the drive motor 2040 as a function of a motor run command on an input line 2065 from the disk drive control circuit and after the motor has started up generates a signal from the pulley drive control circuit on line 2066, which is clocked by a NAND gate 2067 and a monostable multivibrator 2069 controls, which has a time delay of about 4 seconds. After this With a delay of 4 seconds, the monostable multivibrator 2069 clocks a flip-flop 2070, whereby a command is generated on a line 2071, which the switching inverter 2045 turns on Clelchspannungsquelle 2046 supplying voltage. The output signal of the flip-flop 2070 is after clocking with a power supply verification signal also put on a line 2072, via which a monostable multivirator 2073 is triggered, which has a delay of about 50 milliseconds. To the tilting phase of this non-stable multivibrator 2073 a flip-flop 2074 is clocked, which supplies a signal on a line 2075 to short-circuit a resistor of 50 Ohe, which to protect against jumps during the switching period in series with the inverter lies. A signal on line 2072 'provides the command to operate the relay 2043 for switching over from the lines 2041 to the switching inverter 2045. Via the Output line 2075 is another raronostable multivibrator 2076 with a Delay of 40 milliseconds and then a flip-flop 2077 clocked, which provides a signal on an output line 2078. This creates a resistance of 10 Oh short-circuited, which is also in series with the inverter and the same Function as the resistance of 50 Oh outputs.

Referring to Fig. 59A, the voltage leakage phase relation is detected and on a line 2080 which is fed to a voltage controlled oscillator 2081 is coupled. That Output signal of this oscillator a line 2082 is fixed to the phase of the voltage line, so that at Switching from the voltage line to the inverter which is carried out by the inverter to the The voltage supplied to the motor is synchronous with the phase of the voltage line. In order to there is no significant interruption. The output signals of the voltage controlled Oscillators 2081 and 2060 (see Fig. 41B) are coupled via a gate circuit, which is the appropriate output to the three phase logic circuit 2061 as a function the operating condition of the disk drive unit. For example owns the signal on line 2082 has a frequency of 720 Hz (12 x 60 Hz) which is about a NAND gate 2083 an OR gate 2084 and a line 2086 into a ring counter 2085 is fed, whereby on six lines 2087 square-wave output signals with a frequency of 60 Hz, each at 30 ° to each other are shifted in phase. This means that the signals for phases A, B and C are used Control of the switching inverter 2045 gained (not shown in FIG. 59A).

The outputs of three phase logic circuit 2061 are over Optocoupler fed into the switching inverter as control signals. The NAND gate 2083 clocks the output signal of the oscillator 2081 into the ring counter, if on a line 2090 has a high level signal. It's on the line 2090 a signal with a low level, an inverter 2091 switches a NAND gate 2092 effective in order to continue clocking pulses from a line 2093, which are passed through the voltage-controlled Oscillator 2060 (see Fig. 41B) can be supplied with a frequency of 720 Hz.

41B, the voltage controlled oscillator 2060 and the Frequency / phase detector 2054 contained in a single integrated circuit, which receives the input reference signal via line 2055 and the feedback signal the Line 2053 for detector 2054 receives. The error output signal from detector 2054 on line 2057 is transferred to a storage capacity 2095 and via an operational amplifier 2096 for impedance matching to the phase compensation network Given in 2058. The network 2058 prepares the error signal generated by the detector 2054 for feeding into the oscillator 2060. The reference and feedback signals on the line 2055 or 2053 for the frequency / phase detector 2054 is through the Generates circuit shown in Fig. 41A, which via a line 2100 the pulses for sector 000 (index). The index pulses are transmitted through a voltage transformer 2101 shaped to produce narrow pulses on a 2053 line with the correct voltage levels for the following logic for feeding into the detector 2054. Corresponding the reference vertical pulses are on line 2103 through a voltage transformer 2104 formed and fed into a monostable multivibrator 2105, which with a subsequent monostable multivibrator 2106 cooperates in order for a Time period of about 8 milliseconds to prevent the occurrence of a second pulse. An output line 2055 of the monostable multivibrator 2106 provides the reference input signal for the detector 2054. The monostable multivibrator 2106 causes a delay of 5 microseconds and controls a switch 2107 to turn it on during each vertical pulse turn on for 5 microseconds. This creates an offset of 5 microseconds, which improves servo control by eliminating jitter effects, which occur when the index pulse (pulse for sector 000) and the reference pulse are coincident. Line 2108 is to capacitance 2095 on the phase detector output line 2057 coupled, which controls the oscillator 2060. An exit line 2055 of the monostable multivibrator 2106 is on a further monostable multivibrator 2110, which causes a delay of 2 milliseconds and on a Line 2111 generates an output signal which is passed through a differentiation stage 2112 differentiated and via a line 2115 and an inverter 2116 to NAND gates 2113 is given. A monostable multivibrator triggered by the index pulse 2117 creates a 4 millisecond window, i.e. a high level signal a line 2118 for the NAND gate 2113 and a low level signal a line 2119 for the NAND gate 2114. If the one appearing on the line 2115 Pulse within the window generated by the monostable multivibrator 2117 of 4 milliseconds initially drops, indicating that the two signals are already closely phase-related, the NAND gate 2113 sets a register 2120 and activates a monostable multivibrator 2121, whose output line 2122 is led to a NOR gate 2123. The output of this NOR gate 2123 closes a switch 2124 which supplies a voltage from a voltage divider 2125 on line 2108 for the capacitance, thereby increasing the time constant and the gain characteristic usually loop is changed to speed up the phase adjustment. The monostable Multivibrator 2121 closes switch 2124 for a period of approximately 10 milliseconds.

Via the output line 2055 of the monostable multivibrator 2106 a monostable multivibrator 2127 is still triggered, which has a delay of 15 microseconds, with a differentiation stage 2128 in the trailing edge one given to a NAND gate 2129 Signal a narrow one Impulse generated. The further input of this NAND gate 2129 is from a monostable Multivibrator 2131 supplied, which is triggered by the index pulse for sector 000 the line 2053 is triggered. This monostable multivibrator 2131 generates a window of 30 microseconds, which one pulse on a line 2130 for of the NAND gate 2129 is prevented, the phase definition is within + or - 15 microseconds is reached, a monostable multivibrator 2132 also generates a relatively long time delay of one second, an output signal with a low Level on a line 2133. This indicates that the phase for the servo control is set, i.e. the approximate time cycle of the motor relative to the reference vertical synchronous signal is guaranteed.

Computer Control System Flow Charts Figures 63A through 63VV show Flow charts for the operation of the computer control system and describe the various Programs for performing the operations outlined above. Subsequent Tables I and II also give a list of terms which used in the flowcharts. Thus, an understanding of the flowcharts is intended to be suffocated. Certain terms of the flowcharts, which are used in the tables I and II are not included, are standard terms for the DEC microcomputer used here or conventionally used terms.

Table I APLCLC: Calculation of the bit position to form the mean Image level in the channel.

ASEMBL: put together a subroutine.

ASLR2: Arithmetic shift to the left.

ASMCLR: Compile Clarification Program.

ASMCMP: Compilation complete.

ASMCYL: Running track number for compilation.

ASMDRV: Drive unit number, compiled on the drives will.

ASMEOL: Indicator of the end of the list for compilation.

ASMPAK: put together stack numbers.

ASMSTA: First data word number of the compilation.

ASPNXT: Reference address to the next memory location for AAP input.

AUXCLC: Calculation of the input buffer position for a running remote input device.

AUXDSP: Storage area for the content of a special remote input device display.

BCDIK: Reference address for the binary coded decimal 103.

BCDTBI: Converter program for binary coded decimals in binary form.

BIT: Mnemonic code for bit test (PDP-11 assembly language).

BITBCD: Converter program from binary code to binary coded decimals.

BUFDRV: Driver number for buffer stack.

BUFFER: Subroutine for video data buffer.

BUFPAK: Batch number used for buffers.

BUSERR: Restart of the subroutine for CPU time block or impermissible address jump.

CHAVAL: Channel available.

CHCHNG: Identifier set to display a new channel coming Drive unit.

CHItUS: Test program for a channel in use.

CHINVO: chroma inverter shutdown program.

CHKRPT: Error checking program for drive unit.

CHRCLC: Calculation of the bit position to trigger the chromainversion in a channel.

CHSTAT: Channel status positions.

CMND: command.

CYLNEW: Drive unit is looking for a track number.

CYLOLD: Track drive unit is switched on.

DECFLG: Indicates that the data word number has been decremented.

DEFINE: initial batch subroutine.

DEVCHK: Drive Unit Test Analysis.

DRINUS: Drive unit availability check.

DRPSEL: Drive unit deselection program.

DRVERR: Drive unit error reporting program.

DRVID: Batch number as a function of the drive unit table.

DRVTST: Temporary position for playback drive unit number at Transfer.

DSKCYL: Track number read from the data track.

DSKEOL: The last track read was the EOL track.

DTREAD: data track reading program.

DUPCYL: track number doubled.

DUPPAK: Batch number doubled.

DUPVID: doubling of the operating mode identifier.

DVCLC: Calculate the bit position of the input in the digital system Data word.

DVERR: Address to the driver error message.

DVTMP: Temporary drive unit number digit.

EOLTST: End of list test.

ERRCLR: Subroutine for sending blank messages.

ERRDT: Error code when reading data tracks.

ERRDTP: Display of the number of incorrect batch numbers read from the data track.

ERRNUL: Reference address for the blank message.

EXEQ: Jump to correct program for remote input device.

FAIL: Reference address for the test "incorrect operation".

FLGAUX: Identifier for active auxiliary input device.

IDDTR: Identifier set during batch identification.

ILEGAL: Subroutine for printing "not allowed".

ILLGL: Reference address to text not allowed ".

KBAUX: Indicates that auxiliary input device is active.

KBERR: Remote input device sends out incorrect message.

KBMOD: Indicator for the display that the remote input device is in keyboard operation is working.

KBSTR: Remote input device operates in sequence listing mode.

KEYQRY: Subroutine for printing "Key?".

MODREF: Illumination of the remote input device mode button when switched on Tension.

MUTFIN: Termination point for the fade-out and APL program.

MUTYP: constant which triggers black level fade-out.

NULL: Reference address for the sequence of spaces.

NXT: Reference address for the next step ".

OCUPYD: Note address for owns.

OFLFLG: Set flag when batch is off-line.

OFLINE: program for off-line printing ".

OFLN: Reference address for "off-line".

OUTSW: Storage location for data to be sent to the signal system.

OUTSWI: Storage location for data to be sent to the signal system.

PC: program counter.

PGM: program.

PNTCLC: Calculation of the input buffer position.

PRCYL: Track number of the current search.

PROTEK: Indicates that the track is protected.

PRPAK: Batch number for the current search process.

PSI: list data word number.

PSMPNT: Note address for data word list.

PSMST: Starting point in the list.

QPNTR: Current position in que stack.

QSRV: Program for Ques Service.

OSTK: memory block for ques.

PAMDAT: Reference address to the memory block for data track information.

RASCLC: Program for calculating the position in the table for current Remote input device.

RASDSP: Program for sending messages to the remote input device.

RASFMT: Program for obtaining and generating input data for storage.

RASPNT: Reference address for the beginning of the input memory.

RASSTR: Format-compliant remote input device input.

RASTYP: Reference address for remote input device status table.

RCBT: Abort the recording program.

RCINIT: Display the initial text.

RECDUN: Completion of the program for the current data word.

REAL: Program for printing "incorrect operation".

RECSBI: Secondary entry point for recording program.

RECTRY: New counter attempt for new recording.

REREC: Code set in the event of incorrect recording.

RPTOFL: program for printing off-line ".

SEEKA: Secondary entry in search program.

SELLOK: Program for printing Sellock ".

SPNXT: Next data word to be reproduced.

SPRTIM: display and service program for drive unit on-line again.

SPSTRT: First data word in the sequence to be reproduced.

SRCCYL: Track number for source drive unit of a still picture in compilation.

SRCDRV: Drive unit number of the source drive unit in compilation.

SRCPAK: source batch number in compilation.

SSSW1: Output register for signal system.

SSSW2: Output register for signal system.

STINIT: Program for Printing ITM "on display in listing mode.

STRCLC: Calculation of the position in the RASSTR table.

SYSERR: Information address for text SYS ERR ".

TEMPZ: Temporary position for general purposes.

TRKDEC: Decrementing the track number in the input buffer.

TRKFB: Program for sending track digits for display.

TRKINC: Incrementation of the track number in the input memory.

UNAPL: Program for channel shutdown for APL operation.

ZSEEK: Indicator for zero search.

Table II AAP: Input Mapping Field AMDSEQ: Loading Pointing Address data in the display and for input data are fed back in register 3 for digits from remote input device to input buffer.

ASPNL: assignment field.

AUXCLC: AXP formally bound data storage calculation.

AUXFLC: AXP-selected flag.

AUXSTR: AXP formally bound data storage.

AVAIL: channel available.

AXP: auxiliary input device.

BIZZY: system working status.

BMDSEQ: Loading of reference address in register 3 for digits returned Data in display and for input data from remote input device in input buffer.

BRINIT: Trigger display of playback data request.

BULK: Search and record or delete on special cylinders greater than 65.

BULKI: deletion process.

CALC: calculation.

CHAR: sign.

CHNVI: Chromainverter control program.

CLR: delete.

COMMA: Teletype comma key pressed.

CYL: cylinder.

DEC: Decrement.

DELT: delete.

DFINIT: Triggering display of batch definition data request.

DIGSWO: Selection of drive unit for channel.

DMDSEQ: Loading of reference address in register 3 for digits returned Data in display and for input data from remote input device in input buffer.

DPINIT: Trigger display for data duplication request.

DPLY: display.

DRAVAL: Drive unit program available.

DRIVID: drive unit.

DRPSEL: Deselecting the currently selected drive unit.

DUPE: Double up.

DVCLR: Drive unit is working.

DVSLCT: Drive Unit Selection Program.

DVZKEF: Sending playback reference to the drive unit.

DVZVID: Sending video input reference to the drive unit.

ECHO: sending requested data.

EDTEOL: Output of the end of the list.

EE: Purely electronic operation.

EEINIT: Triggering of display of purely electronic data request.

EMDSEQ: Loading of reference address in register 3 for digits returned Data in display and for input data from remote input device in input buffer.

ENDSEQ: Indicator for the end of sequence playback.

EOL: end of list.

EOLFLG: EOL flag.

ERASE: Erase record on cylinder.

ERS: Delete.

FMT: format.

FRSTRK: Search and record on the first available cylinder.

IDCYL: Identification of the current cylinder.

IDDRV: Identification of the memory location of the current cylinder.

IDENT: Stack and cylinder identification.

IDPACK: Identification of the storage location of the current batch.

IMDSEQ: Loading of reference address in register 3 for positions returned Data in display and for input data from remote input device in input buffer.

INC: increment.

INIT: trigger.

INTOFF: Switch off interruptions.

INTON: Interruptions effective.

INTR1: interrupt return one.

INTRET: interruption return.

INTRFC: interface circuit.

ITM: data word.

INERT: cylinder number display.

KBDRST: Keypad return program.

KD: key pressed.

KYBD: keypad.

LSTCLR: Deletion of display positions 30 to 32.

LSTFLG: Indicator for the end of sequence playback for lists / list operation.

MODIT: Company identification program.

NEG: Negative.

NTRFRST: Entry of the first trip.

OCCDIR: Busy address list.

OFLTST: Checking program for requested batch on-line.

ONLINE: Requested batch on-line.

PAINIT: Triggering display of sequence composition data request.

PB: playback.

PLASUB: Subroutine for playback commands.

PLSMIN: plus or minus.

PLUS: Most significant bit Not 1.

PMDSEQ: Loading of reference address in register 3 for digits returned Data in display and for input data from remote input device in input buffer.

PNT: reference address.

PNTRST: Resetting the information address program.

PRTFND: Localization of the position of cylinder identification in OCrDIR.

PRTSET: Setting of "occupied" bit in OCCDIR.

PSI: Playback of sequence data word.

PSINIT: Trigger display of sequence playback data request.

PSL: Playback of sequence list.

PSM: Playback from sequence memory.

PSP: sequence playback.

PSPLOC: Storage location for PSPSTR / PSPSTA pointer.

PSPMOR: Replay from sequence memory.

PSPSTA: AXP sequence playback cylinder point.

PSPSTR: RAS sequence playback cylinder position.

QSRU: Process Service Requirement List.

QUE: service request list.

R: Register followed by its number.

R3, 1678: Triggering a pressed key without first selecting one Operating mode.

RAS: Remote input device or device's own input device.

RASIN: remote input device input buffer.

RASRCV: Remote Input Device Interface Data Register.

RASRST: Interrupt activation for interface switching from remote input devices.

RECGO: Initiate the recording process.

RECRET: Return from the recording process.

RECSUB: recording process.

REINIT: Triggering of display of recording data request.

RETURN: Display wRTN ".

RMDSEQ: Loading of reference address in register 3 for digits returned Data in display and for input data from remote input device in input buffer.

RPT: repeat.

RST: reset.

RT: program (routine).

RTN: Return.

RTS PC: return from subroutine.

SEQ: sequence.

SEQDEL: deletion of special working cylinders.

SP: batch pointer.

SPACE: Teletype space bar pressed.

STORIT: Data on RASIN.

STRINIT: Display "ITM" program.

SRV: service program.

SUB: subtract.

SW: switching.

Status word register.

SYS ERR 1: Batch number in OCCDIR for wrong drive unit.

TGCLR: Switching off the drive unit for receiving commands.

TGSUB: Activate the drive unit to receive commands.

TRKRPT: Displays the number of the current cylinder.

TSTJPM: Direct return to INTRET program if errors in the preceding Program occur.

TSTRTN: Direct return to the call program of subprogram 4 if error occur in search operation.

UNMUTE: Switching off the fade-out.

Claims (14)

Pat entansrUc he @ recording and reproducing device, in particular for recording and playing back video information on or of magnetic media, characterized by generally circular Disc devices (75) with a plurality of generally flat disc surfaces, on which a magnetic recording and of which a magnetic reproduction is feasible, a variety of transducer arrangements for magnetic recording and rendering on and from the disk surfaces, 3 being the disk surface a transducer arrangement is assigned, and by signal processing circuits (93 to 97, 151 in Fig. 6 and 93 to 103 in Fig. 7) for transferring a field of an analog video information signal into a plurality of digital signal components and for feeding the digital signal components into certain converter arrangements for the purpose of simultaneous recording of each digital signal component on each a separate disc surface as well as for simultaneous playback of the digital Signal components from the separate disk surfaces and for combining those reproduced digital signal components back formed fields of the analog video information signal. 2. Electronic time base correction circuit for a device according to claim 1 for the correction of time base errors in digital data, which have their time reference Containing defining component, identified by a multiple register (568) with a multiplicity of data storage cells connected in series, with a data input and a data output as well as write clock and loose clock connections, in which received Digital data as a function of the write clock and reading set connections given clock signals successively in the data storage locations connected in series can be stored, a source (571) delivering stable clock signals, a stage (572) for generating a data clock signal that corresponds to the data time reference defining Component is coherent, stages (569, 570) for coupling the stable clock signal and the data clock signal to the multiple register (568) for the purpose of writing and Reading out the digital data into or from the data storage cells, the digital data be supplied at the data output with a repetition frequency that corresponds to the time reference defining component is coherent, the digital data from the data output of the Multiple registers (568) receiving circuit (582, 583, 616) to determine the time base error contained in the received digital data, and by a die Accepts and passes digital data from the data output of the multiple register (568) the error detection circuit (582, 583, 616) controllable delay stage (621) for Delay of the received digital data as a function of the detected time base error to compensate for this error. Circuit arrangement for a device according to Claim 1 for transmission a digital data sequence over a transmission channel in which due to a different Transfer characteristic for jumps in different directions between two signal interference can occur at logical levels, indicated by a Circle for generating a pulse of short duration for each level change in the data sequence, a circle (1019) for converting the pulses into a pair of pulses with complementary Level, with each pair of pulses for continuation on separate lines (1052, 1054) is given stages coupled to the lines (1052, 1054) (1055, 1056) for generating a level jump on a single line if the Level on the lines during a level jump of the pulses with complementary Level is the same, whereby the pulses are regenerated, and by a stage (1057) for generating a level jump as a function of a jump in a first Direction of the impulses. 4. Circuit arrangement for a device according to claim 1 for selective Insertion of a digital synchronization word into at least one digitally coded word Data sequence that is clocked into an input at a specified frequency and which appears at an output with selectively inserted synchronization words, wherein each data sequence has an information content, the at least one digital component of a composite video signal, and wherein the video signal represents a Color subcarriers, a horizontal blanking interval associated with each video line, and has a vertical blanking interval separating successive video fields, characterized by a controllable generator (459) for a multi-bit synchronous digital word, which can be inserted into the data sequences to identify alternating lines, a Switch (453) which, when switched to a first operating state, is used to delete the Information content in the data sequence is used without affecting the flow of the input (450) given data sequence is stopped, a subcircuit (e.g. Fig. 14) to operate the switch (453) to delete the information content in at least a portion of the data sequence in a first period of time every other one of the successive horizontal blanking intervals and for activation of Synchronous word generator (459) for the purpose of inserting the synchronous word into the data sequence for a first time period in every other of the consecutive Horizontal blanking intervals, and by a sub-circuit for operating the switch (453) for the purpose of deleting the information content in the data sequence for a second Period of time in at least a part of the vertical bus sampling interval, which extends over several successive horizontal blanking intervals lasts. 5. Circuit arrangement for a device according to claim 1 for keying a an analog information signal containing a subcarrier signal in precisely specified Phase points for the acquisition of discrete sample values, which the information content of the Represent the information signal in the specified phase points, labeled by a stage (95) for sampling the information signal for the purpose of generating a the signal representing the value of the information signal at the sampling time as Function of a clock signal fed into stage (95), a circuit (312, 317) for generating the clock signal fed into the sampling stage (95) for the purpose of sampling of the information signal in predetermined phase points of the subcarrier signal, one Phase control circuit (302) for controlling the phase of the output signal of the clock signal generating circuit (312, 317) by comparing the phase of the output signal and of the subcarrier signal for the purpose of generating a first error signal and feeding it in this first error signal in the cycle generating the clock signal (312, 317), to adjust the phase of the clock signal so that the output signal of the clock signal generating circle is set to the phase of the subcarrier signal, and by a circle (307, 307a, 308) for checking the discrete sample values and for generating them a second error signal, this is a measure of phase errors between the actual phase position and the target phase position of the sample values and that in the clock signal generating circuit (312, 317) is fed to the phase of adjust its output signal so that the second error signal has a value of assumes approximately 0, whereby the information signal in the precisely predetermined phase points is keyed with respect to the subcarrier signal. 6. Circuit arrangement for a device according to claim 1 for generation a square output signal with two levels for a change in phase successive video lines of a video signal with a horizontal blanking interval between successive lines and a burst in each horizontal blanking interval, with a switch from one level to the other in every second video line takes place in the output signal and wherein the output signal occurs during the burst signal always has the first level, identified by a circle (324) for generation a first syametric synchronized to the beginning of the horizontal blanking interval Reshtecksignal with a period of two video lines, so that the level of this first square wave signal changes in successive video lines, a circle (312, 316, 320, 322) for generating a second symmetrical square-wave signal with a period of two video lines, so that the level of this second square wave signal changes in successive lines, the second square wave signal generally synchronized with the first square wave signal, but is delayed such that a the level changes generally immediately after the color sync signal occurs takes place, and by a circle (325, 317) to combine the two square wave signals for the purpose of creating the rectangular Output signal that except in the event that the two square-wave signals have the second level, the first Level. 7. Circuit arrangement for a device according to claim 1 for readjustment the DC voltage level of a composite video signal with multiple periods of a chrominance subcarrier following the horizontal sync pulse in the horizontal blanking interval occur, marked by a circle for adjusting the DC voltage level of the video signal as a function of a correction signal fed into it, a the video signal when a control signal is fed in to determine the integrating circuit of the mean value of this signal and for feeding the correction signal into the Adjustment circle, and by a control signal generating circle, the presence of the horizontal sync signal and the control signal for a given Supplies time period in the presence of the periods of the chrominance subcarrier signal, wherein the predetermined time period of an integer number of periods of the chrominance subcarrier corresponds to (Fig. 10). 8. Circuit arrangement for a device according to claim 1 for regression at least one full four-field color television sequence from a recorded one Information with images formed by two fields, where the information keyed into at least one digital data sequence with a predetermined one, an odd one Multiples of the chrominance subcarrier frequency transmit the same data repetition frequency and recorded on a recording medium characterized by a transducer arrangement for reproducing the digital data sequence from the recording medium (75), one Processing circuit (Fig. 7) Mir the digital data sequence and for clocking the Data sequence with a phase-continuous signal with a specified data sequence frequency, a circuit for generating the phase continuous clock signal and for inversion of its phase as a function of a received phase reversal signal, and by a Circuit for identifying alternating video images and for generating the Phase reversal signal in successive reproductions of the recorded image with two fields. 9. Circuit arrangement for a device according to claim 1 for processing an analog color video information signal for recording on a magnetic one Medium in terms of the possibility of an exact reproduction of the signal by a circuit (93) for separating the horizontal sync pulses from the analog color video information signal, a circuit (95) for keying the analog Color video information signal and for converting the sample values into at least one digital data sequence with a predetermined data sequence frequency, which is a multiple is the chrominance subcarrier frequency, and by a circuit (96) for insertion a unique digital sync word in the horizontal blanking interval in at least every other one of consecutive video lines, the sync word is synchronized with the chrominance subcarrier so that the phase increase slope is constant between the sync words and the auxiliary carrier. 10. Circuit arrangement for a device according to claim 1 for the protection of on a plurality of rotating flat circular recording surfaces one Disc drive unit recorded information signals against overwriting by Transducer assemblies, the disk drive unit at Occurrence of a danger signal is switched to ineffective, indicated by a first input circuit for receiving a command signal indicating whether the transducer arrangement is in the recording mode or not in the recording mode is located, a second input circuit for receiving a status signal that indicates whether the transducer array is recording or not, a circuit for generating a key signal at predetermined times, and by one to the first and second Input circuit and the circuit that generates the key signal for generating the danger signal when 1. the key signal is received, the command signal indicates that the transducer arrangement is in the recording mode and the Status signal indicates that the transducer arrangement is not recording, 2. the key signal is received, the command signal indicates that the transducer array is not in Recording mode is and the status signal indicates that the transducer arrangement records. 51. Arrangement for an apparatus according to claim 1 for recording and reproduction of video information and to prevent certain operations in order to minimize them the possibility of undesired destruction of parts of the recorded information by an operator, characterized by disk drive units (73), into the disk stacks (75) with a plurality of flat, circular, recording surfaces Possessing disks can be used and set in rotation, and the transducer arrangements for recording on and for playback from the disks, characterized by a device for moving the Wendler arrangements on the disk surfaces in predetermined radial positions with respect to the center of the Discs, each fladial position defining a separate track in which one Recording or from which a playback can be made, with each disk stack t75) has a large number of tracks, some of which are fixed and a other part is defined as working tracks, a circuit for identification of tracks occupied by information, a circuit for controlling the recording on or the reproduction of the tracks by the transducer assemblies, the recording is prevented on an occupied fixed track in the absence of a control signal, and by a circuit for generating the control signal to enable recording on an occupied fixed track. 12. Circuit arrangement for a device according to claim 1 for generation an output signal that is self-clocking at a first frequency Data pulse train is phase synchronized, characterized by an oscillator (358) to generate the output signal, the frequency of which as a function of a a control input of the oscillator given voltage level is variable, a circuit (354a, 355a, 356) coupled to the control input of the oscillator (358) for supplying a voltage level as a function of a charging current, a first Circuit (351, 351a) for generating a charging current for the to the control input of the Oscillator coupled circuit, this first circuit in the absence of a data pulse supplies a predetermined constant current value, the oscillator thus on the first Frequency holds and which is switched off in the presence of a data pulse, and by a second, coupled to the output of the oscillator and the data pulses receiving circuit (353, 353a) for generating a charging current for the circuit coupled to the control input of the oscillator, which generates a charging current with a given period, which supplies the oscillator on the first frequency holds when a given jump in the oscillator output signal is generally in the middle of the data pulses occurs, the period varying in the event that the jump occurs at a point deviating from the center of the data pulses, around the oscillator to be controlled in such a way that the specified period is formed back. 13. Digital chrominance separation and processing circuitry for one Apparatus according to claim 1 for digitally reproducing a composite color television signal from a selectively stored single color television picture or field signal, characterized by a digital filter circuit (701, 704) for separating the chrominance signal from the stored television signal, a digital circuit (705) for digital inversion of the separated chrominance signal with alternately repeated reproductions of the stored television signal, and by a combination stage (708) which the chrominance signal inverted by the digital circuit (705) with that of the separation the television signal subjected to the chrominance signal to restore the composite Color television signal combined. 14. Frequency equalizer for a device according to claim 1 for a recording and playback channel with non-constant amplitude characteristics and non-linear Phase characteristic, with a reproduced signal representing the temporal mapping of the recorded river is marked through a parallel connection an integrating low pass filter (1002) and a differentiating high pass filter (1003), which record the reproduced signal and output signals of the same size provide the opposite phase shifts of 90 ° with respect to the reproduced Have signal, and by a difference signal of the two output signals supplying stage (1005), the difference signal with respect to the reproduced Signal is equalized in terms of phase and amplitude, so that an equalized Channel with constant amplitude characteristics and linear phase characteristics for all transmitted signal frequencies.