DE2737431C3 - Process for the digital clamping of pulse code modulated video signals - Google Patents

Description

summary

A method for digitally identifying pulse code modulated (PCM) video signals is proposed. According to the procedure, an arithmetic mean of difference values is formed, which in successive blanking intervals by subtracting the PCM video signal to be clamped from a predetermined target binary value can be obtained. The calculated arithmetic mean becomes that stuck PCM video signal in the active area of a horizontal period added as a correction value.

State of the art

The invention is based on a method according to the preamble of the main claim. It was already proposed (patent application P 26 28 662), from an actual binary value in the horizontal blanking interval to be clamped PCM video signal and a predetermined nominal binary value to a binary difference value determine which is added as a correction value to the PCM video signal to be clamped in the active area of a horizontal period. However, this method has the Disadvantage that with disturbed PCM video signals, z. B. those on which noise components are superimposed, quickly alternating changes in the clamping level occur, which lead to a »line-up« in the clamped image signal.

The object of the present invention is to provide a method for digital clamping of pulse code modulated Indicate video signals which does not have this disadvantage.

Advantages of the invention

The invention with the characterizing features of the main claim has the advantage that by the Formation of an arithmetic mean of difference values determined at different times "Time constant" is introduced, which in its effect is similar to that in analog clamping circuits.

The measures listed in the subclaims enable advantageous developments of the im Main claim specified procedure possible.

drawing

Further advantages and details of the invention are given below with reference to exemplary embodiments described and explained in more detail with figures in the drawing. From the figures shows

F i g. 1 shows a basic block diagram according to the invention,

F i g. 2 shows a block diagram according to a first exemplary embodiment according to the invention,

F i g. 3 shows a block diagram according to a second exemplary embodiment according to the invention and

F i g. 4 shows a block diagram according to a third exemplary embodiment according to the invention.

Description of the invention

In the figures, switching groups with the same effect are provided with the same reference symbols.

The in Fig. 1 shown block diagram represents a digital clamping step to reintroduce the lost

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It is assumed that the direct voltage reference in the PCM video signal connected to a terminal 1 has been lost due to an incorrect analog-digital conversion process between the actual binary values of the pulse code modulated video signal at terminal 1 and a nominal binary value ε -average The Γ, οΐΐ binary value is fed to the digital subtractor 2 via a terminal 3 According to the proposed method for clamping pulse code modulated video signals (patent application P 26 28 662), the binary difference value obtained at the output of the subtracter 2 is transferred to a register 4 in the area of the back porch. The correct time transfer into register 4 is carried out by controlling a horizontal-frequency clamping pulse signal fed to a terminal 5. The controller 4 consists of a 2 " bit binary coded video signal. ' for example from π memory flip-flops. By taking over the binary difference value at the register input, the difference value is stored for the duration of a horizontal period The clamped PCM video signal can be removed from the sum output of the digital adder 6 with terminal 7.

Compared to this proposed method, the subject matter of the present invention differs in the insertion of an arrangement 8 acting as a “time constant” between the output of the subtracter 2 and the input of the register 4. The arrangement 8 contains two digital dividers 9 and 10 and a digital adder 11 One input of the digital adder 11 is connected to the output of the subtracter 2 via the digital divider 9 and the other input is connected to the output of the register 4 via the digital divider 10. The division ratio of the two digital dividers 9 and 10 is not the same. While the division ratio of the digital divider 9 is 1: η , the division ratio of the digital divider 10 is (n ~ 1): n, where η is a positive number> 1. The “time constant” of the arrangement 8 becomes greater the greater η is selected.

If λ = 2 is chosen, this can be seen in FIG. 1 Simplify the block diagram shown (FIG. 2). In addition to the digital adder 11, the arrangement 8 contains only one digital divider 12. One input of the adder 11 is connected to the output of the Subtractor 2 and the other input connected to the output of register 4. The one at the exit of the adder 11 lying binary value is divided by 2 in the downstream divider 12 and the input of the register 4 ζ j led Since the correction value determined to \ or is at the output of the register 4 and at the output of the subtracter 2 the current difference value, is repeated arithmetic averaging in this embodiment

ίο made over the duration of a horizontal period. The invention continuously reduces interference in the PCM video signal to be clamped. It is assumed that the binary difference value determined by the subtracter 2 is shifted by the value A from a constant value during a line m of the noise components superimposed by the PCM video signal. During the lines following the line m , the determined difference value is again the constant value. Under this assumption, the digital adder 6 is supplied with different correction values, which are in the

Row m: 1/2 (4 + 2const)
Line m + 1: 1/2 (1/24 +2 const.)
Line m + 2: l / 2 {l / 44 + 2const.)

and

Line /77+/.;l/2(l/2M-l-2konst)

be.
In the case of the FIG. The block diagram of a second exemplary embodiment shown in FIG. 3, the difference value which can be taken off at the output of the subtracter 2 is also fed directly to an adder 11 '. The signal that can be taken off at the output of the adder 11 'is fed via a divider 12' to a series circuit 4 '- 4 * -' of & - 'registers. The signals that can be picked up at the outputs of the registers 4 'to 4 * -' are fed to other inputs of the adder 11 '. With k- 1 registers connected in series, the divisor of the digital divider 12 'is k. The correction value for the digital adder 6 is at the output of the register 4 '.

In the case of one shown in FIG. 4 of a third exemplary embodiment, the difference values calculated with the digital subtracter 2 are arithmetically averaged over k horizontal periods. For this purpose, similar to the embodiment of FIG. 3 instead of a register k registers are provided which are connected in series. The binary signals that can be picked up at the register outputs are added in the adder 11 'and divided by k in a downstream digital divider 12' and fed to the digital adder 6 as a correction value.

For this purpose 2 sheets of drawings

Claims (5)

Patent claims: 1. Method for digital clamping of pulse code modulated (PCM) video signals, characterized in that one during each Horizontal blanking interval of actual binary values of the PCM video signal to be clamped and one predetermined target binary value determined difference value with during other horizontal blanking intervals determined binary difference values is arithmetically averaged and that the through the Binary correction value obtained arithmetically outside the horizontal blanking interval is added to the binary values of the PCM video signal to be clamped. 2. Verfuhren according to claim 1, characterized in that, for the arithmetic averaging, the binary difference value determined during each horizontal blanking interval of actual binary values of the PCM video signal to be clamped and the predetermined nominal binary value is divided by η and added to that with (n— 1) : η multiplied correction value is added. 3. The method according to claim 1, characterized in that for the arithmetic averaging of the actual binary values of the PCM video signal to be clamped and the predetermined nominal binary value during each horizontal blanking interval, the binary correction values determined in k \ horizontal periods are added and then divided by k . 4. Circuit arrangement for implementing the Method according to Claim 1, characterized in that the PCM video signal to be clamped and the predetermined nominal binary value are fed to the inputs of a digital subtracter (2) that the output of the digital subtracter (2) is connected to the input of a digital adder (11), that the output of the digital adder (11) via a digital divider (12) that divides by two is connected to a register (4), which stores the information at the register input when it is available stores a horizontal rate clamp pulse for a horizontal period, and that the output of the register (4) with the other input of the digital adder (11) and with the an input of a further digital adder (6) is connected, the other input of which is connected to clamping PCM video signal is supplied and at its output a clamped PCM video signal is removable. 5. The method according to claim 1, characterized in that for the arithmetic averaging of the during each horizontal blanking interval of actual binary values of the PCM video signal to be clamped and the predetermined target binary value determined by a register (4 'to 4 ^k ) with horizontal frequency k register elements is shifted, the delayed difference values which can be taken off at the outputs of the register elements being added and divided by k to obtain the binary correction value.