DE2525084A1 - TELEVISION RECEIVER - Google Patents

Description

*] (Soaps

PHM 1001C

1 * 1.6.1975 JW / FK / VMAL

"Television receiver"

The invention relates to a fine

Vehempfänger with a voting circuit in which an exit one coupled to a mixer circuit of the receiver Oscillator and an output of a generator for generating a comb of reference signals via a Detection circuit are coupled to a · counting circuit, with the aid of said counting circuit a Signal for tuning the oscillator to a desired frequency can be obtained.

From IEEE transactions on BTR, Issue 16, No. 2, July 1969, pages 220-222 is a television receiver

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-Z- PUM 100 "· C

June 14, 1975

2 5 2 5 0 a 4

of the above type known. Either the Intermediate frequency of the receiver adjusted or a second Mixing stage used.

The invention now aims at another

To create a solution that avoids a different choice of intermediate frequency and a second mixer stage.

A television receiver of the type mentioned at the beginning According to the invention, Art is characterized in that the detection circuit is a matched detection circuit is, which is tuned to such a frequency that for a given intermediate frequency of the receiver and a given position of a spectrum of the received transmitter signals a correct tuning of the receiver is obtained.

If it is assumed that the transmitter frequency = f, then f. = a + x.f, where χ = a

t 'L ·' C

integer and f = .channel spacing. Now must:

f = a + x.f + f. ", where f." = intermediate frequency, eyelet. c Ii ι!

f = oscillator frequency.
eyelet ^

The comb generator generates a number of frequencies corresponding to the following vert: k.f, where k = an integer.

Now, in general, f - kf £ θ.

OSC C

If f, = f - kf is called, then d. eyelet c

609851/1004 originally inspected

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June 14, 1975

a + xf + f. - kf = f,. c if c α

When a detection arrangement was applied which is matched to f, a simple circuit arrangement is obtained according to the invention, where f, is preferably made as small as possible by the choice of k, so that the most precise possible matching to the desired frequency is made possible.

Instead of the usual aaf a phase detection effective control loop to maintain the correct one Tuning of the receiver after the desired frequency has been found, in which control loop the frequency difference f, can be compensated for again according to an elaboration of the invention, a frequency discriminator tailored to f · can be used will.

The invention will now be based on the drawing with the usual for an American frequency standard Examples explained in more detail. With the help of the formulas given above, in which a choice of the Oscillator frequency above or below the transmitter frequency can be taken into account can be simple Way, the frequency f is found for every case that occurs are matched to the detection circuit must become. With an intermediate frequency of ^ 5 j 75 MHz, a station classification according to European

609851/1004

- * h - ■ FHM 1O01C

■ \ h.6. 1975

Norm applied frequency-selective detection to 3 MHz with a suitable mirroring of the discriminator curve, all areas can be painted.

Show it:

FIG. 1 shows a block diagram of the basic functional areas of an automatic frequency tuning circuit according to the invention,

Figure 2 is a schematic block diagram of an arrangement with a preferred embodiment the invention,

Figure 3 is a schematic block diagram of a comb signal generator according to the invention,

Figure h is a schematic block diagram of V: h / : 6 circuits which are used in part of the comb signal generator according to the invention,

FIG. 5 shows a schematic block diagram of an arrangement for presetting counting circuits according to the invention,

Figure 6 is an illustration of a number of idealized waveforms which explain the operation of the present invention in tuning a television receiver to channel 2 through channel k;

FIG. 7 shows a representation of a number of idealized waveforms which illustrate the mode of operation of the

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June 14, 1975

lying invention be'im tuning a television receiver explain on channel 5 or channel 6,

Figure 8 is a representation of a number

idealized waveforms illustrating the operation of the present invention in tuning a television receiver to channel 8k through channel 91 and channel 7 through channel 13,

Figure 9 shows a number

idealized waveforms that explain the operation of the present invention when tuning a television receiver to channel Ik through channel 83,

FIG. 10 shows an illustration of idealized

Waveforms in several places a preferred Execution forms according to Figure 1 or Figure 2 occur, to explain the mode of operation,

Figure 11 is a block diagram of an electrical

niche automatic frequency tuning circuit the invention,

Figure 12 is a circuit diagram of a preferred embodiment of the arrangement that receives the input signal generated by the voltage controlled oscillator,

Figure 13 is a circuit diagram of a discriminator amplifier producing an amplified discriminator output signal generated in response to a first signal and an inverse and amplified discriminator

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1 * 1.6.1975

output signal generated in the absence of the first signal.

Figure 1 shows a block diagram of the

principal parts of an arrangement according to the present invention. In the preferred embodiment, the reference signal generator 11 generates a number of harmonic frequencies which are fed to the superimposition converter. At the same time, the oscillator control circuit 13 supplies the controllable local oscillator 12 with a signal which controls the frequency of the output signal of the local oscillator 12. The signal of the local oscillator 12 is supplied to the transducer 1 and h ¯ signal combined with the signal of the reference *. 11

An output signal from the converter 1h is then fed to the tuned amplifier 15. The amplifier 15 is tuned to an interference frequency or difference frequency f., Which arises from the combination of the local oscillator frequency signal and the set of harmonic signals from the reference signal generator. The output signal of the tuned amplifier 15 is fed to the interference detector 16 and to the discriminator 18.

An interference frequency signal becomes the output terminal of the tuned amplifier 15 is supplied. When the difference between the local oscillator signal and one of the harmonic frequency components of the genera-

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1 * 1.6. 1975

tors 11 from the frequency f. to which the amplifier 15 is matched, deviates. The interference frequency signal is fed to an interference detector 16. Of the Deiektor 16 generates a pulse when the interference frequency occurs and feeds this pulse to the counting and comparing circuit 17.

The counting and comparing circuit 17 contains circuit arrangements for counting the number of interference frequency signals, which are fed to the output terminal of the amplifier 15 and it contains circuit arrangements to compare this number with one stored in a memory part of the circuit arrangement 17 Number. The content of the memory parts of the circuit 17 is introduced by means of the frequency selection arrangement 19, which is also used to preset quantities in certain counting circuits. Upon a determination that the count of the interference frequency signal one in the S ^ attitude 17 introduced by the frequency selection arrangement 19 Number corresponds, the signal fed to the oscillator control circuit 13 is removed, which leads to a dependency of the increase in the frequency of the oscillator output signal leads. By energizing the arrangement 19, a signal is provided from the counting and comparing circuit 17 ensures that the oscillator control loop generates an output signal from the local oscillator with increasing frequency

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lh.6. 1975

testifies. At the same time, daejA.outputssign.al of the discriminator 18, which is fed to circuit 13, for regulating the frequency of the output signal of the local oscillator 12 used.

The discriminator 18 creates a frequency transition to the output signal of the tuned amplifier 15> whereby the network loop, which consists of the discriminator, the oscillator control circuit 13> the local oscillator 12, "the converter lh and the amplifier 15", "locks" on the interference frequency signal, which signal from the The combination of the local oscillator signal and the harmonic signal component of the generator results, which results in the last count of the circuit 17. The mode of operation of this type of automatic frequency control loop is known to the person skilled in the art.

Fig. 2 shows a preferred embodiment of the invention in a television receiver. One antenna 51 receives television signals and applies these received signals to an arrangement of the television receiver to. The antenna 51 could, however, also by a Connection to a cable television system or through another Replaced arrangement for supplying signals encoded from video channel frequencies to the television receiver unit will.

The television receiver input signal becomes

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June 14, 1975

an RF amplifier 52 and the output signal of amplifier 52 is fed to a superimposition converter 53 fed. The RF signal is in the converter 53 with that of a voltage controlled oscillator 4O derived Local oscillator signal "mixed". Since §A.output signal of the Converter 53 is fed to an amplifier 5 ^ (for example tuned to 45 j 75 MIIz intermediate frequency. is), and the output of the amplifier becomes 5 ^ the demodulator and the sound / image processing stage 55 fed.

To select a specific frequency or a specific channel, the difference between the / frequency of the selected channel and the voltage controlled oscillator 40 must correspond exactly to the intermediate frequency to which the amplifier $ h is tuned. Therefore, a separate output signal of the voltage-controlled oscillator ho is necessary to select a channel.

An output signal of the voltage-controlled oscillator h0 is fed to the superimposition converter 41. The signal from a reference oscillator 21 is fed to a harmonic comb signal generator 22. The generator 22 generates a comb signal with evenly distributed frequency signal components (for example in the frequency range), the gap being a har-

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June 14, 1975

monic of the output signal of the oscillator 21 is. The output signal of the chimney signal generator 22 is also fed to the converter k ~ \. A first and a second output terminal of the logic gate 32 are connected to the comb signal generator 22.

The output signal of the converter is hl

an IF amplifier 42 which is tuned to 1 MHz is. The output signal of the amplifier 42 is the interference detector 45 as well as the interference discriminator 44 supplied. The output of the discriminator 44 is fed to the reverse switching amplifier 58 supplied. The output of amplifier 58 wix "* d an input position of a two-position switch 57 supplied.

The interference detector 45 generates a pulse output signal whenever a signal with an interference frequency of 1 MHz is received from the output terminal of the Amplifier 42 is supplied. The pulse signal is fed to the counter circuit 23 and to a second input terminal of the logic gate 32. The counter circuit 23 counts the 'generated by the interference detector 45 Impulses.

A frequency is selected using

of a channel selector 27 · The selection can be made manually , for example by pressing a button, or

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June 14, 1975

with the aid of a remote control arrangement 29. The channel selection arrangement 27 is with the code converter 26, the monostable multivibrator 30 and with the video segment generator 28 connected. The code converter 26 is connected to memory circuits 25 and the memory circuits 25 as well as the counterscld device 23 are connected to the Comparison circuit 24 connected. The comparison circuit 24 is connected to the control voltage circuits 43.

The monostable multivibrator 30 is with

connected to a first input terminal of logic gate 32, with the counter circuit resetting arrangement of the counter circuit 31 and with the control voltage circuits 43 ·

The output of amplifier 54 becomes fed to the discriminator 34 and the output signal the discriminator 34 becomes a second input terminal of the switch 57 supplied.

The arrangement 33 for channel 5 and channel 6

is possible with the channel selector 27 as well as with the control voltage circuit 43 connected. The control voltage circuit 43 is connected to the voltage controlled oscillator 40.

Figure 3 shows the mapping of the reference signal generator 11 according to the preferred embodiment.

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June 14, 1975

A local oscillator 21 supplies the + h / + 6 divider circuit 60 with a 2h MHz signal. The circuit 60 also receives a signal at the terminal 68 and the supplied signal determines when the + h or the + 6 mode is activated. The output of the circuit ¹ 6o is supplied to a first input terminal of the logical AND gate 61st A second input terminal of the AND gate 61 receives a signal from an output terminal of the inverting amplifier 62.

The terminal 67 is connected to an input terminal of the amplifier 62 and to a first input terminal of the logical AND gate 63, a second input terminal of the logical AND gate 63 being connected to an output terminal of the local oscillator 21. A Aasgangssignal of the AND gate 61 is supplied to a first terminal of the logical OR gate 6h, while an output terminal of the AND gate 63 having a second input terminal of the logical OR gate is connected 6h. An output terminal of the OR gate 6h is connected to an input terminal of the comb signal generator 65. The comb signal generator 65 is an arrangement for converting a signal having a particular frequency and providing an output signal containing a number of signals having frequencies which are harmonics of the given frequencies. The output signal of the

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June 14, 1975

Generator 65 is available at terminal 66 .

In Figure h is part of the training

the + ^ / + 6-Teilerscliciltung 60 shown according to a preferred embodiment. The terminal 75 is connected to the clock input cycles of the JK flip-flop circuit 71 and JK flip-flop circuit 72. The Q and Q output terminals of the JK flip-flop circuit 71 are connected to the J and K inputs & terminals of the JK flip-flop circuit 72. The output cycle Q of the flip-flop circuit 72 is connected to the J and K input terminals of the flip-flop circuit 71. The ″ / h terminal is connected to a reset terminal of the flip-flop circuit 72, while the output terminal Q of the flip-flop circuit 71 is connected to the terminal 73.

FIG. 5 shows an arrangement for presetting the counting circuits according to the preferred embodiment. The arrangement, not shown, identifies a selected channel in at least one of the groups defined by Channel 5> Band III (Channels H-83), Band II (Channels 84-91 and Channels 7-13), Band I (Channels Zk) , and Channels 5 and 6 are designated. To identify the selected channel, a positive signal is applied to each of the lines that cooperate with each of the above-mentioned channel mips. The line assigned to channel 5 is with

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- PIIM 100IC

1 * 1.6.1975

a first terminal of the logical NOR gate 81 is connected. The line assigned to band III is connected to a second input channel of the logical NOR gate 81, a first input terminal of the logical NOR gate 82, with a first input terminal of the logical OR gate 83 and a third input of the ones register 93 connected. A line assigned to volume I is subject to a second input cycle of the OR

Tores 82 connected and one of the channels 5 and 6 assigned Line connects to a third input terminal of the OR gate 82 'and to a second terminal of the OR gate 83 connected.

An output terminal of the OR gate 82 is connected to a first input terminal of the ones register 93 connected, while a second input terminal of the register 93 with an output terminal of the OR gate 83 connected is. A fourth input terminal of register 93 and a second, third and fourth input terminal of the tens register 9 ^ are connected to a common terminal tied together. An output terminal of the NOR gate 81 is with a first input terminal of the AND gate 84 and Connected via the inverting amplifier 86 to a first input terminal of the logical AND gate 85. the clamp 90 is to a preset input terminal of the ones register 93 »a preset input terminal of the tens

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June 14, 1975

Registers ^ h, a second input terminal of the AND gate 8h, a second input terminal of the AND gate 85 and an input terminal R. of the logic gate 88 connected.

The output terminal of the AND gate 8h is

connected to a first preset terminal of the logic tool 87, which gate is connected to an output terminal of the AND gate 85. The terminal 80 is connected to an input terminal of the logic gate 87 and to an input terminal S of the logic gate 88. Four output terminals of the ones register 93 are connected to four associated input terminals of the ones comparison circuit 91, while four output terminals of the tens register 9 ^ are connected to four associated input terminals of the tens comparison circuit 92. Four further input terminals of the units comparison arrangement 91 are connected to four terminals which supply input data and four further input terminals of the tens comparison circuit 92 are connected to four terminals for input data. An output terminal of the ones comparison circuit 91 is connected to a first input terminal of the logical AND gate 89, while an output terminal of the tens comparison circuit 92 is connected to a second terminal of the AND gate 89. An output terminal of the ÜND gate 89 is

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June 14, 1975

connected to terminal 95. An output terminal of the logic gate 87 is connected to an input terminal of the ones register 93, while an output terminal of the register 93 is connected to an input terminal of the tens register 9h .

Referring now to Figures 6, 7> 8 and 9, the operation of the preferred embodiment to identify a selected frequency for television channels in band I, channels 5 and. 6, Volume II and Volume III. The two upper waveforms in the figures indicate frequencies of associated harmonics and the relationship of these harmonics to the harmonic signals of Zh MHz. The following waveform in each figure shows the time dependency of the voltage supplied to the voltage controlled local oscillator (which voltage depends on the frequency of the output signal of the voltage controlled oscillator).

The further part in each figure shows the interference frequency envelope of 1 MHz that is generated is when the frequency control signal of the voltage controlled Oscillator with the output signal of the reference signal signal generator and the output voltage of the flip-flop circuit generated by these interference frequencies will.

The lower four velle shapes in these

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June 14, 1975

Figures show the time relationship of certain control signals during the sampling of the signal of the voltage-controlled oscillator. The first two waveforms show the signal for the arrangement that regulates the voltage-controlled oscillator with the aim of increasing or decreasing the frequency. The following waveforms show the timing of a preset voltage signal to the other control signals of the tuning system. The lower waveform shows the relationship of the signal that generates a 2h MHz output from the reference signal generator.

The mode of operation of the preferred embodiment is explained in more detail with reference to FIG. When selecting a television channel (for example corresponding to a selected frequency of the output signal of the voltage-controlled oscillator) by introducing a number into the channel selector 27 by means of the remote control arrangement 29 or in some other way, a signal is supplied from the channel selector 19 to the monostable multivibrator 30, whereby the output signal of the multivibrator assumes a positive value. At the same time, a positive signal is fed to terminal S of logic gate 32, as a result of which an h MHz comb signal is generated by generator 22. The simultaneously occurring zero signal, which is fed to the terminal R., makes the generation of a

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6 MIIz comb signal impossible. The frequency ^{generator 1} 21 consists of a 2h MHz crystal oscillator in the preferred embodiment and either the 4 MHz comb frequency signal components or the 6 MHz harmonic comb frequency components contain the output signal of the generator 22. The UMHz harmonic comb frequency components create an automatic training in the preferred embodiment Tuning to channels 5 and 6. This arrangement is denoted by 33 in FIG. 2 and is coupled to the tuning system in a manner that differs somewhat from that in FIG. A signal from the multivibrator 30 is fed to the reset arrangement of the counter circuit 31. The arrangement 31 resets the count values which have been stored in the counter circuit 23 to a predetermined initial value. A signal from the multivibrator 30 is also fed to the control voltage circuit kj. Through this signal, the output voltage of the circuit hj reaches a predetermined equilibrium value in the time interval between T_ and T and leads to a predetermined initial frequency of the output signal of the Spannurigsge controlled oscillator. The monostable multivibrator 30 retains the positive output signal as long as the circuit remains in the unstable state.

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June 14, 1975

Introducing a channel name in

the channel selector 27 generates signals corresponding to the predetermined channel frequency which must be fed to the code converter 26. The code converter 26 changes the frequency designation from any indication (for example channel number) to a related input number. The input number related to the predetermined oscillator output signal, as well as other parameters, may have an intricate relationship with the designated channel. The input number is fed to the storage circuits 25 and is compared by means of the comparison circuit 2k with a count number in the storage circuits of the counter circuit 23. Activation of the reset circuit 31 brings the counted number to a predetermined value. Due to a difference in identity between the number introduced and the number counted, the. Comparison circuits send a positive signal to the voltage control circuit 43 which ensures that the output voltage reaches a certain value. But the positive signal of the multivibrator 30 has priority and ensures that the predetermined value of the voltage is fed to the voltage-controlled oscillator kO as long as the positive multivibrator signal is present. When the * multivibrator 30 is in the stable

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1 ^ .6.1975

When the state returns, the signal from the comparison circuits 2k ensures that the output signal to the voltage-controlled oscillator changes. The increase or decrease in the voltage supplied to the voltage controlled oscillator ensures that the frequency of the output signal of the voltage controlled oscillator increases or decreases at the same time. The output signal of the oscillator% is mixed in the converter ^ 11 with the 2k MHz signal of the comb signal generator.

When the frequency of the output signal of the

voltage-controlled oscillator deviates by 1 MHz from the first 2k MHz harmonic, with which harmonic the changing local oscillator frequency coincides, the amplifier k2, which is tuned to 1 MHz, carries the interference frequency signal that is created from the dec * mixture of the comb signal generator and the voltage-controlled oscillator , to the interference detector k $ . As a result of the occurrence of the interference frequency signals, the detector U5 sends a pulse to the counter circuit 23 and a positive logic signal to the terminal R. of the gate 32. The counted number in the memory of the counting circuit 23 is increased by one by the pulse supplied to the counting circuit 23. The pulse fed to the gate ensures that the signal that is fed to the Kainmsignalgenerator 22 and that to a comb signal of 2k MHz

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June 14, 1975

leads with harmonic frequency components, which are fed to the converter h \ , is removed and that a
the positive signal fed to the terminal R is fed to the comb signal generator ZZ . The positive signal at the terminal R leads to a comb signal with harmonic frequency components of 6 MIIz or k MHz, which is fed to the converter 41. If the frequency of the output signal of the voltage controlled oscillator changes further, when the output voltage frequency of the
Oscillator and the frequency of one of the harmonic components of the Kanimf frequency differ from 1 MIIz, the interference frequency on. The number counted in the
The memory circuit of the counter circuit 23 is enlarged for each interference frequency signal pair that is detected by the detector 45.

If the counted number in the memory circuits of the counter circuit 23 and the introduced number of the memory circuits 25 are both the same, the positive signal that is fed to the control voltage circuits 43 is removed, by removing the
positive signal (for example at time T ") an automatic frequency control loop regulates the oscillator 4o. The AFR loop consists of the interference discriminator kh,. the amplifier 58, the control voltage circuit 43, the voltage controlled oscillator

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kO , the converter Ηλ and the amplification k2. This arrangement keeps the voltage of the voltage controlled oscillator at the frequency which is determined by the frequency designation which has been introduced into the channel selector 27. The output signal of the oscillator Ίο is mixed with the incoming signals of the antenna 51 and leads to an intermediate frequency of ^ 5.75 MHz for the information of the selected channel. The information of the selected channel is fed to the output stage 55. The amplifier 58 provides an amplified output signal of the discriminator kk with a positive or negative sign, depending on which of the two interference frequency signals (e.g. 1 MHz above or below the associated harmonic component of the chimney frequency) is used in the AFR loop. The sign used by this amplifier can be determined by a signal from the code converter.

The signal frequencies required by the oscillator kO to tune the standardized holiday channels are 101 MHz to 113 MHz in 6 MHz steps (channels 2 up to and including k), 221 MHz to 257 MHz in 6 MHz steps (channels 7 to 13) and 517 MHz to 931 MHz in 6 MHz steps (channels Ik to 83). 101 MHz, 107 MHz, 113 MHz and 221 MHz to 257 MHz are all 1 MHz below the harmonic 6 MHz signals (e.g. generated by the

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U.6.1975

Comb signal generator). Similarly, 517 MHz to 931 MHz are 1 MHz above the 6 MHz harmonic signals. Channel 5 is 1 MHz below and channel 6 is 1 MHz above the harmonic frequency component of k MHz. By activating and switching on the automatic frequency control loop through the associated 1 Mllz interference frequency of the closest 6 MHz or k MHz harmonic frequency signal, the signal of the voltage-controlled oscillator is stabilized on a frequency, which results in demodulation of the incoming signals from the television receiver .

To increase the flexibility of the

Invention contains "a third automatic frequency control loop, a superposition converter 53» the tuned amplifier ^ k , the discriminator 3k, the control voltage circuit h3 and the voltage-controlled oscillator ko . This circuit arrangement can be made effective by a suitable switching of the switch 57. This loop enables the effective demodulation of the channels where, unlike commercial radio kaiai channels, the drift in the frequency of the information-carrying channel can be a problem.

The video segment generator 28 vii ^ d in the preferred embodiment used for rendering

509851/1004

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of the channel on the playback surface that is in arrives at the television receiver.

In the preferred embodiment, can the person operating a receiver each channel designation in the channel selector and in the associated arrangement introduce and that beginning at a predetermined starting position is followed by the successive Channel signal frequencies going the associated local oscillator signal frequency obtain. The speed of electronic voting makes it cyclical It doesn’t pass through and the arrangement provides the information of the selected channel to the audio / picture output arrangement without any noticeable delay.

To transfer channel 5 and channel 6 to the

automatic frequency tuning system of the preferred embodiment generated to match? the reference generator a comb signal of Zk MHz, 6 MHz or k MHz. A positive signal which is fed to terminal 6j from FIG. 3 leads to the generation of a harmonic comb signal of Zk MHz. Removing the positive signal from terminal 67 and a positive signal from terminal 68 results in a 6 MHz comb signal, while the absence of positive logic signals from terminals 68 and 67 results in a k MHz comb signal.

Figure k shows an arrangement for halving

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or trisection. When a zero signal is applied to the terminal lh and a reset terminal of the flip-flop circuit 72, the input terminals J and K are the. Flip-flop circuit 71 is supplied with a positive signal. Because of the truth table for a JK flip-flop circuit, output signals are generated which are presented to the Q-Kbmme of the flip-flop circuit 71 for every other signal that is fed to the clock terminal of the flip-flop circuit 71 , wherein an input signal at the clock terminal of the flip-flop circuit 71 is halved. When a positive signal is applied to the reset terminal of flip-flop 72, the Q output terminal is determined by the signals to the JK input terminals. If the J and K input terminals of flip-flop 71 both receive a positive signal, the output terminals will not provide complementary signals on the Q and Q output terminals with the simultaneously occurring clock pulses. Therefore, an input signal applied to the clock terminal causes a signal with a frequency divided by three at the Q output terminal of the flip-flop circuit 71.The frequency of the input signal at terminal 75 or the frequency of the output signal at 73 can be further halved , where the + ^ / + 6 divider circuit 60 is used. will that by the. positive signals at the reference generator

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gate 11 can be controlled. The signal fed to the terminal ^ k can be regulated by the associated logic circuit that works with the code converter 26.

As is likely to emerge from FIGS. 6 to 9, the mode of operation causes different initial circumstances for the counter circuits for each group of channels. Figure 5 shows the counts initially placed in each register. (FIG. 8 also shows the positions of channels 84-91). In FIG. 9, for example, channel Vh begins with the third flip-flop output. This introduces 11 during a presetting period of the counter in order to bring registers 93 and 9h into agreement with the input data. (FIG. 8 shows a system with channels Qh and 91 and for this reason not six, as in FIG. 5, but eight should be introduced into the register, as would be evident to the person skilled in the art).

Another condition that must be preset is the initial state of the logical gate 87. In Figures 6,7,8 and 9 it can be seen that in order to ensure that the count is introduced into the register regardless of whether a higher or lower interference frequency is used, the flip-flop circuit is used 87 in the off mode for the preset period

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must be brought to the initial state. Appropriate settings for the counter 87 are the column Q_ in Figure 5 can be seen.

Your specialist should understand that

the voltage control circuits must be preset so that suitable output frequencies are obtained for the output signal of the voltage controlled oscillator. In the preferred embodiment, the output frequencies of the oscillator lie between preselected 2k MHz harmonic components in order to avoid the more precise frequency control that would be necessary to bring the frequency of the oscillator signal between the predetermined 6 MHz or ^ MHz signals. The presetting of the output signal of the control voltage circuits can be regulated by the logic circuit together with the code converter circuits, as it should be clear to the person skilled in the art.

It should be evident that the reference oscillator can generate a frequency other than 2k MHz (for example 12 MHz) in the relevant embodiments within the scope of the invention.

The present embodiment of the preferred embodiment is for the purpose of comparison between the counted ones Number and the number received. It should be obvious that other data processing certificates are

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can be turned. The code converter 26 can, for example, feed a quantity directly into the register units of the counting circuits 23. Thereafter, a detection of the interference frequency signals increases or decreases the register unit until a predetermined register state removes the positive signal fed to the rule saving circuits hj.

The above description explains

the operation of the preferred embodiment and is not intended to limit the scope of the invention. The scope of the invention is limited only by the claims below. In the context of the invention many modifications are possible for those skilled in the art.

In Eigur 10, idealized output signals are shown at various points in FIG. In Figure 10a the output signal of the monostable multivibrator 30 is a positive value between T lind T .. In Figure 10b reaches a restoring voltage signal th oscillator is fed by the re gel-voltage circuit-h '} the Spannungsgeregel ·, an equilibrium value during the interval , which _{starts at T n} and increases steadily to T ₁ and after T "reaches an equilibrium value. FIG. 10c shows the output value of the signal from the interference detector, pulses begin at T ₂ and continue until T 1 is reached. figure

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10d shows d ± 3 output voltage of a logic signal which is fed to signal generator 22 through a first terminal of logic gate 32. At the moment T, the logic signal which is fed to the signal generator 22 is given a value of zero and at the moment Tp the logic signal is given a positive value. The presence of a positive signal ensures the presence of a 6 MHz comb signal. FIG. 10e shows the logic signal which is fed to the generator 22 by the tool 32. The logic signal

rr

receives a positive value at the moment T and becomes a logic signal zero at the moment T ". The presence of this positive signal ensures the presence of a 2k MHz comb signal from the reference signal generator. In FIG. 10f, the control signal which is fed to the control voltage circuit 43 by the comparison circuits 2k is a positive value which starts at T and becomes a zero value at the moment T ".

The mode of operation of a preferred embodiment can be viewed with reference to FIG. 2 together with FIG. When choosing a TV channel (For example, according to a selected frequency of the output signal of this voltage-regulated Oscillator) by introducing a number in the channel selector 27 by means of the remote control arrangement 20 or on

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another way, a signal from the channel selector is supplied to the monostable multivibrator 30, whereby the output of the multivibrator becomes a positive value at the instant T_. At the same time, a positive signal is fed to terminal S of the logic gate 32, as a result of which a 2k MHz comb signal with harmonic frequency components is generated by the generator 22. The zero signal that occurs at the same time and is fed to terminal R. prevents the generation of a 6 MIIz comb signal with harmonic frequency components. The frequency generator 21 consists of a 2k MIIz crystal oscillator in the preferred embodiment, either the 2k MHz comb signal components or the 6 MHz comb signal components containing the output signal of the generator 22.

In addition, a signal from the multivibrator 30 is fed to the counter circuit reset arrangement 31. The arrangement 31 resets the counted values, which are stored in the counter circuit 23, to a predetermined initial value. A signal from the multivibrator 30 is also fed to the control voltage circuits k3. With this signal, the output voltage of the circuit k3 reaches a predetermined equilibrium value in the time interval between T and T ₁ and leads to a predetermined initial frequency of the

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1 * 4.6.1975

Output signal of the voltage controlled oscillator ^ O. The monostable multivibrator 30 keeps the positive Output signal for the period of time during which the circuit arrangement maintains the unstable state, for example the time from T to T.

By introducing a channel designation in the channel selector 27, signals are sent to the code converter. 26 which correspond to the designated channel frequency. The code converter 26 changes the frequency designation from any variable (for example number of channels) into a relevant input number. The input number, which is related to the predetermined oscillator input signal as well as other parameters, may have an intricate relationship to the designated channel. The input number is introduced into the memory circuit 25 and is compared with a counted number in the memory circuits of the counter circuit 23 by means of comparison circuits 2k. The activation of the reset circuit 31 brings the gezähl _T te number to a predetermined Vert. A lack of identity between the initial number and the counted number causes the comparison circuits to lead a positive signal to the control voltage circuit ^ 3, as a result of which the output voltage reaches a specific value. The positive signal from the multivibrator

50985171004

- 32 - PHM 1001C

λΗ.β. 1975

30 has however. Priority and that caused the predetermined Voltage value of the voltage controlled oscillator ^ O is supplied as long as the positive multivibrator signal is present.

When the multivibrator 30 i " ¹ instant

T ₁ returns to the stable state, the output signal is fed to the voltage-controlled oscillator for increasing by the signal from the comparison circuits Zh. Due to the increasing voltage which is fed to the voltage-controlled oscillator, the frequency of the output signal of the voltage-controlled oscillator increases at the same time. The output signal of the oscillator is mixed in the converter hl with the 2.h MHz signal of the comb signal generator.

When the frequency of the output signal of the voltage controlled oscillator reaches the value 1 MHz below the first Zh MHz harmonic, which coincides with the increasing frequency of the local oscillator signal, the amplifier 42, which is tuned to 1 MHz, carries the interference frequency signal which is obtained from the mixture of the- The output signal of the comb signal generator and the signal of the voltage-controlled oscillator arises, the interference detector h $ too. The occurrence of the interference frequency signals causes the detector 45 of the counter circuit 23 to generate a pulse and the terminal

5098 5 i / 1004

- * 33 - PiiiM 1 υο LC

lh.6. 1975

'me R. of the gate 32 to a positive logic signal. By the pulse supplied to the counter circuit 23, the counted number in the memory of the counter circuit 23 increases by one. The pulse supplied to the gate removes the signal which is supplied to the signal generator 22 and which leads to a comb signal of 2k MHz with harmonic frequency components and which is supplied to the converter k] , and a positive signal which is supplied to the terminal R is removed , is fed to the comb signal generator 22. The positive signal at the terminal R _Q leads to a 6 MHz comb signal with harmonic frequency components, which is fed to the converter 41. If the frequency of the output signal of the voltage controlled oscillator increases continuously, the interference frequency signal occurs when the frequency of the oscillator output voltage and the frequency of one of the harmonic components of the camshaft signal differ by 1 MHz. The number counted in the memory circuit of the counter circuit 23 is incremented for each interference frequency signal pair which is detected by the detector 'k5.

When the counted number in the memory circuits of the counter circuit 23 and the introduced number of the memory circuits 25 are the same ^ the positive signal supplied to the control voltage circuit k3 is removed. In removing the positive

S09851V1Q04

- 34 - PhM 1001C

June 14, 1973

Signal (for example at the moment T "an automatic frequency control loop controls the oscillator 4o) . The AFC loop contains a discriminator 44, an amplifier 58> a control voltage circuit 43 "a voltage controlled oscillator 40, a V _a traders 4i and an amplifier 42 .. This arrangement maintains the voltage of the voltage-controlled oscillator on the frequency determined by the frequency designation that has been inserted into the channel selector 27. The output signal of the oscillator 40 is mixed with the incoming signals of the antenna 51 and leads to an intermediate frequency of 45 »75 MHz to form the selected channel. The selected channel information is fed to the output arrangement 55. The amplifier 58 generates an amplified output signal of the discriminator 44 with a positive or negative sign depending on which of the two interference frequency signals (for example 1 MHz above or below the relevant harmonic comb frequency component) is used in the AFR loop. The sign used by this amplifier can be determined by a signal from the code converter.

The frequencies of the signal from the oscillator 40 that are used to tune the standardized television channels are 101 MHz to 113 MHz in 6 MHz increments

50985Ϊ / 1004

- 35 - 'PHM 1001C

June 14, 1975

(Channels 2 to k), 221 MHz to 257 MHz in 6 MHz steps (channels 7 to 13) and 517 MHz to 931 MHz in 6 MHz steps (channels Ik to 83). The values 101 MHz, 107 MHz, 113 MHz and 221 MHz to 257 MHz are all 1 MIIz below the harmonic 6 MHz signals (e.g. generated by the channel signal generator). Similarly, 517 MIIz to 931 MHz are 1 MHz above the 6 MHz harmonic signals. When the automatic frequency control loop is activated and switched on up to an interference frequency of around 1 MHz of the nearest harmonic 6 MHz frequency signal, the signal from the voltage-controlled oscillator is stabilized at a frequency that causes the television receiver to demodulate the incoming signals.

The choice of the appropriate interference frequency signal from the series of interference frequency signals is determined by the input number. The code converter 26 determines the number counted for each program channel assigned. In the preferred embodiment, the code converter 26 uses a programming ■ "read-only" memory. By switching to one Other programmable "read-only" memory can use a number of input arrangements on the television receiver will.

To increase the flexibility of the

50985Ϊ71004 *

- 36 - PUM 1Ö01C

lh.6. 1975

In the invention, a second automatic frequency control loop is provided which contains a superimposed converter 53, a tuned amplifier, a discriminator 34, a control voltage circuit k ¹ and a voltage-controlled oscillator kO . This circuit can be switched on by a suitable setting of the switch 57. The loop enables effective demodulation of channels where, in contrast to commercial radio channels, the drift in the frequency of the information-carrying channel can be a problem.

'To tune in to channel 5 and channel 6, the

have an appropriate frequency relationship with the 6 MHz harmonic frequencies, a single array 33 can be provided. For example, a potentiometer can be used to obtain a suitable voltage level at the output of the control voltage circuit k3 , the desired frequency of the output signal of the oscillator ^ O being obtained. In another embodiment, the insertion of the duct 5 or the duct 6 in the channel selector 27 may activate a particular oscillator, whereby an appropriate frequency (or frequencies appropriate) are supplied to the transducer hl.

The video segment generator 28 is used in the preferred embodiment for displaying the in the

50985171004

- 37 - PHK 1G01C

June 14, 1975

TV receiver imported channel used.

In the preferred embodiment, can

the operator of a television receiver any Channel designation (with the exception of 5 and 6) in Introduce the channel selector and into the associated systems, starting from a predetermined starting position sequentially become the successive channel signal frequencies run through until the signal frequency of the Oz't oscillator has been reached. By the high At the speed of the electronic voting, the run is not visible and the arrangement creates that Information of the selected channel to the audio / video output arrangement ohc noticeable delay.

It should be evident that the frequency of the oscillator ho can begin between the third and fourth Hannonian of the 2h MHz comb frequency components. The counting number can then be increased, starting with the 1 MHz interference frequency signal below the fourth harmonic of the Zh MHz comb frequency generator signal. In this way, the signal of the control voltage _{circuit does not reach the value zero during the interval T Q} to T _1, but instead a voltage value arises, which results in an oscillator frequency between 73 MHz (3 2h MHz + 1 MHz) and 95 MHz (h χ 2h MHz - 1 MHz). It should be evident that a

509851/1004

-38- PHM 1001C

^ k.6. 1975

Another embodiment comprises the value of the output signal of the oscillator kO, whereby an output frequency value between the fourth and fifth harmonics of the 2k MHz comb signal is achieved, whereby the oscillator frequency decreases until the interference frequency signal above the fourth harmonic of the 12 MHz comb signal generates a count. The frequency of the oscillator output signal is then changed in the direction of an increase in the signal frequency. It is also possible that the output frequency of the oscillator starts between · suitable (η χ 6 MHz + Ί MHz) and ([Ji + ij [6 MHz - 1 MHz) frequencies, with the harmonic comb signal of 12 MHz being switched off; but a more precise regulation of the output signal of the regulating voltage circuit is necessary. It should also be obvious that in the beginning the frequency of the output signal of the oscillator can be made dependent on the channel drawing. Because of the speed of the electronic frequency swing, this embodiment can make the arrangement more intricate without producing a corresponding improvement that is perceptible to the eye.

"It should be clear to a person skilled in the art that the reference oscillator in the relevant embodiments can generate a frequency other than 2k MHz (for example 12 MHz) without influencing the principle

S098Si / 1004

- 39 - PHM 1001C

H.6.1975

pial effect.

The purpose of the relevant design of the preferred embodiment is to compare the logic signal between the number counted and the number introduced. It will be understood that other data processing schemes can be used. For example, the code converter 26 can introduce a variable directly into the register units of the counter circuit 23. In addition, the detection of the interference frequency signals increases or decreases the register unit until a predetermined register state removes the positive signal that was fed to the control voltage circuit k3.

The above description explains

the operation of the preferred embodiment and does not limit the scope of the invention. The scope of the invention is only indicated by the following characteristics limited. Many modifications are possible within the scope of the invention for those skilled in the art.

In Figure 11, a controllable local oscillator generates 113, a signal having a frequency determined by the output signal of the oscillator control circuit 122 is determined. In the preferred embodiment, the local oscillator consists of a voltage controlled one Oscillator. The output of the oscillator 113 becomes

50985 ^ / 1004-

- ItO - PHM 1001C

June 14, 1975

the mixer circuit 112 and the terminal 125. The mixer circuit 112 is a superimposed converter in the preferred embodiment. An output signal of the reference signal generator 111 is also supplied to the mixer circuit 112. The output of mixer 112 is fed to tuned amplifier 114. The output signal of the amplifier 11h is fed to the discriminator 118 and to the interference detector 115. The discriminator 118 is a circuit arrangement which generates an output signal, the amplitude of which is dependent on the frequency of an input signal. The interference detector 115 produces an output signal that is essentially the envelope of the input signal. The reference signal generator 111 can be an arrangement for generating an output signal with only one frequency, an output signal with a plurality of frequencies or an output signal with comb-shaped harmonic frequency components.

The output of the interference detector 115 is fed to the programmable counter system 116. In the preferred embodiment, the programmable meter system 116 is via the terminal 127 to a summing network 117 a positive signal to · after removing a reset signal that the terminal 123 of the system 116 was fed. The po-

50985t / 1004

PHM 1001C

June 14, 1975

Sitive signal ¹ is removed from the output of system 116 upon detection of a given number of pulses supplied to system 116 by detector 115. The number of pulses required to remove the positive signal from the axis output of the Sys-r teras 110 can be changed by signals that are fed to terminal 12h.

The output of the discriminator 118 is supplied to the reversing switching amplifier 129. The amplifier 129 is coupled to the system 116 and the output of amplifier 129 is at one Input clamp of switch 121. An output signal of the AFR discriminator 119 of the receiver is fed to a second input of the switch 121. An output terminal of the switch 121 is connected to the summation network 117 via the terminal 126 · The output signal of summing network 117 becomes the oscillator control circuit 122 supplied. An input terminal 123 for supplying a reset signal is applied to the oscillator control circuit 122. The backlash signal is set represents the initial value of the signal applied to terminal 128 and consequently to oscillator 113, thereby increasing the frequency of the oscillator signal.

FIG. 12 shows a circuit diagram of the summing network 117 and the oscillator control circuit 122. Terminal 126 is connected to a first terminal of a resistor

509851/1004

- 42 - PHM 1OO1C

June 14, 1975

Stand 131 connected. A second terminal of the resistor 131 is connected to the terminal via resistor 132 1271 at the base of the pnp transistor 134 and on the base of npnp transistor 133 · The emitter of transistor 133 and the emitter of transistor 134 are located at a common · terminal. The collector of transistor 133 is connected to one through resistor 135 ■ first terminal of resistor 141 and at the base of pnp transistor 144. A voltage source V, is connected to a second terminal of the resistor i4i, via the resistor 1 42 to the emitter of the transistor 144 and via the potentiometer 143 to the common terminal. The sleeper of the potentiometer is connected to the sink of the field effect transistor 145. The gate of transistor 145 is connected to terminal 123, while the source of the transistor 145 is connected to terminal 128.

"The collector of transistor 134 is connected via the resistor I36 at the base of the npn transistor 14o and at a first terminal of the resistor 138 · A voltage source V is connected to a second

Terminal of resistor I38 connected and across the resistor 139 to the emitter of transistor 14θ. the Terminal 128 is across the collector of transistor 144, the collector of transistor 140 and across the capacitor

50985171004

- 43 - PUM -.001C

June 14, 1975

sator 137 at the common terminal.

The collector of the pnp transistor 1 k6

is connected to the base of the transistor ikh via the resistor 1 ^ 8. The emitter of transistor 1 h6 is connected to the common terminal, while the base of transistor 146 is connected to terminal 153 via resistor 1 ^ 7.

The collector of the npn transistor 1 k $

is connected to the base of the transistor 1 hO via the resistor I50. The emitter of the transistor 1 k9 is connected to a common terminal, while the base of the transistor 1 49 is connected to the terminal via the resistor I5I.

The ^ emitter of transistor 144 is present

the cathode of diode I63. The anode of the diode I63 is connected via the resistor 164 to the voltage source V. and via the resistor 162 at the cathode of the diode Ιοί. The cathode of the diode Ιοί is also about 4n resistor 160 is connected to the voltage source V., while the anode of the diode I61 is connected to the emitter of the transistor 140 is connected.

The base electrodes of the transistors 133

and 134 are connected to the cathode of diode I56 and to the Anode of diode I58 connected. The anode of the diode is connected to the cathode of diode 155 while

509851/1004 *

- kh - PHM 100'1C

June 14, 1975

the anode of the diode 155 with an output terminal of the Signal level shifting arrangement 159 is connected. The cathode of diode 158 is with the anode of the diode 157, while the cathode of diode 157 is connected to the output terminal of displacement assembly 159 is. The input terminal of the arrangement 159 is at terminal 15 ^.

FIG. 13 a is a circuit diagram of the reverse switching amplifier 129 which is located between the discriminator 113 and the switch 121. The terminal 180 is via the resistor 183 at a first Eingangskleinme of the amplifier 188 and the resistance of ¹ 18 ^ at a second Eingangskleinme 188. The Ausgangskleiiime of the amplifier 188 is via the resistor 192 to terminal 182 and is connected to a first terminal of the resistor 190 connected. A second terminal of resistor 190 is connected to the common terminal via resistor 19I and to the first input terminal of amplifier 188 via resistor 189.

The second input terminal of amplifier 188 is at the collector of transistor 187. The emitter of transistor 187 is at the common terminal. The base of the transistor 187 is connected to the terminal I8I via the resistor 185 and via the resistor 186 connected to the voltage source V.

50985Ϊ71004

FKM 1001C lh. 6. 1975

Figure 13b 'shows the function of the inverse

ting amplifier that works together with the discriminator 118 is used. The upper curve shows the envelope of the interference frequency signal with constant amplitude with respect to a center frequency. the Middle frequency shown in Figure 13b can be in the preferred embodiment one of the frequencies of a Be a comb of harmonic frequency signals. the The lower curve shows how the output signal of the discriminator must be reversed depending on the Use of the upper or lower interference frequency in the automatic frequency tuning circuit. It will be apparent to those skilled in the art that if the interference frequency is below the center frequency, and the local oscillator increases, the interference frequency decreases. For the position of the interference frequency above the center frequency the interference frequency increases when the Local oscillator increases.

The output of the frequency controllable local oscillator 113 creates a frequency that is in a Receiver unit is used, which is connected to terminal 125 connected is. The local oscillator frequency is or is mixed with a received or sent signal superimposed on this signal to generate a simple intermediate difference frequency to which the respective receiver

50985171004

PHM 1001C IU.6.1975

catcher clialtungen are coordinated. The intermediate frequency continues to react to changes in the frequency of the sent signal due to corresponding changes in the intermediate frequency, in the preferred embodiment the local oscillator 113 consists of a voltage controlled oscillator. .Transmitted by a television station However, signals have relatively stable and well-defined frequencies, which makes them easier to use an internal frequency signal source is possible in an automatic frequency tuning system.

'The output signal of the voltage controlled Oscillator is mixed with or superimposed on a signal that has a frequency spectrum that is determined by an internal oscillator that includes part of the reference signal generator, such as a crystal oscillator. The output signal of the reference signal generator is matched with the output signal of the voltage controlled oscillator in the mixer circuit 112 mixed.

In the preferred embodiment, the tuned amplifier 114 tuned to 1 MHz, so that J if the frequency of the local oscillator signal and the frequency of the signal generator are 1 MHz from each other differ, a signal is generated at the output terminal of amplifier 114.

50985171004. *

- 47 - HiM 100IC

The output of amplifier 114 is liird an interference detector 115 and the discriminator 118 supplied. Because the oscillator 113 generates a signal with changing frequency, the output signal is the Interf ercMizdetektors a Tmpials and becomes a programmable one Counter3'stem 110 supplied. When removing the The programmable counter system carries the preset signal 116 of terminal 127 of the oscillator control circuit 122 a positive signal. This positive signal ensures a continuously increasing voltage level the output mine of the oscillator control circuit 122. Due to the increasing voltage level, the voltage controlled Oscillator a signal with increasing frequency.

Venn has, however, receive a vorbcstimmte number of pulses from the system 116 by the interference detector 115, the terminal 127 supplied signal, which ensures that the oscillator control circuit 122 produces an increasing voltage is removed and by the discriminator 118 and the Umkehrungsumschaltverstärker 129 loop formed determines the signal that regulates the voltage-controlled oscillator 113. In the preferred embodiment, the positive signal from the progranim system 116 exceeds the signal from amplifier 129.

509851/1004

- l \ 8 -. PHM 1001C

1 ^ .6.1975

arrangement of the automatic frequency control type
creates the stabilization of the frequency of the signal
of the voltage controlled oscillator. It should be evident that the output signal of the discriminator circuit must be reversed if the interference frequency is selected above the center frequency and, conversely, below the center frequency. In the preferred embodiment, a signal from the system automatically controls the mode of operation of amplifier 129 * Es
It should be evident that the signal generated by the signal generator and the frequency to which the amplifier 114 is tuned must be selected in such a way that the frequency of the output signal of the voltage-controlled oscillator has the desired frequency.

In one embodiment, the programmable counter may include the interference frequency signal count the result of the mixture of the changing signal of the voltage controlled oscillator and the signal with a comb frequency generated by the generator 111 becomes, arises. Upon recognition of the preselected counts the AFR loop with the discriminator 118 stabilizes the output voltage of the oscillator. To Another embodiment may have a specific frequency are generated by the reference signal generator 111 and

509851/1004

P ¹ TM mo ic 14.ό.1975

the first interference frequency detected by system 116 can ensure that the automatic frequency control loop stabilizes the oscillator. The frequencies to which the system can be tuned kaniij are determined by the frequencies that can be obtained from the signal generator 111 and by the Frequency to which amplifier 114 is tuned.

It should be apparent to those skilled in the art that

the starting frequency of the oscillator cannot be arbitrary can. Therefore, the terminal 123 of the control circuit 122 is supplied with a reset signal. By this reset signal becomes a voltage, which is determined by the position of the wiper of the potentiometer 1 ^ 3, the Oscillator 113 is supplied, with an initial frequency is determined. Similarly, the positive signal from system 110 must be fed to control circuit 122 is applied to terminal 123 of system 116 upon removal of the reset signal. Besides that the reset signal is used to reset the counting circuits of the system 1-16. After resetting of the counter, terminal 12 ^ is used to the system 11 6 information related to the signal frequency of the stabilized oscillator by specifying the circumstances for removing the positive Signal from control circuit 122.

5098SiVIO (U-

- 50 -. PIiM 1001C

1 '+. 6.1975

The circuit arrangement according to FIG. 12

shows the oscillator control circuit and the summing circuit of the preferred embodiment, the reset signal is fed to the gate of transistor 1 ^ 5 via terminal 123. The capacitor 137 is discharged to a predetermined value by the position of the wiper of the potentiometer

113 · Then the positive signal of terminal 127 «

supplied, whereby the capacitor stores an increasing charge that results from an increasing. tension on terminal 128. After detection of the relevant signal (for example a certain number Pulses) from the interference detector 115 becomes the positive Signal from terminal 127 and from control circuit 122 removed. Then the drift in the oscillator frequency, caused by changes in the charge of the capacitor or other changes using the feedback loop with the discriminator 118 corrected. An error signal that the amplifier 20 ai> via terminal 126 or the Sunimiernetzwerk 117 is supplied, is used to correct the frequency changes used. The capacitor 137 forms a memory that the desired frequency during a Time period.

In certain areas of application

509851 / 100A

- 51 - PHM 1001C

14.0.1975

a channel converter and other arrangements for changing the frequency of the information of the channels are used. Such an arrangement can contain the information relating to the frequency stability of the signal which for example, consists of commercial television signals. A recipient discriminator 119 can replace the discriminator 118 placed in the feedback loop In this case the center frequency of the discriminator will be by mixing a received (e.g. radiated) signal and the signal of the voltage controlled oscillator is determined. The voltage controlled The oscillator is used to "synchronize" or to follow the drift of the received signal, this ensures that the intermediate frequency arrangement works in an appropriate way. The capacitor 137 can form a memory for a temporary Loss of the received signal. The one with the. Capacitor 137 will be cooperating parameters for a relatively slow response to the input signals, with any detrimental effects due to the presence of the AFR feedback loop be limited to the minimum. It should be apparent to those skilled in the art that it is possible to use a Switch 121 having an arrangement for replacing the discriminator 120 with the discriminator 118 if lost

509851/1004

- 52 - P'IM 100 IC

June 14, 1975

of the received signal.

In the preferred embodiment, the output of the discriminator 110 of the clamp 15 ^ + and then a signal level shifter, whereby the / output signal of the discriminator and a Equal voltage bias signal arises. the Diodes 155, 156, 157 and I58 form a threshold circuit for signals from the slider 159 · 'The rocker switch forms a block for low noise afflicted signals which otherwise cause an incorrect change in the working frequency of the local oscillator could. The parameters of the circuit arrangement are selected in this way in the preferred embodiment been that the output of the discriminator 119> caused by a mixture of the / signal of the oscillator and the received signal, a larger one Effect on transistors 133 and 134 than that Signals from amplifier 129 · But if there is a fading effect of the received signal, the signal from amplifier 129 stabilizes that of terminal 126 in FIG is supplied, the frequency of the output signal of the Oscillator 113 · The arrangement of the shifter 159 and the threshold network with the diodes 155> 156, 157 and 158 create the function of switch 121, as shown in Figure 11 in a schematic manner

509851/1004

- 53 - pum loo ιc

June 14, 1975

is. It should be obvious to the person skilled in the art that the one described is Training does not lead to discrete switch positions.

A positive signal that is fed to terminal 181 will ensure that the signal shown in FIG 13a amplified amplifier with one polarity, that is opposite to that which would be complete if the positive signal is removed. So there is only one amplifier at the output of the discriminator 118 requires. The application of the positive voltage pulse is in the preferred embodiment determined by circuitry that works with system 116. The detection that a Interference frequency above or below the center frequency will determine the state of the amplifier 129. This decision can be determined by suitable logic circuitry in the programmable system 116.

One feature of the present invention is to reduce the charge capacity of capacitor 137 as short-term storage mechanism for maintaining a certain constant voltage at terminal 128 during time periods depending on the properties of the associated Circuit to 'use. Furthermore, the circuit values result in a relatively slow response

50985171004

PHM 1001C June 14, 1975

on input signals, with any disturbing effects, caused by the presence of the AFR feedback loop are kept to a minimum will. However, it is desirable when scanning the frequency range for changes in the frequency of the signal of the Oscillator 113 that are faster than those which can be supplied by the static circuit elements. In addition, certain Applications are best carried out through an arrangement that has a relatively rapid negative as well as positive sampling of a frequency range by the output signal of the oscillator 113 can perform. For this purpose, a signal is fed to terminal 153 when the capacitor is being charged relatively quickly 137 is desired and a signal from terminal 152 fed when a relatively rapid discharge of the capacitor 137 is desired. These signals switch second resistors with the charging resistor 1 ^ 2 and the charging resistor 139 in parallel, whereby the time constant for the charging capacitor 137 decreases.

The above description is illustrative of the operation of the preferred embodiment and is limited the invention by no means. The scope of the invention is limited only by the claims below. Several modifications are within the scope of the invention for those skilled in the art possible.

509851V 1004

Claims (1)

τ 55 - -PHM 1001C (but «S5uHc / Si>) | n NAOHQEREIQHt PATENT CLAIM: 1.1. TV receiver with a voting switch. device in which an output of a switch with a Mis of the receiver coupled oscillator and an output of a generator for generating a comb of reference signals via a detection circuit with a counting circuit are coupled, with the help of this counting circuit a signal for tuning the oscillator to a desired frequency can be obtained thereby characterized in that the detection circuit (15> 16, 18) is a tuned detection circuit tuned to a frequency such that for a given intermediate frequency of the receiver and a given position of a 'spectrum of the received transmitter signals a correct vote of the recipient is obtained. 2. Television receiver according to claim 1, characterized in that the receiver contains an AFR circuit which is responsive to a received transmitter signal (3 ¹ +, 57, 20). 3. .Fernsehempfänger according to claim 2, characterized characterized in that the receiver has a switching arrangement (57, in Figure 2), with the reception of weak signals from one by the AFR circuit specific vote on a by the voting 509851/1004 ' PHM 100 IC tung bestimir.le voting of the recipient switched will. H. Television receiver according to claim 1, 2 or 3, characterized in that the deletion circuit (15 »16, 18) contains a frequency discriminator (68), of your an output with a control circuit (13) of the Oscillator (12) is coupled. 5. television receiver according to claim k, characterized characterized in that the receiver has a circuit arrangement (129) contains for switching the control rule of the discretionary laboratory (II8). 509851/1004 Blank page