DE2458331A1 - DATA PROCESSING SYSTEM FOR ADDRESSING A DATA SET STORED IN A SECONDARY MEMORY - Google Patents

Description

51-01270 Ge December 9, 1974

HONEYWELL INFORMATION SYSTEMS INC.

200 Smith Street Waltham, Mass., USA ■

Data processing system for addressing a data record stored in a secondary memory.

The invention relates to a method for addressing an in a secondary memory stored data set, as well as a plant to carry out this procedure.

The usefulness of an information system is of the creation and maintaining a comprehensive database dependent. Because there are millions of words stored in a database some suitable form of subdivision is required in order to be able to find each word at the appropriate time. Such a database can be compared, for example, with a dictionary in which millions of words are given in a given Order so that each word can be easily found. Although the comparison with a dictionary Not in all respects, a database must be logically divided into a number of files, with each file a number of memory sections, hereinafter referred to as "pages". Based on the comparison with the dictionary can save the files as a group of one or more

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The first letter of the alphabet is considered v / earth. Any file contains a number of pages which are further subdivided into a number of data records, based on the one referred to Comparison of a data set corresponds to a word. In a data processing system, a data set contains discrete Information, e.g. B. the information regarding an employee in a company.

In large files, a part of each data record is generally used to uniquely identify it. This identification consists of a number that is different for each data record or of alphanumeric characters, which can be converted into numbers. For example, the social security number or a name can be used as an identifier of the data set is used. If corresponding identification instructions are assigned to all data records, then these can may be used as address numbers with slight modification. Often, however, only a small one will be Part of the available identification numbers are used, these being selected in a mathematically random manner. Will then a memory location is assigned to each possible identification number, so only a small part of the memory space is included Records are occupied, so that valuable storage space is wasted within secondary storage. To this problem To overcome the storage space can be effective by simply storing it of the data records within a file are used without the memory addresses corresponding to these data records and identification numbers can be added. However, this requires a certain procedure to find the records, since it becomes necessary to develop a known address identifying the data records. As a result of this well-known In the circumstances, practical methods have been developed which compromise these two extreme storage methods discussed represent. For example, one becomes partial

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Assignment of identification numbers and addresses made- and on the other hand, a large part of the storage space of the secondary memory is used by clicking on a corresponding label the data records are dispensed with.

Because in this case only a partial assignment between identification numbers and addresses, various searches of the data processing system are required when it comes to this goes to find a record again. Such searches are undesirable because the secondary storage is essentially magnetic drums and disk storage devices are used which have a relatively long access time. While the main memory of a Data processor is much faster, but the size of a typical database is generally an obstacle. the fast main memory, which is limited in its storage capacity to use to store this database. Thus, the effectiveness of a secondary storage device depends on it whether it is possible to search for a data record in a first attempt. In order to meet this requirement, various Addressing process developed.

In the most commonly used addressing systems for secondary storage the files are sorted on the basis of identification numbers so that the identification numbers are in an "appropriate order. A known way to find a record in a sorted The file uses its identification number and, with regard to the files stored in the secondary memory, compares the identification number of the data record sought with the middle data record of the File. This comparison shows in which half of the file the data record you are looking for is located. The next comparison is performed on the middle record of the selected half, thereby determining which quarter

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the file is where the data record you are looking for is located. This process continues until the data record you are looking for is found. The effectiveness of such a system depends · on the statistical Characteristics of the file. If the identification numbers are selected from the point of view of perfect uniformity, then With this system, a data record can be found much faster than with randomly selected or non-uniform ones Identification numbers is the case. In any case, however, the addressing systems have which from a sorted file Make use of various disadvantages. First of all, the file must be sorted before being saved, the sorting being a represents a time-consuming process. Second, the sorted file does not allow the insertion of new records and the extraction of records that are no longer required without the need to reorder.

One often proposed system for retrieving records involves storing a table in secondary storage Use, with the table for each identification number assigned to a record, the actual address of the stored Data record. When looking for the data record, the table is read into the main memory, which makes the search very can be done much faster. On closer inspection of this method, however, it becomes clear that here too certain Disadvantages occur. Although an increased operating speed is achieved through the use of the main memory, the transfer of the table to the main memory and the associated use of memory locations in the main memory as not proven economically. In addition, the total time required to find a data record is large because of the secondary storage must first transmit the table pages and then the desired page of the data records.

It is the object of the present invention to provide an addressing system specify, with which a direct access to the data sets

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the database is possible, although the records are without a specific Ordering principle using the full storage capacity of the secondary storage in this are arranged. the This object is achieved according to the invention by what is stated in the claim 1 marked procedure. Further advantageous embodiments of the method and a system for carrying out the Process are characterized in the subclaims.

On the basis of an embodiment shown in the figures of the accompanying drawings, the invention is described below described in more detail. Show it:

Figure 1 is a schematic representation of various hardware structures, as they are used in the present invention,

FIG. 2 shows a general block diagram of a data processing system for carrying out the method according to the invention, FIG. 3 shows the schematic representation of a flow chart for a data field descriptor as used in the present invention Is used

FIG. 4 is a block diagram of the circuitry used in the data processing system of FIG. 2 and FIG FIG. 5 shows a flow chart relating to the execution of the control command. .

Before the addressing system to find records within a secondary memory is described in more detail, let the field in which the invention lies> explained in more detail for the purpose of better understanding of the invention. The scope of one Information to be processed by users requires the information to be stored in secondary storage. Secondary storage facilities can be divided into smaller units. For example, a disk storage can be divided into several contiguous Sectors are subdivided and each sector can be easily accessed. Each sector can thus be viewed as one information page, with each information page having a plurality

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of records may contain. Each data set contains certain information, some of which can be used to clearly identify the data record itself with regard to its storage location. For example, the size the weight or gender of a person cannot be used to uniquely distinguish that person from another Distinguish person. However, regarding an employee, their employee number or name can be used for a clear labeling is sufficient. In a disk storage system, per sector, i. H. several different ones per side Records are accommodated. Regarding tape storage, different tracks and tape sections used the information can also be subdivided.

Since a magnetic disk or a magnetic tape requires much more time to find the information than a main memory, the data records to be searched for must be stored in such a way that this expenditure of time is reduced to the lowest possible level. However, this leads to problems if there are only sparse labeling instructions with regard to the data records. For example, if an employee is to be searched for in a database on the basis of his or her social security number, there is generally a discrepancy between the number of employees in a company and the number of people with social security. For example, a company has only a few to 10,000 people, while the social security number is intended for several million people. It has thus been found that a mechanism which the labeling information, e.g. B. the social security number used to determine the final location, _t z. B. Determine the page number that best suits your needs. This mechanism necessarily assumes that the actual distribution of the records on a page

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occurs stochastically, d. H. that certain pages within the File does not have a much larger number of records have opposite another side.

While a flat frequency of distribution, e.g. B. one with an identical number of records on each page is stored, can only be achieved on the basis of a very special calculation, it has been found that a Poisson distribution is sufficient for storage purposes. It has been empirically found that a stochastic process which this Poisson distribution results, acceptable for secondary storage purposes is. ·

With regard to the implementation of the stochastic feature required to obtain a Poisson distribution, it has been found that experience has shown that the use of the bit positions within data words does not take place uniformly. The lower bit positions of a data word are characterized by a higher degree of utilization. The probability that the numbers used will decrease is low. In the present invention, these experimentally found results are used to specify a stochastic method which gives a good distribution by mixing the high degree of utilization. This is accomplished by shifting the identification number of the data set so that those ^1- bit positions of the word which have a high degree of usage are combined into a common number with those bit positions of the word which have a low degree of usage.

In addition to the above circumstances, it has been recognized that the tag numbers of the word are of some size can. For example, an employee number is usually very much smaller than the social security number. With everyone

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individual application, the identification number can be expressed in a way that suits the individue'llen application purpose is appropriate.

According to Figure la, a command 100 is shown, which the development of a key address for direct access made possible according to the invention. The first 8 bits in the instruction 1OQ represent an operation code OP. The operation code is the most significant byte of a command and is used to identify a special command. In the present case the operation code identifies a control command ("hash" command). A control command is understood to be a command which enables the accidental retrieval of something already known. The next 4 bits, i.e. H. bits 8 to 11 determine a general register GR of the data processor, which contains information assigned to the command. With the present When used, the general register contains a constant which is suitable for generating a favorable distribution. Bits 12 through 31 identify an address syllable which is a logical representation of the address of the operand. This operand can, for example, be the identification number of a data record to be searched for.

The command 100 refers to a data descriptor, which in Form of the descriptors shown in Figures Ib to Id 102, 104 and 106 may be present. The data descriptor represents an effective address and has a hint part in its first two bit storage locations. In the present case, this reference part has the code 01, which refers to that an extended data field descriptor is to be used. This extended data field descriptor is in the form of the Word 108 according to Figure Ie. The word 108 contains the designation information relating to the data set. The data-

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Descriptors 102, 104 and 106 included in the remaining Bit positions further information, which refer to tables and the absolute address of the operand, e.g. B. the to defining data set ^ develop. The address syllable AS des Instruction 100 is developed to match two words, e.g. B. one of the VJorte 102 to 106 and the word 108. One of the words. 102-106 is used to determine the operand and word 108 describes the characteristics of this Operands, as will be seen below.

In word 108, bits 32 to 34 identify a bit string, which offers the user the possibility of packing the information of his files tightly in the form of bit strings. Bit 35 must always be 0 and is irrelevant in connection with the present invention. Enter bits 36 to 38 an array, and bit 39 refers to a changeability indicator bit, which is also not used in connection with the present invention.

Bits 40 to 63 of word 108 determine those parts of the Data field descirptors, which describe the characteristics of the operand in the database. In particular, bits 40 through 47 determine the data type of the operand. The data type is a description of certain characteristics of the information format intended by the user. For example, in the 8-bit data type field, the The following codes can be used with the following meanings: A binary code from 0000 0000 refers to an alphanumeric string, a binary code of 0000 0001 indicates an unpacked decimal number and a binary code of 0000 0010 indicates an packed decimal number. It has been found that 90 to 95% the data record determinants ,, z. B. the labeling information result from the aforementioned data field types. As a result, other representations of the information format, as provided by the user, should be replaced by the

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system described here are not covered. The data type encodings from 0000 1010 to 1000 0000 indicate an illegal data type coding, and the data type coding 1000 0000 to 1111 1111 identify data types which are used for other purposes Are available.

Bits 48 to 55 determine the code field of the operand. The key field describes certain features of a particular one Data type, ζ. B. the data type format of the operand. That The code field thus represents a second overlay of requirements for the data type. In the present situation, where the identification part of the record is the address of the storage location of the particular data record sought is generated, the identification key data field descriptor is not used.

Bits 56 through 63 of word 108 provide an 8-bit length description of the operand to be looked up. In particular, the length field determines the number of bytes that the operand contains having. If a byte string is present, the length of the operand can be less than or equal to 256 bytes. In the fore. lying case becomes the one triggered by the control order The operation is always carried out on the basis of a byte string so that in the event that the operand length exceeds this limit, there is an illegal data exception.

The mode of operation of the command 100 shown in FIG. 1 a, as well as the data descriptors resulting from the address of the command 100 according to Figure Ie can be better understood if the block diagram of Figure 2 is used as a basis, which Figure 3 illustrates a data processing hardware system making use of the invention.

According to FIG. 2, a main memory 201 consists of 4 modules of a metal oxide semiconductor memory (MOS). The 4 memory modules 0 to 3 are via a main memory sorter 202 to the central

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unit 200 connected. The 4 main memory modules 0 to 3 are still via the main memory sorter 202 and a Input / output controller 220 (IOC) to a peripheral subsystem connected, which consists for example of magnetic tape units and disk drive units. Of the Main memory sorter 202 offers the possibility of accessing and controlling all 4 main memory modules. Since the operation of the main memory sorter 202 may overlap with the cycling of the main memory, each at a given point in time, more than one memory module 0 to 3 can be cycled through. The central processing unit 200 (CPU) and a buffer memory 204 and the input / output control unit 220 (IOC) can use a double word (8 bytes) for each memory reference. to process. However, the central unit either the 4 high order bytes or the 4 low order bytes are selected, leaving only 4 bytes of information can be received by the central processing unit 200. The operations of the central processing unit are stored in a read-only memory ROM controlled, hereinafter referred to as control storage unit 210 is. Each memory location of the control memory 210 can can be used to control a central unit cycle. When reading out each memory location of the control memory unit 210 the corresponding information content is decoded by a micro-operation decoding function. Any micro-operation decoding function causes the central processing unit to carry out a specific operation. For example, the data bits 1, 2 and 3 are read out and decoded with 010, they trigger a micro-operation decoding function which does the shifting of the content of a Α-register after a B-register. Since each storage location of the control storage unit 210 is 30 to May contain bits, a variety of micro-operation decode functions can be initiated on each control store cycle.

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By arranging storage locations in groups, steps can be made of the control memory is achieved by means of a specific operation or command with respect to the central unit is performed. Since each command is sent by the central processing unit 200 is triggered, certain bits within the operation code can be used to determine the start sequence of the control store to determine. The checking of certain flip-flops, not shown, which are set by a command decoding function or reset, allows the tax store, if necessary, a branch to a more specific sequence of steps.

The control store interface adapter 209 is available for control the operation of the control memory with the control memory unit 210, the data management unit 206, the address control unit 207 and the arithmetic unit 212 in communication. The control store interface adapter 209 has Logic circuits for a control store address modification, for testing, for error checking and for a hardware address generation on. Hardware address generation is generally used used to develop the start address of error sequences or for an initial sequence of steps.

The buffer memory 204 is used to store the information previously most frequently used in the processing by the central processing unit 200. The buffer memory is relatively small, has a very high operating speed and includes 128 columns and 2 rows, the two rows neighboring _t the following as the upper and lower line are indicated. The buffer memory is logically divided into preset blocks, which can be uniquely addressed. These blocks are labeled pages and each memory page contains 3.2 bytes of information. A particular page can be represented by the most significant 16 bits of the

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-η.

Main memory addresses are addressed, with the 5 being the least significant bits are used to represent a special byte of the Address information within the page. The pages can be transferred from the main memory to the buffer memory, a fixed column assignment is maintained, e.g. B. a page from column 1 in main memory is always in the column

1 of the buffer memory. The decision, however, whether the information should be stored in the top or bottom row of the column depends on availability. Two pages are provided in the buffer memory for each column of the main memory pages. For example column 37 in main memory can be any of

2 pages of information contained in 'column 37 of the buffer memory. The 2 pages of information contained in the buffer column depend on which pages at any given time have previously been widely used by the central unit, d. H. the two most frequently used pages previously are typically in buffer memory 204.

Whether a predetermined information page is in the buffer memory 204 can only be determined by checking the contents of the buffer memory address list 205. The buffer address list is logically divided in the same way as the buffer memory, but each column of the buffer memory address list 205 contains the main memory row address of the associated information in the buffer memory 204 instead of information pages. For example, if column 0 of buffer 204 contains page 20 in the bottom line and page 0 in the top line, then the buffer has memory? Addresses in the lower and upper lines have the codes 10100 and 00000 accordingly. Thus, by accessing the buffer memory address list 205 with the column number and by comparing the required line number with the line number stored in the memory location of the buffer memory address list, the central processing unit 200 can determine whether a specified page is contained in the buffer memory.

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The data management unit 206 provides the data interface between the central processing unit 200 and the main memory 301 and / or buffer memory 204. During a memory read operation information can be read from the main memory or buffer memory. It is the responsibility of the data management unit 206 to distribute the information in the registers of the central processing unit at the appropriate time. The data management unit 206 continues to do the blanking during partial write operations.

The command fetch unit 208, which with the data management unit 206, the address control unit 207, the arithmetic unit 212 and the control storage unit 210 cooperate is for is responsible for supplying the central unit 200 with commands. The instruction fetch unit 208 seeks to receive the next einstruction in take their registers in before the current instruction is finished. To have this ability is that Instruction fetch unit 208 equipped with a 12 word instruction register. which can normally accommodate more than one command. In addition, the instruction fetch unit 208 requests, under the control of the control memory 210, commands from the main memory 201, before this instruction is actually needed, which creates the 12 word instruction register is continuously updated. The instructions are fetched using normally unused memory cycles. the Instruction fetch unit 208 decodes and informs each instruction other units about the length and format of the command.

The address control unit 207 is above the control store interface adapter 209 with the instruction fetch unit 208, the buffer memory address list 205, the main memory sorter 202, the arithmetic arithmetic unit 212, the data management unit 206 and the control storage unit 210 in communication. The address control unit 207 is for any address development

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responsible within the central unit. All operations of the address control unit are controlled by control store microinstructions and logic circuits carried out within the unit. The normal operation of the address controller is more dependent on the type of addresses of the command than on the type of command itself. Depending on the address type, the Address control unit can perform different operations for each address of an instruction. ·

The address control unit 207 further contains an associative memory, which is typically the base address of the 8 previously most frequently used memory segments along with their segment numbers saves. Every time a memory request is made, the segment number is stored with the contents of the associative memory compared to see if the base address of the Seg- ■ mentes. is already developed and saved. If the base address is contained in the associative memory, this address is used in the absolute address expansion and it becomes saved a considerable amount of time.

If the base address is not contained in the associative memory, it is developed by accessing the main memory tables. ' After the segment's base address is developed, it is stored along with the segment number for later reference stored in the associative memory. -

With the address control unit 207, the command fetch unit 208 and the control storage unit 210 is connected to the arithmetic processing unit 212, which is the primary work area of the Central processing unit 200 represents. The basic function of the arithmetic Computing unit 212 consists in carrying out the arithmetic operations and the data manipulations required by the central unit. The operations of the arithmetic processing unit 212 are completely dependent on the microinstructions of the Control storage unit 210.

5 0 9 8 2 570 9 A 6

The arithmetic processing unit 212 and the control storage unit 210 is assigned an internal storage unit 211, which consists of a 256-space solid-state memory and the corresponding selection and read / write logic circuits for the memory can exist. The internal memory 211 is used to save the control and availability information of the central unit. The internal memory 211 also contains Work memory locations / which are primarily for the temporary storage of operands and partial results during data manipulation to be used.

The central unit 200 typically contains 8 base registers which are arranged in the arithmetic unit 212 and which are used in the address calculation method to determine a segment number, an offset and a ring number. The offset is an indication within the segment and the ring number is used in the address validity calculation to determine the access rights for a special reference to ' to determine a segment.

The input / output control unit 220 represents that part of the data processing system .dar that provides a data path between a Number of peripheral subsystems and the main memory. The control unit establishes the communication link via which peripheral commands are triggered and it controls them resulting data transfer. The input / output control unit can process a maximum of 16 channel control units and each channel control unit can act on a peripheral control unit. The peripheral control units also supply the central unit the files of the users.

According to Figure 3, a flow chart is shown from which the general rules for using the control command and the data field descriptor according to FIG. 1 emerge. Will figure 3 in

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Read in connection with Figures 2, 4 and 5, the Overall operation of the data processing system understandable. Figure 4 is a schematic diagram showing the transmissions, and illustrates the manipulations of the data field descriptor according to FIG. 3 and the control operation according to FIG. 5 at the system level. FIG. 5 shows a flow chart of the general rules regarding the use of the control command.

According to FIG. 3, the reference numeral 300 denotes the start of the operation with regard to the control command. To this Time is the command 100 according to Figure la in the command register 400 of the command retrieval unit 208 according to FIG. The opcode is provided by the control store interface adapter 209, which in turn examines the control storage unit 210 to perform a series of tests for selected bit fields of the command. These tests are performed on the basis of microinstructions generated by the Control storage unit 210 are generated. The results of these tests can lead to the fetching of the next microinstruction of the "control storage unit" 210 modify so that more involved, the determined State containing microinstruction is generated. It is obvious that a micro-branching technique was used with the signals received by the control store interface adapter 209 into a direct address signal the control storage unit 210 can be implemented. The resulting operation creates a direct path of conduction for a subsequent data transfer, taking into account the previously established state. The above The sequence of events mentioned occurs with respect to each diamond representation in Figures 3 and 5 and will not be discussed below described in more detail. .

In step 302, bit field 11 is checked for the presence of the. Binary value "0" examined. If this test is successful, then

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In step 304 the bit field 12 is examined for the presence of the binary value "1". Steps 302 and 304 become simultaneous executed. If one of the bets required in these fields is not present, an illegal format field exception is raised in step 306 caused, which the control storage unit 210 together caused by the control store interface adapter 209 to execute a hardware exception routine. this will Realized by a branch in the, control storage unit 210 and the appending of a message, whereby the nature of the occurred Exception is displayed.

Bit 11 has the binary value "0" if two general registers GR are required with regard to command 100 according to FIG. If bit 11 has the binary value ¹¹ O ", the next general register GR is used, which has the same first three bits and the binary value" 1 "in the fourth bit position. Two general registers are required for a data field descriptor , since one register stores the effective address as it is developed from the instruction and the second register stores the extended data descriptor according to Figure Ie,

Bit field 12 indicates whether with regard to the address development indirect addressing with the address syllable is required. In the present example, the bit field 12 is on examines the presence of the binary value "1", which indicates that an indirect addressing method is required. In this context, the segment address development mentioned earlier must be taken into account, as these are the exact ones for which Development of an indirect address syllable describes the necessary rules.

Once it has been established that an extended data descriptor is to be developed and that the indirect addressing process is required, step 308 according to FIG. 3 is carried out.

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Any known indirect addressing technique may be used in step 308, such as that described in U.S. Patent No. 3,412,382. For the sake of completeness , this known indirect addressing method will be briefly discussed.

In step 308 it is thus determined that an address development with the present address syllable, d. H. is to be executed with bits 12 to 31 of command 100. The address syllable is used to designate an operand in memory by means of a base register. The segmented effective The address of the operand is derived from the content of the address syllable and the content of the base register determined by the address syllable developed. Once the effective address has been calculated, it identifies that containing the data descriptor. Segment. The data descriptor is a first word from the group of words as shown in Figures Ic to Ie.

The first word of the data descriptor has a hint field with bits 01, which indicates that the data descriptor not only indicates an operand, but also has a length greater than a word. This additional word, e.g. B. the extended data descriptor 108,. describes the characteristics of the operand, which is replaced by the first word is determined. . ...

The first word of the data field descriptor contains a to the Storage space of the segment (STN and STE) indicating information, and a relative shift to indicate where the operand is stored in the segment. Through another address development The absolute address of the operand is then calculated and stored via a base register. It should be pointed out that the actual main memory address is related to the absolute main memory address through the use of tables.

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The effective address, ζ. B. the first word is below designated with Xl and should be distinguished from the address syllable and the absolute address, since each of these in different Units of the central unit is stored. The address syllable thus determines the data descriptor, which 2 words having. The first word identifies the operand and the second word describes the characteristics of the operand.

In step 310, an effective address, as shown in FIGS. Ib to Id, is stored in register 404 of FIG Address control unit 207 is stored. The control store unit 210 together with the control store interface adapter 209 then checks whether the information field of the effective address has the coding 01 in its first two bits. These notice bits determine an extended data descriptor 108 which contains the descriptors of the operand. Indicates the hint field the bit constellation 01, then that shown in Figure Ie Word from main memory 201 or the buffer memory 204 read out. After this word has been read out, it is brought into the data management unit 206 via the DN register 402. The word is then transferred from the data management unit to the internal memory unit 211 and in a Working register of a buffer memory 406 is stored. If the bit constellation deviates from the value 01, the control storage unit branches 210 after an exception state, as shown in Step 312 is shown which causes an illegal data descriptor exception is marked. This exception condition is created in the same way as the previously mentioned illegal format field exception treated.

Assuming that the descriptors have an oil hint field, step 314 is executed. In step 314 the extended data descriptor according to FIG. 1e, as shown in FIG the main memory 406 of the internal storage unit 211 is stored is under control of the control storage unit 210

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transferred to an AC register 408. Regarding the AC register 408 it is possible to select any byte from this and to subject this byte to certain tests. this may be accomplished by a selection mechanism 428 which picks out any byte in the AC register 408 or by shifting the contents of the AC register to a predetermined one Digit and subsequent transmission of this byte. These features are not described in detail as they are in the prior art Technology are well known.

In step 314 use is made of the features described above by specifying the data type, i. H. bits 40 to 47 of the word 108 that are in the AC register are transferred to an AA register 412. The AA register 412 is part a byte calculator 410 which performs simple parallel addition and subtraction in accordance with the microinstructions of the control storage unit 210. The byte calculator 410 can any parallel adder or subtracter as are well known in the art. Within the Byte computer 410 is an AG register 414 and logic circuits 416, which perform the arithmetic calculations on the selected byte fields. Step 314 is continued with the Data type byte in register 408, which was selected by selection mechanism 428, performed. This byte is then transferred to the AA register 412 of the arithmetic processing unit 212. At the same time, the control storage unit 210 a constant is loaded into the AG register 414. In this case, the constant is a binary-coded 3, which is determined by the bit constellation 0000 represents 0011. Logic circuitry 416 then performs a subtraction with the contents of the AA register and the AG register. The result of this subtraction is detected by the control store interface adapter 209 and the control store unit 210 determines whether the data type for the control command is appropriate or not.

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If the subtraction result is greater than or equal to zero, e.g. B. So a positive number, then step 316 according to Figure 3 executed. In this step the "in the · AG register 414 .being constant through the binary-coded number 6, i.e. H. replaced by the bit constellation 0000 0110 and, it becomes a subtraction is carried out again. Depending on the result of this subtraction, either a branch to carried out in step 320 or in step 318, wherein a test condition is generated by the control storage unit 210. If the value of the received data type is less than 0000 0110, a termination routine according to step 318 is carried out. This is achieved by entering a status code in the status register 418 of the arithmetic processing unit 212 accordingly a binary coded decimal number 3 is written. By the · status code of 3 indicates that intervention is required is to end the operation. This intervention is required if there is a processable data type, but a special subroutine for handling the processable data types is requested. In step 318, the status code of FIG interpreted by the control storage unit 210 so that the effective address Xl and the data field descriptor according to the general register identified by the address syllable according to FIG. la be transmitted. In the general register determined by bits 8-11, the word Xl, e.g. B. the effective address and the extended data descriptor 108 is placed in the next general register. An indication is given below that the control command has been carried out as far as possible which is indicated in step 324.

If the data field descriptor describing the data type is greater or is equal to the coded number 0000 0110, then step 320 according to FIG. 3 is executed. This step will performed by the control storage unit 210 a new Constants generated for register 414 and AA register 412 maintains the same information. Through the computing circuit

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a subtraction is then carried out with the contents of the AA register 412 and the AG register 414 and in the event that the subtraction result is 0 or greater than 0, the termination process in step 318 is performed. Is the subtraction result less than 0, the control storage unit 210 in step 322 an illegal data type exception is generated. In step 320 it is determined whether the data type for a special use is reserved.

At step 326 it is known that the operand, e.g. B. the identification number has a data type that is editable by the control command. Step 326 provides the logical Control command, which is based on the first word of the data field descriptor the specified operands.

Step 326 is shown in greater detail in FIG and will now be described in more detail. In Figure 5, step 500 indicates that the length descriptive Data field descriptor, e.g. B. bits 56 to 63 of word 108 is handled. This step is performed by the Selection mechanism 428 addresses the last byte within AC register 408 and transfers this byte to AA register 412. " The length characteristic indicates the number of bytes in the operand.

The control command handles each of the 3 legal data types in form ^; a byte string. Since the control command affects groups of 4 bytes, the byte character strings must be examined to see whether they represent an integer multiple of 4 bytes. If the length of an alphanumeric string of a packed decimal number or an unpacked decimal number does not represent a multiple of 4, the data field must be supplemented by bytes with the value "0". If, for example, a byte is left over and is to be processed by the control command, 3 bytes with the value "0" must first

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2A58331

to be added. With regard to the packed decimal representation, the length can have an operand of half a byte. If this occurs, 4 bits with the binary value ¹¹ O "are added to the first part of the operand, whichever is read into the isolation register to be explained below.

It should be noted here that the packed decimal format comprises a series of contiguous bytes, each byte having two 4-bit number encodings contains, with the exception of the byte furthest to the right, which is a number coding and a sign coding having. The unpacked decimal format consists of a series of contiguous bytes, with each byte representing a zone and has a digit coding. For both formats, the digit coding represents the size representation of a decimal whole number Thus, with an unpacked decimal representation, a decimal integer is encoded by a byte, while with a packed Decimal representation two decimal whole numbers can be encoded by one byte. For an alphanumeric string each character is encoded by a byte.

Since the operation triggered by the control command depends on an exact determination of the length of the operand, the length described by the data field descriptor is significant The use of the length field in the extended data descriptor acts on a hardware mechanism in the address control unit, thereby ensuring that only the operand described by the length field is retrieved so that the same unique identification key address is always generated for direct access.

In step 502, certain operations are performed with respect to the length field now in AA register 412. First the number of words of the operand is determined,

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by dividing the number of bytes in the length field by 4. The division of the length field by 4 can be done by known devices. For example, the constant 4 can be loaded into the AG register 414 and subsequently subtracted from the content of the AA register 412 via the arithmetic circuit 416. After each subtraction step in which the value in the AA register 412 remains positive, the content of a temporary storage register in the main memory 406, which is referred to below as N, can be increased by 1. The N register thus indicates the number of words in the operand subjected to the control command. The content of the N register is then brought into the AA register and a further subtraction of this content from the content of the AG register 414 is carried out. If that is in
stored in the AA register. Result becomes negative, the
remaining remainder, e.g. B. the value from which the constant.4 could not be subtracted ·, stored in a second temporary working register in the main memory 406, which register
hereinafter referred to as the R register. In this way
registers N and R contain the length information of the operand and are used to control the stochastic method according to steps 506 and 528.

In step 502, the absolute address X of the operand is transferred to the working register S of the working memory 406. Here, the absolute address X is transferred from the main memory 201 to the
Data management unit 206 is read out via the DN ^ register 402. The word is then transferred from., The data management unit 206 to
the internal memory unit 212 and stored in the register S. The number of words of the operand is thus indicated in the main memory 406 by the. N register, the remaining bytes of the operand by the R register and the operand itself by the S register.

In step 504 the »by the control command according to FIG certain contents of the general register GR are transferred to a circulation register 420 according to FIG. The content of the general

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Register GR is given by a constant, which the search of data sets within the same secondary storage. This constant can be changed after the data set distribution has been investigated. This investigation can be carried out through a utility program not described here which generates a statistical report on the data set distribution, giving the user the determination the number of records allowed in each page of the file. Based on this statistical report, it is then known how close the identification key address for direct access generated by the control command comes to a Poisson distribution. If the resulting distribution is unfavorable, the initial constant can be changed. The constant acts on that Result, so that a more favorable distribution of the data sets within the file is generated. Optionally, the number the pages that store the data records are subject to change. .

The stochastic method used by the control command is functionally represented in steps 506 to 522. In particular the operand indicating the total number of words is subjected to a test for the value 0 in step 506. This test can be done by adding the value of the N register to the AA register 412 of the main memory 406 is transferred. The AG register 414 is loaded with the constant 0 and the logic circuit 416, under the control of the control store unit 210, subtracts the value of the AA register 412 from the value of the AG register 414. The result is then passed through the control store interface adapter 209 is detected, and if this result is 0, step 520 is carried out. The case that a to be chosen However, the record that is so small is relatively rare. The value of the content of register N is generally greater than 0, so that step 508 is executed.

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In step 508 the value of the N register, e.g. B. the number of words to be processed, stored in the AA register 412. A constant with the value 1 is stored in the AG register 414 is loaded and a subtraction is performed by means of the logic circuit 416, and it becomes the subtraction result transferred back to the AA register 412. The operand determined by the absolute address is used with regard to its first 4 bytes, d. H. fetched for its first word and stored in isolation register 422, which register follows referred to as the IR register. At this point the Address incremented by 4 so that it points to the next word to be retrieved. Thus at this point the first word is the Operands stored in isolation register 422, and the absolute Address points to the first byte of the next word to be fetched.

In step 510, the contents of... Of the circulation register 420 shifted 19 bits to the left. The circulation register 420 can be implemented as a known shift ring register, which a circular displacement of its content is permitted. By shifting the contents of the circulation register by 19 bits to the left, the position of the information previously subject to high usage is changed. This operation is going through the control storage unit 210 is executed.

In the next step, the control storage unit 210 causes an addition, the contents of the CR register and the IR register can be added together. A word calculator 424 is used for this purpose. The result of the addition is then stored back in the circulation register 420. If there is an overflow, e.g. B. if the addition of the CR register and the IR register results in a carry, the carry bit is added to the lowest bit in the CR register. this will performed by storing the overflow ^ bit in a register 426 and subsequently an addition between the content

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of the CR register 420 and the contents of the register 426 the result of this addition being stored in the circulation register 4 20. The control store interface adapter 209 checks whether there is an overflow condition and in the event that this overflow condition is present, initiated he branches the control storage unit 210 to another addition microinstruction which contains the contents of the IR register leaves untouched.

The one's complement of the CR register is formed in step 514. This is done by writing the binary value "1" in all digits of the carry register 426. The contents of the circulation register 420 are then subtracted from the contents of the carry register 426 and the result is transferred back to the circulation register 420. Other methods known in the art may as well be used to form the one's complement.

The value of the one's complement stored in the circulation register 420 is then shifted 18 bits to the left in step 516. This shift is done in the same way as this has been described with reference to step 510. The value obtained in this way is then transmitted via the word calculator 424 in step 518 added to the same 4-byte operand in isolation register 422. As was the case in step 512, the overflow is if any, stored in register 426 and another addition of the carry with the lowest bit is made carried out within the circulation register.

The reason for the above steps is in creation to see a stochastic number, the bit positions of the operand, which have a high degree of use, used v / earth. By changing the bit positions in steps 510 and 516 there is a shuffling of the bit positions achieved.

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After step 51S, step 506 is carried out. In this step is the new one contained in AA register 412 Checked for the value O. For example, if the operand had 5 bytes, the value in the N register results number to 0 so that step 520 is carried out. If the operand was much larger, the steps explained above, i.e. H. steps 508-518 are performed.

In step 520, the value in the R register is taken from the main memory 406. This value is then used in the Register 412 stored. If the number of bytes was equal to 4 ", there is no remainder and step 524 is triggered. This result is checked by loading the AG register 414 with the value 0 and this value from the contents of the AA register 412 is subtracted and by the control store interface adapter 209 then checked the result of the subtraction.

If the content of the R register is not equal to 0, it must have 1, 2 or 3 bytes. In step 522, the control store unit, in conjunction with the control store interface adapter, determines how many bytes remain. This is done by loading the AG register 414 with the binary value "1" and continuously subtracting this value from the contents of the AA register 412, the AA register 412 containing the value of the R register. As soon as a 0 is determined during the subtraction, the control storage unit 210 knows the number of bytes used. The control storage unit 210 then adds zeros to the IR register 422 for the remaining bytes. Steps 510 to 518 are then carried out. If both the contents of the N register and the R register have the value 0, then step 524 is triggered. In step 524 the contents of the circulation register 420 are shifted 17 positions to the left. This is done in the same way as in step 510. Likewise

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the addition of the contents of the circulation register 4 20 to the contents of the IR register 422 in step 526 in the same Manner as in step 512 performed. These steps serve a further stochastic distribution of the operand.

With the stochastic distribution now stored in the circulation register 420, the control storage unit initiates 210 transferring the contents of the circulation register back to the general register in step 528. This in general Contents stored in register GR, now specifies the identification key address for direct access through which the memory location of the data record in the secondary storage is determined.

If there is a requirement to monitor two data sets, the general register can contain a constant, which is derived from the stochastic distribution of the first data set, as illustrated by step 528, and the second data set can be introduced via the isolation register .422. This situation occurs when, for example an employee is employed in different departments of a company. It may be desirable to have your account number with the various department numbers in which he was employed. By processing the Department number and creation of a constant in the general register, results in a new combination, whereby the specific searched record is set in the secondary storage.

A multiplication or division is then carried out on the operations specified by the control command. Of the The first value in this calculation is the value contained in the general register, and the second value is the number of Pages contained in secondary storage. The overflow number resulting from the multiplication or division, e.g. B. the Number greater than the 32nd bits or the remainder at the division, can be stored in a second general register will. This value identifies the final page, which the

saves the data set searched for.

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When more records are to be processed than one page contains an overflow technique. For this- can any method known in the art can be used.

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Claims (28)

Claims (lj / method of addressing one in secondary storage stored data record / marked by the following steps: Storage of a data field of a data record as well as of Data field pescriptors, which define the characteristics of the data field determine, whereby the data field uniquely identifies the data record in the secondary storage, Check by means of the data field descriptors whether the data field can be used within a data set to find the data set Genus lies and Control of the data characteristic in a stochastic process, with this control step creating an identification key address for direct access that enables the discovery of the data record in the secondary storage. 2. The method according to claim 1, characterized in that the control step takes the following measures includes: Determination of the number of 4 bytes in the data field and Determination of whether less than 4 bytes remain in the data field. 3. The method according to claims 1 and 2, characterized in that the control step comprises the following further measures: " Transfer of 4 bytes of the data field to a first register, transfer of one contained in a general register Constants in a second register and execution of predetermined actions on the two Register for the stochastic handling of the data field. 509825/0946 4. The method according to claim 3, characterized that the predetermined measures include the following steps: Shifting the content of the second register by a first predetermined number of positions, Adding the content of the second register to the content of the first register, Storage of the addition result in the second register, Completion of the content of the second register, shifting the content of the second register by a second, predetermined number of positions, Adding the content of the second register to the content of the first register and Storage of the addition result in the second register 5. The method according to claim 4, characterized in that the predetermined measures follow further steps include: Transfer of the next 4 bytes of the data field to the first Register and Repeat the measures of the mentioned control step until each of the mentioned 4 bytes of the data field has been dealt with. 6. Method according to claim 5, characterized in that after the treatment of all of the 4 bytes mentioned, the remainder of the data field is subjected to the following measures: Transfer of a constant to the one not used by the data field Byte storage locations of the first register and repetition of the measures of the control step mentioned with regard to the remaining part of the data field. 509825/0946 7. The method according to claim 6, characterized that the control step continues the following Measures include: Shifting the contents of the second register by a third predetermined number of positions after the bytes of the Data attribute have been added twice to the second register, Adding the content of the second register to the content of the first register, Storage of the addition result in the second register and Transferring the contents of the second register to the general one Register. - 8. The method according to claims 4 and 7, characterized in that that the first, second and third predetermined numbers of positions in terms of the content shift of the registers are different from each other. 9. The method according to claim 4, characterized that each of the said adding steps is the addition of one from the addition to the lower-order Bit of the second register includes approximately resulting overflow. 10. The method according to claim 1, characterized in that the data field descriptors describe the data type and the length of the data field. 11. The method according to claim 10, characterized by determining whether the data type represents an alphanumeric character string, an unpacked decimal number or a packed decimal number. 509825/0946 245-331 12. The method according to claim 11, characterized by the following test steps: Storage of the length field in a third register, division of the length field of the data field descriptor by 4 for the purpose of determining the number of bytes of the "data field and" to be continuously transmitted
Storage of the remainder of the division in a fourth register. 13. The method according to claim 12, characterized 'indicates that the control step following further Measures include: a gradual decrease in the content of the first register, after a set of 4 bytes has been transmitted, and a check of the third register as to whether its content is zero wearing. ·, 14. The method according to claim 13, characterized. marked that the control step is a gradual. Includes lowering the contents of the fourth register to Hull, if, the content of the first register is zero and the remainder of the length field - if available in the second register has been transferred. 15. System for carrying out the method according to claim l _r wherein the secondary memory is divided into a number of memory sections called pages, each page contains several data records and wherein some of the data records are assigned a data field which uniquely determines the data record, characterized by a memory for storing each data field of the data sets and associated data field descriptors, which the marker. times of the data field, "... a device for generating a control command, a first device, which is dependent on a first part of the control command, for searching for a data field assigned to the data field Data field descriptors, 509825/0946 a second device, dependent on a first word of the data field descriptor, for looking up the data field and one dependent on a second part of the control command Computing means for computing-in accordance with a second word of the data field descriptor ~ a passkey address for direct access to the data field, the identification key address being a page that stores the data record of the secondary storage. 16. Plant according to claim 15, characterized in that by the data field descriptor The features described relate to the data type and the length of the data field. 17. Plant according to claim 16, characterized in that the data type feature encodings for comprises an alphanumeric string, an unpacked decimal digit, and a packed decimal digit. 18. Plant according to claim 15, characterized d u r c h an additional, from the control command to Checking the characteristics of the data field descriptor dependent device to decide whether a given data field can be processed by the computing device. 19. Installation according to claim 15, characterized in that the identification key address for direct Access to write in and retrieve the data set is used. 20. Plant according to claim 15, characterized by a third, from a third part of the control command dependent facility for finding one, an initial constantc containing register, wherein the arithmetic unit the initial constant with the data field for the purpose of generation concatenated to the passkey address for direct access. 509825/0946 21. Plant according to claim 20, characterized by a device for changing the initial constant in order to achieve a more favorable distribution of the data sets in the secondary memory. 22. Plant for performing the method according to claim 1 with an internally programmable data processing system, which is controlled by commands read from the main memory and for looking up data records in a secondary memory by means of a device which uniquely determines the data record in each case Data field is used, marked by a memory unit which, on the basis of the commands received, logic control signals for the execution of micro-operations in the logic circuits of the system generated, a storage, the data field of the data set and the assigned data field descriptors in the main memory, a device for looking up the data field via the. ordered data field descriptor depending on a command type and '. a device for executing the one type of command under Control by the control storage unit, one type of instruction together with the assigned data field descriptors calculates an identification key address for direct access to the data field; thereby its storage space in the secondary storage is fixed. 23. System according to claim 22, characterized in that one type of command is a control command is. 24. Plant according to claim 22, characterized in that that the control storage unit as a function of the control command the data field descriptor a test to determine whether the control command is executable with respect to the data field. 509825/0946 25. Plant according to claim 24, characterized in that that the data field descriptor stores the data • Describes the type and the data length of the data field. 26. Plant according to claim 22, characterized., that the means for searching the data field comprises: a first register,
a second register, a device for selecting the first register, which is responsive to a first part of the control command, second means for looking up the data field descriptor, wherein the control storage unit stores the contents of the first Register chained to a second part of the control command,. " a third to the part of the first word of the data field descriptor appealing facility for selecting the second register and a fourth device for looking up the data field of the Data record, wherein the control storage unit combines the content of the second register with the content of a second part of the first word of the data field descriptor. 27. Plant according to claim 26, characterized by a third register containing an initial constant, a selection of the third register via the control storage unit by means of a fourth part of the control command, the control storage unit dividing the data field in 4-bit sections transfers to a fourth register and a shift and addition of the content of the fourth register to the content of the third register for the purpose of forming the identification key address causes for direct access. 509825/0946 28. Plant according to claim 27, characterized in that that the third register is an isolation register and the fourth register is a circulation register is. ' 50982 & / 0946 HO Blank page