DE2334528A1 - DEVICE FOR SYNCHRONIZING A RECEIVER OF NUMERICAL INFORMATION - Google Patents

Description

DR.MÜLLER-BORE DIPL .-? HY £. DR. MAMTZ I) IPL-CHEM. DR. DEUFEL DIPL.-ING. FINSTERWALD DIPL.-ING. GRÄMKOW

PATENT LAWYERS ~ «ο / C O O

Munich, ^{July 6th} Hl / fe - C 2745

CJOIiPAGHIE ninJS'ÜKIELLE DES ■ jELEGOH-UlilCSDIOIiS GIi-ALGAi ¹ EL 12 rue de la Baume

c Paris / France

Device for synchronizing a recipient of numerical information

The invention relates to the reception of information which are coded in a group of consecutive pulses, each one of which is identified by its rank in the group has a certain information content.

The invention relates to a device that enables the beginning of the code word, which is, for example, a received Level encoded, and thus each impulse to be identified

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Dr. Müller-Bor Dr. Manitz Dr. Deufel Dipl.-Ing. Finsterwald Dipl.-Ing. Grämkow Braunschweig. Am Bürgerpark · · Munich 22. Robert-Koch-Straee 1 7Stuttgart-Bad Cannstatt. Marktstrasse 3 Telephone (0831) 73 · «7 Telephone JOWD 2936«. Telex 5-22050 mbpat Telephone (0711) 587261 Bank: Zentralkaeee Bayer. Volksbanken. Munich, account no. 9622 Post check: Munich 95-WS

to give correct weight so that everyone received sample an amplitude is assigned which corresponds exactly to the amplitude of the sample taken during transmission, or more generally to give each impulse an information content that corresponds to the coding when it was transmitted (for example the primary color in three-color color transfer). the Invention is applicable to the synchronization of messages, by numerical transmission, for example in the MIC raster (trame MIC) or quantization of a group signal is received in a frequency division multiplex; she is also applicable to the encryption (cryptage) of messages or the formation of error detector codes.

When receiving quantized levels / lsi; with η Bis, ie with (2 ³¹ ^ i) other than zero, since aer ^{a (} cäiaraln; e ^I r of any transmitted information is essentially uncertain, the distribution of the bits is uncertain or Random Ensures synchronization.

In general, ösb lock word comprises several bits, the in the message are either continuous or distributed. The longer the locking word, the faster it gets identified in the received message.

In the case of transmitted messages that comprise q bits, the information is divided into segments of the same length with q cycle times using a counter of capacity q divided. When the counter is synchronized with the transmission, the bits of the

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Lock word found again at locations known in advance. In the opposite case, the bits of the locking word are not found in the predetermined positions. A Error detector, which is constructed in a suitable manner as a function of the interlocking word, then supplies a signal, used to restore synchronization.

For this purpose it is known to change the counting rate or the counting rate of the counter by either adding an additional Pulse or several additional pulses can be inserted between two cycle times or by a time cycle or several clocks can be suppressed or by switching on a delay line.

The procedure der'abrupten change of the cadence or the Clock at the input of the counter can lead to malfunctions in a counter that is operating at high speed (several megabits per second) 'works. The method of inserting the delay line is not flexible enough that it introduces an analog element into a numerical process, which is undesirable, all the less so as as a result of changes that experience a signal that is sometimes a little above the noise level, the receive clock control can be affected by an excessively long sequence (gigue), which is a delay line with a more rigid Education does not adapt.

According to the invention, action is taken in a different way: if the error detector detects an error, ie if there is no coincidence for a predetermined value, which is displayed twice in succession by the counter, between two successive code words extracted from two successive messages, which should be identical , then by means of a coincidence circuit the counter displays a

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forced to a predetermined value. This mode of operation is very fast, takes less than one cycle time and does not change the cadence or the cycle of counting. It is repeated until synchronization is achieved: from this moment on, the error detector no longer sends out a signal. Of the Forced or impressed displayed value is selected in such a way that that synchronization is achieved as quickly as possible.

In the case of a message word of a given length, the length of the locking word accesses the information word: if the locking word is longer, its determination is faster and more reliable, but is from the information word cut off as much.

In order to preserve the greatest possible fineness for the quantization of the transmitted or sent level, it is preferred the locking word is limited to a single bit. If, in a special case, the structure of the message is so is that a (single) bit is quasi-permanent with a very high probability, for example of more than 80% this bit can be used as an interlock identifier.

According to a preferred type of application, a tag bit from hang k is included in the message, which comprises a total of q bits is used, which is alternatively 1, O, 1, O, etc. With η Level bits, a sign or sign bit and a locking bit or synchronization bit thus apply q = η + 2. For example, for η = 9, the 11-bit message provides the codes from O to + 511 and from O to - 511.

The position of the lock bit, which has a predetermined rank k in the message, is indicated by a "time window."

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(fenetre de temps) "marked by a clock control timer Capacity q is supplied, the state k of which is determined by a decoder. If the change is 1, O, 1, O etc. is not observed, which is determined by comparing the content of the "time window" of two states k of the counter which are separated by an interval of q cycle times, the counter is reset by a command from the counter detector or reinstated.

To make a new comparison cycle like that. To be able to start again as soon as possible, the counter is advantageously in the State (k-1) returned: this appears in the Cycle time that immediately follows the reset, a time window k with which a new comparison process is started.

In order to avoid triggering a reset of the counter in the event of a temporary (harmful) fault, a precautionary rule is imposed: for example, a reset for three successive errors is triggered by means of a device for booking or "recording errors" (three times 1 on the output of the error detector); and the synchronization is considered to be restored if at least two successive zeros are present: the reset is not triggered in the event of a single error or two successive errors, but only in the event of three successive errors. If after three times Λ a zero resetting is suspended; if this zero is followed by a 1, resetting or resetting is immediately resumed; if this zero is followed by at least a second zero, this operation is terminated: to resume it must be repeated three times 1. Follow another ana Logical rule is also possible.

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The invention is illustrated below with reference to the drawing, for example described; in this shows:

1a shows an electrical block diagram of the entirety,

Fig. 1b shows a detail of the block diagram shown in Fig. 1a, in which a variant is shown,

Fig. 2 is a block diagram of an error detector,

3a shows a block diagram of an organ for booking or Registration of errors and

Fig. 3b is a table in which the advancement of information in an organ as shown in Fig. 3a is illustrated.

The following describes a device that uses a lock bit used with regularly changing value.

According to FIG. 1a, a message M containing q coded pulses arrives at 1. It is in a timing recovery organ 2, which is of a known type, for example a resonant circuit excited by shocks. That The reproduced clock control signal or synchronization signal H is applied to a counter 3 with the capacitance q. Of the Counter 3 is symbolically represented in the form of several bistable flip-flops, three of which are shown, from each of which has a terminal a for splitting to 1 and a terminal b * for resetting to zero.

The counter 3 has a decoder 4-, which has an output pulse for a state k of the counter 3 supplies. The status indicates the rank of a locking or blocking

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Bits in the message M. In the operating state, the output rate is or output sequence of the pulses from the decoder h = H / q.

An error detector 5 receives the message on one side M through a line y and the clock control or synchronization signal h on the other side.

If there are errors in the regular alternation of 1 and 0 in each state k of counter 3, this indicates that the state k of the counter does not correspond to the rank of the blocking bit in the message. The error detector 5 then sends a 1 to an organ 6 which books or records the errors, the structure of which is explained below.

The output of the organ 6, denoted by ρ, is either sent to a terminal a or to a terminal b of each of the counters 3 forming flip-flop is applied via a purely passive connecting element 7, which has as many outputs as flip-flops are present in the counter 3, the outputs of which are either connected to a terminal a or to a terminal b in the manner are connected that the counter 3 »when a signal 1 on the Line ρ appears, is led to the state (k - 1).

The output ρ of the organ 6 is on the other hand with an inhibiting input an AND gate 8, the other input of which is connected to the outputs of the counter 3, which is through a Line w are shown symbolically, on the successive pulses corresponding to the states of the counter 3 1, 2, q appear.

A distributor 9 known type, the message M via a

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Line y ¹ receives, also receives the output signal of gate 8 as an advance signal. It controls an equally known balancing circuit or weighting circuit 10 as a function of the rank of each bit (1, 2 ... q) in the message. The restored message is received at 11 at the output of the weighting circuit 10.

When the organ 6 reports an error to be corrected, it impresses the counter 3 via its output ρ via the connecting organ 7 shows the state (k-1). At the same time, the advance of the distribution circuit is made through the inhibition input of the gate ET 8 stopped.

In a simplified embodiment, the organ 6, the the error books or registered, omitted and the connecting element 7 directly to the output of the error detector 5 can be connected.

In Fig. 1b is a detail of the block diagram shown in Fig. 1a which corresponds to the case where, for example, in the case of an MIC raster with η paths, the The nature of the message changes from one route to the other, where a rank k of the synchronization bit can vary from one path to another. In this case, the "word" varies Reset ("mot" de recalage) (k-1) also from one way to the other.

Due to the simplicity of the means used according to the invention, it is easy in this case to replace the single connecting element 7 in FIG 6 (Fig. 1a) are connected, of which, however, only a single one for inhibition or fixing or backward displacement or resetting

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(Recalage) of the counter 3 is used by a step-by-step circuit 12, for example by a Raster demultiplexer (demultiplexeur de trame) 13 is controlled.

In Fig. 2 the block diagram of an error detector is shown, which is denoted by 5 in FIG. 1a.

It comprises a first bistable multivibrator 21 of type D and a second bistable multivibrator 22 of the same type as well like a circuit 23 comprising three AND gates 24, 25, 26, in which an OR EXCLUSIVE function is provided.

The message M arrives at the terminal D of the flip-flop 21. The terminal Q of the flip-flop 21 is with the terminal D of the flip-flop 22 connected, while the terminals C of the two flip-flops receive the clock control signal or synchronization signal h. The AND gate 24 is at its inputs with the outputs Q, Q of the flip-flops 21 and 22 connected. The AND gate 25 is at its inputs with the outputs Q, Q of the multivibrators tied together. The output of the third gate 26 is denoted by s.

As is known, a flip-flop of the type D reproduces an information existing at its input D at its terminal Q, if the rising edge of a pulse of a clock control signal applied to G arrives. If to two consecutive Times or cycles h at D of 21 signals of the same value arrive, which represents an error, a 1 appears for s

In Fig. 3a a logic circuit diagram of an organ is shown, that books or registers the errors. The precautionary rule (rogle de prudence) applied is the one given above

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233 ^ 528

and is listed in the table below. In the table, which has seven rows and four columns of 0 and 1, the column labeled P denotes the value of the last error signal at the output of the error detector, while the three columns to the left of it the value of the signal P at three previous clock control times indicate.

The additional column has an R, which indicates that a restitution or distribution or inhibition operation has been triggered by the configuration of the assigned row. According to the fourth line, if the first 0 appears after several ones, the inhibition is interrupted, but (fifth line) resumed if a 1 appears after a single 0. On the other hand (seventh line) a 1 after two zeros does not trigger any inhibition:

0 10 0

0 110

0 1 1 1 R.

1110

110 1 B-

110 1

10 0 1

The circuit comprises five flip-flops of type D, which are labeled A, B, C, D, E. They are interconnected in the form of a shift register, the output Q of a trigger stage of slope j being connected to input D of the trigger stage of range j + 1, except for the last one. The terminal D of the first flip-flop receives the signal from the output s of the organ 5, which is the error detector shown in FIG. The clamps. C of the five toggle stages receive the clock control signal h.

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-AA-

An AND circuit 31 has four inputs with the terminals Q of flip-flops A, B, G and terminal Q of flip-flop D. tied together. An AND circuit 32 has four inputs connected to the outputs Q of the flip-flops A, G, D, E.

A third AND circuit 33 receives the outputs of the circuits 31 and 32 and provides a signal J at the output, the on the one hand to the terminals a for resetting to 1 of the flip-flops A, B, G, D and a terminal b for resetting zero of the flip-flop E and on the other hand to the organ 7 O? ig. Ό is created.

This signal J is the logical function:

A.B.G.15 + A.G.D.E. equivalent to.

In Fig. 3b a table is given, the advancement of the accepted information in the stages of the four tilting A to E shift register formed to six consecutive Times ti - t6 under various assumptions that the new information arriving at A is either 1 or 0, as well as represents the "resulting value of signal J. The Signal 0 indicates that the trigger stage E is more indifferent Way has the state 1 or the state 0.

The states labeled X and Y follow one another.

Of the possible cases, only those that differ from the previously known cases are entered. After the first Line shows the effect of the signal J on the flip-flops. It has not been specified below, so as not to overload the table, and has none

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practical effect on the result.

The result corresponds to the table below.

The organ for posting or registering errors is only one example from other analogous cases.

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Claims (6)

Patent claims . 1) device for synchronizing a receiver of a transmission with coded pulses to a counter whose capacity q is equal to the number of bits o ^e d ^it is message and is made up of bistable multivibrators, the one terminal to reset to 1 and a terminal for Have reset to 0, with a decoder assigned to the counter, which can identify a time window of rank k, and with an error detector, characterized in that at least one passive connecting element (7) is provided which connects the output of the detector (5) with a Terminal for resetting to 1 or a terminal for resetting to 0 connects each flip-flop of the counter (3), so that the counter is transferred to a predetermined state in the event of a synchronization error detected by the error detector (5). 2. Device according to claim 1, characterized in that that the predetermined state is state k-1. 3. Device according to claim 1, characterized in that that an organ for booking or registering the error (6) between the error detector (5) and the connecting organ (7) is switched. 4. Apparatus according to claim 1 with a locking word consisting of a single bit, the value of which changes from a message to the following message, characterized in that the error detector (5) has two bistable flip-flops (21, 22) in series and one 309884/0590 OR EXCLUSIVE circuit (23). 5. Apparatus according to claim 3> based on a rule for Error registration is based on an error signal for three consecutive errors and a confirmation of the Synchronization for two consecutive times The absence of an error provides, characterized in that the organ (6) for registration the error is a shift register with five bistable multivibrators A to E and one of three AND circuits (31 »32, 33) formed coincidence circuit, the output J of which is connected to the connecting member (7). 6. Apparatus according to claim 1, characterized in that that several passive connecting members are provided, each of which is operated by a commutator can be set, which is positioned according to the rank of a path to be decoded in a grid (trame). 309884/0590 Blank page