DE2245688C3 - Transistor, suitable for digital electrical memory circuits, method for operating such a transistor and application in a circuit consisting of a memory matrix and decoders - Google Patents

Description

The invention relates to a transistor suitable for digital electrical memory circuits, with a channel and with a layered gate insulator, the transistor, its threshold voltage depends on the stored electrical charge in the gate insulator, in a fixed manner Substrate lying at potential is arranged, whereby the storage of the electrical charge or the deletion of a stored electrical charge by applying electrical voltages between Gate electrode and the substrate takes place.

The invention also relates to methods of operating such a transistor.

In Component Technology, VoI. 4. No. 5 of October 1970, pp. 17-21 is one Memory arrangement containing such transistors described. The matrix of this memory arrangement consists of MNOS transistors.

U.S. Patent 3,604,988 describes a transistor with a stacked gate insulator. This gate insulator consists of a silicon dioxide layer and a zinc sulfide layer.
However, such known arrangements have disadvantages. To switch the transistors when information is written in or to read and delete information, voltages of different signs are required with respect to the semiconductor substrate. In the case of memory arrangements using single-channel technology, the memory matrix and the associated decoders must therefore be built on substrates that are separate from one another.

Single-channel semiconductor technology is understood to mean a technology in which either only p-channel MOS field effect transistors or only n-channel MOS field effect transistors are used. As a rule, only a diffusion in the semiconductor substrate is required for this.
A memory arrangement has also become known from US Pat. No. 3,651,490 in which transistors with a layered gate insulator made of a silicon dioxide layer and an aluminum oxide layer (Al ₂ O ₃ ) are used. In the

Arrangement of these memory transistors in a matrix, as shown in Figures 6 to 9, for writing information or for reading and erasing also different voltages Polarities needed.

A three-dimensional memory arrangement has also become known from this USA patent, in the, as in the Γ i g. 1 and 12, for information writing and reading, respectively and erasing only voltages of one polarity are used. In Fig. 10 is the memory matrix this memory arrangement shown. However, each point in this matrix consists of one Storage transistor with a layered gate insulator and made up of a transistor that is not storing Possesses properties.

An object of the invention is to provide a transistor with a laminated gate insulator for electrical Specify memory circuits in which, depending on the stored in the gate insulator electrical charge, the threshold voltage with only one polarity between the gate, source and drain electrodes on the one hand and the common substrate on the other hand can be changed.

This object is achieved by a transistor as described at the outset, which according to the invention characterized in that both for storing and for erasing the in the gate insulator layer stored electrical charge voltages of the same sign between the gate electrode and the common substrate or between the source and drain electrodes and the common Substrate are applied and that the channel length of the transistor is shorter than double when Storage or barrier layer thickness that occurs when deleting.

Such transistors are preferably MNOS transistors which are applied to a common 10 ohm cm η-conductive silicon substrate. The gate insulator of the transistors consists of an approximately 2 nm thick SiO ₂ layer and an approximately 55 nm thick Si., N ₄ layer applied to it. The channel length of the transistors is advantageously 1 to 5 μm, and the voltages used for writing, reading out and erasing information are preferably 0 and 40 volts, respectively.

In terms of process technology, the object is achieved in accordance with claims 5 or 7.

An advantage of a memory arrangement with transistors according to the invention results from the fact that it is not necessary, as is the case with the stated prior art, the common substrate by diffused areas, such as those in complementary channel MOS technology or bipolar Technology are usually divided into electrically separate sections.

This advantage is particularly evident when using the transistor according to claim 4.

Further explanations of the invention can be found in the description and the figures of preferred exemplary embodiments the invention and its further developments.

F i g. 1 shows a schematic representation of an MNOS transistor;

F i g. 2 shows a schematic representation of a memory matrix made up of MNOS transistors; in

F i g. 3 are the storage characteristics of an MNOS transistor according to the invention with a short one Channel length shown; .

4 shows a schematic representation of a Storage arrangement with inventive transit

disturb. _T,. _ "" ·

In FIG. 1 is the substrate of the p-channel transistor, which is preferably a 1 G ohm cm substrate made of η-conductive silicon, denoted by 1. The p-guiding The source area has the reference symbols 2 and

ίο the p-conducting drain region has the reference symbol 3. νΛΓ, π ««, ««. These areas are in the substrate ι

These areas are preferably diffused into the substrate. The gate insulator of the transistor is layered. It preferably consists of a 2 nm thick SiO., Layer 4 and a 55 nm thick Si ₃ N ₄ layer 5 applied to it. The electrode of the source region is marked with 22, the electrode of the drain region with 33, the The connection electrode of the substrate is denoted by 11 and the electrode of the gate is denoted by 55.

The channel length 8 of the MNOS transistors according to the invention is shorter than twice the barrier layer thickness during writing or erasing. The channel length is preferably as indicated above and in FIG. 1 shown MNOS transistor 1 to 5 μπι. The barrier layer thickness is understood to mean the thickness of the space charge zone in the substrate around the source or drain region as a function of the voltage applied to the source or drain electrode. At the boundary layer between the SiO ₂ layer 4 and the Si ₃ N ₄ layer 5 there is a large number of terms 9 (traps) which are charged or discharged by different voltages of the same sign at the source, drain or gate. As a result, the transistor has either a high or a low threshold voltage. The threshold voltage is understood to be the voltage at the gate at which the transistor becomes conductive. These two states can be used to store the information »Ο * and» 1 «.

In FIG. 3 are the storage characteristics of a transistor according to the invention as described above shown with a channel length of 3 μπι. With 6 is the straight line when writing the state "1", with 7 the straight line when preventing the writing of a "1" and with 10 the working line when reading out. At 19, the Line of work for erasing, d. H. for writing the status »0« into an MNOS transistor with a large channel length. The curve 18 is the operating characteristic for the deletion in an inventive Short channel length MNOS transistor. As can be seen from lines 19 and 18, is at MNOS transistors with short channel lengths have an influence of the drain and source voltage on the gate voltage recorded.

To write a “0” into transistors according to the invention, the gate is set to 0 volts and the source and drain placed at -40 volts. When writing 60 a "1", the source and drain are at 0 volts, whereas -40 volts can be applied between electrode 11 of the substrate to the gate. Deleting Information written into a transistor is done by setting the state "0". Of the 65 The readout process corresponds to the write process. However, that applied to the gate electrode 55 is Reading voltage preferably -10 volts. Using a memory matrix with 2X2 transistor

The function of an MNOS memory matrix is now to be renamed explained. In FIG. Such a matrix is shown in FIG. It consists of the Transistors 14, 15, 16 and 17. Before starting operation, a "0" is first written into all transistors, d. that is, the entire memory is erased. For this purpose the gate lines 555 are connected 0 volts, source lines 222 and drain lines 333 at -40 volts.

Then the matrix is written line by line, for which purpose the "0" in certain transistors in a line is rewritten into a "1". If, for example, a “1” is to be written into transistor 15, then the potential -40 volts is applied to its gate line and also to the gate line of transistor 14. The supply voltage V _D , which is preferably approximately −20 volts, is applied to the drain line 333. The source lines 222 can be connected to ground via the switches 12 and 13. In order to prevent a "1" from being written into transistor 14, the corresponding switch 12 in the source line is left open. The inversion layer of the transistor 14 is thus at the potential of the supply voltage V _n . The gate voltage on line 555 of transistor 14 is not sufficient to switch transistor 14 to the “1” state. It remains in the "0" state. The switch 13 in the source line 222 of the transistor 15 is closed; the full gate voltage is between the gate and the substrate. The transistor 15 is switched to the "1" state. A “1” is thus selectively written into transistor 15, whereas all other transistors remain in their “0” state.

To read out the information, the read voltage is preferably applied to the relevant gate line the voltage -10 volts applied. The source line is read on OVoIt and the Drain line placed at preferably -20 volts. The transistors in the "0" state are then conductive, the transistors in the "1" state are blocked.

In the case of high-capacity memories, it is necessary in front of the individual gate lines that form the gate electrodes connect a row of the memory matrix to put a decoder so that the number of connecting lines can be kept low. The gate lines lead in a matrix with a decoder to diffused areas and form a pn junction with the substrate. With single-channel technology in solid silicon, d. ta. if only p- or n-channel transistors are arranged on a chip, with respect to the substrate only voltages of one Polarity must be applied, otherwise the pn junctions would be polarized in the forward direction.

In a memory arrangement with MNOS transistors according to the invention, the channel length is short the writing of information in the memory with a voltage of a predetermined potential and only a given polarity at the gate, while the gate is open when the information is erased 0 volts ground potential is held and source and drain at a correspondingly high potential of the same Polarity can be placed.

FIG. 4 shows a memory arrangement which is made up of MNOS transistors of short channel length and consists of the memory matrix, decoding gates and exclusive OR. The exclusive OR has the task of inverting the logic state at the output of the decoding gate optionally with the help of a pulse. The decoder consists of the transistors 41, 42, 43, 44 which form the decoding gate. The gate is "selected" when the address applied to transistors 41, 42 and 43, as shown in the figure, selects gate line 422 with transistor 421. In this case the potential of the point 53 is at the output of the gate. This output of the gate leads to an exclusive OR, which is formed by the transistors T _iS , 7 " _4e , T ₄₇ , T _iH and T _M. Looking at the selected gate and 0 volts at the input 54 of the exclusive OR, so, since the transistor 46 is conductive, the transistors 48 and 410 are blocked, that is, the write voltage is applied to the selected gate line 422, which is connected to the gate of the transistor 421, via the input 56 and the transistor 411. No ao write voltage is applied to any of the unselected gate lines, since these are then short-circuited by the conductive transistors 410.

The transistor 419 is used to write the information. If a "1" is to be entered, so the source line of the respective Speicheras column is connected to ground. Should keep a "0" the source line of the corresponding spoke column is interrupted. This transistor

419 corresponds to switches 12 and 13 of FIG. 2.
The reading process corresponds to the writing process.

Here, however, the read voltage, which is preferably approximately -10 volts, is applied via transistor 412 the selected gate line is placed. During the reading process, the transistor 420 is via the input 57 made conductive. There are then all source lines of the individual transistors Trap to ground. The transistor 414 is during the reading process, via the Input 58 controlled, also in the conductive state, so that, depending on whether the memory transistor 421 is in the "0" or "1" state, at output 59 the output voltage is 0 volts or the voltage of point 60, preferably -10 volts.

During the deletion process, an impulse starts

transistor 417 is made conductive at input 51, ie the source and drain lines of the transistors of a matrix column are short-circuited. The erase voltage is applied to the source and drain lines via transistor 418, which is controlled via input 52. The transistor 414 remains blocked so that the high erase voltage does not appear at the output 59. The transistors 419 and

420 remain blocked so that the erase voltage is not short-circuited to ground. The address line is selected at the same time. A voltage is applied to the input SA , and a write voltage is applied to all gate lines via the transistor 411. In the exclusive OR belonging to the selected gate, the transistors 49 and 48 conduct, the write voltage is short-circuited, and the gate line is practically on OVoIt. In the non-selected gate line, however, the transistors 49 and 410 remain blocked, the high write voltage is effective on all gate lines. As a result, the source, drain and gate of the memory transistors of these rows are at the same potential. The state of these elements is therefore not changed.

1 sheet of drawings

Claims (8)

Patent claims: 1. Transistor, suitable for digital electrical memory circuits, with one channel and with layered gate insulator, the transistor whose threshold voltage differs from that in the Gate insulator stored electrical charge depends changeably and in a fixed potential lying substrate is arranged, wherein the storage of the electrical charge or the deletion of a stored electrical charge by applying electrical voltages takes place between the gate electrode and the substrate, characterized in that both for storing as well as for erasing the electrical ones stored in the gate insulator layer Charge voltages of the same sign between the gate electrode and the common Substrate or between the source and drain electrodes and the common substrate are applied and that the channel length of the transistor is shorter than double when storing or the thickness of the barrier layer occurring during erasure. 2. The transistor according to claim 1, characterized in that the layered gate insulator consists of an SiO., - Layer and a Si ₃ N ₄ layer applied thereon, the SiO., - Layer being arranged on the substrate. 3. A transistor according to claim 2, characterized in that the transistor is applied to a 10-Ohmcm silicon subsirate, that its channel length is 1 to 5 μm and that the layered gate insulator consists of an approximately 2 nm thick SiO ₂ layer with an approximately 55 nm thick Si ₃ N ₄ layer applied thereon. 4. Use of a transistor according to one of claims 1 to 3 in an electrical circuit in single-channel technology, which essentially consists of a memory matrix and decoders, the individual gate electrodes of the transistors in a row of the matrix having a common Gate lines are connected together and the source electrodes are one column the matrix via a common source line and the drain electrodes of the individual transistors of a column are connected to one another via a common drain line, with one each Decoder is assigned to a gate line. 5. A method for operating a transistor or an electrical circuit according to one of the Claims 1 to 4, characterized in that the state "1" is written into a transistor when its source electrode is approximately at substrate potential, its drain electrode is on any potential and its gate electrode when using a p-conductive substrate a relatively large positive potential compared to the substrate potential and when in use an η-conductive substrate to a relatively large negative compared to the substrate potential Potential are placed, with all potentials having the same sign. 6. The method according to claim 5, characterized in that the substrate electrode and the Source electrode to 0 volts and that the gate electrode to a potential that <-30 volts, the substrate being an η-conductive substrate. 7. A method for operating a transistor or an electrical circuit according to one of the Claims 1 to 4, characterized in that for writing the state "O" in one MNOS transistor or to erase the »1« state of an MNOS transistor in the memory matrix the gate electrode is held approximately at substrate potential and the source and Drain electrodes of the transistor to a relatively large positive compared to the substrate potential Potential are applied if the substrate is a p-substrate, and that the source and Drain electrodes of the transistor to a relatively large negative compared to the substrate potential Potential can be applied if the substrate is an η substrate. 8. The method according to claim 7, characterized in that the substrate electrode and the The gate electrode is connected to 0 volts and that the source electrode and the drain electrode are connected a potential which is <-30 volts, can be applied, wherein the substrate is an η-conductive substrate.