DE2221681A1 - Electronic clock - Google Patents

Description

PATENT LAWYERS

HELMUTSCHROETER KLAUS LEHMANN DIPL.-PHYS. . DIPL.-INC. 8 MÖNCHEN 25 · LIPOWSKYSTR. IO

jx-ri-10 RIEHL ELECTRONICS CORPORATION λ * \ j - »

May 03

Electronic clock

The invention relates to an electronic watch with a pulse generator, which generates pulses of a constant predetermined frequency and in addition to a power source for the pulse generator a counter is provided which counts the pulses and outputs a plurality of electrical clock or time signals which correspond at least to the hours and minutes to be specified · · and in which the time is displayed by a digital display device takes place, which shows the visual image of the time signals emitted by the meter.

For electronic wristwatches or other solid-state technology There are a number of proposals to build clocks or integrated circuit technology bistable electronic counters can be used to display the time. In general, this is the display device on top of the. Wristwatch provided because of the arrangement of the dial and hands of mechanical clocks has been naturalized in general and corresponds to the customs. For example, in US patents 3 427 797.3 54-0 209 * 3 258 906.3 466 498.3 509 715. ' 3,276,200, 3,485,033 and 3,505,804 each from the viewing surface or the like as a synonym for the upper side

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or upper face of the watch. Also in the electronic watch described in US Pat. No. 3,194-003 this embodiment of the time display is provided on the top of the clock.

Some devices have also already been proposed for the precise setting of an electronic clock, but these all have the disadvantage that they imitate the functionality known from mechanical watches, that is, the time display continues to run while the setting is being made. This ongoing time display makes it difficult for precise Clocks the exact synchronous setting to an exact time signal. That is, during the setting process continues to run, the clock user must observe the display of the clock to be set and another clock at the same time, whose seconds display continues or he has to listen to a time signal and then his display within a few seconds set according to the time signal more or less precisely to the time signal you just heard. In the case of the US patents 3 4-56 152 and 3 195 011 described electronic This type of time setting is provided for watches.

This time setting device also acts on the counters or the counter parts with a lower ordinal number into the counter or counter parts with a higher ordinal number. This is not particularly annoying with the transition from minutes to hours, but it is particularly annoying when the after setting the "trial and error" method generated pulses on the counters or counter parts for days and months of a calendar clock reach. Then a further "spin" is required to lower the counter after setting the counter Ordinal number in the event of time zone changes or time corrections to bring these counters up to date. With the so far Known or proposed circuitry for calendar display is the day setting on the first day of a Month is generally left to the watch user. It was previously thought to be impractical or too burdensome to do one

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special monthly counter, in particular a counter of this type that automatically adjusts to leap years, because of the difficulties associated with displaying and setting the counter (s). It was hitherto also assumed that the circuits associated with the calendar display provide an additional display device and thus require additional wiring, etc. inside the clock.

Other proposals for electronic wristwatches assume that a continuous time display is required is. If light-emitting elements are used here, a continuous display requires a relatively large amount of money large power requirements. This is necessary with the currently available and customary light-generating elements a battery of a certain size. In known watches of this type, there are still separate electronic elements and units such as resistors and capacitors for noise or Noise suppression and / or signal control required. Furthermore, from each display element to the associated electronic circuit in the execution of these clocks no fewer than 33 connections for a four-digit display when displayed in seven segments or columns with Decimal point required.

The invention is based on the object of eliminating the disadvantages indicated in known electronic clocks.

The invention consists in an electronic clock of the type mentioned in that a device for generating a plurality of electrical date output signals corresponding at least to the data, a device for visual reproduction of the date output signals by the display device and a device for automatic Resetting of the data output of the meter is planned at least after 31 days.

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With such an electronic watch, as in will be further explained below, largely eliminate or largely eliminate the problems of the prior art at least greatly improve. In the preferred embodiment of the invention to be explained below, a A special method is used and the units, in particular, are used to fulfill the desired functions Circuit units specified. In general, a clock according to the invention has integrated circuits that are disclosed by a quartz crystal originating and controlled oscillations maintain and subdivide, so that a total of a clock or Time generator is created, which generates an impulse per second and from which the seconds, minutes, hours, days, Months and years are counted. The circuits provided for this purpose time-divide, select and distribute the coded ones Output signals of the provided counter on a decoding matrix, which these signals on a numerical display device transmits with seven segments, the light-emitting diodes in a four-digit arrangement and the im Time-division multiplex or time-sharing operation one digit each is controlled per time unit.

A two-line nickel-cadmium battery is also provided, which is connected to a solar cell array, which also serves as a power source and is charged by the ambient light. To select the desired display and to set the time are still magnetically operated Reed or reed contact switch provided. That means- it are to select the time display according to hours and minutes or according to minutes and seconds and continue to select one Date display after days of months and after the month number on the display device, three such Ried switches available. In those times when neither a time nor a date display is desired, the display can be used for Switch off power savings. To set the clock to the different time zones and to set the exact time Time there are three more control switches. Through this

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the counters for the minutes, hours and days are switched over each time the relevant switch is pressed or contacted one step far .et.

The hour or day switch switches its assigned Counter repeats by one cycle without influencing the day or month counter, so that an erroneous Advancing the month and year counter is avoided. The switch for advancing the minutes moves the minute counter each time the switch is actuated one counting position further and while the switch remains closed, the remains Second counter to zero and can accordingly be synchronized with a time signal that occurs every full minute be released. The time reading device can be energized while the minute advance switch is held closed so that the user of the watch can determine the exact time of the minute or Second counter release can wait.

In a preferred embodiment, the display or read-out device is the electronic watch according to the invention attached to a side surface that is perpendicular to the upper surface of the watch and above the articulation point of the bracelet, so that the display for the viewer takes place in a natural wrist position and at the same time that of Ambient light incident above is at least partially blocked in order to excessively bleach the light to prevent emitting diodes. The arrangement of the display on the side allows at the same time, the intended Install solar cells on the upper surface of the watch with the maximum area or, if no solar cells are provided, a much more stable watch case can be provided on the top than is the case with conventional ones Clocks is possible. The readout or display area is ■ with a circularly polarizing filter that acts as a red color filter Material covered for maximum contrast ratio with minimum reflected light *

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The entire interior of the watch structure is enclosed by a tight housing and / or in a transparent plastic material embedded, so that a watch capsule is formed, which is absolutely impermeable to moisture, dirt, Dust and the like is. The only connections leading out of the capsule are the light display in and / or exits and the magnetic fields for operating the Rieds.chalter continue to work. The hour meter is arranged in this way and built up that it can easily be differentiated from a twelve hour counting cycle can switch to a twenty-four hour counting cycle, in that a single lead on the the housing enclosing the electronic parts is connected to the positive or negative terminal of the supply source. If the clock is operated in a twelve-hour cycle, occurs at the time display also has a small light display in the hours corresponding to the second half of the day (PM hours), so that for the watch user when setting or changing the time zones, a display related to midnight is given is to prevent a date change related to the daytime.

There is a connection from the electronic circuit units for sampling and setting to leap years in the year counter outwards. This connection is usually only for a suitably trained technician or the like accessible. In the case of the date display, the light used for the PM display is also used to display the full years, while another light is used to indicate when the full year is a leap year, i.e. it is done in binary Form a display of the calendar year according to the current one valid part of a four-year cycle.

The invention is illustrated in the following by means of an exemplary embodiment explained in more detail with reference to the drawing.

Fig. 1 shows an embodiment in perspective a wrist watch according to the invention, at the same time part of the bracelet is shown;

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Fig. 2 shows a section, seen in the direction of arrows 2-2 in Fig. 1 to illustrate the arrangement of the mechanical Elements;

Figs. 5 through 8 show the left, right, rear and front view and the 'view from above and from below for the wristwatch according to Figures 1 and 2;

9 illustrates in a block diagram the entire electronic circuit of the wristwatch to be explained, with For better explanation, a subdivision of the individual areas has been made by dashed lines, which are based on the other figures are explained in detail;

Figs. 10 to 18 show the electronic one in detail The circuit structure of the individual sections of the block diagram according to FIG. 9;

19 shows a dynamic digital frequency divider circuit used in the counter-dividers according to FIGS. 11 and 16 Is used and

20 shows the circuit diagram of a synchronized or synchronizable astable divider.

In the preferred embodiment of the invention, particularly according to FIGS. 1 and 2, all of the internal components the watch 10 encapsulated in a block-like, transparent plastic case and in a wrist watch case 12 of the Inserted underside. A second window 13 be provided that a silicon solar cell arrangement 15 on top of the housing or it can also be the plastic encapsulation of the device directly as this Surface can be used. Pairs of magnetically operated reed holders17 or magnetic ones that work according to the Hall effect Resistors are embedded in the plastic cover and can be controlled by sliding magnetic control buttons 18, 19 and 20 press, which is in a corresponding guide on the Vorderbzw. Rear edge of the watch case are attached. Each slide button is held in its central position by spring or snap action and can optionally have one or two magnetic

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Operate the switch when it is moved forwards or backwards alongside the housing.

In the lower part of the housing 12, adjacent to a housing for a quartz crystal 27, there are nickel-cadmium cells 25 and 26 sealed inserted. The electronic part 30 consists essentially of a hermetically sealed ceramic housing block, which contains the integrated circuits and amplifiers or driver transistors. The block serves at the same time as a stable holding surface for the silicon solar cells 15 »The connecting wires leading out of the block at the front end are led to a control panel or a switchboard 32, which is used to hold the readout elements or Module 35 to 38 is used. The one on the back of Block 30 Outgoing connections establish the connection to the supply source and the associated reed so holders 17. The watch case has a lower cover 39 or can also be open in order to keep the total thickness of the clock as small as possible, in which case the lower surface of the plastic block forms the lower top surface of the watch.

According to FIG. 9, the readout modules 35 to 38 consist of four Modules each with seven connections or connection bars plus a connection for decimal point. These modules can be used in hybrid technology on a substrate or as encapsulated circuits be constructed from individual elements. The colon display 40 results from the fact that the third digit position from the left is installed in the reverse position, so that its decimal point forms the upper point of the colon, while the decimal point of the following digit position forms the lower point of the colon.

The module 35 (Fig. 6) is installed in the inverted position so that its decimal point 41 is in the upper left corner of the Display panel comes to a standstill. As will be explained below, this decimal point is 41 and the decimal point 42 arranged on the right side of the fourth module 38

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and serve for the binary display of the position of the year counter when displaying the date. The decimal point 41 of the fourth Digit position from the left on module 35 is also used to display the hours of the second half of the day (EM hours), if the hour counter is set to a twelve-hour counting cycle, and a time display is displayed.

The readout modules 35 to 38 have light-emitting diodes in a matrix arrangement, so that a time division multiplex operation of the decoder is possible, which controls these diodes, so that the to be displayed digit positions or digits can be selected synchronously in the readout device repeatedly so that the The impression of a continuous display is created. If, on the other hand, the display unit has glow elements, separate ones must be used Diodes can be provided in series for this purpose or the elements could be controlled individually instead of the common supply according to FIG. 9.

According to FIG. 16, a quartz crystal 27 forms the time reference for the entire watch. In this preferred embodiment, the crystal cut is chosen so that it is on a Frequency of 32.768 kHz oscillates. This quartz crystal lies in an oscillator circuit 28, the output of which is connected to a binary frequency divider 4-5. This divider points multiple outputs, with the frequency of the highest output 2048 Hz. Furthermore, outputs with 1024, 512, 256, 128 and 64 Hz are provided on the divider. The exact frequency of the quartz crystal 27 is relatively uninteresting as long as it corresponds to an integer multiple of 2048 Hz.

These output signals serve as marking and time signals, as will be explained below with reference to FIGS. The 64 Hz output signal is also passed through divided a plurality of counters, the BCD output signals (binary coded decimal signals), the time and Date display serve.

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The division of the frequency from the crystal natural frequency or the tuning frequency of a tuning fork to 64 Hz is under Using dynamic digital flip-flops 4-5 achieved based on 19 will be explained in more detail. For these flip flops a single phase clock pulse signal is required on the output line or lines of the previous stage and they are provided a single-phase output signal at the Q or Q output, which with regard to its time sequence is squat by the V / ert 2. These flip-flops are made up of ten integrated field effect transistors of the P or N type. The advantage of this embodiment in particular is that normally for digital dividers in this division there are sixteen transistors are required when stable operating conditions in both possible Initial states are to be achieved.

This common part-by-two arrangement is shown in Figure 17A. It consists of two stage sections that are connected to one another in series via two transmission gates are. The clock pulse phase for the transmission gates is selected so that a section memory stores, while the other section is in a different switching state switches over so that a change occurs at the output during each clock pulse or during each clock pulse change, whose value is reduced by 2 compared to the input. These switching states are continuously transmitted further, so that overall no further measures are required for the time constancy. However, there are sixteen in this circuit Transistors required regardless of its type of use. In the dynamic digital divider of Fig. 19A, only ten transistors are required. Its working method is as follows: The inverters 50 and 51 are in series with each other connected and the signals Q and Q appear at the outputs. The switching state of an inverter 52 is determined by the output signal Q set via the transmission gate 53 when the clock pulse is at its lower level. The transmission gate 54- is open when the clock pulse is in the lower Switching state is so that the input of the inverter 50 in

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The range of a statistical voltage level fluctuates approximately corresponding to the value that was established as the transmission gate 54 was closed for the last time, which connects to the output of inverter 52. The gate capacitance and the extremely high input impedance of the field effect transistors with insulated gate electrode used ensure that this voltage remains stable during the period that the impedance of transmission gate 54 is "open". The opening of the transmission gate has no influence on this voltage, since a changing clock pulse with approximately the same capacitance value in each phase is coupled, so that at the point of transmission of the signals there is practically the total influence of zero. If the clock pulse rises, the transmission gate disconnects the circuit at the inverter output 52 to the inverter input from and the transmission gate 53 opens the circuit from the output of the inverter 51 to the input of the inverter 52. The The input of the inverter 52 "floats" essentially on the potential coupled in from the Q output terminal. The transmission gate 53 opens fully before the new reversed Charge from the output of inverter 52 to the input of the inverter 50 and due to the ripple on the Q terminal accordingly the transmission delay through the inverters 50 and 51 can occur.

The switching states Q and Q are reversed when there is an increase of the clock pulse, since the output of the inverter 52 the reciprocal of the previous state of Q and is now fed to the input of inverter 50, which in turn is the Q-state to the state previously assumed by the value Q switches, whereupon the inverter 51 the switching state Q to reverses a slightly too late point in time to the "floating" potential at the input of the inverter 52 still to influence. If the clock pulse drops, the switching states Q and Q are due to the floating potential at the input of the inverter 50 as the transmission gate 54 opens. This creates a new switching state through the transmission gate 53 switched to the inverter 52, which the new

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Status of the Q ~ terminal. The output of inverter 52 reverses polarity a little too late for the input of the inverter 50 can still be influenced. So that returns the output signal changes once when the clock pulse rises or, in other words, passes through a full one Switching cycle of two discrete switching states for each two changes in the clock pulse on the input side, so that there is a division by a factor of two.

The semi-static version of this flip-flop is in Figure 19B shown. This structure is essentially the same except that an additional transfer gate 55 is provided by the Q terminal is provided to the input of the Q inverter, so that each of the two switching states is possible at the output remain constant when the clock pulse is low. In this arrangement there are two additional transistors, the means a total of twelve transistors are provided, and this arrangement fully serves the same purpose as that sixteen transistor arrangement described above.

If the circuit of each flip-flop is disconnected at terminal 57, access to the device via the B input enables operation as a data flip-flop, with the Switching state of the B input is acted upon from the output of the unit when the clock pulse rises while Changes to the B input at times other than during the transmission instant of the clock pulse have no effect exercise at the exit.

This arrangement of two flip-flops requires much less space for the active elements on one Rolling paper or an integrated circuit chip, so that overall a cost-saving arrangement of high packing density is possible. But it still emerges additional benefits. One is that the clock pulse input only controls half as many transmission gates must as with the flip-flop arrangement made up of sixteen transistors in the initial divide-by-two stage, so

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that the capacitive loading of the incoming signal is reduced, which in turn saves power the control of the device means. This has the advantage that, despite power savings, higher frequencies can be used, which is particularly advantageous in the construction of wristwatches, because it can with approximately the same power requirement or with lower power requirement based on a certain input frequency . Quartz crystals with a higher natural frequency are used in the oscillator.

The lower power requirement when switching the inverter results from the fact that only three instead of four Inverters are provided so that the power requirement during transmission can be reduced by a factor of 25%. These flip-flops work better, the higher the input frequency is due to the load factor and the inherently better stability of the flow potential at short switching cycles at the input of the inverters 50 and 52. This structure enables operation on one at the same time higher total frequency for a number of dividers for a given supply voltage, since the minimum switching or ■ The operating speed of the first stage is limited by the output capacitance it feeds. With this one Structure, the input capacitance of the subsequent stage is low.

At lower operating frequencies, the capacitance can exceed due to larger gate electrodes or metallized areas the connection point oxidized on the substrate to the entrance the inverters 50 and 52 slammed v / ground, or it a simpler flip-flop with only six transistors can be used, in which an integrated capacitor, for example as shown in Fig. 190 is provided. at this unit is the state of the output signal of the inverter 16 via the transmission gate 61 on the capacitor C1 given when the clock pulse in the lower

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stood stands. The transmission gate 62 is an open circuit which enables the input of the inverter there is a "floating" potential that determines the Q output. If the clock pulse rises, the transmission gate transmits 62 the reverse phase to the input of the inverter 60, namely that in the capacitor C1 during the Opening time of gate 61 stored voltage, so that the voltage on C1 and the input of inverter 60 are common "swim". In this circuit, the capacitor 01 must be considerably larger in terms of its capacitance value than the input capacitance of the inverter 60 or some other unit that is used when summing to the Q output connected is.

Another Be connected to the inverter in the! "All, in which the capacitance ratio of the capacitor G1 to Q load and the input of inverter 60 prescribes a much larger value for C1. In particular, the Capacitor C1 be so large that with the transmission gate closed 62, the charge stored at the input of inverter 60 does not have a dominant influence on the new voltage exercises. If the value of the capacitor C1 is equal to the gate input capacitance of the inverter 60, the new voltage would only be half the supply voltage when the transmission gate closes 62. Therefore, the value for C1 must be about four or five times the gate input capacitance of the inverter 60, so that the voltage is not at an intermediate value of the transmission or throughput characteristic for the inverter 60 stands.

Fig. 11 shows six dynamic subdivision levels 65, the divide the 64 Hz signal down to one pulse per second. This one pulse per second is fed to a seven-stage binary counter 77, which starts from the zero state counts up to a binary ten, which is tapped off by a NAND gate 78. This samples a NAND gate 80 and

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activates a NAND gate 81, producing rapid 1024 Hz pulses get to the input of the binary counter 77. As a result, the counter 77 is quickly switched over to the switching states 10 and 11, whereupon the binary twelve is tapped by a NAND gate 85, whereby the NAND gate 80 is switched through and via the NAND gate 81, in turn, the rapid pulses for advancing the binary counter via the Binary levels 12, 15, 14 and 15 can be enabled.

The binary state is when the next pulse arrives the first four stages to zero, while the switching state of the fifth stage is one, so that a BCD ten (binary coded decimal ten) is present. The stages 10 to 15 are successively grounded via the NAND gates 78 and 83 switched off by rapid counting in a 1024 Hz sequence. This means that six pulses are required in a 1024 Hz cycle, so that a time requirement of a little less than 6 milliseconds is required is required. These six milliseconds are negligibly short compared to one second, so that no overlapping of the output pulse of the divider cut 75 is present, which is the seven-stage binary counter 77 to the first of the undesired switching states, the is called the ten, when switching advances, so that the NAND gate 85 pulses without interruption during half a Second can record.

The rapid forwarding via the undesired switching states this binary counter also takes place too quickly to be perceived on the display unit and amounts to in total only a very insignificant fraction of the total number to be displayed. This process takes place as long as until a binary six is detected by NAND gate 86 in the last three stages of the binary counter. This will make that NAND gate 80 is activated, which in turn activates the NAND gate 81 switches so that 1024 Hz pulses reach the input of the counter. Since NAND gate 86 is both binary Six as the binary seven of the last three levels -

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asks, it lets impulses through until these three levels are switched back to the binary zero, so that when switching off there is coincidence with the first four stages, the are also in the binary state zero again due to the natural counting sequence of the binary counter.

So this is how the binary coded decimal output numbers generated for the units and tens for displaying seconds on the watch. These output signals are a multiplex switch for distribution to the decoder with seven connections and the display elements 35 to 38 supplied. The NAND gate 86 generates on line 89 also a negative going impulse, which at the time of the first undesired switching state of the last three stages begins and ends when the counter returns to the counting state zero. This pulse is used for switching of the minute counter.

In one embodiment of this wristwatch in hybrid technology, If single gates are used, this can be an advantage, as this results in a negative output as a carry pulse. However, an integrated circuit structure in which a single monolith arrangement is provided is preferred, and in which the Q and Q outputs of the seven-stage counter 77 are used.

The special circuit for connecting the counter about the undesired binary switching states can be using a relay logic or additional metal oxide semiconductor circuits in symmetry arrangement and monolith technology replaced using fewer transistors than would normally be the case with a gate of this type with feedback are required for synchronous counters or for counters that work according to BGD code, whereby at the same time a pulse train output is available when required or desired.

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A NOR gate 90 samples when the counter is not in the zero state or in other words when a logic binary one is at the output of any of the stages of the counter stands. Activated at all times except in the zero state the reset switch 92, the NAND gate 93 »which in turn energizes the NAND gate 80 and via the NAND gate 81 Let 1024 Hz pulses get into the counter, while the previous dynamic stages via a reset line which is also connected to the reset switch.

The switch 92 serves a dual purpose. Once will be at Each time the minute counter is pressed, it is advanced by a full minute and it can also be used to make corrections the time display. In general, the time difference is less than a minute due to the high Accuracy of the quartz crystal and the tuning fork oscillator, Pressing the button therefore advances the clock to the next full minute and the user can then use the time signal 'Wait to match the time display just set.

A clock can be set to a few minutes ahead of the actual time, provided that the minute and seconds counters are affected, by repeatedly pressing the same switch, so that the minute counter for example, it is advanced to the full hour until the desired minute display is available.

The actuation switch 92 also controls the counter advanced through its remaining switching states to zero, at the same time the 1024 Hz pulses are interrupted so that the seconds counter is also held at zero and via the line 89 a transmission pulse reaches the minute counter, so that it is on the display of the advance next minute. This switch also holds the dynamic stages in the zero count state, so that the possible error in the unused period of this

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Switch is limited to half a period of the 64 Hz signal, i.e. to 1/128 seconds. The purpose of this The main purpose of the switch is to synchronize the watch with a time signal, so that when you let go the switch counts the seconds from the starting point Zero begins.

The primary purpose of this measure in relation to the seconds counter 77 is to account for the switch bounces, which can occur when the reset switch is closed. It can be easily checked that when the Switch sets the value 59 as the highest seconds display. The switch bounces and delivers a multitude of pulses to the NAND gate 93, the switch is advanced by these several pulses when the 1024 Hz source is on Input of the NAND gate 81 is high. The fact that the counter is given a discrete number of pulses to be reset the switching state zero supplied, ensures at the same time for the required time setting that all switch bounces or dying processes have subsided before the desired final state is reached.

Research has shown that the actual The number of bruises to be expected from a magnetic miniature reed switch varies between four and sixteen. Even if all sixteen bruises occur during the short time that the 1024 Hz signal is switched through, the counter could be incremented no more than sixteen discrete steps. It would therefore have the zero state not overflowed, as from the highest BDC output of 59 at least 32 individual pulses would be required to achieve the to reset the seven-step binary counter to zero. So there is a digital filter against switch bounce voltages, without the need for external timing elements such as resistors and capacitors, and without the use of any digitally clocked switch bounce voltage filter, which is usually is provided in other wristwatches of the generic type.

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This means that the entire switch system can be used as an integrated
Build a unit from purely active circuit elements. To the
Achieving the same purpose it would also be possible to use the
to provide known and customary feedback loops to achieve the desired counting process and the switch only to reset both the dynamic and the
to use static steps of the seconds segment, in which case monostable multivibrators could then be used,
to which "the transmission pulse is fed through OR gates. However, this would require some clock circuit and resistor-capacitance networks and, in digital transmission, at least two stages of binary dividers, of which
one would have to be a clocked filter for switch bounce voltages, the output of which would have to go through both the "on" and the "off" state before the hold state could be released, so that the minute counter could read the
would advance the next full minute while being held so that the time display button on the watch was activated
could be caused by this reset switch
recorded time display can be observed by the user
could before the switch is released.

Another advantage of this feedback system with signal circulation, in which a rapid pulse causes a rapid passage of the undesired switching states, is that the
binary subdivision levels can be built as integrated standard elements, with only the Q outputs being led to the outside, so that no metal connections are required either to the Q, the data input or the reset terminals of the binary level counter. This allows space to be saved in the integrated circuits, which can be important, in particular if the elements are to be arranged next to one another, since in this way the need for surfaces to be contacted can be significantly reduced.

Fig. 17B shows section 100 of the minute counter of the wristwatch in which seven standard static flip-flops, such as
they are shown in Fig. 17A can be used to form a

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seven-stage binary counters connected in cascade, and in which the undesired switching states are scanned and can be switched through quickly in exactly the same way as with the seconds counter. In this case, it is desirable that at the reset point from 59 to zero minutes only one Carry pulse is generated, which gets into the hour meter 120 and the input of this hour meter is not on a Holds the switching state that would inhibit or interrupt the input of pulses from the hour advancement button, which can be entered manually at any time and in any switching state of the minute counter. These must be entered manually Continuation impulses are clocked via the Switch bounce filter 110 shown in FIG. Without a carry pulse from the minute counter, the Input for manual switching during the 40 and 50-minute periods of the minute counter can be inhibited or blocked.

Alternatively, an exclusive OR gate can also be provided so that the input to the first counting stage of the hour meter would be reversed in phase by each manually entered input pulse, regardless of the switching status of the carry pulse or carry signal from the minute counter. However, this would do the carry function both Complicate directly as well as indirectly, since the other functional units would also be more complicated, since the manual hour advance pulse to be entered the day counter during passage not moving further through midnight.

Fig. 12 shows the hour meter 120 of the wristwatch. The first counting stage 121 of this hour counter can be yours Continuously advance the counting state and are not subject to any feedback pulses. Press NAKD gates 122 and 123 the states of the binary 10, 11, 12, 13, 14 and 15 in the Counters 125 and allow the 1024 Hz signal to rapidly increment the counter to zero when the first four Levels are in a higher switching state than one

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corresponds to binary coded decimal -9. The first counting stage 121 which controls an "A" line of the hour display unit, is triggered to a new state at the end of the input transmit pulse so that when "A" is high, the Input transmit pulse is shifted to the remaining five stages through a NAND gate 124. At the end of When the input transmission pulse occurs, the signal on the "A" line drops back to zero and thus follows the correct sequence of binary outputs A, B, G, and D of counters 121 and 125.

This transmission system enables a high or low switching state on the Α line, if an undesired one Binary state is determined via the feedback. This is required because the hour meter is designed to run either a twelve or twenty-four hour cycle depending on the Choice is counted through a single external control line 128, which is at a plus potential for a twelve-hour cycle and can be connected to a minus potential for the twenty-four hour cycle. Everyone achieves this Counting cycles its first undesired counting state in a different state from the counting state of the counter 121. Different Expressed in the twenty-four hour cycle is a first undesired switching state for a binary coded 24, the means reached with an even number, while with the 'twelve-hour cycle the first undesired switching state with a binary coded 13 is reached, which is an odd number Number is. Therefore, line A of counter 121 is high in one case and low in the other when the 1024 Hz signal occurs, in which case the carry signal on the Α line must be such that it does not interfere.

This is achieved by an interlock, consisting of NAND gates 126 and 127, which switch on or through of the 1024 Hz signal. The triggering occurs when the first undesired switching state occurs, definitely by means of the operating mode selector switch and the switch-off takes place, if the counting state -determined by the same switch the Count value reached zero. In the case of the twelve-hour counter

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cycle, the interlock is established by the main input transfer pulse switched on by the minute counter when the output on lines A, B, C, D and E of counters 121 and 125 corresponds to a binary coded 12. The line E controls the unit digits of the binary coded hour output for the tens of the hour display. The two-way output corresponding to the binary counting decimal code is used for the Ten hours display held by the NOR gate 2 in the counting position 12 at a negative value. The lock is reset by a NAND gate 129 when the potential on line E drops back to zero. So long the line A of the counter 121 is held in the "high" state, the reset to a binary coded one takes place Decimal-1 instead of zero. Line P of counter 125 leads to AM / PM display 41 if the time is displayed, so that the user knows whether the hours displayed are before or after noon when they put their watch on wants to set a specific time zone so that it can be determined whether the date counter is at noon instead of Midnight far opened.

When the clock is operated on a twenty-four hour cycle, a binary coded 23 scanned and with the next Main input transfer pulse is entered into the interlock, and the 1024 Hz signal switches the counter until the Tension on the "!" 'Line drops. This corresponds to the zero state of the counter and provides the zero clock display Safe at midnight if the clock system is operated in a twenty-four hour cycle. The AM / PM indicator 41 is at Twenty-four hour cycle disabled. A NOR gate I3I generates a date carry pulse on line 132 as soon as the counter overflows due to an input pulse from the midnight minute counter. Through the line P is ensures that this occurs when operating in a twelve-hour cycle happens in PM hours. The line connected to the minute input gate 135 ensures that this is not the case happens when there is a manually entered advance input pulse.

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A gate 136 is used to display Z for the decimal point. or the decimal point 42 "illuminated when a date display is displayed and the year counter in an integer Switching status within the four-year leap year cycle of the calendar area of the wristwatch, so that a visual display of the relevant status is within this cycle is provided by the watch without the need for external test connections. The other The binary level of the year counter is connected to the decimal point position of the sample display W in order to obtain the remaining bit of the display binary information necessary to determine the leap year cycle when a date display is reproduced.

The Pig. 13A through 13D give the tactile switch bounce pilter again, which ensures that each time the button is pressed to advance the hours or days only a pulse reaches the assigned counter. These switch bounce filters make RC time switch or delay networks and Form C contacts for switch control and / or monostable multivibrators and the like superfluous.

The diagram of the pig. Figure 13A shows the logic circuitry of the keyed switch bounce filter for this embodiment a wrist watch. The sampling or clock frequency must be so low that it is ensured that no more can occur as a clock pulse rise during the entire possible time constant of the switch bounce. To this The purpose can be a D-Plip-Plop to key the switch input can be used in such a way that the output remains stable with repeated input keying. This represents sure that the switch is keyed when bouncing, but certainly not keyed when the next clock pulse bounce vibrations should still be present.

This means that regardless of the switching status of the switch when the clock pulse rises, the output remains un-

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neither in the previous state or changes according to the closing of the switch, then being subsequent Clock pulses, even if they occur repeatedly, only result in the same condition if the clock pulse occurs randomly a switching state of the switch that is closed during bouncing occurs or a switchover to the new switching state at the next! clock pulse occurs when the bounce contact period is just over. In the particular embodiment, an inverter 145 is forced to positive Output state switched when the clock pulse is low stands, so that the inverter 146 has a negative output state adjusts. If the clock pulse rises, then the inverter 145 maintains its positive output state due to the negative feedback from the output of inverter 146.

A transmission gate 150 is on when the Clock pulse is "high", so that in Pig. 13A circuit of switches 151 during the period is excited, in which the clock pulse is high and thus forces the "positive output state of the inverter 146, the is inverted by the inverter 145. Thereafter, the positive output state of the inverter 146 is ensured despite the switch bouncing, and this switching state is transmitted directly via the transmission gate 150 and the inverter 152 and 153 are transferred to the output.

If the clock pulse falls, the transmission gate 150 opens and the transmission gate 155 is switched to continuity, so that the initial state is retained, which is present when the clock pulse falls. The inverter 145 is switched "up" on the output side and switches in turn, the inverter 146 "low". Since, however, during this Time the switch bouncing has subsided, the output of inverter 146 is forcibly made by the switch itself switched to positive. If the clock pulse rises again, this switching state is retained, with the inverter 145 and 146 remain at rest in this special switching state.

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If the switch 151 is opened, the next following clock pulse reverses the output of the inverter 146 with its falling edge before the next clock pulse rise transmits this new state via the transmission gate 150 to the output. The advantage of this circuit over a straight D-flip-flop arrangement is that no integrating resistor located outside in or on the switching line is required and not as many transistors are required as with a fully static D-flip-flop. This triggerable switch resistance effect results in lower power losses than is the case with transistors in the static "on" state.

If desired, the transmission gate 155 can also be saved, since the transmission gate 150 is already used as Duty gate can be considered, the output of which is stored by the electrode capacitance of the input of the inverter 152 becomes similar to the way in which the dynamic digital divider works »In this case, the inverter 153 can be saved, depending on the desired input and output phase, so that the total number of transistors required can be reduced to eight, if Both phases of the clock pulse are available and the inverter 156 is not required. In contrast, the inverter 156 will provided to increase the number of metallic conductors within an integrated large-scale circuit reduce, the arrangement can be made so that the clock signal in the "low" state has a short cycle time, so that the desired switching of the inverter 146 into the negative state when the output of the inverter 145 is switched high, is very short, so that the effective power loss in the resistive line part of the inverter I46 can be reduced. An H-type transistor is used to ground point X when the switch is closed, thereby reducing the amount required to operate the circuit Can reduce the power requirement in comparison with a conventional embodiment of a passive. Tear-off resistance network. . ν:.: ■ '.. = -.

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222) 681 ■. *, η

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A further simplification for the same basic considerations results from FIG. 13B. In this arrangement, it feels Pass or transfer gate 160 the polarity of switch 161 when the clock pulse is high, and this Polarity is in the input gate capacitance 162 of the circuit stored, which is controlled by the contact bounce eliminator aird. If the clock pulse drops, it opens Pass gate 160 and leaves the stored charge in the driver circuit, the N-type transistor 163 tries to pull to the negative end of the supply source when the switch voltage output is turned on. This can while the switch is bouncing. However, this bouncing will have subsided by the time the clock pulse rises again, so that the same positive voltage again when the transmission gate 160 is switched on from the switch. If the switch 161 is released, so the next time the clock pulse falls, the input of the transmission gate is lowered by the N-type transistor. If the clock pulse rises again, the new charge is pushed on to the driver circuit, provided that that the integrated circuit capacitance 162 is greater than the input capacitance of the driver circuit, and by a factor of 3 to 4.

Repeated "pumping" of the circuit by the clock pulse possibly causes the input capacitance of the driver circuit to be charged to a negative potential, that of the integrated Capacitance 162 is impressed by transistor 163, so that the apparent capacitance 162 is amplified, perhaps even in reverse of the requirement that this capacity should be greater than the capacity of the driver circuit input ·

Fig. 13G shows the best of all embodiments, the special qualities of this circuit are retained even if the inverter 164 is omitted.

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Pig. 13D shows a simplified double inverter flip-flop that from a Form C switch 170 to one of the two switching states is controllable. This switch forcibly switches the inverters 171 and 172 to the on-state and back to the other state when the switch returns to its original position, thereby eliminating switch bounce and the power loss in every switch position is almost zero, with no resistor or capacitor required is, and at the same time there is the advantage that only a single line or connection from the integrated circuit leads to the switch. The only disadvantage with this circuit design is that the magnetic form C reed switches are considerably more expensive than the simple contact switches, while the few additional transistors within the integrated circuit shown in FIG. 13A or 13C in terms of the cost of a largescale integrated Circuit are negligible.

14 shows the day counter 175 of the calendar section of the wristwatch. The forwarding by one day takes place through a pulse from the hour meter on line 132 from Transfer gate 131 or from the day advance switch 18 via the switch bounce filter 176 (Fig. 9). In principle works this counter as well as the minute, second or hour counter insofar as the undesired ones here as well Switching states of a binary counter arrangement with six levels can be rejected or suppressed. A carry output 177 is only generated by the carry input and the reset takes place in such a way that manually entered advance pulses from switch 18 do not trigger any generation of carry-over pulses in the month counter, so that a user can reset the day can also make a desired earlier day beyond the end of a month without advancing the month counter, otherwise a day forwarding over the entire four-year cycle of the calendar section is required would make or it would have to have a further control circuit to excite the month counter or the year counter be provided.

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To sample the first undesired switching state, which indicates the end of the month, a locking circuit 178 with sampling gates is used, which triggers an input of 1024 Hz pulses until the counter 180 reaches the first of the month positions. The interlocking circuit is reset by keying or logically interrupting the incoming 1024 Hz pulses. A multiple detector is provided which scans the 29th, 30th, 31st and 32nd binary coded switching status of the counter output. Many of these sampled values are decisive, is determined by the inputs fed back by the month counter (Pig. 18) and the four-year leap year counter (Pig. 18). If, for example, there is no leap year and the month February is displayed, the NAND gate 181 scans the 29th day of the month, activates the lock and thus rejects all further switching states until the first output signal of the month locks via a NAND -Gate 182 resets again.

If there is no output signal at the output of gate 181, since there is a leap year, the February signal appearing via the NOR gate 183 and the NAND gate 184 at the input of the NAND gate 185 and triggers the locking 178, when the 30th switching position in the binary code has been reached, whereupon all further switching states are again rejected until the first of the month is reached. In the months of September, April, June and November, however, this will be NAND gate 186 energized on the 31st, its output being about the NAND gate 184 reaches the NAND gate 185 and thus with the tens bits (line E) of the tens section of the counter 180 and then via the gate 187 with the Twenty bits (line F) of counter 180 is ANDed.

Note that the twenties bits (line F) on the NAIID gate 187 are required to generate the reset trigger pulses for locking. There is none of the above conditions before, do the 32nd switching state of the binary coded output excites the NOR gate 183, which transmits a signal the NAND gate 184 to the input of the NAND Gatterπ 105

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·· 29 -

passes on where an AND connection is made with the tens bits and passes through NAND gate 188 and is ANDed with the twenty bits, thereby activating NAND gate 187 that triggers the lock. This counter system with changeable module can be done relatively easily by using the flow counter arrangement · The non-leap year signal 190 of the year counter and the September, April, June and November signal 191 from the month decoder and the February signal 192 from the month decoder make sure that the day counter runs through 180 and a carry pulse for the continuation of the month counter generated on line 177 after the corresponding number of days elapsed

Pig · 18 shows the month counters 195 "and 196 and the year counter 197 »in which six static binary counting levels are provided. The ^ first four stages go through and generate the binary one to twelve on lines A to D. The first stage changes its switching state indefinitely · The The zero state of the counter is never reached because the months are numbered from one to twelve and the zero state is not required and the code signal is more easily transmitted or converted to the BCD output of the decoder 200 lets · NAND gates 205, 206 and 207 generate the tens bits of the BGD tens output of the month counter. The NOR gate 208 generates a signal whenever the counter is in February

NAND gates 210, 211 and 212 generate on the line 191 a signal when the counter 195 or 196 in the month of September, April, June or November stands · These outputs are detected together with the one through the NAND gate 215 Non-leap year signal fed back to the day counter 175, so that the day counter is reset at the correct number of days for the month in question. A NOR gate 206 illuminates the year 2-bit indicator 41, which is the decimal point of the keyed readout output W corresponds if a day display is displayed,

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The February signal 192 need not be generated on a single line, as shown, but can simply be can be derived from three transistors, which are provided in place of each transistor in the day counter that points to the February receipt is marked, according to the logical Function required to represent the logic branch of the feedback system, with two additional Transistors saved compared to the direct replacement of the gate logic shown. Similarly, regarding the September, April, June and November signals and the non-leap year signals to save each two more transistors are proceeded.

Fig. 10 shows the multiplexer holder and the key signal generator unit the clock. There are three display control switches 19, 20 and 20a that can be used to selectively control the supply of seconds, time and data BGD signals to the input of the Decoder according to Fig. 15 can be controlled. The timer enables hours and minutes to be played back. The date switch enables the display of months and days of the Month. The seconds switch enables seconds to be displayed on the Y and Z indicators.

NOR gate 221 generates a short duration pulse at the end of the W, X, Y and Z display duty cycle. The impulse of NOR gate 221 sets the logic zero or negative output at the A, B, C and D output terminals by means of a group of N-type transistors 223, as indicated generally by the reference numeral 222. While this is done, the indicator switch inputs are de-energized by three P-type transistors 224 and three N-type transistors 225, so that the time, date and seconds selection transistors 226, 227 and 228 from the outputs 222, i.e. from A, B, C and D are opened.

The P transistor group 229 to 232 is switched on during the V /, X, Y or Z time grid switched on sequentially, so that the coded time hours are one-hour and ten-minute

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and the one-minutes sequentially at A, B, C and D of the exits 222 should be connected if the P transistor group 226 is switched on by the timer switch 20 · The transistor groups 233 and 234 are used in conjunction with the Transistor group 228 of a similar puncture when the seconds dial 19 is closed. The transistor groups 235 "to 238, also in connection with the transistor group 227, fulfill the same function for the monthly and Day counter output when the date selector switch 20a is closed will.

The transistor group 239 is used to determine the priority of the pages, date and seconds display switches so that no contradicting signals can reach the outputs 222, i.e. A, B, C and D. This is done through shutdown the date and seconds signals are reached as soon as the timer 20 is closed and by switching off of the seconds signals when the date switch 20a is closed.

The transistor group 240 is used for scanning, if one of the selector switch 19 _f 20 or 20a actuated, to · a line 241 a signal appears which turns on the display amplifier and the Spannungstastverstärker in the decoder of Fig. 15.

A transistor group 245 is used to operate a decoder by 64 and 128 Hz signals and sets the four Basic time grid within the follow-up time of the 64 Hz signal for the Vi, X, Y and Z signals. The transistor group 246 switches the W, X, Y and Z signals to zero or if during the key output signal of the NOR gate 221 the solar cell voltage is low and the transistor group 247 is the solar cell voltage control transistor group 248 not de-excited. All mentioned conditions for the transistor group 246 are queried by a HOR gate 249 .

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_β 32 - 3x-ri-10

By the multiplexing arrangement, not only the usual advantage results in a reduction of the compounds, but also the negative output to the gate or gate input capacitance is stored of the amplifier or driver circuit so as to connect the output of the multiplex switch to the inputs of the different time determining counter only half as many transistors are required, since only the outputs of these counters corresponding to the positive switching states have to be transmitted to outputs 222, that is to say A, B, 0 and D of the multiplex switch. In a conventional arrangement, a group of complementary N-Iyp transistors would have to be provided for transferring the negative or zero states of the counters determining the time to the outputs A, B, C and D of the multiplex switch.

The transistor groups 250 to 253 are output driver circuits for the ¥, X, Y and Z! East signals. Each group has a Darlington amplifier that feeds a 30 ohm resistor connected to the base of an output transistor. The internal voltage drop in the forward direction at these three base-emitter junctions ensures that if the battery voltage drops below 2.1 V, the output transistor is biased in the reverse direction and only draws the leakage current from the supply source ₉

In the case of a two-line Mckel-Oadmium battery 2 $ 1 V an output level that indicates that enough stored Power from the batteries "has already flowed away, so that further power consumption by the Ausleseeijihsi'c; should be demeaned to the remaining saved To have power available for the time-keeping elements of the circuit - the battery voltage The scanning circuit thus reduces the supply of the readout units when the battery voltage is 2.1 V approaching * The 'resistance in the base price of the output transistor switches the current level to asu output transistor when the

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- - 33 -

Battery voltage is above 2.1V and can be adjusted to any desired Decrease in power output consumption. Es "with a battery voltage can be set above 2.1 V. The three diodes shown are connected in such a way that the current is limited is when the voltage drop across the resistor is sufficient, when this is related to the internal voltage drop at the base-emitter junction of the first two! transistors is added to achieve a total of 2.1 V, which is the internal voltage drop which corresponds to three diodes in the forward direction. When the battery voltage reaches 2.8 V (four times 0.7 V), start conduct the diodes and limit the voltage supply to the first transistor. This regulates the current flowing to the base of the output transistor to a constant value, as soon as the supply voltage exceeds 2.8 Y.

If the solar cell output voltage is at high intensity of the ambient light high enough, so sets the N-transistor group 248 sets the duration of the W, X, Y and Z signals so that they represent the full portion of one-quarter of the 64 Hz signal repetition time correspond. If, on the other hand, the solar cell voltage is so low that the IT transistor turns off and the P transistor group 248 is switched on, the transistor group 247 limits the duration of the V /, X, Y and Z signals to one eighth of their normal Pulse width. This new arrangement limits the width of the pulses to be fed to the light emitting diodes, to thereby limit the power consumption when the watch is operated or read in low ambient light conditions «

Pig. 15 shows a decoder that receives the BOD output signals of the four lines A, B, C, D of input 222 converted into a digital display code on seven terminals Table of values for this signal logic and the generation of the Numbers on the display are in their own. 15B reproduced »

The inverter group 254 supplies the signals of reversed pola ° » rity of the A, B, C and D input components in the decoder required are. The transistor group 255 forms the

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final part of the logical decoder connection network. They control the saddles of the output transistors in the group 256 into the positive, so that these segments a "to e according to turn on the BCD code if the transistor group 257 and transistors 258 are on. The NOR gate 259 drives the gates of the output transistors 256 negative via the transistor group 260. This switches at the same time NOR gate 259 turns off transistor 258. The signal of the NOR gate 259 occurs at the beginning of the V /, Z, I and Z time pattern and serves to restore the logic negative output of the outputs a Ms e, so that during the remaining V /, X, Γ and Z time grid the transistor group 255 only connects the positive logic outputs that are required for the individual digits to be displayed. One An even more expedient arrangement would result if a set of complementary transistors is provided in group 255, to bring the various outputs to the desired negative state.

• The mentioned negative output state is based on the input or gate capacitance of the output transistor group 256 the provision by the transistor group 260 is stored.

The transistor group 257 switches the positive output drive group of the decoder as soon as the logical input circuit is on a Desimall-llüil and the read-out button arrangement after, Fig. 10 is in the ¥ -Seitraster, so that the more significant. Eullen hours to be displayed for 51s or Months to improve the reading clarity and sur performance savings be hidden.

A group 261 for spanming scanning works exactly the same as the output group 25 * 0 in Hg * 10, it is before. of line 241 off on _? which activated by ο inen cer Änseigesteuorschaltsr v / ir5 aiiu on ground potential for the Ä'asgangsvsz'i3tärker-'2 "/ a" i.i3is "- :. rgruppe 2f> 6 surüoklrehrt who; oils Batten ie spamru -; ^" bsi 2. _s - \ V or closer, so that

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- 35 - jx-ri-10

the base power consumption "when the battery voltage is too low is prevented, so that a further display takes place without using the battery, if possible always for the time-keeping Elements of the circuit should be saved.

Pig. 20 shows a synchronized astaMlen Seiler. This unit works essentially in the same way as a normal astable multivibrator, the resistor R and the capacitor Ö forming a coupling network through which the two inverters 270 and 271 are coupled in one state or another through the feedback capacitance, if R is not the capacitor C discharges to the point at which the process is reversed and the coupling capacitance now holds the reversed switching state, while the voltage supplied to resistor R reverses and again causes capacitor C to be charged in the opposite direction. This process is repeated indefinitely according to the size values for R and C. If the transmission gate 275 is inserted into the feedback loop, as shown, and if it is controlled by higher-frequency clock signals, the gate 275 works as a gating gate, so that the voltage at the input of the inverter 270 is switched on according to the RC charging characteristic until the keying is finally carried out and the inverter 270 is triggered and the locking condition of the flip-plop reverses. The capacitance of the input circuit of the inverter 270 stores the duty cycle during the periods in which the transmission gate 275 is open.

In order to achieve maximum stability, the astable part of the circuit is set so that it oscillates at a natural frequency that is slightly higher than the desired output divider frequency. The arrangement is such that the key signal occurring at the end impinges on a voltage has exceeded the trigger point of inverter 270 already considerably during the switching through the gate "That means the output of the inverter 271 changes simultaneously with the Pührungsflanke of Eingangstastimpulses _o

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A further increase in stability can be achieved if the period of the input frequency is changed in this way is that the transmission gate is open longer than closed, whereby the duty cycle shortened and more Time is available for the RC network to run through the trigger voltage of the inverter 270. To this A single-stage frequency division in the ratio of 200: 1 can be reliably achieved if according to the present one Proposal the complementary symmetrical MOS circuit is built in integrated circuit technology.

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Claims (30)

Claims \ 1 J Electronic clock with an impulse source, the impulses "constant predetermined frequency generated and by a Power source is fed, with a counter that counts the pulses and a plurality of electrical clock or Emits time signals that correspond at least to the hours and minutes to be specified and with a digital Display device which displays the visual image of the time signals emitted by the counter, characterized by means for generating a plurality of electrical date output signals which at least correspond to the positions, a device for visual reproduction of the date output signals by the Display device and a device for automatically resetting the data output of the counter at least at the end of 31. 2. Electronic clock according to claim 1, characterized in that that the display of the time signals and the date signals on the same digital display device he follows. 3. Electronic clock according to claim 1, characterized in that to facilitate an accurate A control device sets the clock to synchronize with a time signal tuned to whole minutes to change the minute output signal of the counter is provided after a fraction of a minute, during which the pulse source is reset and held at the pulse value zero. 4. Electronic clock according to one of the preceding claims, characterized in that for relief the precise setting of the clock a control device for changing the hour output signals of the 209848/1174 Counter is provided without the when it is actuated Pulse source and minute outputs can be changed. 5. Electronic clock according to one of the preceding claims, characterized in that for setting the clock a control device for changing the day signal output of the counter, "when it is operated the minute and hour outputs of the counter are not intended to be changed. 6. Electronic clock according to one of the preceding claims, characterized in that in addition to the Time signal outputs of the counter outputs for seconds display are provided and that in addition to the electrical Date outputs There are outputs that display the months. 7. Electronic clock according to claim 6, characterized in that by a control or selection device the optional display of either the hours and minutes or the months and days or the Seconds on the display device. c Electronic clock according to claim 6 or 7, characterized in that to facilitate the Setting a control device to change the meter's output display over the end of a month is also provided without changing the monthly output display of the meter, 9. Electronic watch according to one of the preceding claims, characterized in that for setting the clock a control device for changing the Hourly output signal of the counter beyond midnight without changing the daily output signal of the counter is provided. 209848/1174 10. Electronic clock according to one of the preceding claims, characterized in that "at Daily output of the counter an automatic control takes place in such a way that 30 was on the display device for the months of September, April, June and November, 28 days for February and 31 Sage for the remaining months of a year. 11. Electronic watch naoh claim 10, characterized marked that for automatic compensation in leap years the day output signals of the Counters are controllable in such a way that an automatic display of 29 days for the month of February after each expiry of four years. 12. Electronic clock according to claim 11, characterized in that that from the meter an electrical output signal corresponding to each year of a four-year cycle is generated, which can be visually displayed as a year display. 13. Electronic clock according to one of the preceding claims, characterized by a control device for only selective control of the display device, "so that the power source in favor of the pulse source and the counter only during a desired time or date display by the display device is burdened. 14. Electronic watch according to one of the preceding claims, characterized in that the display device has light-emitting display elements is equipped that the power source is connected to solar cells and that to control the light-emitting Display elements to be supplied power provided a device responsive to the solar cells is to protect the power source when the luminous intensity of the surrounding light is low. 209848/1174 15 · Electronic watch according to one of the preceding claims, characterized by, an essentially water- and air-impermeable embedding or potting material, which the power source, the pulse source, the counter and the display device surrounds like a capsule and that a housing receiving the capsule is provided is. 16. Electronic clock according to claim 15, characterized in that that for the selection of the time and date display outputs of the counter a magnetically operated Switch is provided, which is also surrounded by the Yergußmaterial and that for actuating the Switch a relative to this displaceable magnetic actuating element is present. 17. Electronic clock according to one of the preceding claims, characterized by a selection control device to select a 12 or 24 hour display on the display device. 18. Electronic watch according to one of the preceding claims, characterized by a wrist watch case with essentially parallel lower and upper surfaces, which are connected to one another by end and side surfaces are connected, the current source, the pulse source, the counter in the tree enclosed by the housing and the display means are incorporated, and wherein for attaching both ends of a tape to the end faces of the housing holding elements are provided and wherein the digital display device on one of the End faces is arranged above the tape holding elements. 19. Electronic clock according to claim 18, characterized in that that the display device in the housing to protect the display device against external Exposure to light is built-in. 209848/117 4 20. Electronic watch according to claim 15, characterized in that that the solar cells connected to the power source on the upper surface of the watch case are arranged, and that the potting material is largely transparent at least in the area of the solar cells is. 21. Electronic clock according to one of the preceding claims, characterized in that the possible The power output of the power source can be controlled and that a device checking the power source is provided that a further supply of the pulse source and the counter takes precedence over another Ensures power consumption by the display device. 22. Electronic clock according to one of the preceding claims, characterized in that the counter . ler has an electrical AM / PM output for distinguishing between the ^{hours before and after 12:00} noon and a display device for visual AM / PM display. 23. Electronic clock according to claim 1, characterized in that the power source is connected to a solar cell, and that a device responsive to the solar cells is provided to control the power to be supplied to the digital display device in order to protect the power source when the intensity of the ambient light is low. 24. Electronic clock according to one of the preceding claims, characterized by a device for selective resetting of the counter, the one manually operated switch and a filter device for receiving an input signal from the switch to Resetting to the selected counter position has the fact that the filter has a shift register which can be controlled by lactic pulses and which is connected to the switch 209848/1174 Has input, and that a clock pulse source emits pulses of such a length that the duration of a clock pulse cycle is ¹ longer than the duration of the plurality of input signals derived from the switch during the contact, and that the filter on or after each completed switch actuation only provides an output signal. 25 · Electronic clock according to one of the preceding claims, characterized in that a device for optional resetting of the counter is provided, which has a manually operated switch, that a clock pulse generator supplies additional pulses to the counter and that one to set the counter Number of pulses of the clock is required, which is higher than the number of the manually operated Switch generated pulses when making contact when the switch is reset to a certain state is initially closed. 26. Electronic clock according to one of the preceding claims, characterized in that the counter at least one astable multivibrator with an input, an output and a feedback circuit comprises that the connection between the feedback circuit and the input by a through or Transmission gate is interruptible, which is synchronous with the pulse source is opened and closed and that the natural frequency of the multivibrator is set to a value which is slightly larger than the value of an integer! division of the! frequency of the pulse source j so that the multivibrator switches to continuity on the leading edge of the .impulses input. switches to the conductive state, which is an integer Corresponds to multiples of the cultivator frequency. 209848/1174 27. Electronic clock according to one of the preceding claims, characterized by a selection device for selective connection of the time signal outputs with the digital display device, the one Have a plurality of transistors with sufficient base or gate storage capacity, for at least temporary Storage of a voltage representing a selected logical condition, a device to to apply the voltage corresponding to the selected logic condition to all transistors, one on the Counter responsive device for changing the logical condition with certain of the transistors and with means for interrogating the logical condition of each transistor to provide a visual indication. 28. Electronic clock according to one of the preceding claims, characterized by a device for optional connection of the time signal outputs to the digital display device, with a multiplex switch having a plurality of inputs connected to the counter and outputs which are connected to the display device, a timing or clock circuit for. optional and repeated excitation or activation of the display device simultaneously with the selection of the inputs of the multiplex switch and in that the inputs of the multiplex switch is connected to the digital display device via common output lines are that a minimum number of output lines is required to display the time signal outputs. 29. Electronic clock according to claim 28, characterized in that the time or clock circuit delivers signal sequences so fast that the visual impression of a continuous display is created. 209848/1174 30. Electronic watch according to at least one of the preceding Claims, characterized in that that at least part of the counter is constructed as a binary counter, one input of which is connected to the pulse source is connected and one output is connected to a decoder, the undesired counting states of the Counter determined, and that an input pulse source delivers as many impulses with an IT frequency, the higher lies than the other input pulses that the binary counter advances to a desired counting state during the blanking interval between the input pulses. 209848/1174