DE2057342C3 - Control unit for an information presentation system - Google Patents

Description

The invention relates to a control unit for an information display system which can receive information, in particular, with several display devices for representation of the symbols in the television raster, _w ith a memory for receiving and storing the information to be represented in binary form, a generator for generating segments of a displayed Svmbols and a multiplex circuit for the distribution of the individual segments to the individual display devices and for the composition of the complete symbols. .

From British patent specification 1 129 502, st «n Information presentation system known in which the data fed to a memory in binary form by means of a character generator in V.deos.gnale fur the, partial display on a television raster screen device being transformed. The code given by the character generator in parallel form ^, each correspond to the grid display of a single line of an individual to be displayed Character. The character is thus composed of individual segments. This is done by the character generator on the one hand in parallel the character coding and on the other hand a Steaerinformat.on, which the single line, i.e. in the learning grid as next recorded on the screen w.rd indicates. From this combination w.rd d.e of this line and segment coding associated with this special character, which is then displayed on the screen is fed. This known character generator supplies the segments for a single video display device. For each video device there is a separate character generator with complex logic necessary.

There are also symbol generators for information display systems known be, which a group of video display devices input signals: from a "corresponding group of synchronous access memory devices receive. Delay lines are used as the fallback storage devices or rotating magnetic plate.! uses this Synchronous storage devices receive as input signals a series of picture information, i.e. can be generated by a corresponding number of character generators, with each individual character generator the full character for a. dsch.rmgerät or possibly also for /.we, display devices generated. The input signals of this group of

Character generators consist of parallel D.g.tal information, which are usually supplied from some kind of buffer store.

In systems of this type, many mine generators and many synchronous Spe.che.elemente are required to generate the information de to solder that the memory as ^ ^k f "g ^ ^,. Learn core memory as an asynchronous memory, which the input information are fed to a connected mt of the ^ ™ ^ _Γ

lung ^^ J ^ Z ^ JLhme and intermediate number of line buffers to AU ^ _{l correspond} -

^s P ^eic i ^er _ ^ung / ° _n ⁿ Z ^ _a ⁿ _t 7 _on 7 _s signals that the binary informal, on * S ™ ξ is _{a segment}

connected to the A ^^ ™ ⁰¹ ^ ^J each segment generator * ^ · _{from the} respective

generator, a ^ 'f' * ^^ ^e J _ary symbol signal ent »o line buffer zugefiihrten bina y ^ _{Zei, enpuffer}

^^ '^ SgeSltet'. S.nd that the output of de rar h ^'NTE ™'; ⁱⁿ _le ^ ^C g ichfalls as input to the .f ^etting "^ 37 _{u" cf} is _ührt ^8, etc., until finally.

^ «* ^^? J £ _{en line} buffer as input * 5 the output of the ν ο belt η ^. ^ _{That each}

f ^m ^ ^zth ^ '^ ₀ ^"s _{[P est} value Eicher contains the Segmen generator ^ ^inen _ftiondesvom Segmentd.edarzustellendjV ^ o ^ n _{th each darzli.} generator to e ™ ^u ge _{sch, ie} ugly from ^S \ ^ ^{ell de} , ⁿ _e / ^y _s ^ ^b _m , _n ^ _n e _r ators to the multiplex gang of the Segm "^ ⁿ ; _{nsetzu and} distribution of SchaUung for ^ u _Darst el! ungsgeräte ange-Symnolsegmente .in

^sch '" ^Sb . ^e ." ^S '_{"{errindun, s" e} MAESSEN control unit generates At di' e '^ _{T' of a s d} as _mbohi

every segment enerator has one of _these

^ ^ ₁₀ fstellt mrdensoMun the

Ze.t [^ / fj% J ^ rLzU immediately afterwards free first part of an aymn _ol * _the symbol or

^^^ "J ^ Ss on another Dar _can , _while nd the other

f ^^^ Ηεη Ret of the first symbol ^Se g ^mentge "" f ^ """" generate signals of these segment genes ^. Ausga, »p» g _Multiplex .Gattern

45 rotors will ^ * _{for a G} , _{ouppe of Dar} .

"SnSä to final display data ^ enag y ^. ^ _{It is possible}

«Good

^I : '"
50 number of

to

y ^. ^ _{is it possible} .

^. ^ ^ _{size at} .

ten to steamer. Furthermore, _{on the basis of} this structure, _{or to be} reduced in size, and thus γ ^ ^er ° _e " _{u & come} to J'e ^A ™ in a simple way

^We * ^e ™ S * _and advantageous developments and 55 ϊ ™ Nahrungsmittel * 1 & ™ "of the tax claims according to the invention can be found in the Un ξ _iere i _{nhcit as} part

D ^^ "^ ^ T information display viewed emc systems zu ^ mto _{jt dnes Compute} rs

60 earth d "aί ¹ ™ _d ^ ^e _nformatione n passes to a group ^^^^^ J X.vorrichtungen and receives f ^^^ information. As Em - "., Be-Auseabe devices, the presentation gifts A" sgaDe _{to use} , but s.ch

6 ₅ b ^^ J ^ mgpnJ * _{control unit} "" _{on dif} production-appropriate signals to W.eder-

5 "6

The control unit according to the invention, which takes place at the central time grading of the signals according to the Taeinhcit of the computer at an interface and a belle of Fig Generate 20; is connected to a second interface, Fi g. 11 shows a hexadecimal notation of the information that is to be displayed, 5 image data for a series of characters with odd stores these and finally generates display scanning and even scanning, and one sees the or image signals which are representative of the data to be displayed which are information to be provided by each of the segment generators. Thereby only one point in time will be generated,
only character generator is used, which consists of several In the F i g. 1 and 11 corresponds to the controlled Dar segment generators, with each of these segment io position of the letter B not the actual mentgeneraloren to one or to a group of the conditions in the television shaving. It was connected to the outputs of the storage device, made for the sake of clarity,
and wherein each of the segment generators has a fixed F i g. Figure 4a is a block diagram illustrating how laid segment image representation of each symbol creates the basic symbol generator to be expanded to be displayed. The multiplex 15 can include lowercase characters;
Circuit Made Up of Various Gates Fig. 12 is a block diagram showing how it brings the outputs of the group of the system to the group of segment generators for the odd display units in question in the correct time sequence by using a separate segment generator. and even fields of a television field are expanded

In the execution type described below, 20 can be;

a symbol set is used in which each FIG. 13 shows in a block diagram like the

Symbol a block of ten vertical columns and multiplex circuit additional information about

16 horizontal lines of a display or picture - the color of complete words can be supplied

schirmgeräles with Abtaslraster claimed. With this you can;

Embodiment can be a single segmented line. FIG. 14 is a block diagram illustrating how

Chengenerator, which can be expanded from five segment generators to the multiplex circuit so that

stands. Generate image signals for 32 display devices. Infoimations are included, which represent

Due to the great flexibility of the inventive tativ for the color of a single character;

Control unit, which is basically only with a sign - F i g. 15 shows another in a block diagram

generator, the segmented character generator, ar- 30 execution type of the fallback memory and the seg-

working, this can be used in particular to mentgeneraloren, in connection with a smaller

Image information for raster display devices, number of display devices used;
Steering beam indicators or digital plotters

to create. Detailed description of the invention

On the basis of the execution described below, 35 _o « ν r

The structure and the mode of operation of the system configurat.on

the control unit according to the invention shown in more detail. As shown in FIG. 2 can be seen, is an

will be. The figures show in detail: number of display devices 101 to 132 to a picture

F i g. 1 shows a graphic illustration of the screen device control unit (TSU) 200 via lines

creation of individual symbol patterns, specifically for a 4 ° 201 connected. The display device control unit

Group of eight display devices; 200 stands with a central processing unit

F i g. Figure 2 is a block diagram showing a system (CPi /) 50 communicating over lines 52.

Figure 3 illustrates configuration embodying the invention; For purposes of illustration, the symbols A and B are shown as

F i g. Fig. 3 is a block diagram depicting an on-screen display of the first two symbols of the first row of characters

Represents control unit according to the invention; 45 each of the eight first display devices 101 to 108

F i g. 4 is a block diagram showing a segmented.

based character generator with a fallback memory ....,,. _ ". ,.
represents that to the inputs of the various' display device control unit
Segment generators is connected; In FIG. 3 is the display device control unit F i g. 5 shows a block diagram of an embodiment 50 200 in the form of a block diagram. That of a single segment generator; incoming information is sent via Lei-I i g. 6 shows in a block diagram the connections 52 to an input / output unit 204. The fertilizer between the segmented character generator input / output unit 204 then forwards the to and a group of parallel-series registers; Hitting signals via lines 2D6 to a return F i g. 6a shows, in more detail, the structure 55 of the handle memory 300 in parallel. The fallback memory of a representative parallel write register; 300 has multiple output lines 208, 210, 212, 214 FIG. 7 is a block diagram showing the generators 16 and 216, which are sequentially connected to segment generators of the various synchronization and control signals PCG1 410, PCC / 2 430, PCG 3 440, PCG 4 450 and, which are used to operate the multiplex circuit PCG5 460 are connected. The data transfer will be needed; 60 between the fallback memory 300 and the one from FIGS. Fig. 8 is a timing diagram illustrating the relationship between segment generators and character generator 400 between Vcrükal synchronization signals over each of the aforementioned lines in parallel with which the group of display devices is in byte form. The character generator 400, which is also controlled as; segmented character generator has 1 i g. ¹ J is a table illustrating how the image 65 more Ausgangslcitungcn, and each of the five signals for the monitor apparatus 1 and the screen segment generators 410, 430, 440, 450 and 460 results in device are ycsUffclt time 20; a group of lines in parallel wcp. The I-inhcil I ij? 10 shows the circuit with which the PCG1, that is to say the Scgmcnlgcneralor 410, is connected to a

^ ltiplex-SchaKun g 500 via CME line group 428 ^^^

^ 2 ^ iomd «^ UC ^ u ^ u ^ Ll ^ U the symbol data bit 3. Her output 424 of the

tungsgruppc 438 PCG 3 via e, ι, Lc »" group «» _OR _ _S chaltiing 414 represents the symbol-Dalcn-

PCC4 via cmc Leilungsgruppc 458 and dcrbcgmcn J ^ ^LI ^ d ODERShlt 415

4 reprä y

425 of the OR circuit 415

length Syf7f ^ 3 Stcucrungscinhci 600 and scanning signals which are sent to the get over lines 201

, Id xo it can be seen that the number of data buses that are used for Vertee fcncc ijiiu, _d Symbolinformalioii

f ^ ^ schac ^ ^ y ^ ^ ^ ^^ ^

depending on the symbol group specifically affected.

g 603 and fed to the multiplex circuit 5UU ^ Unuerade-Ücradc signal. This signal

Lines 604. _{becomes y} ^ _{n cincm,;} | i _p .,. I _{op 4} | _{7 is} generated whose left

_{Rückgrifl'spcicher 20} output signal is the vertical synchronization signal,

As can be seen from FIG. 4, the reverse is fed to the flip-flop 417 via a line 658

fvl iuch Γ i R 3) mt resorting comparable memory 300 is _25, which is to be generated Dc Ausgangsle.tungcn 'in Kea 302. The memory core 428 of the ROM 420 represent en single honing

5S53ti SS3SSSS335SS

"End," urdc. The Zcilcnpullcr 320 330 3 «I and

_; . _fa

The outputs of the Zc.lcnpuffcr are in the same way

the described

generator 440 and at d.c 1 mgangc of Ze pj

340 connected. The outputs of the / cilcnpuffcrs 340 «

are via lines 214 to the slopes of the segment ^^

generator 450 and in a hurry to the 1st entrance of the 50 diev

Zc, lenpulTers350 connected. De exits of the whole _; A.o. \ J «

ZclcnpulTcrsa »are via lines 216 to the η cmc η

^ _{3M m 34 () unJ} ^ _cm _

_lcr ^ ₁ . " _{Liiu 51U} . ₅₂ ,,; _{S3ll llud} 540 <^ _cr , _{completely isl} , _worJcn

* J _{Wct 63} “^ _{ühcr Ld} .

_{k 6} i _0a ..gCM: -.!. «sen

if to increase so that the sys

the desired range of symbols can be adjusted.

Partial symbol accelerator

_n . _{h | chcr 2 (Shift 2) becomes lilvr a,. egg} . ^ _{6n applied to the} Sciiicberegisler 529. Du Signal / eilenschicbcr 3 (Shirt 3) is sent via a l.eiliinf

which are the

buffer

Lei.un.en SII. 521, 531 and 541

9 10

Multiplex circuit device 560 is connected to a fifth input of the OR circuit 562 connected so that the fifth line

In the F i g. 6, 6a, 9 and 10 are the multiplexes of each field of each symbol row appearing on the image data links shown that are needed, screen device 1 is to be generated in this way around the image signals: for example for the screen S is generated.

devices 1 and 20 within a collection of It is clear that when using another

32 display devices. Symbol set the number of segment generators or

According to FIG. 9 it is incremented or decremented to produce the correct one of the line count outputs

Image signals for the screen device 1 necessary that can be, as is the case for a special synibole

at the time of line counter value 1 the output PCG IGR 1 io is required. In such a case, the

of the segment generator PCG I (see also Fig. 6) for the number of UNi ") circuits 552 to 560

Image line must be switched through and that speaking increased or decreased, just like the number

at the time of the line count value 2 PCGlGRl for the image of the inputs of the OR circuit 562.
line must be switched through. In the same way, the output 563 of the OR circuit 562 is on

PCG3GRI must have an input of a synchronization mixer 564 at line count value 3, PCG4GR I 15

at line count 4 and PCG5GRI at line- connected. The second input signal of the syn-

count value 5 for each data field for the video line through the synchronization mixer 564 is the vertical synchronization

switched to a complete horizontal sationssignal 1 on line 651 (see Fi g. 7),

Row of symbols for the display device 1 that is provided by a vertical synchronization counter 650

to reach. ^{M is} generated.

Accordingly, to generate the image sync mixer 564 can be any

signals for the screen device 20 are used in the number of lines of the various circuits that

value 4 the segment generator PCCl GR3, where lines are known from television technology, to

count value 5 PCG2GR 3, at line count value 6 PCG3 information signal a synchronization signal is added.

GR3, add PCG4GR3 at line count value 7 and at 25 so that the correct display on a picture

Line count value 8 PCG5GR3 for the video line for the screen device takes place.
Screen device 20 switched through. The output 565 of the synchronization mixer 564

The outputs of the P / S registers 505, 506, 507, 508 are finally connected to the display device 1, which is the

and 509 are connected to the multiplex picture gates corresponding to the reference numeral 101 , as shown in FIG

speaking of the in F i g. 9 is supplied to the table shown. 30 Fig. 2 can be seen.

In the case of the display device 1, the output 511 is like FIG. 9, the image of the parallel series register 505 is connected to the AND switching signals for the display devices 1 to 8 from the device 552 as an input, as can be seen from the signals GR1 of the segment generators PCG1, PCG2, F i g . 6 and 10. A line 641 generated by PCG3, PCG4 and PCG5. The group signal comes to an eight line counter 640, as shown in FIG. 7 35 GR2 supplies a control signal for generating the picture shows, is to a second input of the AND switching signals for the display devices 9 to 16. The group 552, as shown in FIG. 10 shows, connected in this way, the pen signal GR3 provides the control signals for the Erzeudes that the information on the line 511 for ORing the image signals for the video display devices 17 to 24 circuit 562 is conducted, via an output and the group signal GR4 generates the control signal output line 553 at the count value LCl. Corresponding to 40 for the generation of the image signals for the screen is the output line 512, which PCGLGR1 represents devices 25 to 32.

sentiert, to a first input of the AND circuit. Let us now return to FIG. 9 and 10, reference 554 is connected, while a line 642 is taken from FIG. 3, according to which the image signals for the picture eight-digit counter 640 are fed to a second input of the display device 20, which is shown in FIG. 2 is not shown, AND circuit 554 is performed. The output 555 45 in the AND circuit 572 through the line count 4 of this AND circuit 554 is connected to a second input via the line 644 and PCG1GÄ3 on the line output of the OR circuit 562 and 531 are generated in the AND Circuit 574 through represents the second horizontal line in each field that the line count 5 is to be displayed on line 645 and PCG2- on display device 1. GR3 on line 532, in AND circuit 576. Line 643 is on an input of AND 50 through line count 6 on line 646 and circuit 556 connected along with the line from PCG3GR3 on line 533, in AND device 513 from PCG3GRI. The output 557 of circuit 578 through line count 7 on AND circuit 556 is connected to a third input of line 647 and of PCG4GR3 on line 534 OR circuit 562 and sets the horizontal line in as well as in AND circuit 580 by line third each field for each symbol 55 count value 8 on the line 648 and from PCG5GR2 series, which are generated on the display device 1 on the line 535. The outputs 573, 575, 577, 575 should. A line 644 is connected to an input of the AND and 581 of the AND circuits 572, 574, 576, 578 or circuit 558, just as the line 580 is connected to the relevant inputs of the OR circuit 514 of PCG4GRI to this AND circuit circuit 582 .

connected. The output 559 of this AND 60 also has the OR circuit 582, as well as wi (

Circuit 558 is connected to a fourth input of the OR circuit 562 for generating the image

Circuit 562 connected and represents the fourth line signals for the display device 1, an input for

each field of a row of symbols represents a marking signal on the image.

screen device 1 is to be displayed. A line 645 The marking signal can be on any conventional

is generated at one input of the AND circuit 560 65 and is used at the OR

connected, while line 515 from PCGSGR 1 OR circuits 562 or 568;

at a second input of the AND circuit 560 inserted into the image stream
closed is. The output 561 of this AND circuit The output 583 of the OR circuit 582 is mi

connected to a synchronization mixer 584, in which at another input a vertical synchronization signal 4 arrives over line 654 generated by Yerlikal sync counter 650 will. The sync mixer is 584 identical to the circuit of the synchronization mixer 564; Circuits of this type are in the department well known. The output 585 of the synchronization mixer 584 is connected to the screen device 20 connected to the reference numeral 120.

Timing and control

According to fig. ⁷ , X and 12, a clock signal generator 610 generates a circular clock signal which is used to generate all the clock signals required for the display device control unit 200. The output of the clock generator *, 610 is connected to a synchronization generator 620 via a line 612 and to the group shift counter 630 via the line 613. The synchronization generator 620 generates the horizontal synchronization signal which is present on the line 621 as well as a downward synchronization basic signal which is present on the line 625. The synchronization generator 620 is also connected to the vertical synchronization counter 650 via the line 625 and to the eight-line counter 640 via the line 621.

The eight-line counter 640 generates the line count signals LCl to LCS, which are required for multiplexed image signal switching. The vertical synchronization counter 650 generates a series of η vertical synchronization signals, all of which are offset in time by a horizontal time period, as shown in FIG. 8 can be seen. The vertical synchronization signals 1 to 8 are present on lines 651 to 658. The time shift of the vertical synchronization signals is shown in FIG. 8 shown. There, A equals the time span for a horizontal line, including forward and reverse.

As a result of the time shift of the vertical synchronization signals 2 to 8, the image signals for each of the 32 video display units 101 to 132 (see FIG. 2) on the screen of the display unit can begin at the same relative position. The F i g. 9 it can be seen that if the vertical synchronization signals were not shifted in time, the first raster line of the same symbol would only appear on the display devices 1, 9, 17 and 25 in the first raster line. At the beginning of a second horizontal line scan in each field, the first raster line of the first symbol would then only appear on screen units 2, 10, 18 and 26 in raster line two, at the third horizontal line scan on screen units 3, 11, 19, 27 in raster line three etc .; the display on four further units begins with each subsequent horizontal line until all 32 display devices display symbols.

By staggering the vertical synchronization signal, the image signal for each of the 32 screen devices on the first horizontal line of each field in the same relative location on each display device start.

The group shift counter 630 generates four shift signals, Shift 1 to Shift 4, which are carried on lines 631 or 632 or 633 or 634 . These shift signals are fed to the parallel-series registers, and with their help the image information for the correct screen device is switched through to the multiplex screen at the correct time.

Production of Klcin /. Oak

According to FIGS. 1, 4a and 11 this can so far System described generate a symbol set, the ten horizontal lines for symbol creation as well as claim a further six horizontal lines for the line distance between the symbol rows.

ίο It is most common in alphanumeric display systems to use a symbol set that contains only uppercase characters, which generally means uppercase letters. The system according to the present invention is able to generate lower case characters, ie lower case letters, in which the descender reaches below the base line of the large characters; this also requires two line buffers for 64 characters with three bits each, parallel conversion logic for converting six bits to three bits and two segment generators with permanent memory. This means more precisely that the descenders of the small characters get into the horizontal lines Π to 14.
According to FIG. 4a, the line buffer 350 is connected via the line 216 to a line buffer 360 for 64 characters with three bits, which at its input has parallel conversion logic for converting six bits to three bits, in addition to its connection to the segment generator 460.

The output 218 of the line buffer 360 leads to a segment generator 470 and further to the input a line buffer 370. Line buffers 360 and 370 can hold a full series of 64 characters of three each Store bits. As a three-bit character enables eight combinations, and as es there are five lower case letters in a normal alphabet which go below the baseline (g, j, p, q, y), and a coding for upper and lower case characters that do not go below the baseline Deactivation of the segment generators 470 and 480 is reserved, two codings remain, those for other symbols in grid lines 11, 12, 13 and 14 of each horizontal row of symbols can be used. The output 478 of the segment generator 470 and output 488 of segment generator 480 is to additional parallel-serial registers which have to be added for the small symbols.

Furthermore, additional logic is necessary for the execution of the parallel series register as well as further multi-tipiex AND gates, which are required to generate small characters.

System expansion

12, the number of display devices that can be connected to the system according to the present invention can be increased from 32 to 64 by dividing a set of segment generators 410, 430, 440, 450 and 460 into two groups 491 and 492, with which the odd and even fields of the two groups of display devices are generated at the same time. The odd-even flip-flop 417 switches lines 208, 210, 212, 214 and 216 to the segment generators 491 or 492 when the fields change, so that the read-only memory elements 420 (see FIG. 5) of each segment generator do 100%. to take advantage of.

The complete double structure is not shown, since it was after the previous description of the Basic design is unique.

Generation of color information

According to Figures 13 and 14, the present invention includes embodiments for Generation of color information for display on a screen device, either on the basis of the Color information character by character, as shown in FIG. 14, or on the basis of the color information Word by word as shown in FIG.

Color word for word ¹ S

The buffer outputs 208, 210, 212, 214 and 216 are not only sent to the segment generators, as in FIG. 4, but also to an AND circuit 710, as shown in FIG This color code signal appears only in the space between the words in the flow of information to be displayed of the color switch 1 720 is connected to a first input of each AND circuit of a group of AND circuits which form the AND group 730. A second input of each of these AND circuits is connected to the eight-digit counter 640, in the example shown are lines 641, 642, 643, 644, 645, 646, 647 and 648. Similarly, an AND circuit and a color sounder in each group of '.'<i} gates are required for each of the segment encoders 410, 430, 440, 450, and 460 shown in Figure 4. These parts are not shown here because they are replicas of the logic that is required to generate the color information for the first two lines of each symbol, which is represented by the output signal from the segment generator PC (H. The output 731 of the first AND circuit in the AND group 730 is connected to a first input of an OR Circuit 780 '. The outputs 2 to 8 of the AND group 730 are connected to other OR circuits for generating ear information for the display devices other than display device I. The second output is the same 742 of the AND group 740 connected to a temporary input of the OR circuit 7JtO, the third output 753 of the UNI) -Gnippe 750, the fourth output 764 of the AND group 760 and the fifth output 775 of the AND group 770 are in corresponding W also connected to the respective inputs of the OR circuit 780 in order to provide a complete color information Ro for a word of symbols, each of which takes up ten horizontal lines on a display device.

The AiisjKinj! 781 of the OR circuit 780 is connected to an AND soundiinj! 784 and to an inverter 782 fir, ani'iM lil (isMi). The Ansj'anj.'783 of the inverter 782 is at riren ciMen I inj'ani ¹ a 1 ¹ NI) -Si1iallimt! 786 aiij'L- '. Tlilossen. One / far input is provided to AND circuits 784 and 786 from the associated mulliplex image gates 562 on line 563, as shown in FIG. 10 shown. The output of the UN D circuit 784 supplies a shift signal to a three-bit color shift register 790. The output 787 of the AND circuit 786 forms a through-circuit for the color gates 794, 796 and 798. The three primary colors RoI, green and blue are through the outputs 791, 792 and 973 of the color shift register 790 are shown and are connected to second inputs of the "color gates 794, 796 and 798. The outputs 795, 797 and 799 of the color gates 794, 796 and 798 are connected to a circuit 810 which is called" Color — gray level encoder and synchronization mixer ". The vertical synchronization signal 1 on line 651 is fed to circuit 810 so that the correct synchronization signals are present. The output 811 of the" color gray level encoder and synchronization mixer " 810 supplies image signals for the display device 1, and these signals can be used in addition to the information that is to be displayed he contain the word color or about the shades of gray.

With the definition of the color of words on the screen device described here, it goes without saying the gray tone rendering of the information to be displayed can also be specified.

Color sign by sign

In FIG. 14 is an exemplary embodiment which allows the generation of color information on a character-by-character basis. It is basically required for this mode of operation, three more bits parallel to the symbol code bytes to add color coding for each individual symbol. The lines 208 (compare E i g. 3) Not only are there recourse to storage connected to the generator, but they are now extended so that they have three more lines which are connected to a group of AND circuits 820, which in this case consists of three AND circuits, each of which produces an active output signal when the input signals are a Represent color coding. The output lines 821 of the AND circuits 820 are connected to an additional area 822 of the parallel serial register 505 operating with three bits is connected.

The parts of this run are not detailed here, as they were discussed earlier, either in the description of the basic design of the crfindungsgcmäUcii device or in the completion for the printing of color words.

The I arhinfoimalion that the one working with three bits Area 822 of the parallel series register 505 is now directly on the Dalcnwcg for Imaging brought. The circuits 730, 780 and 790 are the same as previously described. The conductor line is at the input of a counter 824 631. The counter 824 counts continuously to II, and whenever the counter value exceeds 3, it becomes an output signal submitted. The output 825 in question is to an I IND circuit 830 and to an inverter 826 connected, which is connected to an input of the AND circuit 828, which on line 829 the color · transfers information to register 790. If the

15 W 16

If the count value exceeds 3, there is symbol information. Since there are now only three groups of outputs from the point of coloriformalion. Then there is the segment generators, the required effort output line 825 of the counter 824, the AND switching to multiplex logic is significantly reduced.
tung83ü activated, so that the signal on line 831 sends the symbol information through the operating mode
Color information specific gates 832, 834 and 836, respectively

can get. The outputs 833, 835 and 837 of these. Referring to FIG. 2, 3, 4 and 5 gates are again connected to first inputs of OR - now the operation of a preferred embodiment circuit 840, 842 and 844, the form of the invention described,
in turn back to the signaling 810 "color-gray io the information that is to be displayed is level encoder and synchronization mis ^ her" to the central processing unit 50 (FIG. 2) are closed. Via lines 52 to the screen device control unit. It should be pointed out again that every 200. The screen device control unit 200 of the embodiments described so far only then generates suitable image signals for the sent signal path for the screen device 101 to which screen devices have been specified, specifically in accordance with the. The same circuits are for each of the information it receives from the central processing other 31 display devices in the unit 50 described here. These image signals are provided via a typical Leitsystem, and the necessary lines 201 to the video display devices 101 to 132 connections are carried out according to the table in FIG.

F i g. 9. 20 The display device control unit 200 takes the

Information from the central processing unit

Reduced system _{50 with nj} | _{fe of the} input-output control unit 204

In those applications where only soft (Fig. 3); this performs all of the required a small number of display devices to the picture interfaces information exchange with the central screen device control unit is connected, processing unit 50 is through. The information will A system as small as possible is desired, in order to then be transferred to the recourse memory 300 and avoid liquid components. In the F i g. 15 and 16 are stored in core memory 302. In the right time, such a system is shown in a scaled-down version which shows the timing and control unit 600, in which the character generator is symbol-correct (FIG. 3), information bytes which information generated for four display devices only. 30 represent the symbols to be displayed.

In this embodiment, the output of the core is transferred to the first line buffer 310. The line memory 302 (see also FIG. 4) at the input of the buffer 310 acts as a buffer between the core memory segment generators PCG 1 with the reference numeral 410 302 and the first segment generator PCd 1 with and to a group of OR circuits 308 to reference lines 410. Line buffer 310 is closed in. The output signals of the OR switch are not required for those applications in which lines 308 are simultaneously the input signals of the operating speed of the core memory with the line buffer 310. The outputs of the line buffer 310 of the segment generator are comparable. The segments are connected to the segment generator PCG 2/4 with the generator 410 (PCGX) generates the first scanning line drawing characters 430 and to the line buffer 320 to one symbol in each symbol row for the odd ones. The outputs of the line buffer 320 are 40 horizontal scans and the second line of a scan connected to the segment generator PCG3 / 5 with the reference symbol in each symbol row for the even horizontal characters 440 and to AND circuits 306 corresponding to the information. A counter 660, which is an eight line counter, bytes from line buffer 310.

similar to line counter 640, with additional gates each of line buffers 310, 320, 330, 340 and 350

for generating output signals C1, C3, C4 and 45 causes a delay of one sampling period

C5 is on an input line 621 for one horizontal line, so that the output signals

connected, on which the signal Morizontalsynchron- from the line buffer 310 to the line buffer 320,

sation is pending (see Fig. 7). The counter 660 from the line buffer 320 / u to the line buffer 330,

accordingly has the output signals C2, C3, C4 and from the line buffer 330 to the line buffer 340

CS. The signals C2 and C'4 are the segment 50 and from the line buffer 340 / u the line buffer

generator PCG1] A r. with the reference numeral 430 to 350 at the beginning of a Syinbolreihc. Generated

guided and control the mode of operation of this segment - is thus, according to the 1st input signals from

generator in such a way that either the drill and the relevant Zcilciipiiffcrn, from the Scgmcnt-

the fourth line of a symbol or the seventh and eighth generator PCGl 430 the third / line of each symbol

Line of a symbol is generated. Similarly, 55 bols in a row for the odd horizontal ones

the outputs Ci and C5 of the counter 660 are the samples and the quarters of each symbol in

Segment generator PCG3 / 5 with reference character 440 of a row for straight horizontal loads,

supplied, whereby the segment generator PCG3 so from the segment generator PCG3 440 the fifth line

it is controlled that lines 5 and 6 of a symbol of each symbol in a row at the odd horizontal

or. 9 and 10 of a symbol can be generated. The off-zone scans and the sixth line one

Output C3 of counter 660 is also associated with each symbol in a row with the even horizontal ones

the AND circuits of the AND group 306 vcr samples, from the segment generator PCG4 450

bundcn so that one cycle of the symbol information at the seventh line of each symbol in a row

malion is possible. The outputs of the AND group correspond to the odd horizontal samples as well as the

306 are connected to the second group of inputs of the 65 eighth line of each symbol in a row

OR signals 308 connected so that the straight horizontal scans and finally from

Wicdciumlauf the Symboliiifoimalion to the line- the Segmenlgcneiator / '(' (/ 5 460 the ninth line

buffer 310 can be done. of each symbol in a row for the odd ones

17 18

horizontal scans and the tenth line of one in turn are the image signals for each screen Symbols in a row for the straight horizontal units 109 to 116, 117 to 124 and 125 to 132.

talen samples. Due to the working speed of the core

It is clear that this system will be expanded to include memory 302 and segment generators 410 bis

that larger characters can be dealt with, 5 460, it is possible to use four signal groups in parallel or can be shrunk so that smaller characters can be a single group of line buffers and a can be dealt with by processing that single segmented character generator.

Line buffers and segment generators added or according to FIGS. 6 and 10 transmits the

be omitted. Output line 511 the image signals for the first

The timing and control circuit 600 controls the io segment of each symbol that appears on the screen

the switching through of each of the four groups of information devices 101 to 108 is to be displayed; the multi

mationssignellen from the line buffers to the segment piex gate 552 is through the signal LCl on the Generators over lines 208 etc. and controls line 641 switched on, during the

also the chronological order of the fixed total line 1 of each row of symbols

memory elements 420 to the multiplex image signal 15 odd horizontal scans and during

Generator 500th of the entire row 2 of the first row of each

The output of the character generator 400 series of symbols with straight horizontal placement a parallel signal that samples the image information. The image signal which is transmitted via line 511 contains. The timing and control unit 600 at the time of the first line of an odd horizontal also supplies control and time signals via lines 20, scanning is in hexadecimal notation 604 to the multiplexed image generator SOO. The multi "18" and it is sent via the OR circuit 562 to the plex image generator 500 passes the image signals to the synchronization mixer 564 (FIG. 10). In the synchronization mixer 564, the image output further. Signals synchronization signals added to a

With reference to FIGS. 1, 2, 3 and 11 are intended to obtain 25 composite image signals that are sent to the

the generation of two representative symbols display device 101 is now forwarded. The synchro

explained. nization signal VERTSYNC 1 represents a group of

If, for example, according to FIG. 2 represent scan synchronization signals which cause the wish to place the capital letter A on the first symbol - the grid on the display devices 101, 109, 117 in the first row of symbols on each of the 30 and 125 by a horizontal line scan period of the first eight display devices and the Upper case begins before the raster scan for the image letters B at the second symbol position in the first screen devices 102, 110, 118 and 126 to generate the series of symbols on each of the first eight screen devices synchronously with the synchronization signal VERT screen devices, so does the system work like SYNC 2 ,
follows: 35 This "graduation" of the synchronization signals and

A group of information signals in parallel - thus the raster scan of the groups of image byte form, which represents the symbol A, is made possible by the screen devices that the optical image, central processing unit 50 to the screen which shows each screen device on the same relay control unit 200 given and in the core memory tiven position on the screen of each display device 302 saved. 40 starts.

Each of these information bytes reads "in binary If the synchronization signals are not" staggered " Form 000001; this is the binary representation of what would be, would be when looking at eight screen icons A. At the right moment of time, synchronizing devices next to each other determine that each row sized with the raster scan for the display devices, of characters in the second and the following image the information byte, which is the symbol A for 45 screen devices vertically down by two horizontal ones the first row of symbols of the first screen line, based on the previous screen device represents, moves to the sequential line buffers. The result would then be similar directed (Fig. 4). as in Fig. 1 shown when looking at the first icon

The binary representation 000001 acts as an address for each display device side by side on a single one

would bring a special group of storage elements in the 5 ° overall display device.

Segment generator 410 in which the image representation for In a manner similar to that described above is obtained

the first line of the symbol A is saved. the binary representation 000001 a horizontal line

In binary form using eight bits, the amount of time after the information byte has passed

is the image representation for the first line of the symbol through the line buffer 320 to the segment generator

bols A 00011000. This binary information is also 55 430, which then corresponds to this input

referred to as "18" in hexadecimal notation. The address signal and if the odd-even-

Information in binary representation with eight bits, the flip-flop is in the "odd" state, the

Binary expression 01111110 is generated via lines 428 to the parallel-to-serial converter, which contains line 3

505 passed on (Fig. 6, 6a). of the symbol A. At the same time it comes

The parallel-serial converter 505 brings the image 60 information signal, which is the first symbol for the

representation with eight bits in serial form and gives this display device 102 represents to the segment generator

Series representation via the lines to gate 410. To simplify the explanation, the

552 of the multiplex image generator (see also FIG. 10). first symbol in the first row of symbols on the

Since this example only relates to the data, display device 102 is to be generated, including the

the capital letter A taken for the first eight display devices 101 to 108 65.

In a manner similar to that described above, the other output signals are generated

521, 531 and 541 of the parallel-to-serial converter 505 image signal from segment generator 430 (FIG. 4) in FIG

not explained in more detail. These output signals are brought into series form and passed to gate 554,

which is switched through by the signal LCl during the second line of each row of symbols in each horizontal scan. Accordingly, the BilddarstellungOllilJ ¹ O in the correct time sequence is supplied to the display device one hundred and first

How to get the F i g. 1, the data representing the first line of the first row of symbols for the display device 102 are brought to the display device in a similar manner. The connection is not shown in detail for the case of the video display device 102, since in the table of FIG. 9 the appropriate through-connection conditions for each of the display devices for each line count LC and each segment generator PCG are specified.

In the same way, one horizontal line period later, the information signal representing the capital letter A is fed to the segment generator 440 (FIG. 4), which reacts to generate the image representation 11000011 which corresponds to the fifth line of the symbol A. At the same time, line 3 of the first symbol is generated on the display device 102 , as is line 1 of the first symbol for the display device 103.

In the same way, lines 7 and 9 of the first symbol in the first row of symbols for the display device 101 are generated on the first odd horizontal scan. The image representation for line 7 is 11111111 and for line 9 is 11000011.

At the time at which line 7 is generated on display device 101 , line 5 is generated for display device 102 , line 3 is generated for display device 103 and line 1 for display device 104. It can now be seen that when the first icon to be generated by each display device is displayed, segment generators 410, 430, 440, 450 and 460 (FIG. 4) corresponding to the one shown in FIG. 11, the segment generator 460 does not generate line 9 for the first screen device 101 before the segment generator PCG \ 410 generates the first line of the first symbol for the screen device 105.

With reference to FIGS. 9 and 10 should now be shown how the multiple use of the image representations for generating the visible images on the display device 120 (7Ύ2Ο in FIG. 10) takes place.

The display device 120 is located in the third group of eight display devices combined in multiplex operation. It can be seen that the image signals representing the image to be displayed on the display device 120 are in each case from PCGXGRi on line 531, from PCGlGRi on line 532, from PCGiGRi on line 533, from PCGAGRi on line and from PCGSGRi on line 535 .

Since the display device 120 is the fourth unit in the third group, the staggered synchronization signals are the same as in the case of the display device 104.

The first image line for each symbol that is to be generated on the screen device 120 is therefore switched through by the signal LC4 on the line 644 . This means that during the generation of the fourth segment (line 7 for odd scans or line 8 for even scans) of each symbol on the screen device 101, the first segment (line 1 for odd scans or line 2 for even scans) of each symbol, is generated on the display device 120 In a fclcichc manner, the second segment is generated at the time ν <o, iLC *, the third segment to the ZcI of LC6, the ν.eric seement at the time LCl and the fifth segment

D ^ iitSlnTÄden in synchronization mix. 584 mixed with the vertical synchronization signal Vtrl SYNC 4, so that the visible image which is displayed begins at the same relative SteMe on the display device as be. every other B.! d-

rur ueii Slavic.H.11, character set used here become eight dots in the horizontal direction and ten lines in the vertical direction, plus another six Lines that make up the space between the rows of symbols (line spacing) and another two points, which make up the horizontal space between characters in each row is required by Das I ormat can of course be designed very flexibly, and the invention described can be used in conjunction with any symbol format can be used.

Although the operation of the device according to the invention is now mainly for an odd horizontal Field, the method of operation is the same for a straight horizontal field, however line counts 1 through 8 then represent horizontal lines 2, 4, 6, S, 10, 12, 14, and 16, respectively, for each row of symbols instead of lines 1, 3, 5, 7, 9, 11, 13 or 15.

Lowercase characters

According to the in the F i g. 4a, the system according to the invention offers the possibility of being expanded in such a way that "descenders" can be generated for those Klcinzcichen in which parts are below the baseline for large characters. For the lowercase letters g, j, p, q and y, for example, the part above the baseline of the character is generated in the manner described above, and the part of the character below the baseline, i.e. the descender, is generated using additional Segment generators 470 and 480 created with which it is possible. Generate information for four additional lines of each symbol block.

Line buffers 360 and 370 store 64 three-bit symbols that represent the lowercase information of a symbol to be generated or that indicate the lack of lowercase information. For example, the three-bit character 000 can be used to represent all upper-case characters as well as all lower-case characters that do not extend below the baseline, in which case the segment generators 470 and 480 are not used at all because they consist of three bits existing characters 000 none of the active positions of one of these two segment generators was addressed.

The three-bit character 001 could represent the lowercase letter g and the character 010 denotes Lowercase letter j, the character 011 the lowercase letter p, the character 100 the lowercase letter q and the character 10.1 the lowercase letter y. This information is then switched through by the multiplexing circuit in a manner similar to that for large characters is described. The details of the transit

21 22

Leadership in these characters can result in color signals from one. When the count of the

A person skilled in the art can easily make, counter 824 is over 3, the image information

In view of the foregoing description, which extends through AND circuit 830 to color gates 832,

related to the spontaneous generation of large characters. 834 and 836 stirred. The color image I! Iformation on

5 is then given to lines 833, 835 and 837

System processing _{if with a} marker signal via gates 840, 842

According to FIG. 12 it can be seen that the and 844 to the circuit »color-gray-gray-level-

Number of display devices that the multiplex encoder and synchronization device « 810

Character generator supplied, thereby doubling the brachl. The composite image-color signal that

can that the group of segment generalors in io contains the marking information, is then on the

odd and even subgroups 491 and 492 on line 811 sent to the screen device,

is divided so that a subgroup of segment- As mentioned above, can use the same

generators 491 an odd field for a first system instead of color rendering gray-tinted

Group of 32 display devices. Playback of the picture information to be displayed cr-

while the second group of segment generators 15 is sufficient. Color gray informalion can also be used

492 the image information for a straight horizontal is encrypted with more or less than three bits

Field for the second group of 32 display devices.

^{cr / cllgL Downsized} system

Spontaneous generation of color information _{20 Unlcr Bc} z _U gnahme to FIGS. 15 and 16 is

13 and 14 it can be seen that a now a scaled-down system is described which is intended for characters containing only color information, of which those applications are intended in which a system is easily processed at that time a small group of display devices to a Image can "in which a space between words is attached to a screen unit.
is in any series of symbols. 25 In this embodiment, three Scgmcnt-

Fin word color signal goes to AND gate 710 used by generators 410, 430 and 440 , the

and is determined by this (FIG. 13), segment generator 1 410 always the first line of a

Which"; then the color switch 1 with the reference symbol is generated for each horizontal scan,

character 720 sets. This color switch 1 then remains with the segment generator 430 being the second and fourth

for the whole word, which is displayed in a special color on each 30 line of each symbol on each horizontal line.

should be confirmed. The image information is generated by scanning and the segment generator 440

The segmented character generators then use the third and fifth lines of each symbol to create a horizontal

dcm 1 arbschattcrsignal generated over a series of logical scans. To get this downsizing too

gates to the color shift register 790. The information bytes that the

The output of the color shift register is determined to represent 35 symbols to be generated, one more time

which combination of the three gates 794, 796 and 798 circulate through the line buffers 310 and 320. When

in the Color-Grau-Nivcau-Encoder and Synchroni- the first line of each symbol from the segment generator 1

The information signals are sent to the station 10 encrypted and to which the image 410 is generated

schirmgcrätc is given. It should be noted here that the segment generator is 430 and the control line is C2

instead of color information, gray tone information is also activated, which indicates that the second line of each symbol

mationcn is to be transmitted with the same system and generated verbally. In the same way becomes a

can be worked. horizontal line span later the control line

In the embodiment for color information C3 is active, whereby it is the segment generator 440

Sign Door Signs (Fig. 14) will be the third line of each symbol at each facility used to produce essentially the same as 45 horizontal scan

im 1 all of the execution type for color information but then the whole system is not yet complete

Word for word, with the exception that the color code is when riser C3 is active, the information runs

parallcl with each symbol, which is displayed mation at the output of the line buffer 320 via the

is to be supplied and, as an additional three bits, gate 306 to the ODF K circuit 308, from where it is then carried out through the parallel scribe converter. The 50 this information / to ZcilcnpulTer 310 is brought.

Counter 824 is connected to shift line 631 . As a result, the scan generator 430 can use the second

thus between color information, which during the passage of the information signals the fourth line

first three bits are present and image information that is generated for each symbol that is to be generated,

the iiits 4 and 11 are available, can be distinguished. when the control line CA is active and the control line The counter 824 is reset at count 11, 55 C2 is inactive. Similarly, a horizontal line is

since this counting word activates the sequence C5 later a full character from the color information time span bc

mation and image information. inactive structure C3, so that the segment

If the count of the counter 824 is below 3, generator 440 the fifth line of each symbol bc

will be able to generate the information from the parallel-sericn-order every horizontal scan. Zi sclzcrn 505 and 822 / u dem 1 arbschicbcrcgistcr 790 60 at this point in time the information signals are running, d:

brought that then decrypts the color information the StcticrlciUing Γ3 is not active, not through dii

and Sipnalc generates which dL · correct primary gates 306.

For this purpose 4 sheets of drawings

Claims (1)

Patent claims: 1. Control unit for an information display system, which in particular receives information can, with several display devices for displaying the symbols in the television grid, with one Memory for receiving and storing the information to be displayed in binary form, a Generator for generating segments of a symbol to be displayed and a multiplex circuit for the distribution of the individual segments to the individual display devices as well as for the composition of full symbols, characterized by the fact that the memory (3GO) as access memory from a core memory (302) as asynchronous storage, to which the input information are supplied, and a storage part connected to it, which is synchronous with the raster display and which consists of a number of line buffers (310, 320, 330, 340, 350) for receiving and temporarily storing one each Line of symbols corresponding binary information signals is built up that at the output (208, 210, 212, 214, 216) of each line buffer (310, 320, 330, 340, 350) one segment generator (410, 430, 440, 450, 460) is connected, with each segment generator (410, 430, 440, 450, 460) a Line segment of the binary supplied by the respective line buffer (310, 320, 330, 340, 350) Symbol signal corresponding symbol generated that the line buffers (310, 320,330,340, 350) are connected in series that the output (208) of the first line buffer (310) also as The input is routed to the second line buffer t320) and so on, until finally the output (214) of the penultimate one Line buffer (340) is fed as an input to the last line buffer (350) that each segment " generator (410, 430, 440, 450, 460) contains a read-only memory (420) which contains the video information to be displayed of the segment to be generated by the segment generator (410, 430, 440, 450, 460) each to be displayed Symbol contains that finally the outputs (428, 438, 448, 458, 468) of the segment generators (410, 430, 440, 450, 460) to the multiplex circuit (500) for assembly unit Distribution of the symbol segments to the display devices (101 to 132) are connected. 2. Control unit according to claim 1, characterized in that the number of line buffers (310, 320, 330, 340, 350) and the number of segment generators (410, 430, 440, 450, 460) of the number corresponds to the number of raster lines required to display a symbol line. 3. Control unit according to claim 1, characterized in that the number of line buffers (310, 320, 330, 340, 350) and the number of segment generators (410, 430, 440, 450, 460) with an even number Number of raster lines half of the number of raster lines required to display a symbol line the read-only memory (420) of each segment generator (410, .430, 440, 450, 460) by means of a flip-flop circuit (417) on the corresponding to the even or odd raster lines Symbol segments is switchable. 4. Control unit according to one of the preceding claims, characterized in that a Timing and control unit (600) synchronization signals for the memory (300), the symbol generator (400) and the multi-plex circuit according to claim 4, characterized in that the timing and control unit (600) for the generation of a number of Sets of synchronization signals are provided, each set of Synchronisat.onss.gnalen a group of display devices is synchronized and the vertical synchronization signal within the group is separated in time from the previous one by an integral number of horizontal line time periods, whereby the presentation of the information on each of the presentation devices in the same relative location begins. 6. Control unit according to one of the preceding claims, characterized in that a conversion circuit (790, 810) for characteristic information (color / gray value) for generating characteristic Darsiellui.gsarten is provided for each symbol to be displayed, which is associated with the multiplex circuit (500 ) connected is.
• 7. Control unit according to one of claims 1 to 5, characterized in that a conversion circuit (790, 810) for characteristics information (color / gray value) is provided for generating characteristic types of representation for groups of symbols to be displayed, which are associated with the multiplex Circuit (500) is connected. 8. Control unit according to one of the preceding claims, characterized in that the segment generators a first set of segment generators (410, 430, 440, 450, 460) for generation a first set of symbols (e.g., capital letters) and a first part of a second set of symbols (e.g. lowercase letters) and a second set of symbol generators (470, 480) for generation of a second part (e.g. descenders) of the second symbol set. 9. Control unit according to one of the preceding claims, characterized in that switching means (306, 308, 660) for introducing symbol generator input signals into a feedback branch are provided to the input signals to the inputs of the segment generators (430, 440) for multiple use several times to be supplied (Fig. 15). 10. Control unit according to claim 9, characterized in that a first set of segment generators (410) for generating a first set of segments of each symbol to be displayed is provided and that a second set of segment generators (430, 440) is provided for generating a plurality of segments in each segment generator of this second set of Segment generators that the generation is under the control of the switching means (306, 308, 660) takes place in such a way that each segment generator of the second set of segment generators has several Segments of each symbol to be displayed are generated. 11. Control unit according to claim 1, characterized in that the fixed saliva (420) consists of a Number of individual memories is constructed, each of which has a single binary representation of a single segment of a symbol to be generated. 13. Control unit according to claim 11, characterized characterized in that the individual memories are constructed from magnetic memory elements. fan and tw to be able to do one n group of Dar