DE202022103193U1 - A system for developing a lightweight block cipher for resource-constrained applications - Google Patents

Abstract

A system (100) for developing a lightweight block cipher, the system (100) comprising:
a key formation module (102) for forming a plurality of round keys, each 4-bit wide, derived from a plurality of sub-keys obtained by dividing the 64-bit master key into a plurality of parts, wherein the multiple subkey sequences generated from the 64-bit master keys provide resilience to key attacks;
an encryption module (104) connected to the key generation module (102) and having XOR and XNOR gates (104a, 104b) for repeatedly passing the generated keys through the gates in a plurality of successive rounds, after each round Intermediate ciphertext outputs are generated, which are immediately fed to a next round to obtain a final ciphertext (CT) output, processing the round keys to obtain a 64-bit plaintext given as input to ensure maximum security in a cipher with only the gate count consumed by the XOR and XNOR gates, resulting in reduced gate area consumption; and
a decryption module (106) coupled to the encryption module (104) for performing decryption of the ciphertext output, the decryption technique being performed by forming an inverse operation of the encryption technique performed by the encryption module (104).

Description

FIELD OF THE INVENTION

The present invention relates to a field of encryption devices. In particular, the present invention relates to a field of developing a lightweight block cipher for resource-constrained applications.

BACKGROUND OF THE INVENTION

The Internet of Things (IoT) is an enormous research topic that has reformed human life through its ability to offer myriad advanced computing capabilities. Today's world is rapidly changing and becoming intelligent through various demanding application areas with the blessing of IoT. The IoT is evolving amazingly fast in the world of information and data, but continued growth can be severely hampered by a lack of adequate privacy and security measures. The main function of IoT devices is to collect different types of data collected by different sensors, some of which are extremely sensitive and confidential and should not be shared.

Data security is the number one concern of today's IoT users, according to a survey across industries. For this reason, applying the concept of cryptography is a good option for the physical limitations of IoT devices. Before sending to the backend cloud server, IoT devices use cryptographic algorithms to maintain the integrity of the data and prevent hackers from spying on the data.

In the last decade, the block cipher, which is a type of secret-key cryptographic approach, has proven particularly useful for achieving easy implementation in hardware and software due to its high diffusion and error propagation properties.

KR101387799B1 discloses about the encryption method that the data input block is reversibly processed to generate at least partially randomized character strings. The randomized string is then encrypted by the block cipher. During decryption, the input block of the encrypted data is first decrypted in connection with the block cipher. After that, the randomization is reversed.

The old block cipher requires about 3400 gate equivalents (GE) of area. It is very difficult for traditionally designed block ciphers for wireless devices to be implanted into the device. The gate equivalent is a unit used to measure the complexity of manufacturing-independent digital circuits. Conventional structured Feistel ciphers require an enormous amount of time and energy to produce block ciphers because they go through a large number of round functions compared to the substitution permutation network (SPN).

Few popular algorithms are still used in various application areas such as Tiny Encryption Algorithm (TEA), HIGHT, mCRYPTON, CLEFIA, PRESENT, KTANTAN and KATAN, GOST, PICCOLO, SPONGENT, Light Encryption Device, PHOTON, KLEIN, PRINCE, Low power Encryption Algorithm ( LEA), MIDORI, PRIDE, SIMON and BACON are used. A few new lightweight cipher blocks were discussed that heralded the Substitution Permutation Feistel Network (SFN) encryption method by combining both the Feistel structure and the Substitution Permutation Network (SPN) together. The above method uses a 64-bit input with a key length of 96 bits, with the last 32 bits of the key acting as a control signal and the remaining 64 bits used for key expansion and the round-shape encryption process. HIGHT is an ultra-light block cipher intended to be used for resource-efficient devices such as sensors in USN or RFID tags that perform simple operations using 3048 GEs in 0.25 µm technology to be energy efficient. Another 64-bit block cipher for tiny resource-constrained devices called mCRYPTON encrypts data in twelve rounds using nibble-wise substitution, column-wise bit permutation, column-to-row transposition, and addition of the key. The hardware implementation requires 2420 GEs. A well-known Russian encryption algorithm GOST 28147-89 has been revised by optimizing its design by choosing only one S-Box instead of eight different boxes to reduce the footprint to 651 GE. Researchers developed a new member of the family of lightweight block ciphers for resource-constrained devices like sensor nodes and RFIDs called KLEIN, which uses an SPN structure for encryption and decryption and requires 2629 gates in area. Some researchers proposed a collection of lightweight cipher blocks called CHAM, based on a four-tab Feistel structure, containing addition, rotation, and XOR (ARX) operations. This design requires little space when implemented in hardware because the keys selplanning is easy without updating the status of the key. In order to use the reduced set of keys repeatedly in the iteration, the various round functions in this method are designed in this way. LiCi, a lightweight block cipher algorithm developed by one company, consisted of lightweight substitution fields of dimension 4 x 4 that went through 31 rounds consecutively. This design supports 64-bit input as plaintext with a key length of 128 bits. Gate equivalent area, memory, and power consumption were 1153 GEs, 1944 bytes, and 30 mW.

In 2017, a researcher presented a lightweight approach to SPN-based cryptographic encryption called BORON, where the input was 64-bit plaintext and a key length of 128 or 80 bits. This method included 25 levels of encryption with 4 x 4 substitution fields and operations such as round permutation, bit shifting and XOR, making it resistant to differential and linear attacks. For a 128-bit key and an 80-bit key, the footprint for the software and hardware implementation of BORON is 1939 GE and 1626 GE, respectively. The architecture of PRESENT was revised and an improved version of the SPN-based block cipher called GIFT was proposed. This new method essentially introduced a cheaper and smaller S-Box by presenting a bit permutation that resulted in less circuit complexity and faster computation. With a constant key size of 128 bits, GIFT had two variants: GIFT 64 and GIFT 128 with 28 and 40 encryption rounds, respectively. A new algorithm for a 64-bit block cipher called QTL has been introduced by researchers for encryption that merges a substitution permutation network and a regular Feistel network. The main disadvantage of QTL is its inability to protect against normal statistical attacks. A family of lightweight compact regular cipher blocks combining the advantages of SIMON and SPECK, both known as SIMECK. The implementation in hardware took place in a 130 nm and 65 nm CMOS process. SIMECK showed its weakness against random byte error attacks and bit flip error attacks.

Therefore, in order to overcome the above limitations, there is a need to develop a system that implements a lightweight symmetric key cryptography method for lightweight IoT devices that overcomes all the shortcomings in previous works.

The technical advance disclosed by the present invention overcomes the limitations and disadvantages of existing and conventional systems and methods.

SUMMARY OF THE INVENTION

The present invention relates generally to a system for developing a lightweight block cipher for resource-constrained applications.

An aim of the present invention is to combine the advantages of Feistel and substitution combination network (SPN) to achieve a fast diffusion process;

Another object of the present invention is to provide a circular key management strategy compatible with the encryption technique

Another object of the present invention is to provide energy efficient hardware that consumes less node power and uses more gate operations to provide sufficient protection with lower power consumption, and

A further aim of the present invention is to enable encrypted and secure transmission of data.

In one embodiment, a system for developing a lightweight block cipher, the system comprising: a key formation module for forming a plurality of round keys each 4-bit wide and derived from a plurality of subkeys obtained by partitioning the 64th -bit master key are obtained into a plurality of parts, with the plurality of subkey sequences generated from the 64-bit master keys providing resilience to key attacks an encryption module connected to the key generation module and having XOR and XNOR gates to repeatedly pass the formed keys through the gates in a plurality of successive rounds, with intermediate ciphertext outputs being produced after each round, which are immediately fed to a next round to obtain a final ciphertext (CT) output, wherein the round keys are processed, to a 64-bit Kla to obtain rtext given as input to achieve maximum security in a cipher while consuming only a number of gates by the XOR and XNOR gates, resulting in reduced gate area consumption; and a decryption module connected to the encryption module is connected to perform a decryption of the ciphertext output, the decryption technique being performed by forming an inverse operation of the encryption technique performed by the encryption module.

In one embodiment, a plurality of sensors included in cryptographic chips convert unmasked measured data into masked data to configure a sensor-level encryption mechanism.

In one embodiment, an analog-to-digital converter coupled to the plurality of sensors converts an analog signal generated by the plurality of sensors into a digital signal that becomes an input to the security chip.

In one embodiment, the digital signal is encrypted based on a cryptographic technique and transmitted for storage in a cloud server after passing through a data analysis center, where an authorized user from the cloud server accesses the encrypted ones provided by a cloud service provider accesses data.

In one embodiment, sixteen round keys, each 4 bits wide, are derived from eight subkeys obtained by splitting the 64-bit master key into sixteen parts.

In one embodiment, the formed key undergoes an iterative series of steps involving the XOR and XNOR gates for eight consecutive rounds of operation, with the output produced upon completion of eight consecutive rounds being the final ciphertext (CT) output.

In one embodiment, a first bit obtained after an XOR or XNOR operation goes to the first two bits in the next round, followed by the first bits from each of the four-bit groups, with the second bit from the Four-bit group is rearranged in such a way that mixing and scrambling occurs.

In one embodiment, a 64-bit key of the encryption method is first divided into sixteen 4-bit subkeys, which in turn are fed to the key generation module, which primarily scrambles the bits of the input and provides sixteen round keys of 4-bit length, where the round keys used in encrypting the data to provide the ciphertext output in all subsequent rounds of the encryption process.

In order to further clarify the advantages and features of the present invention, a more detailed description of the invention will be made by reference to specific embodiments thereof illustrated in the accompanying figures. It is understood that these figures show only typical embodiments of the invention and therefore should not be considered as limiting its scope. The invention will be described and illustrated with additional specificity and detail with the accompanying figures.

character list

• 1 ein Blockdiagramm eines Systems zur Entwicklung einer leichtgewichtigen Blockchiffre zeigt,
• 2 ein architektonisches Layout des Verschlüsselungsprozesses von mICRO zeigt, und
• 3 ein architektonisches Layout der Sub-Schlüsselgenerierungseinheit von mICRO zeigt.

These and other features, aspects and advantages of the present invention will be better understood when the following detailed description is read with reference to the accompanying figures, in which like characters represent like parts throughout the figures, wherein:

• 1 shows a block diagram of a system for developing a lightweight block cipher,
• 2 shows an architectural layout of mICRO's encryption process, and
• 3 shows an architectural layout of mICRO's sub-key generation unit.

Furthermore, those skilled in the art will understand that the elements in the figures are presented for simplicity and are not necessarily drawn to scale. For example, the flow charts illustrate the method of key steps to enhance understanding of aspects of the present disclosure. Furthermore, one or more components of the device may be represented in the figures by conventional symbols, and the figures only show the specific details relevant to an understanding of the embodiments of the present disclosure to avoid deleting the figures with details to overload, which are easily recognizable to those skilled in the art familiar with the present description.

DETAILED DESCRIPTION

In order to promote an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the figures and specific language will be used to describe the same. It should be understood, however, that no limitation on the scope of the invention is intended thereby, contemplating such changes and further modifications of the illustrated system and such further applications of the inventive principles illustrated therein will occur that would normally occur to one skilled in the art.

Those skilled in the art will understand that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not to be taken as limiting.

When this specification refers to "an aspect," "another aspect," or the like, it means that a particular feature, structure, or characteristic described in connection with the embodiment is present in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment," "in another embodiment," and similar phrases throughout this specification may or may not all refer to the same embodiment.

The terms "comprises," "comprises," or other variations thereof are intended to cover non-exclusive inclusion such that a method or method that includes a list of steps includes not only those steps, but may also include other steps that do not expressly stated or pertaining to any such process or method. Likewise, any device or subsystem or element or structure or component preceded by "comprises...a" does not, without further limitation, exclude the existence of other devices or other subsystem or other element or other structure or other component or additional device or additional subsystems or additional elements or additional structures or additional components.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The system, methods, and examples given herein are intended to be illustrative only and not limiting.

Embodiments of the present invention are described in detail below with reference to the attached figures.

1 Figure 12 shows a block diagram of a system (100) for developing a lightweight block cipher, the system (100) comprising: a key formation module (102), an encryption module (104), XOR and XNOR gates (104a, 104b), a decryption module ( 106), a plurality of sensors (108), an analog to digital converter (110), a cloud server (112) and a data analysis center (114).

The key generation module (102) for forming a plurality of round keys each having a 4-bit width derived from a plurality of sub-keys obtained by dividing the 64-bit master key into a plurality of parts, the plurality of Subkey sequences generated from the 64-bit master keys provide resiliency against key attacks. A 64-bit key of the encryption method is first divided into sixteen 4-bit sub-keys, which in turn are fed to the key generation module (102), which primarily scrambles the bits of the input and provides sixteen round keys of 4-bit length, where the round keys used in encrypting the data to provide the ciphertext output in all subsequent rounds of the encryption process.

The encryption module (104) is connected to the key generation module (102) which includes XOR and XNOR gates (104a, 104b) to repeatedly pass the generated keys through the gates in a plurality of consecutive rounds, with intermediate after each round - ciphertext outputs are generated, which are immediately fed to a next round to obtain a final ciphertext output (CT), processing the round keys to obtain a 64-bit plaintext given as input for maximum security in a cipher with only the gate count consumed by the XOR and XNOR gates, resulting in reduced gate area consumption. The digital signal is encrypted based on a cryptographic technique and transmitted for storage in a cloud server (112) after passing through a data analysis center (114), where an authorized user from the cloud server (112) accesses the data from a accesses encrypted data provided by cloud service providers.

The first bit obtained after the XOR or XNOR operation goes to the first two bits in the next round, followed by the first bits from each of the four-bit groups, with the second bit from the four-bit group is arranged again in such a way that mixing and scrambling occurs.

The key formed goes through an iterative series of steps involving the XOR and XNOR gates for eight consecutive rounds of operations, with the upon completion output produced by eight consecutive rounds is the final ciphertext (CT) output.

The decryption module (106) is connected to the encryption module (104) to perform decryption of the ciphertext output, the decryption technique being performed by forming an inverse operation of the encryption technique performed by the encryption module (104).

The majority of the sensors (108) are contained in cryptographic chips that convert unmasked measurement data into masked data to configure a sensor-level encryption mechanism.

The analog to digital converter (110) is connected to the plurality of sensors (108) and converts an analog signal generated by the plurality of sensors (108) to a digital signal that becomes an input to the security chip.

$${\text{K}}_2=\text{K1}\left[2\right],\text{K2}\left[2\right],\text{K3}\left[2\right],\text{K4}\left[2\right]$$

$${\text{K}}_3=\text{K1}\left[3\right],\text{K2}\left[2\right],\text{K3}\left[2\right],\text{K4}\left[3\right]$$

$${\text{K}}_4=\text{K1}\left[4\right],\text{K2}\left[4\right],\text{K3}\left[4\right],\text{K4}\left[4\right]$$

$${\text{K}}_5=\text{K5}\left[4\right],\text{K6}\left[1\right],\text{K7}\left[1\right],\text{K8}\left[1\right]$$

$${\text{K}}_6=\text{K5}\left[2\right],\text{K6}\left[2\right],\text{K7}\left[2\right],\text{K8}\left[2\right]$$

$${\text{K}}_7=\text{K5}\left[3\right],\text{K6}\left[3\right],\text{K7}\left[3\right],\text{K8}\left[3\right]$$

$${\text{K}}_8=\text{K5}\left[4\right],\text{K6}\left[4\right],\text{K7}\left[4\right],\text{K8}\left[4\right]$$

$${\text{K}}_9=\text{K9}\left[1\right],\text{K10}\left[2\right],\text{K11}\left[1\right],\text{K12}\left[1\right]$$

$${\text{K}}_{10}=\text{K9}\left[2\right],\text{K10}\left[2\right],\text{K11}\left[2\right],\text{K12}\left[2\right]$$

$${\text{K}}_{11}=\text{K9}\left[3\right],\text{K10}\left[3\right],\text{K11}\left[3\right],\text{K12}\left[3\right]$$

$${\text{K}}_{12}=\text{K9}\left[4\right],\text{K10}\left[4\right],\text{K11}\left[4\right],\text{K12}\left[4\right]$$

$${\text{K}}_{13}=\text{K13}\left[1\right],\text{K14}\left[1\right],\text{K15}\left[1\right],\text{K16}\left[1\right]$$

$${\text{K}}_{14}=\text{K13}\left[2\right],\text{K14}\left[2\right],\text{K15}\left[2\right],\text{K16}\left[2\right]$$

$${\text{K}}_{15}=\text{K13}\left[3\right],\text{K14}\left[3\right],\text{K15}\left[3\right],\text{K16}\left[3\right]$$

$${\text{K}}_{16}=\text{K13}\left[4\right],\text{K14}\left[4\right],\text{K15}\left[4\right],\text{K16}\left[4\right]$$

2 shows an architectural layout of mICRO's encryption process. All rounds of the encryption process require sixteen round keys, which are generated from the sixteen subkeys K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11, K12, K13, K14, K15 and K16. 16 round keys {K ₁ , K ₂ , K ₃ , K ₄ , K ₅ , K ₆ , K ₇ , K ₉ , K ₁₀ , K ₁₁ , K ₁₂ , K ₁₃ , K ₁₄ , K ₁₅ , K ₁₆ } become both needed for both the encryption and decryption processes, and the same subkeys are used for both processes. The round key for each round is generated by the key generation module by taking the subkeys for each round. Input to key generation module = Ks (subkey). Key generation module output = Kr(round key). The round keys are generated as follows: $${\text{<figure-callout id="1" label="K" filenames="DE202022103193U1\_0018.png,DE202022103193U1\_0019.png" state="{{state}}">K</figure-callout>}}_1=\text{K1}\left[1\right],\text{K2}\left[1\right],\text{K3}\left[1\right],\text{K4}\left[1\right]$$

$${\text{<figure-callout id="2" label="K" filenames="DE202022103193U1\_0018.png,DE202022103193U1\_0019.png" state="{{state}}">K</figure-callout>}}_2=\text{K1}\left[2\right],\text{K2}\left[2\right],\text{K3}\left[2\right],\text{K4}\left[2\right]$$

$${\text{<figure-callout id="3" label="K" filenames="DE202022103193U1\_0018.png,DE202022103193U1\_0019.png" state="{{state}}">K</figure-callout>}}_3=\text{K1}\left[3\right],\text{K2}\left[2\right],\text{K3}\left[2\right],\text{K4}\left[3\right]$$

$${\text{<figure-callout id="4" label="K" filenames="DE202022103193U1\_0018.png,DE202022103193U1\_0019.png" state="{{state}}">K</figure-callout>}}_4=\text{K1}\left[4\right],\text{K2}\left[4\right],\text{K3}\left[4\right],\text{K4}\left[4\right]$$

$${\text{<figure-callout id="5" label="K" filenames="DE202022103193U1\_0018.png" state="{{state}}">K</figure-callout>}}_5=\text{K5}\left[4\right],\text{K6}\left[1\right],\text{K7}\left[1\right],\text{K8}\left[1\right]$$

$${\text{<figure-callout id="6" label="K" filenames="DE202022103193U1\_0018.png" state="{{state}}">K</figure-callout>}}_6=\text{K5}\left[2\right],\text{K6}\left[2\right],\text{K7}\left[2\right],\text{K8}\left[2\right]$$

$${\text{<figure-callout id="7" label="K" filenames="DE202022103193U1\_0018.png" state="{{state}}">K</figure-callout>}}_7=\text{K5}\left[3\right],\text{K6}\left[3\right],\text{K7}\left[3\right],\text{K8}\left[3\right]$$

$${\text{K}}_{\mathrm{8th}}=\text{K5}\left[4\right],\text{K6}\left[4\right],\text{K7}\left[4\right],\text{K8}\left[4\right]$$

$${\text{<figure-callout id="9" label="K" filenames="DE202022103193U1\_0018.png" state="{{state}}">K</figure-callout>}}_9=\text{K9}\left[1\right],\text{K10}\left[2\right],\text{K11}\left[1\right],\text{K12}\left[1\right]$$

$${\text{K}}_{10}=\text{K9}\left[2\right],\text{K10}\left[2\right],\text{K11}\left[2\right],\text{K12}\left[2\right]$$

$${\text{<figure-callout id="11" label="K" filenames="DE202022103193U1\_0018.png" state="{{state}}">K</figure-callout>}}_{11}=\text{K9}\left[3\right],\text{K10}\left[3\right],\text{K11}\left[3\right],\text{K12}\left[3\right]$$

$${\text{<figure-callout id="12" label="K" filenames="DE202022103193U1\_0018.png" state="{{state}}">K</figure-callout>}}_{12}=\text{K9}\left[4\right],\text{K10}\left[4\right],\text{K11}\left[4\right],\text{K12}\left[4\right]$$

$${\text{K}}_{13}=\text{K13}\left[1\right],\text{K14}\left[1\right],\text{K15}\left[1\right],\text{K16}\left[1\right]$$

$${\text{K}}_{14}=\text{K13}\left[2\right],\text{K14}\left[2\right],\text{K15}\left[2\right],\text{K16}\left[2\right]$$

$${\text{<figure-callout id="15" label="K" filenames="DE202022103193U1\_0018.png" state="{{state}}">K</figure-callout>}}_{15}=\text{K13}\left[3\right],\text{K14}\left[3\right],\text{K15}\left[3\right],\text{K16}\left[3\right]$$

$${\text{K}}_{16}=\text{K13}\left[4\right],\text{K14}\left[4\right],\text{K15}\left[4\right],\text{K16}\left[4\right]$$

3 shows an architectural layout of mICRO's sub-key generation unit. The process of merging and encrypting occurs without the use of an F-function. On closer inspection, the F-function of each block cipher performs the same confusion and diffusion operation to achieve maximum security in the cipher. No conventional F-box is used here for this purpose. The bit-shuffling operation does not require additional area in terms of gate equivalents. In most literatures, the F-function uses mathematical and logical operations for the confusion and diffusion, resulting in unnecessary consumption of gate area, which also consumes more power. Here this problem is overcome by using a new gateless bit-encryption strategy that also ensures optimal security of the ciphertext by preserving the scrambling and diffusion property. The novel approach is designed to meet all possible necessary constraints, which not only reduces space, energy and deceleration requirements, but also ensures high safety.

According to one embodiment, the proposed lightweight cryptographic system is designed and written in Verilog and its correctness is verified in ModelSim 2020.3 by running the behavioral simulation with one input as 32-bit plaintext and another input as 64-bit key and a 32-bit ciphertext is output. After that, the design is synthesized on a (Virtex-7) XC7VX330T FPGA board with 28nm process using Xilinx ISE 9.2i and Xilinx ISE 14.7 to verify the delay and area parameters. A miniature version of the algorithm with a 16-bit key and plaintext input was implemented on the Artix XC7A100T-CSG324 board to demonstrate real-time execution of the newly developed encryption scheme.

The proposed system turns out to be extremely fast with a combinatorial path control delay of 0.865 ns and has an extremely low LUT count of only 32 out of 20400 and consumes only 196 GE of area, which is less than all previously reported work. In addition, the newly designed system consumes an extremely low power of approximately 0.1567 mW as observed when synthesizing on Synopsys Design Vision with a 65 nm process. The number of LUTs in the design is directly proportional to the area and resource consumption of the system. To reduce the number of gates, the design was made to use a minimal number of logic operations. A total of eight 4-bit XOR gates and eight 4-bit XNOR gates are used throughout the design. Bit jumbling and scrambling operations are the main basis for the confusion and diffusion properties of this encryption strategy. A fair comparison of delay and LUT count between different popular encryption engines (104) after implementation on the same platform.

According to one embodiment, the proposed method is resistant to different types of cryptographic attacks. Some common cryptanalytic techniques are used against this cipher to confirm its security level.

Any block cipher that depends on the length of the key, regardless of the key generation mechanism, is attacked by a key collision attack. This type of cryptographic attack produces a message of ^2k/2 complexity, where the length of the key is k. In this case the complexity of the generated message is 2 ⁶⁴ / ² =2 ³² .

According to one embodiment, mICRO uses eight 32-bit jumblers that perform the same operation as a conventional F-function and are described by thirty-two thirty-one degree algebraic equations, with the number of terms far greater than the 8-bit S -Box from HALKA and PRESENT using a 4-bit S-Box.

The attack via the side channel depends on the data obtained during the implementation of the encryption technology. The proposed system is protected against side-channel attacks since the key used here does not depend on the chosen plaintext and a random number is used for the encryption process. The input and output dependency is negligible in this proposed system. Again, the proposed technique provides security from other types of cryptanalysis. The two weakest parts of any cryptographic technique are the round functions and the key used, seen by an attacker. For this reason, the key generation technique and the design of the round functions are carried out with the utmost seriousness in the development of any encryption method. Cryptanalysts attempt to recover the original key by closely observing the bit patterns of the returned ciphertext when performing appropriate key attacks. Security against this type of attack is guaranteed with the proposed method because it uses different subkeys in different rounds of operation. Therefore, it can be said that the proposed method is well protected from side-channel attacks, since it is extremely difficult for an intruder to discover the correct pattern of the subkeys used in the proposed system.

Self-similarity attacks are used when there is similarity between round features. mICRO's round functions are similar, but the use of variable subkeys prevents the use of these types of attacks on the cipher. The system is set up so that although each round is structurally similar, they are used in reverse order in alternate rounds.

One of the most commonly used cryptanalytic techniques on lightweight block ciphers specifically suited to software platforms is the impossible differential attack. Due to the cipher's Feistel structure, the highest number of rounds in which impossible features can be seen is five, so this type of attack is not valid for this cipher since the number of rounds is eight.

All ciphers analyzed are assumed to have independent values between encryption levels. This does not mean that an assumption is necessarily true, but it can simplify the analysis without changing the result significantly. In addition, the analysis assumes the “worst case”, ie a best-case scenario for the intruder, which in most cases is not the case. So if the assumption isn't even true, it's very likely that our boundaries are far from narrow. The computer-assisted search is used to simplify finding differentials with a high degree of certainty. The best differential trait for a round of ^mICRO has a probability of 2-10. Consequently, (2- ¹⁰ ) ⁸ = 2- ⁸⁰ is the maximum probability for eight rounds of differential features. Even with linear cryptanalysis, the best linear approximation for a round has a probability of ^2-5 , and thus a probability of ^2-40 for eight approach laps. As a result, mICRO is secure against linear and differential attacks.

Like the bottleneck attack and the integral attack, structural attacks use word-like structures in the ciphertext. The permutation used in mICRO is bitwise, which is the reason for its imperviousness to structural attacks, since no word-like structures can be derived in this case.

The number of active ^jumbler blocks messing up the data for 8 rounds is 8. The maximum difference probability for an F-function is about 2-10. So with 8 rounds, the maximum probability is ( ^2-10 ) ⁸ = ^2-80 . Therefore an 8-round differential cannot be used to attack the cipher.

Therefore, a novel lightweight block cipher model called mICRO is presented, which is designed exclusively for extremely resource-constrained IoT devices as it requires very little area and power. This model of the newly introduced cipher uses both the SPN and Feistel structures to take advantage of both structures, linked by the idea of the linear box. The mixed blocks used in mICRO help defend against differential and linear attacks. The use of a small number of gates in the new design greatly improves computation time, and security is maintained through bit-jumping and shuffling. After rigorous safety tests, the proposed system promises a reasonably high level of safety with reasonable delay, power consumption and area consumption.

The figures and the preceding description give examples of embodiments. Those skilled in the art will understand that one or more of the elements described may well be combined into a single functional element. Alternatively, certain elements can be broken down into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of the processes described herein may be changed and is not limited to the manner described herein. Additionally, the actions of a flowchart need not be performed in the order shown; Also, not all actions have to be carried out. Also, those actions that are not dependent on other actions can be performed in parallel with the other actions. The scope of the embodiments is in no way limited by these specific examples. Numerous variations are possible, regardless of whether they are explicitly mentioned in the description or not, e.g. B. Differences in structure, dimensions and use of materials. The scope of the embodiments is at least as broad as indicated in the following claims.

Advantages, other benefits, and solutions to problems have been described above with respect to particular embodiments. However, the advantages, benefits, problem solutions, and components that can cause an advantage, benefit, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component of any or all claims.

Reference List

100

A system for developing a lightweight block cipher.

102

Key generation module

104

encryption module

104a

XOR gate

104b

XNOR gate

106

decryption module

108

A variety of sensors

110

Analog to digital converter

112

cloud server

114

Data Analysis Center

QUOTES INCLUDED IN DESCRIPTION

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Patent Literature Cited

• KR 101387799 B1 [0005]

Claims (8)

A system (100) for developing a lightweight block cipher, the system (100) comprising: a key formation module (102) for forming a plurality of round keys, each 4-bit wide, derived from a plurality of sub-keys obtained by dividing the 64-bit master key into a plurality of parts, wherein the multiple subkey sequences generated from the 64-bit master keys provide resilience to key attacks; an encryption module (104) connected to the key generation module (102) and having XOR and XNOR gates (104a, 104b) for repeatedly passing the generated keys through the gates in a plurality of successive rounds, after each round Intermediate ciphertext outputs are generated, which are immediately fed to a next round to obtain a final ciphertext (CT) output, processing the round keys to obtain a 64-bit plaintext given as input to ensure maximum security in a cipher with only the gate count consumed by the XOR and XNOR gates, resulting in reduced gate area consumption; and a decryption module (106) coupled to the encryption module (104) for performing decryption of the ciphertext output, the decryption technique being performed by forming an inverse operation of the encryption technique performed by the encryption module (104). system after claim 1 wherein a plurality of sensors (108) built into cryptographic chips convert unmasked measurement data into masked data to configure an encryption mechanism of the sensor layer. system after claim 2 wherein an analog-to-digital converter (110) is connected to the plurality of sensors (108) and converts an analog signal generated by the plurality of sensors (108) into a digital signal that becomes an input to the security chip. system after claim 2 , wherein the digital signal is encrypted based on a cryptographic technique and transmitted for storage in a cloud server (112) after passing through a data analysis center (114), based on the encrypted data provided by a cloud service provider are accessed by an authorized user from the cloud server (112). system after claim 1 , in which sixteen round keys, each 4 bits wide, are derived from eight subkeys obtained by splitting the 64-bit master key into sixteen parts. system after claim 1 , wherein the formed key undergoes an iterative set of steps involving the XOR and XNOR gates for eight consecutive rounds of operation, the output produced upon completion of eight consecutive rounds being the final ciphertext (CT) output. system after claim 1 , where a first bit obtained after an XOR or XNOR operation belongs to the first two bits in the next round, followed by the first bits from each of the four-bit groups, with the second bit from the four -bit group is in turn arranged in such a way that it forms a shuffling and scrambling. system after claim 1 , in which a 64-bit key of the encryption method is first divided into sixteen 4-bit sub-keys, which in turn are fed to the key generation module (102), which primarily scrambles the bits of the input and sixteen round keys of 4-bit length where the round keys are used in encrypting the data to provide the ciphertext output in all subsequent rounds of the encryption process.

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