DE202013009597U1 - Device for replacing a defective memory cell with a free cell for a memory circuit - Google Patents

Abstract

A memory interface device, the device comprising: an address input configured to receive address information from an address stream of a host controller; an address output configured to drive address information, the address output (s) being coupled to a plurality of memory devices; an address matching table having at least one corrected address corresponding to a free memory location; a control module configured to determine, during runtime operation, address information from an address stream from an address command bus coupled to a host controller, the control module configured to compare each address from the address stream and configured to: that it determines whether each address matches a stored address in the address match table to identify an invalid address and is configured to replace the invalid address with the corrected address of the free memory location; and a multiplexer coupled to the address input and coupled to the address output.

Description

BACKGROUND OF THE REVELATION

In storage systems, there are two general classes of storage. These classes include low latency storage. Low-latency memories effectively have an infinite life or infinite number of use cycles, and their quality does not degrade due to age or repeated access. Additionally, such classes also have relatively longer latency memories that do not have an infinite life or infinite number of use cycles, and whose quality may degrade by age or repeated accesses. A trend in the development of memory cells is that cells have become smaller due to advances in process technology and the need for ever-increasing storage capacity. This necessarily leads to a reduction in the sizes of the access transistor and the storage capacitor, which may lead to several limitations. For example, each access transistor exhibits a charge drain that causes stored charge to drain slowly from the storage capacitor. This charge drain feature - and thus the data retention time of each cell - varies from transistor to transistor; however, variability increases as the size of the access transistors is reduced. Another problem is that a smaller memory cell leads to a smaller storage capacitor and thus a reduced storage capacity. This can also adversely affect the data retention time characteristics of the cells.

BRIEF SUMMARY OF THE INVENTION

In one embodiment, the present invention provides a memory interface device. This device may include an address input or address inputs, an address output or addresses, an address match table, a control module and a multiplexer. In a specific embodiment, the memory interface device may be selected from a register device, a buffer device, an extended memory buffer, an on-board buffer, a memory controller, or the like, and combinations thereof.

The address input (s) may be configured to receive address information from an address stream of a host controller or processing element while the address output (s) are to a plurality of memory devices or other memory interface device or other memory interface devices and may be configured to drive address information. In a specific embodiment, the plurality of memory devices may include a plurality of DRAM devices, flash devices, or other similar memory devices. Furthermore, the multiplexer, which may be a MUX or DEMUX, may be coupled to the address input and the address output.

The address matching table may include an array of SRAM cells or the like. In a specific embodiment, this address matching table may include a plurality of invalid address information and a plurality of free memory locations. Each of the plurality of invalid address information may be associated with one of the plurality of free memory locations. Each of the plurality of invalid address information may include a rank ID, a bank ID, a chip ID, a row address, and a column address. Additional parameters may also be included, such as an offset ID. Each of the plurality of free memory locations may include a first column, a second column, and an nth column. Different numbers and configurations of free memory locations may be used depending on the design and related applications. The address matching table may be configured to receive invalid address information and may be configured to transmit the free memory location to replace the invalid address associated with the invalid address information.

The control module may be a command and address module or the like. This control module may be interleaved with the address matching table. In a specific embodiment, this control module may be configured to determine, during a runtime operation, address information from an address stream from an address command bus coupled to a host controller. This control module may be configured to compare each address from the address stream, and may be configured to determine whether each address matches a stored address in the address matching table to identify an invalid address. The control module may also be configured to replace the invalid address with the corrected address of the free memory location.

In a specific embodiment, the control module may include an input receiver module or a control and status register module exhibit. The control module may also include an input command module, an input address module, and an input chip select decoder module. Other components, such as a parity checker module, a signal inversion module, a signal delay module, a PLL (phase-locked loop), a command and address control module, an input buffer termination module, a clock stop shutdown module, a reset module, and the like, may also be incorporated into FIGS Memory interface device be included.

In a specific embodiment, the memory interface device may be coupled to a plurality of DRAM devices. Each of these DRAM devices may include a plurality of address inputs, a plurality of control inputs, a plurality of data inputs / outputs, a plurality of memory arrays, and a free group. Each of the plurality of memory arrays may include a plurality of memory cells, each of which may be coupled to a data input / output. The free group may include a plurality of free memory cells. Each of these free memory cells may be externally addressable using the address match table. Furthermore, the free group may consist of one or more free rows, one or more free columns or one or more free banks.

In one embodiment, the present invention may provide a memory IC device. This device 500 may comprise a plurality of regular address inputs, at least one free address configured for a selected mode or for a non-selected mode, a plurality of control inputs, a plurality of data inputs, a plurality of data outputs, a plurality of memory arrays and a free group of memory cells.

In a specific embodiment, each of the plurality of memory arrays may include a plurality of memory cells. Each of these memory cells may be coupled to a data input / output. In addition, the free group of memory cells may have a plurality of free memory cells. The free group of memory cells may include one or more free rows, one or more free columns, one or more free banks, or the like. Each of these memory cells may be externally addressable using an address match table and may be configured with the free address input. The free address input may be coupled to the address match table to access the spare memory cells. In a specific embodiment, the free address input may include one of three unused column address inputs A11, A13 and A17.

In a specific embodiment, the group of memory cells may access the plurality of spare memory cells using the free address input during the selected mode. During a read operation, data accessed from the free memory cell may be transferred to one of the plurality of data outputs. During a write operation, data from one of the plurality of data inputs may be transferred to the accessed free memory cell. During the unselected mode, the free address input may remain inactive while the plurality of regular address inputs remain active.

In addition, the free group of memory cells may have different free column and free address input configurations. For example, the free group may include the first to seventh free slots, and the free address input may include the first to third free address inputs. Or the free group may include the first to third free slots, and the free address input may include first and second free address inputs. Other variations, modifications and alternatives to these configurations may be used.

The memory IC device may also include a coded command and address bus having a shared command signal and an address signal, an internal data input reference voltage circuit, a command and address parity check circuit, a set of connectivity test supporting circuits, a reset input signal, a set of general-purpose status registers configured to be read, or the like, and combinations thereof.

Many advantages are achieved by the present invention over conventional embodiments and techniques. For example, embodiments of a memory IC device may have improved performance and lifetime. Embodiments of a memory interface device may facilitate the "repair" of invalid or defective memory cells or even memory cells undesirable due to aging, wear or the like. Free memory cells from a memory IC device may be redirected via a memory interface device upon detection of predetermined features of memory cells to be replaced. These implementations provide several means to maintain or improve memory performance, depending on different hardware and / or software requirements of specific applications can be customized.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to better understand the present invention, reference is made to the accompanying drawings. It should be understood that these drawings are not to be considered as limitations on the scope of the invention, and the embodiments described in this document and the best mode of the invention described in this document will be described in additional detail by use of the accompanying drawings, in which:

1 a simplified block diagram of an interface circuit according to an embodiment of the present invention illustrated;

2 illustrates a simplified address matching table according to an embodiment of the present invention;

3 illustrates a simplified diagram of free memory cells in a DRAM device according to one embodiment of the present invention;

4 a simplified block diagram of a memory interface device according to an embodiment of the present invention is illustrated;

5 a simplified block diagram of a memory IC device according to an embodiment of the present invention illustrated;

6 illustrates a simplified flowchart for applying the address matching table according to an embodiment of the present invention;

7 a simplified diagram of a memory IC device according to an embodiment of the present invention illustrated.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE DISCLOSURE

A trend in the development of memory devices is that memory cells continue to shrink due to advances in process technology, memory cells in low-latency memories such as DRAM devices become susceptible to errors due to aging effects or repetitive ones Accesses occur. Furthermore, the number of weak bits will continue to increase due to natural process variations. Accordingly, it is desirable that free memory cells can be used to correct for the presence of defective memory cells in low latency memory that may develop over the life of the device.

The present invention relates to memory devices for electronic applications. In particular, embodiments of the present invention contemplate memory interface devices and integrated circuit (IC) integrated circuit devices that may be implemented in various computing devices, servers, and the like. For example only, these devices may be configured for memory devices or implemented as memory devices, such as SDRAM, DDR SDRAM, RDRAM, SRAM, and Flash devices, and the like. But it can be seen that the invention has a wide range of applications.

A system is provided to replace faulty or weak memory cells in a memory system through the use of an improved memory interface circuit or an improved memory controller device and the use of redundant memory cells.

In one example, the present techniques provide support for the management of weak cells in DRAM devices. It is expected that as DRAM process technology progresses, the memory capacity of DRAM cells will continue to decrease and more and more DRAM memory cells will be unable to meet the specified data retention time requirements. Furthermore, as the number of weak DRAM memory cells increases, the DRAM devices as a whole will be unable to provide a sufficient number of redundant rows and redundant columns to effect repairs and give the appearance of perfect memory devices. According to the present example, the techniques provide DRAM memory cell coupled logic devices to help heal defective DRAM devices and mitigate the deleterious effects of the weak DRAM cells. Further details of the present system are to be found throughout the present specification and more particularly below.

Example: Using an Address Match Table in a Memory Interface Circuit, Controlling Free Memory Cells to Dynamically Replace Faulty Memory Cells in Memory Devices, as Illustrated in FIG.

1 FIG. 12 shows a usage example of an improved interface circuit that, in combination with free cells in DRAM devices, may function to replace faulty memory locations in the DRAM devices. In 1 is one with 110 labeled improved memory interface circuit shown with a 120 labeled command and address control unit and one with 130 contains a labeled address matching table. The improved memory interface circuit drives addresses and commands from the host controller to the DRAM devices, one of which in FIG 1 With 140 is labeled, continue. The DRAM devices include free DRAM cells whose addresses can select the improved memory interface circuit and cause the replacement of faulty or weak memory cell locations, as indicated by the table in FIG 2 illustrated.

For example, the DRAM device may include a plurality of memory cell arrays, a plurality of switching blocks, and a plurality of sense amplification units. Each of the memory cell arrays has at least one memory cell, and each memory cell may be connected to a word line and a bit line. Of course, other features are also present in the DRAM device.

2 FIG. 12 shows an example of the Address Match Table (AMT) shown in FIG 1 With 130 is labeled. 2 shows that the address matching table contains addresses of defective memory cells. In the case of 2 the addresses are listed in the form of DRAM address formats: rank ID, bank ID, row address and column address. The free reference ID can be "0" or "1", although there may be deviations here. The free ID may be used to indicate a data bus offset, or it may be used as an offset ID to select one or more subsets of DRAM devices to respond to the selection of a vacant location. For example, the offset ID may indicate, for example, that only the left side of the memory module is to be aligned with the invalid memory address, only the right side of the memory module is to be aligned with the invalid memory address, the total width (one rank) of the memory module is to coincide the invalid memory address or a single DRAM device is to be matched with the invalid memory address.

Other implementations may also use address fields for the chip ID (CID) and bank group ID. The addresses of faulty or weak memory cells contained in the address matching table may be determined by testing during manufacturing or special runtime testing. The entries in the address match table may also be dynamically updated at run time if it is determined that additional memory locations are weak or erroneous. The function of the address match table is to serve as a filter for addresses and commands issued by the improved memory interface circuit 110 to run. In the event that a particular memory access is matched with an entry in the address match table, the address match table replaces the address of the memory access with the address of a free memory location. In this way, the presence of the faulty or weak memory address is hidden from the host memory controller, and the improved memory interface circuitry allows the memory devices to present a contiguous memory address space without faulty or weak cell locations, as in FIG 3 shown.

The AMT may be a data structure that is part of the address path of a Registering Clock Driver (RCD) or a register or a DRAM device or a memory controller. The AMT contains the list of invalid or weak memory cells, which is a WCL (Weak Cell List) or a list of known WBAs (Weak Bit Addresses, weak bit addresses). These lists can be loaded from non-volatile memory into the AMT during system boot. During normal operation, the AMT checks the addresses of the instructions passing through the RCD for addresses to known invalid or weak memory cells. In the event of a match, the AMT may initiate a cell repair process that involves replacing data from the ESC (Externally-Addressable-Spare-Columns) in the DRAM device. DRAM devices that may use such techniques include DDR4 RDIMM, LRDIMM with DDR4 SDRAM or other similar devices.

The AMT may have multiple parallel AMTs for performing parallel address matching and self-cleaning or error detection and correction operations. For example, an AMT can be a Perform a self-cleaning operation while another AMT continues to operate and respond to DRAM commands. Processes for repairing weak cells and cell optimization processes can also be performed in parallel during normal operation. The number of AMTs in a particular implementation may vary, and may be determined by the maximum number of logical ranks that can be supported in a given storage system.

For example, each AMT may have a Row Address Match Table (RAMT) structure and a Column Address Match Table (CAMT) structure, which is a Fast Column Address Match Table (FCAMT) Address matching table). The RAMT may include a plurality of row addresses associated with specific rank, bank and column addresses. When a row access command is received, the row address can be sent to each RAMT. In the case of a row address match, the column address associated with the row address may be shifted to fill the associated entry in the CAMT structure. The row addresses may be configured to support 1, 2, 4 and 8 or more ranks of DRAM devices supporting independent and parallel address bus addresses.

3 shows an exemplary implementation of free memory cells in a DRAM device. The free memory cells are arranged in the form of added columns for each row. 3 Figure 12 shows one row of a DRAM memory cell organized in blocks, each with 32 DRAM cells per block. A block of 32 DRAM memory cells is in 3 With 310 labeled. 3 also shows that in the exemplary DRAM device, the column addresses A [9: 3] are used to select between different blocks of DRAM memory cells by means of a block of circuits collectively labeled as a large multiplexer. The big multiplexer is in 3 With 320 labeled. 3 also shows the implementation of two blocks of 330 labeled free DRAM cells. 3 further illustrates that the two blocks of free DRAM cells by using the column address A [3] by means of a 340 labeled multiplexer circuit can be selected separately. Finally, the column address A [13] can be used to use the in 3 With 350 labeled multiplexers to select between data from the baseline memory array or data from the free memory cells.

To demonstrate the principle and operation of the present techniques, examples have been prepared. These examples are for illustrative purposes only and are not intended to limit the scope of the claims set forth in this document in an undue manner. One of ordinary skill in the art would recognize many variations, alternatives and modifications.

AMT:

Address Match Table (Adressenabgleichstabelle)

CID:

Chip-ID

IFR:

In-Field Repair (Instandsetzung vor Ort)

LRDIMM:

Load-Reduced Dual Inline Memory Module (Lastreduziertes duales Inline-Speichermodul)

MB:

Memory Buffer (Speicherpuffer)

MemBIST:

Software-Tool zum Generieren integrierter Selbsttest-Blöcke für eine Speichermatrix als VHDL-Modell für das gesamte Speichersystem.

RCD:

Registering Clock Driver (Register-Takttreiber), wird auch einfach als das „Register” bezeichnet

RDIMM:

Registered Dual Inline Memory Module (Registriertes duales Inline-Speichermodul)

RID:

Rank-ID

SPD:

Serial Presence Detect

VRT:

Variable Retention Time (variable Haltezeit)

WBA:

Weak Bit Address (schwache Bitadresse)

WBAL:

Weak Bit Address List (Liste schwacher Bitadressen)

WCM:

Weak Cell Management (Verwaltung schwacher Zellen)

To facilitate reading, the following terms have been defined as examples.

AMT:

Address Match Table

CID:

Chip ID

IFR:

In-Field Repair (repair on site)

LRDIMM:

Load-reduced dual inline memory module (load reduced dual inline memory module)

MB:

Memory Buffer

MEMBIST:

Software tool for generating integrated self-test blocks for a memory matrix as a VHDL model for the entire memory system.

RCD:

Registering Clock Driver is also referred to simply as the "Register"

RDIMM:

Registered Dual Inline Memory Module (Registered Dual Inline Memory Module)

RID:

Rank ID

SPD:

Serial Presence Detect

VRT:

Variable retention time

WBA:

Weak Bit Address (weak bit address)

WBAL:

Weak Bit Address List

WCM:

Weak Cell Management

In one example, techniques include a system provided within a framework, wherein DRAM devices are characteristic features thereof, weak cells are recognized within the DRAM devices, their address locations are stored in non-volatile memory locations, and subsequent use of the weak address list occurs to cause dynamic repairs that are transparent to the host storage controller. Descriptions of test algorithms for detecting weak cells are provided in the MemBIST section, and the WBAL storage format section specifies their storage format in nonvolatile memory, and the sections describing specific repair concepts provide details of the Use of WBAL to cause management of weak cells.

In one example, the present description provides a high level architecture specification that is independent of specific DRAM types, DIMM specific types, and weak bit replacement concepts. It is envisaged that this specification will act as a master specification from which an implementation-specific architectural specification can be quickly derived.

In one example, the concept of externally addressable free columns in DRAM is designed for implementation on a DDR3 or DDR4 register DIMM (RDIMM) or an LRDIMM. The concept of externally addressable free columns in DRAM also uses a known Weak Bit Address List (WBAL) stored in one or more Address Match Tables (AMTs) to compare to addresses of DRAM instructions passing through the Address and Command paths of the RDIMM or LRDIMM. In the case of a match with a known weak bit address, the address match table replaces the column address of the column access command with a column address to a set of free columns in the DRAM devices. The free columns are used to provide reliable storage locations for data rather than columns of known defective or weak DRAM memory cells.

Illustrated by an example 4 a DDR4 register DIMM in which the DDR4 register has been modified to integrate one or more address match tables. The address match tables check addresses of DRAM instructions as the DRAM instructions pass through the DDR4 registers based on known weak bit address locations. In the case of an address match, the DDR4 register replaces the column address of the column access instruction with the address of a free column in DRAM devices.

To facilitate the implementation of the free column concept in DRAM, the architecture description of the address match table and the externally addressable free columns in DRAM can be found in the following sections: (1) address match table; (2) Externally addressable free columns in DRAM.

In one embodiment, the present invention provides a memory interface device. As in 4 shown, the device can 400 an address input or address inputs 411 , an address output or address outputs 412 , an address matching table 420 , a control module 430 and a multiplexer 410 exhibit. In a specific embodiment, the memory interface device 400 may be selected from a register device, a buffer device, an extended memory buffer, an on-board buffer or the like, and combinations thereof.

The address input or the address inputs 411 may be configured to receive address information from an address stream of a host controller while the address output or addresses are out 412 may be coupled to a plurality of storage devices and configured to drive address information. In a specific embodiment, the plurality of memory devices 401 a plurality of DRAM devices, flash devices or other similar memory devices. Furthermore, the multiplexer 410 be coupled with the address input and the address output.

The address matching table 430 may comprise an array of SRAM cells or the like. In a specific embodiment, this address matching table may be 430 a variety of invalid address information 440 and a variety of free memory locations 450 exhibit. Each of the plurality of invalid address information 440 Can with one of the variety of free storage locations 450 be connected. Each of the plurality of invalid address information may have a Rank ID 441 , a bank ID 442 , a chip ID 443 , a line address 444 and a column address 445 include. In addition, additional parameters may be included. Each of the plurality of free memory locations may have a plurality of memory groups 451 having a first column, a second column and an n-th column. Row and bank configurations may also be used, while different numbers and configurations of free memory locations may be used depending on the design and related applications. The address matching table may be configured to receive invalid address information and may be configured to transmit the free memory location to replace the invalid address associated with the invalid address information.

At the control module 420 it may be a command and address module or the like. This control module 420 can be intertwined with the address match table. In a specific embodiment, this control module 420 be configured that way during a runtime operation address information from an address stream from one with a host controller 402 coupled address command bus 403 certainly. This control module 420 may be configured to compare each address from the address stream, and may be configured to determine whether each address has a stored address in the address match table 430 matches to identify an invalid address. The control module 420 may also be configured to return the invalid address by the corrected address of the free memory locations 450 replaced.

In a specific embodiment, the control module 420 an input-receiver module 421 or a control and status register module 422 exhibit. The control module may also have an input command module 461 , an input address module 462 and an input chip select decoder module 463 exhibit. Other components, such as a parity checker module 470 , a signal reversal module 471 , a signal delay module 472 , a PLL (phase-locked loop, phase locked loop) 473 , a command and address control module 474 , an input buffer termination module 475 , a clock stop module 476 , a reset module 477 and the like may also be incorporated in the memory interface device 400 be included.

In a specific embodiment, the memory interface device may be coupled to a plurality of DRAM devices. Each of these DRAM devices may include a plurality of address inputs, a plurality of control inputs, a plurality of data inputs / outputs, a plurality of memory arrays, and a free group. Each of the plurality of memory arrays may include a plurality of memory cells, each of which may be coupled to a data input / output. The free group may include a plurality of free memory cells. Each of these free memory cells may be externally addressable using the address match table. Furthermore, the free group may have a free line, a free column, or a free bank.

5 Figure 12 illustrates a simplified block diagram of a memory IC device according to an embodiment of the present invention. As shown, this device can 500 a variety of regular address inputs 510 , at least one free address configured for a selected mode or for a non-selected mode 520 , a variety of control inputs 530 , a variety of data inputs 540 , a variety of data outputs 550 , a variety of memory arrangements 560 and a free group of memory cells 570 exhibit.

In a specific embodiment, each of the plurality of memory arrangements 560 a variety of memory cells 561 exhibit. Each of these memory cells can be connected to a data input / output 540 / 550 be coupled. In addition, the free group of memory cells 570 a variety of free memory cells 571 exhibit. The free group of memory cells 571 may have a free column, a free line, a free bank, or the like. Each of these free memory cells 571 can be done using an address match table 580 can be externally addressable and can with the free address input 520 be configured. The free address input 520 can with the address matching table 580 be coupled to the free memory cells 571 access. The address matching table 580 can be within a storage interface device 581 with a control module 582 be provided. This storage interface 581 can be similar to the one for 4 be described above. In a specific embodiment, the free address input 520 include one of three unused column address inputs A11, A13 and A17.

In a specific embodiment, the group of memory cells 570 during the selected mode using the free address input 520 on the multitude of free memory cells 571 access. During a read operation, data may be taken from the free memory cell 571 that was accessed, to one of the multitude of data outputs 550 be transmitted. During a write operation, data may be from one of the plurality of data inputs 540 to the free memory cell 571 to be transferred. During the non-selected mode, the free address input 520 remain inactive while the multitude of regular address inputs 510 remains active.

In addition, the free group of memory cells 570 various configurations of free columns and free address inputs. For example, the free group 570 the first to seventh free slots include, and the free address input may include the first to third free address input. Or the free group may include the first to third free slots, and the free address input may include first and second free address inputs. Other variations, modifications and alternatives to these configurations may be used.

The memory IC device 500 also has a coded command and address bus 591 with a shared command signal and an address signal, an internal data input reference voltage circuit 592 , a command and address parity check circuit 593 , a set of circuits designed to support connectivity testing 594 , a reset input signal 595 , a set of general-purpose status registers 596 which are configured to be read out, or the like, and combinations thereof. These modules and circuits can work with a host controller 590 be coupled. One of ordinary skill in the art will recognize further variations, modifications and alternatives.

Many advantages are achieved by the present invention over conventional embodiments and techniques. For example, embodiments of a memory IC device may have improved performance and lifetime. Embodiments of a memory interface device may facilitate the "repair" of invalid or defective memory cells or even memory cells undesirable due to aging, wear or the like. Free memory cells from a memory IC device may be redirected via a memory interface device upon detection of predetermined features of memory cells to be replaced. These implementations provide several means to maintain or improve memory performance, which can be customized according to different hardware and / or software requirements of specific applications.

• 1. Empfangen von Adressinformationen aus einem Adressenstrom eines Host-Computers an einem Adresseingang oder an Adresseingängen einer Speicherschnittstellenvorrichtung;
• 2. Verarbeiten des Adressenstroms aus einem mit dem Host-Controller gekoppelten Adressenbefehlsbus während eines Laufzeitbetriebs;
• 3. Aufeinander folgendes Vergleichen jeder Adresse aus dem Adressenstrom mit Informationen in einer Adressenabgleichstabelle, um zu bestimmen, ob eine Adresse mit einer gespeicherten Adresse in einer Adressenabgleichstabelle übereinstimmt;
• 4. Identifizieren einer in der Adressenabgleichstabelle vorgesehenen ungültigen Adresse; und
• 5. Ersetzen der ungültigen Adresse durch eine korrigierte Adresse einer freien Speicherposition;
• 6. Übertragen der korrigierten Adresse an einen mit dem Adressausgang gekoppelten Multiplexer;
• 7. Treiben von Adressinformationen von einem Adressausgang oder von Adressausgängen der Speicherschnittstellenvorrichtung zu einer Vielzahl von Speichervorrichtungen; und
• 8. Durchführen weiterer Schritte, wie gewünscht.

In one example, the present invention provides a system for operating a memory interface device, as outlined below.

• 1. receiving address information from an address stream of a host computer at an address input or at address inputs of a memory interface device;
• 2. processing the address stream from an address instruction bus coupled to the host controller during runtime operation;
• 3. Successively comparing each address from the address stream with information in an address match table to determine if an address matches a stored address in an address match table;
• 4. identifying an invalid address provided in the address matching table; and
• 5. Replace the invalid address with a corrected address of a free memory location;
• 6. transmitting the corrected address to a multiplexer coupled to the address output;
• 7. driving address information from an address output or address outputs of the memory interface device to a plurality of memory devices; and
• 8. Perform additional steps as desired.

As shown, the present system implements a sequence of steps that may be varied, modified, replaced, rearranged, expanded or contracted, or any combination thereof. This means that the system repeats each of the above steps. Such steps may be performed alone or in combination with others that are described or not described. The steps may be performed in the order shown or in other orders if desired. The steps may also be performed using a combination of hardware and software using other process steps. The steps may also be performed using hardware or other processes implemented using software and the like. Of course there can be many other changes, modifications and alternatives. Further details of the present system are to be found throughout the present specification and more particularly below.

6 FIG. 12 illustrates a simplified flowchart for performing an address matching operation to replace an invalid cell with a spare cell according to an embodiment of the present invention. As shown, the system implements a configuration 600 that in step 610 begins receiving address information from an address stream of a host computer at an address input or at address inputs of a memory interface device. This memory interface device may be coupled to a host computer. The memory interface device may be selected from a register device, a buffer device, an extended memory buffer, or an on-board buffer. These memory devices may include a variety of DRAM devices, flash devices or other similar devices and combinations thereof.

During a runtime operation, in step 620 the address stream is processed from an address command bus coupled to the host controller. Each address from the address stream may be in step 630 successively to determine if an address matches a stored address in an address match table. The address matching table may include a plurality of SRAM cells and may have a plurality of invalid ones Have address information and a plurality of free memory locations. Each of these invalid address locations may be associated with one of the free memory locations. Each of the invalid address information may include a rank ID, a bank ID, a chip ID, a row address, and a column address. Each of the free storage locations may include one or more storage groups having columns, rows or banks, and the like. In a specific embodiment, each of the free memory locations may include a first column, a second column, and an nth column.

An invalid address in the address match table can be found in step 640 be identified, and she can step in 650 be replaced by a corrected address of a free memory location. The corrected address can be found in step 660 be transmitted to a coupled to the address output multiplexer. The address matching table may be configured to receive invalid address information and transmit the free memory location to replace the invalid address associated with the invalid address information. Besides, the system can 600 in step 670 routing address information from an address output or address outputs of the memory interface device to a plurality of memory devices.

In a specific embodiment, the comparing, identifying and replacing can be done under the control of a control module. This control module may be interleaved with the address match table and further include an input receiver module, a control and status register module, an input command module, an input address module, and an input chip select decoder module and other similar modules. Further details regarding the components of these devices and methods have already been described with reference to 1 to 5 described. Furthermore, in step 680 If desired, further steps can be performed according to the various specifications and applications.

7 illustrates a simplified diagram of a memory IC device according to an embodiment of the present invention. As shown, the device can 700 an RCD module (registering clock driver, register clock driver) 710 exhibit. The RCD 710 is with a variety of memory arrangements 720 and a variety of data buffers 730 coupled. The data buffers 730 are over tax buses 731 with the RCD 710 coupled. The device 700 has an SPD module (Serial Presence Detect) 711 which may contain SPD data to provide a standardized technique for accessing information about the memory module.

The RCD 710 may include or be coupled to a host controller and an address matching table. As previously described, the memory interface device modules may have the address path of the RCD 710 to be provided. The memory module 740 , which may be a non-volatile memory such as an Electrically Erasable Programmable Read-Only Memory (EEPROM), stores the WCL to be loaded into the AMT. By means of the WCL, invalid or weak memory cells within the memory arrays may be used 720 through free memory cells 721 be replaced.

Various exemplary embodiments as described with reference to the accompanying drawings in which embodiments have been shown. However, the inventive idea can be embodied in many different forms and should not be construed to be limited to the embodiments set forth in this document. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like reference numerals designate like parts throughout the application.

It should be understood that although the terms "first", "second", etc., and "first", "second", etc., and "first", "second", etc., may be used in the present document In order to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the inventive idea. As used in the present document, the term "and / or" includes any and all combinations of one or more of the associated listed items.

It should be understood that when an element is stated to be "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. If, on the other hand, it is stated that one element is "directly connected" or "directly coupled" to another element, there can be no intervening elements. Other words used to describe the relationship between elements should be interpreted analogously (for example, "between" and "directly between," "adjacent" and "directly adjacent," etc.).

The terminology used in this document is for the purpose of describing particular embodiments and is not intended to limit the inventive idea. As used in this document, the singular forms "a" and "an" as well as "the", "the" and "the" are intended to include plurals, unless the context clearly indicates otherwise. It is further understood that the terms "having," "comprising," "comprising," "comprising," when used in the present specification, includes the existence of the recited features, integers, steps, operations, elements, and / or specify components, but do not rule out the presence or addition of one or more of them.

Unless defined otherwise, all terms (including technical and scientific terms) used in this document have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive idea belongs , It is further understood that terms, for example, those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the art of interest and that they are not in a single context idealized or overly formal sense, except as expressly defined in this document.

It should be understood that the above description is an example of the disclosure, and that modifications and changes may be made to the examples which are within the scope of the claimed disclosure. Although the embodiments have been described above with respect to a specific example using an interface IC, the address matching table and related circuits may reside in a host controller, memory controller, microprocessor, or other IC device. Therefore, the broadest interpretation should be accorded to the scope of the appended claims, so that all such modifications and similar arrangements, including a full range of equivalents, are included.

Claims (17)

Memory interface device, the device comprising: an address input configured to receive address information from an address stream of a host controller; an address output configured to drive address information, the address output (s) being coupled to a plurality of memory devices; an address matching table having at least one corrected address corresponding to a free memory location; a control module configured to determine, during runtime operation, address information from an address stream from an address command bus coupled to a host controller, the control module configured to compare each address from the address stream and configured to: that it determines whether each address matches a stored address in the address match table to identify an invalid address and is configured to replace the invalid address with the corrected address of the free memory location; and a multiplexer coupled to the address input and coupled to the address output. The device of claim 1, wherein the memory interface device is selected from a register device, a buffer device, an extended memory buffer or an on-board buffer. The device of claim 1, wherein the plurality of memory devices comprises a plurality of DRAM devices or a plurality of flash devices. The apparatus of claim 1, wherein the address matching table comprises a plurality of invalid address information and a plurality of free memory locations, each of the plurality of invalid address information associated with one of the plurality of idle memory locations. The device of claim 4, wherein each of the plurality of invalid address information includes a rank ID, a bank ID, a chip ID, a row address, and a column address. The apparatus of claim 4, wherein each of the plurality of free memory locations comprises a first column, a second column, and an n-th column. The device of claim 4, wherein the address matching table comprises an array of SRAM cells. The apparatus of claim 4, wherein the address matching table is configured to receive invalid address information and is configured to transmit the free memory location to replace the invalid address associated with the invalid address information. The device of claim 1, wherein the control module is a command and address control module; and wherein the control module is interleaved with the address matching table. The apparatus of claim 1, wherein the control module further comprises an input-receiver module or a control and status register module. The apparatus of claim 1, wherein the control module further comprises an input command module, an input address module, and an input chip select decoder module. The apparatus of claim 1, further comprising a parity check module, a signal inversion module, a signal delay module, a phase-locked loop (PLL), a command and address control module, an input buffer termination module, a clock stop module, or a reset module. The device of claim 1, wherein the memory interface device is coupled to a plurality of DRAM devices, each of the DRAM devices comprising: a plurality of address inputs; a plurality of control inputs; a plurality of data inputs / outputs; a plurality of memory arrays, each of the plurality of memory arrays having a plurality of memory cells, each of the plurality of memory cells coupled to a data input / output; and a free group having a plurality of free memory cells, wherein each of the plurality of memory cells is externally addressable using the address matching table. The device of claim 13, wherein the free group comprises a free line, a free column, or a free bank. Integrated circuit device, the device comprising: an address input configured to receive address information from an address stream; an address output configured to drive address information; an address matching table having at least one corrected address corresponding to a free memory location; and a control module configured to determine, during a runtime operation, address information from an address stream from an address bus, the control module configured to compare each address from the address stream, and configured to determine whether each address matches a stored address in the address match table to identify an invalid address and is configured to replace the invalid address with the corrected address of the free memory location. DRAM IC device, the device comprising: a plurality of regular address inputs; at least one free address configured for a selected mode or a non-selected mode; a plurality of control inputs; a plurality of data inputs; a variety of data outputs; a plurality of memory arrays, each of the plurality of memory arrays having a plurality of memory cells, each of the memory cells having a storage capacitor coupled to an access transistor, each of the plurality of memory cells coupled to a data input / output; and a free column of memory cells having a plurality of spare memory cells, each of the plurality of free columns of memory cells being externally addressable using an address match table and configured with the free address input, whereupon the free address input is coupled to the address match table to apply to the free column of memory cells to access. The apparatus of claim 16, wherein the free column of memory cells comprises a first free column, a second free column, a third free column, a fourth free column, a fifth free column, a sixth free column, and a seventh free column; wherein the at least one free address input comprises a first free address input, a second free address input and a third free address input; and wherein the apparatus further comprises: a coded command and address bus having a shared command signal and an address signal, an internal data input reference voltage circuit, a command and address parity check circuit, a set of connectivity test supporting circuits, a reset input signal, or a set of general purpose status registers configured to be read out.

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