DE19743266C1 - Address management method in binary search tree - Google Patents

Abstract

The method involves removing an address from a binary search tree. Two pointers, i.e. the lower pointer and the upper pointer, are stored with each valid entry in the search tree, which refer respectively to a valid entry of a deeper level (level 0, I, II..). The position of the entry to be removed is located and temporarily stored. The entry of a deeper level, which has the lowest value, is located under the pointer of the entry to be removed, which refers to the entry of the next deeper level (level I, II, III) with the higher value. This entry with the lowest value is set to the position of the entry to be removed, and takes over the pointers of the removed entry.

Description

The subject of the application relates to a method for adding or remove an address in a partially occupied Search tree.

From GWEHENBERGER, G .: "Digital Search Trees", in Applied In formatik 3/74, pages 115 to 121 are unbalanced binary Trees, called digital symmetrical trees there become known in principle.

Especially in the area of ATM (Asynchronous Transfer Mode) and Ethernet routing must also be used for a large address range (typ. M = 2ˆ33 addresses) determined quickly and efficiently be able to determine whether an address is valid. The number of valid Ger addresses is usually relative with N = 2ˆ14 = 16000 small. While storing the valid data with few Mbyte of memory can be handled is a Be handling of the entire address pool with several gigabytes Storage not economically possible. In the mediation technology is also subject to the requirement that was previously valid Delete addresses and insert new valid addresses.

A possible approach to address the problems outlined NEN is based on a restriction of address allocation. It who which are allocating ever larger address areas at once. This however, leads to poor exploitation of the available Storage area, further changes to the given address range afterwards only with difficulty, or no longer possible.

Another approach to deal with the problems outlined is based on the use of a CAM (Content Addressable Memory) as a hardware solution. However, this ASIC element is not a standard  dardelement and the use therefore with relatively high costs connected. Support the building blocks currently available usually only one address range for 1k to 8k connections.  

Another approach to counter the problems outlined is based on the construction and use of a search tree (binary tree) to iteratively determine the address. The search time depends on the height of the tree. The minimum number of search accesses is proportional to log ₂ N. By balancing the tree, the tree structure can be minimized.

Previous implementations of a search method are based on a search tree using the target set N. The achievable search time t = A.1,44.log ₂ N is minimal (A duration of a single access, 1.44 Fibonacci number as a limit for AVL trees, 3 accesses for a rotation double rotation step), but the balancing requires a maximum of approx. t _N = 3.A.1,44.log ₂ N = 69.A.

A minimal tree structure has a minimal search time to maintain the minimum tree structure at Lö Adding or inserting addresses is an extensive task processing of algorithms required that correspond with a the time required.

The subject of the application is based on the problem, a ver drive of the type concerned to indicate that an optimization of searches, removal and inserting valid addresses.

The problem is in the subject of registration by the Merk male of claim 1 or the features of claim 2 ge solves.

The object of registration allows the search structure to be sorted mes simultaneously with the delete / insert operation, where a not to be exceeded for switching applications is always observed. The registration counter who was not balanced and therefore minimal Search depth (M instead of N) shows a minimized processing function and thus offers a cost-effective implement  mentation for searching, deleting, inserting in simple hardware (ASIC or FPGA) where scaling with the ver available technology is given. By using RAM Structures and a user-definable comparator There are further options for linking with Sta tusbits, which are used for additional selection criteria can be.

The subject of registration is hereinafter referred to as execution example to the extent necessary for understanding hand described in more detail by figures. Show:

Fig. 1 shows the basic structure of a binary field of depth 4 with 2ˆ4 = 16 elements, so to speak, the entire range of values.

Fig. 2 shows an example of a number of 10 valid address entries {0,1,2,7,8,9,11,13,15,25}.

Fig. 3 shows the address entries from Fig. 2 in binary representation.

FIG. 4 shows the partially filled search tree resulting from FIG. 2.

Fig. 5 shows the minimum, balanced search tree.

Fig. 6 shows the replacement process in the partially filled search tree.

Fig. 7 shows a circuit arrangement for shortening of the search operation.

In the figures, the same designations denote the same elements ment.

Fig. 1 shows the basic structure of a binary field with levels I, II, III and IV.

Fig. 2 shows a partially occupied in Example 10 with valid address entries {0,1,2,7,8,9,11,13,15,25} search tree. By using the complete binary field, the position of each entry is precisely defined. The maximum search length is determined by the height of the tree with H = log ₂ M.

FIG. 3 shows the address entries from FIG. 2 in binary representation.

In principle, an entry has the following structure:

In an address space with M = 2ˆ33 addresses, performing the search using the binary search in the partially occupied binary field for typical applications with KM = log ₂ M = 33 accesses instead of KN = log ₂ N = 16. Nevertheless, a shortening of the search tree by z. B. C = 13 heights (ie 2ˆ13 = 8k direct pointer, 4 accesses for first pointer access) with t _Max = A / 2. (4 + log ₂ (MC)) = 22.A a cheaper worst case time behavior achievable.

FIG. 4 shows the partially filled search tree resulting from FIG. 2. The search tree is not minimal in height, but its maximum height is limited to H.

FIG. 5 shows the minimal balanced search tree as it would result for the example from FIG. 2. In this case, the balanced search tree has a height that is 1 less than that in FIG. 4. In order to obtain this search tree, many positions have to be re-sorted. U ≈ N.log ₂ N operations are necessary in the worst case.

If not all binary roots are occupied, the result is as a result always a shortening of the maximum tree.

In the first level (level 0) there may be a division of the search tree according to the MSB (Most Significant Bit) 0 or 1 be given, when looking for an address in the first level (level 0) a branch according to the he Most bit position of the searched address occurs. Then is for the decision in level 0 is only the (2ˆm-0) first bit place relevant. This is particularly true when using egg  nes hardware comparator (circuitry implemented Comparator), the width of which can be greatly reduced, is advantageous noticeably noticeable.

For the search for entry {25} (Entry {25}) the Ver immediately in the i-th recursion step at the bit set <2ˆm-i <. Due to missing entries in the binary list (missing link), the evaluation itself is done here ner not applicable bit position. By including the already processed positions with missing entries in ei This can be seen in a parallel comparison can be taken into account, whereby the pointer selection (P_lower, P_upper) is corrected if necessary. However, this has no influence on the worst case search speed, because in in this case (at least one level is not occupied) promise the entry was reached too early. The parallel A comparison across all processed bit positions can be done if "slow" from <i <to <i + 1 <, because with a Missmatch in V bit positions, hence V search positions over jumps and thus saved as many comparison operations were.

Fig. 6 shows the replacement process in the partially filled search tree. Should z. For example, if entry {7} is removed from an existing list, the next largest entry takes its position. In the present case, the entry {7} must be searched for, whose position is saved; Then the entry {7} - P_upper is searched for the smallest entry (furthest left), and Entry {15} - P_lower is now set to the position of Entry {8} (Aktion_1). Entry {8} receives the stored pointers on Entry {7} - P_lower and Entry {7} - P_upper (action_2), the pointer Entry {11} - P_lower also receives the value Entry {8} - P_upper (action_3).

The deletion process therefore requires 3 actions more than one ver comparable pure search access.  

A subsequent insertion process for Entry {7}, with a new En try {7}, update of Entry {9} .P_lower and En try {15} .P_lower also requires 3 actions.

The proposed algorithm does not only allow a search comparable to CAM access, it also offers the possibility sorting z. B. targeting the smallest or largest Access entry. An extended use e.g. B. for sortie Data cells based on sequence numbers (sequence number or timestamp, healing with random routing) is supported bar.

As already mentioned, in an address space with M = 2ˆ33 addresses, the search must be carried out using the binary search in the partially occupied binary field for typical applications with KM = log ₂ M = 33 accesses instead of KN = log ₂ N = 16.

One way to shorten the search process is to shorten the search depth. If the search tree is shortened by z. B. C = 13 heights (ie 2ˆ13 = 8k direct pointer, 4 accesses for first pointer access) with t _Max = A / 2. (4 + log ₂ (MC)) = 22.A, a cheaper worst-case behavior can be achieved.

Since the arrangement is sorted, z. B. the upper part the search tree directly in a RAM (Random Access Memory, Random access memory) area can be mapped. With In the case of 2 entries, the search must only begin at level n. For example, 16k memory entries are available redu the search depth is around 14. Alternatively, in the 16k DirectMappings also all possible entries of level n + 1 storable. The search depth is then reduced by 15; at egg If you search above level 15, the search starts at Ur root.  

Another way to accelerate the search is given by the fact that the search principle is expanded to more than 2 points. When using appropriately 2ˆi pointers, a tree height of H = log ₂ M / i results.

Fig. 7 shows a hardware implementation for a search pointers 4, wherein it is not absolutely necessary, the poin terwerte introduce to the comparator.

An entry-RAM is driven by a tristate bus of exactly that type Pointer RAM from a plurality of Pointer RAMs (Pointer 1 R.A.M. . .Pointer i RAM) addressed, the output of which is via a chip Select signal is activated. Lying P_upper and P_lower in the same pointer RAM, which means no selection nes tristate bus via chipselekt, an ex ternal multiplexer may be provided. The exit of the entry RAM is connected to the comparator.

Example: as with STM1, there are 64 cycles for the resolution of one Entries from 8k possible are available, so this can be done by Using a 1Mbit RAM 32k.32 can be achieved. In 16k 32k DirectMappings are available (2 cycles); Reduce Search depth by 15. With 3 accesses to evaluate the Entries (create address; read entry; read pointer) needed for the search in 17 level 16.3 = 51 bars. Connection assembly and disassembly is possible in empty cycles, maximum should be this requires 51 + 2 + 3 = 56 bars.

Claims (2)

1. Method for removing an address from a partially occupied search tree, in which two pointers (pointer lower, pointer upper) can be saved with each valid entry in the search tree, each of which points to a valid entry of a lower level (level 0, I, II...) Refer accordingly

• - The position of the entry to be removed is sought and cached
• - under the pointer of the entry to be removed, which refers to the entry of the next lower level (level I, II, III) with the higher value, the entry of a lower level is found which has the lowest value
• - this entry with the lowest value is set to the position of the entry to be removed
• - This entry with the lowest value takes over the pointers of the removed entry.

2. Method for adding an address in a partially occupied search tree, in which two pointers (pointer lower, pointer upper) can be saved with each valid entry in the search tree, each of which points to a valid entry of a lower level (level 0, I, II...) Refer accordingly

• - the position of the entry to be added is sought
• - For the entry located on the searched position in the direction of the position which is equal to the value of the address of the entry to be moved, the first free position is sought and stored there
• - The entry to be added is stored in its position, taking over the pointer from the entry previously stored there.