DE19706496A1 - Clock supply system for a microcomputer system - Google Patents

Abstract

The invention relates to a clock pulse supply system for a microcomputer system in which flexible power management drastically lowers the power consumption of the overall system during both normal and stand-by operation of the microcomputer. At the same time, through this quasi-decentralized clock pulse supply, flexible power management also ensures the greatest possible functionality. Furthermore, making available additional clock pulse rates also adjusts performance in line with the prevailing requirements. The invention further relates to a sleep mode by which the clock pulse supply system can be switched to a stand-by-like operating mode which is similar to the power-down mode but from which it can be woken without a hardware reset or interrupt. By means of a so-called intelligent power-down mode the module groups and/or individual modules are switched off or switched down only when an active data transfer or protocol run has been fully completed.

Description

The invention relates to a clock supply system for a Microcomputer system consisting of a system clock generator supply device and a variety of individual modules that over clock lines with the system clock generating device are connected.

The requirements for modern microcomputer systems have increased expanded in recent years. Stand in past years The focus is on performance and price play in today's system designs of microcomputer systems additional technical requirements increasingly play a role. There the areas of application of microcomputer systems are increasing Dimensions to be extended to battery-based systems is coming reducing the power consumption of these microcomputersy are becoming increasingly important. This sets you up a lot low stand-by power consumption as well as low Power consumption in the operating state ahead. Another tech African requirement arises from electromagnetic ver inertness, that is, the radiation of the system. By a reduction in current consumption would be more advantageous also the electromagnetic radiation from Microcompu reduce systems.

Typical areas of application for microcomputer systems, de the demands of low power consumption in the switched operating state and in stand-by mode as well as a low electromagnetic radiation is crucial Telecommunications are an example (Mobile phones), consumer electronics (stand-by Operation of TV and video equipment) and in the automotive sector (Microcomputer for airbag control, engine control). Advantage unfortunately results from a reduction in electricity consumption  need a lowering of the overall system basic costs.

Known methods and concepts for reducing electricity Consumption in microcomputer systems are, for example Microcomputer system components, C 165, 16-bit CMOS single Chip Microcomputer, User's Manual 08.94, from Siemens AG known. Chapter 15 of the above User Manual contains the IDLE-MODE and with the POWER-DOWN-MODE two methods for Current reduction of microcomputer systems specified.

In IDLE-MODE, the CPU memory is decoupled from the clock system pelt while the peripheral units continue to be on the clock system are connected. The IDLE-MODE can be reset or Interrupt command can be terminated.

Both the CPU memory and the are in the POWER DOWN MODE I / O units disconnected from the system clock and located stand-by mode. The POWER DOWN MODE can in contrast IDLE-MODE set can only be ended by a hardware reset the. Usually in today's microcomputer systems a combination of IDLE-MODE and POWER DOWN MODE used.

The different modules of a modern microcomputer need several different and sometimes delayed Clock frequencies. But since the microcomputer usually comes with only one external clock is fed, the additional required clocks on the chip of the microcomputer itself testifies.

The power consumption of the individual components of a Microcom computer is essentially divided into the following three components:

• a) Clock lines: The power supply depends on the clock lines need almost exclusively from the transhipment capacities. The transhipment capacities are dependent on the lei  tion length, so that the power consumption is proportional relates to the cable length.
• b) Clock driver: The arrangement and distribution of each Clock driver of the microcomputer on the chip affects also on electricity consumption.
• c) Synchronization modules: The individual measures must be given if necessary adapted to each other via synchronization modules will. These synchronization modules in turn require additional electricity.

Conventional clock systems are based on two different ones Principles.

The first principle is all for the different modules of a microcomputer required clocks in a central Clock generator generated and large area over the chip to the led individual modules. This has the disadvantage that the relatively long clock lines unfavorably on the Impact electricity consumption.

In the second principle there is only one bar and for each module is locally the clocks required by the module testifies. This in turn has the disadvantage that a large number of individual clock drivers distributed over the entire chip are arranged. In addition, the individual must generate locally th clocks can be adjusted via synchronization modules. This also results in increased power consumption or an increased power consumption of the microcomputer system.

The object of the present invention is therefore to create a new one Clock supply system for a microcomputer system the one gangs mentioned to create the total power consumption of the system and the electromagnetic radiation both in Operating case as well as in particular in the stand-by mode of the Microcomputers drastically reduced.  

According to the invention this object is achieved by a clock supply system of the type mentioned, which is characterized in that

• a) at least one module group is provided, the one Contains a large number of identical individual modules, wherein each module group has a group clock driver holds, the input side via system clock lines of the Sy master clock is supplied and the output side via clock lines are connected to the respective individual modules,
• b) at least one of the individual modules and / or at least one nes of the group clock drivers via shutdown devices (EN), which the clock of the respective individual mo module or group clock driver can be switched off.

This new clock supply system, also called quasi-decent tral clock supply system can be referred to divides the system clock into several clock subsystems. Quasi decentralized clock supply system optimizes the ratio between reducing power consumption through the shorter cycle lines and smaller clock drivers and the increase in Power consumption due to the larger number of clock drivers. In this way, the power consumption of the entire Sy stems drastically reduced.

This optimization is already in the normal operating mode the microcomputer system a significant reduction in Power consumption compared to known clock supply systems reached. This reduction is increased significantly, if whole module groups as well as the associated clock system can be switched off. This clock supplier The system therefore has the highest degree of flexibility on, which reduces the overall power consumption of the microcomputersy stems can be minimized.

In a further training is a flexible power management for Microcomputer systems specified that be at the beginning written methods and concepts to reduce the  Power consumption such as IDLE-MODE or POWER-DOWN-MODE builds up. The power consumption of these microcomputer systems can be controlled by soft goods are scaled and thus the respective operating state of the overall system can be optimally adapted. Software can NEN individual modules or module groups, for example in Stand-by mode cannot be used, specifically switched off will. Since these modules are still on the clock supply system are connected, their last status is saved and can be used when restarting this module continue working in the last saved state. Thereby there is no need for a complicated hardware or software Reset, for example in IDLE-MODE or POWER-DOWN-MODE is required.

In one embodiment, the system clock is a system clock generator provided, the clock divider and Clock multiplier. This way it is possible in addition to the "normal clock" also a clock with reduced Provide frequency.

In a further development of the invention, further cycle parts between the group clock driver and one or all downstream individual modules may be provided. This is it is also possible to add one or more individual modules Working frequency specifically adapted for this single module to provide. Group clock driver and optional additional Tete clock divider devices are advantageously flat if software controlled.

An advantageous division of the different module groups results if, for example, a module group the CPU module as well as internal memory modules. The associated one Clock drivers then supply the individual modules with the core clock. The CPU module group and the assigned individual modules are allowed must never be switched off.  

At least one further module group is expedient provided, which has the peripheral units. This includes typically module elements such as AD converters, counter- Timer module, PWM module, CAN module, interrupt controller, cap ture Compare module, etc. belong.

Furthermore, one or more further module groups with In Interface units can be provided. Such interface units can for example be a synchronous and asynchronous serial Interfaces, parallel interfaces, watchdog timer modules, In be terrupt modules.

The interface clock driver supplies all individual modules that are used for Communication with the environment of the microcomputer system gave way are active. With the interface modules, the Microcomputersy stem can be "woken up" by its surroundings as long as the In Interface clock driver is active. All other individual modules can be switched off. With this function a stand-by Operation can be programmed with minimal power consumption.

In a further embodiment of the present invention the input clock is generated externally by a quartz. It would be also conceivable, the input clock through an integrated quartz or by alternative methods such as an oscillator rieren. The external quartz is advantageously a reason vibrating quartz.

Modern microcomputer systems have a very wide range frequency range from 1 MHz to 50 MHz for the clock supply. Using a suitable integrated clock divider or clock multiplier The internal CPU clock can be set to the desired frequency be programmed. When connecting the input clock the power consumption is shared with an external quartz Wiring in a static and a dynamic component on. Both components strongly depend on the specific Pa of the quartz used.  

The static component depends heavily on the internal tree overcircuit of the microcomputer system. The dynamic Component, however, which is quadratic on the frequency depends on the use of a fundamental wave quartz low frequency and a downstream PLL as a clock multiplier can be minimized.

The problem with choosing a quartz is that for very high frequencies <16 MHz very large crystals ver must be applied. However, large crystals are expensive and mechanically unstable. Secondly, they are problematic when starting up and exhibit an increased electromagnetic Radiation on.

For small frequencies <3.68 MHz usually small Quartz used, which are also very expensive. This small NEN crystals show increased scattering, from which he increased frequency inaccuracy results. They're also small Long-term unstable quartz.

For this reason, it is advantageous for the generation of the to use externally coupled clock quartzes, which in Nor oscillation range between 3.68 MHz to 16 MHz. By a Limitation of the frequency range for the clock supply to 3.5 MHz by means of an external fundamental wave quartz The internal quartz driver can be optimized at 16 MHz and the stati electrical power component can be minimized.

This restriction does not affect the wiring of the Microcomputer systems with an external oscillator. At the This circuit can continue the full frequency range (1 MHz to 50 MHz) can be used for the clock supply. Through this optimization, the electricity consumption of the entire Oscillator circuit additionally reduced by a factor of 5 the.  

An important property that is used for clock supply of a low-frequency fundamental oscillation crystal its better mechanical stability against high frequencies ten crystals. This property is particularly evident in automotive technology as advantageous.

The invention is based on the in the figures of the Exemplary embodiments illustrated in the drawing. It shows:

FIG. 1 shows the general embodiment of the clock supply system of the invention for a microcomputer system with power management,

FIG. 2 shows a concrete embodiment of the inventive SEN clock supply system for a Microcomputersy stem with power management,

Fig. 3 shows an advantageous embodiment of the device for system clock generation.

In Fig. 1 of the drawing is a summary of the concept of the clock supply system according to the invention for a computer system Microcom shown. In addition to the known methods for saving electricity, such as POWER-DOWN-MODE or IDLE-MODE, this concept includes additional methods for saving electricity. These additional methods for saving electricity are based on the well-known power saving modes and complement them sensibly. The concept is referred to as flexible power management in the following.

A clock signal of the frequency f _{ET is} generated by an external crystal XTAL. This signal is fed to a microcomputer and coupled into an internal oscillator. The internal oscillator generates a signal of the frequency f _OSC from the input clock signal. This oscillator clock signal is supplied from the output side to a device for generating the system clock. The system clock generation generates a signal of frequency f _{ST on the} output side. This signal is referred to as the system clock signal in the fol lowing.

The device for system clock generation in the present example comprises a clock divider and a clock multiplier. A possible implementation of the device for generating the system clock is subsequently described in more detail in FIG. 3.

The oscillator output signal is sent to another output a signal real-time clock device RTC supplied. Typi This RTC device is usually an RTC driver switches. The oscillator input signal as well as the input system clock generation signal can be via a device that work according to the POWER DOWN MODE described at the beginning be interrupted.

The system clock f _ST is a variety of module groups M _A , M _B ,. . . M _X supplied. Each of these module groups contains at least one individual module A _ν , B _ν ,. . . X _ν and a group clock driver A, B,. . . X. In the present example, module group M _{A has} 2 individual modules, module group M _B x individual module and module group M _X × 3 individual modules.

The system clock is fed to the clock input CLK of each group clock driver. The group clock drivers each generate a clock signal f _A , f _B ,. . . f _X , which is supplied on the output side to the clock input CLK of the respective downstream individual modules via group clock lines. The clock frequency f _A , f _B,. . . f _X in the respective group clock lines is specific to the requirements of the respective individual modules A _ν , B _ν . . . X _ν adjusted.

Optionally, further clock dividers can be provided in the group clock lines, which, as indicated for the individual module X ₁ , are directly connected to one or more individual modules. This would make it possible to define a specific cycle for each individual module.

The group clock drivers and the individual modules contain Ab switching devices EN. The shutdown is fiction, ge programmatically via software. Optionally, the soft ware program also the setting of the divisor factor of the Make clock divider.

Through the software-controlled clock divider setting and the Possibility of software-controlled shutdown of the module groups and individual modules it is possible to change the clock frequency both for entire module groups and for individual modules targeting the requirements of the entire clock supply system stems to adapt. This is the greatest possible flexibility the clock supply of the entire system of the microcomputer ben.

In the present example, each group clock driver A, B,. . . X and each individual module A _ν , B _ν,. . . X _ν via a software-controlled switch-off device EN and can therefore also be switched off if necessary. In reality, it is of course not necessary or often not desirable to be able to switch off individual module groups or individual modules.

In FIG. 2, a concrete application example of the clock supply to the invention OF INVENTION system is shown with a flexible power management. The clock supply system from FIG. 2 is based on the concept of the clock supply system from FIG. 1.

Fig. 2 has three module groups: a CPU module group, an interface module group and a peripheral module group.

The CPU module group has a CPU clock driver. On the output side, the CPU clock driver generates a signal with the clock frequency f _CPU . This clock signal is coupled into the clock inputs CLK of the two individual modules connected downstream. In the present example, the individual modules are a CPU memory module and an internal memory module.

Only the CPU clock driver is available in the CPU module group via a switch-off device EN. The shutdown device EN the CPU clock driver can be described using the input IDLE-MODE can be switched off. The downstream CPU memory memory module and the internal memory module have hinge typically does not have a shutdown device. This at the modules must not be separated, but only together be switched.

The interface module group comprises an interface clock driver which provides a signal with the clock frequency f _{IF on} the output side. This clock signal is fed to all downstream individual modules. The individual interface modules in the present example are an asynchronous and synchronous serial interface, a watchdog timer module and a module for fast external interrupts.

The two serial interface modules each have a software-controlled shutdown device EN. The module for fast external interrupts and the watchdog timer module typically do not have shutdown devices. These two security and monitoring modules may not under no circumstances can be switched off. For this The upstream interface clock driver shows the reason if there is no switch-off device.

The peripheral module group has a peripheral clock driver which generates a signal of the clock frequency f _P on the output side. This clock signal is fed to the downstream individual modules. The peripheral individual modules in the present example are an analog-digital converter, a counter-timer module, a fast PWM module, a capture compare module, an interrupt controller and a full CAN module. With the exception of the interrupt controller, these individual modules and the peripheral clock driver each have software-controlled shutdown devices EN.

The concept of a clock supply system that also Me contains mechanisms for reducing the power consumption is called Referred to as power management. The power management from Micro computer systems differentiates between so-called "transparent", "quasi-transparent" and "active" power Management components.

The transparent components are not affected from the outside bar and do not affect performance or that Behavior of the microcomputer system. The main trans Parent component in microcomputer systems is the Taktsy stem.

The active components, on the other hand, provide the user with Mecha nisms for optimal adaptation of the power consumption to each operating state available. By means of this mecha The clock of the Micro can be used for software, for example computer systems from the preset work cycle a reduced, programmable clock can be switched. Because the current draw of most modules of a microcomputer systemens depends linearly on the frequency the frequency reduction a significant reduction in Ge total electricity consumption can be achieved.

Another active component is the targeted shutdown of individual modules as well as module groups and thus all Modules that are supplied with the clock of the module groups.

A quasi-transparent component for power consumption represents the power supply. For most Microcom The supply voltage is approximated to the power modules square in the current consumption. For example  a reduction in the supply voltage from 5 V to 3 V one Reduction of the current consumption by a factor greater than 2.

However, to reduce the total power consumption do not reduce the supply voltage arbitrarily. The admissions liquid supply voltage depends on the Manufacturing technology of the microcomputer systems and of Fact to what extent the output clock drivers with a re reduced supply voltage of, for example, 3 V for the required applications can be operated.

The present concept of flexible power management for Reduction in power consumption links the well-known trans parent and active components and defines a so-called quasi-decentralized clock supply system.

The quasi-decentralized clock supply system divides the Sy master clock in three clock subsystems: the CPU clock, the peripheral rietakt and the interface clock. The CPU clock supplies the CPU Memory and the internal memory during the periphery Rietakt all I / O modules and the interface clock all In interface modules supplied.

The peripheral clock and interface clock are only one single clock line led to re-transhipment capacities reduce. To switch off entire module groups and the Enabling subtle clock lines are essential for the periphery rie and interface clock system two local clock drivers to Er Generation of the locally required clocks provided.

The quasi-decentralized clock supply system optimizes the Ver Relationship between reducing electricity consumption due to the brevity ren clock lines and smaller clock drivers, and the rise of electricity consumption due to the larger number of clock driver. Is this optimization already in normal loading drive mode of the microcomputer system a considerable reduction tion of power consumption compared to known clock supply  systems achieved, this reduction is still considerable supports when entire peripheral groups as well as the associated be switched off.

This clock supply system shows the highest degree Flexibility on what the total power consumption of the Micro computer systems can be minimized.

The new flexible power management for microcomputer systems builds on conventional energy saving methods. The Stromver need of these microcomputer systems can be per Software are scaled and so the respective company state of the overall system can be optimally adapted. Via software individual modules that are in stand-by Operation not used, be switched off specifically.

Since these modules are still on the clock supply system are coupled, their last state is saved and can be restarted from the last saved Condition continue to work. This eliminates the need for a com complicated hardware or software reset, for example in IDLE-MODE or POWER-DOWN-MODE as described at the beginning is required.

The targeted shutdown of individual modules as well as whole ones Module groups is one of the main characteristics of the quasi decentralized clock supply system. Are in special Be drive states of the overall system Do not use individual modules det, so these can be individually or as a whole group be switched. In this way, the total current significantly reduce system consumption.

The clock supply of a single module to a frequency reduced from 0 Hz - this corresponds to switching off the Clock supply - this module lingers in his eyes viewable condition. In this state, this module no electricity consumed. After creating a working frequency  greater than 0 Hz, the module works exactly at the stopped point continue.

Switching off a single module can be done in two ways fen. Either the supplied clock is outside the module switched off by means of the higher-level clock driver. This Switching off corresponds to switching off the entire module group. Another option is to switch off the in a single module integrated local clock generator. There the individual module remains in its last state before Shutdown, the control register of the individual module, however remain writable or readable.

The individual modules can be switched on and off during loading be carried out by software and is just like that Clock switching by a special security mechanism protected. This is an individual caused by disturbance exclude module shutdown.

Fig. 3 shows an advantageous embodiment of a system clock generating device. This device comprises a first area with a reduced microcomputer clock and a second area with a "normal" microcomputer clock. On the input side, the system clock generating device is coupled with a clock signal with the frequency f _OSC .

The input clock signal is firstly coupled into a first area with a reduced microcomputer clock in a clock divider. In the present example, the clock divider is a slow-down divider (SDD). A clock signal with the frequency f _SDD is available on the output side of the clock divider. In the present example, divisor factors from 1 to 32 can be set for the division factor of the slow-down devider. This allows a very wide scalable cycle range to be set. The setting of the divider factors of the slow down devider are typically software controlled.

In addition, the oscillator signal is coupled into a second area of a clock multiplier, which in the present example is formed by a phase locked loop (PLL). A signal with the frequency f _PLL is output on the output side of the clock multiplier. Depending on the divider factor of the PLL, the clock frequency of the output signal is greater than the frequency of the oscillator signal f _OSC . In the present example, factors between 1.5 and 5 are chosen. In addition, it is also possible not to change or halve the clock frequency of the oscillator input signal.

The unchanged oscillator signal f _OSC , the signal with half the oscillator clock frequency f _OSC / 2 and the output signal of the clock multiplier f _PLL are then fed to a first selection device which makes a clock selection. This clock selection is made by a reset configuration.

The clock output signal of the first selection device is fed together with the frequency clock signal f _{SDD to} a second selection device. The second selection device makes a second selection under software control, so that the system clock signal at frequency f _{ST is} coupled out on the output side of the system clock generating device.

Reference list

A,

B,. . . X group clock drivers
A _ν

, B _ν

. . . X _ν

Single modules
M _A

, M _B

,. . . M _X

Module groups
PLL phase-locked loop
RTC real-time clock
SDD slow down devider
CLK clock input
EN enable device, shutdown device
f _A

, f _B

,. . . f _X

Output frequencies of the signals of the various group clock drivers
f _CPU

Core clock frequency
f _ON

externally generated input frequency
f _IP

Clock frequency of the interface module group
f _OSC

Oscillator frequency
f _P

Clock frequency of the peripheral module group
f _PLL

Output clock frequency of the PLL
f _SDD

Output clock frequency of the SDD
f _ST

System clock frequency

Claims (14)

1. clock supply system for a microcomputer system best consisting of a system clock generating device and a plurality of individual modules which are connected via clock lines to the system clock generating device, characterized in that

• a) at least one module group is provided which contains a multiplicity of identical individual modules, each module group each containing a group clock driver, to which the system clock is supplied on the input side via system clock lines and which is connected to the respective individual modules via clock lines on the output side,
• b) at least one of the individual modules and / or at least one of the group clock drivers has switch-off devices (EN) via which the clock of the respective individual module or group clock driver can be switched off.

2. Clock supply system for a microcomputer system after Claim 1 characterized in that the shutdown devices (EN) are software controlled. 3. Clock supply system for a microcomputer system after one of claims 1 to 2, marked by IDLE-MODE power saving devices and / or POWER-DOWN-MODE- Energy saving devices. 4. Clock supply system for a microcomputer system after one of claims 1 to 3, characterized in that the system clock generating means clock dividing means and / or clock multipliers. 5. Clock supply system for a microcomputer system after one of claims 1-4,  characterized in that in the clock line between at least one of the group clock driver and at least one of the downstream individual modules le switched at least one further clock divider device is. 6. Clock supply system for a microcomputer system after one of claims 4 or 5, characterized in that the clock dividers and clock multipliers are software controlled. 7. clock supply system for a microcomputer system according to one of claims 1 to 6, characterized in that a module group is the CPU module group that contains a CPU memory module and internal memory modules, the group clock driver assigned to the CPU module group the core clock (f _CPU ). 8. Clock supply system for a microcomputer system after Claim 7 characterized in that the CPU module group does not contain any shutdown devices (EN). 9. clock supply system for a microcomputer system according to one of claims 1 to 8, characterized in that at least one peripheral module group is provided, the associated group clock driver generating the peripheral clock (f _P ). 10. Clock supply system for a microcomputer system after Claim 9 characterized in that  the peripheral module group at least one of the elements AD converter, Counter timer module, PWM module, CAN module, Inter ruptcontroller, capture compare module contains. 11. clock supply system for a microcomputer system according to one of claims 1 to 10, characterized in that at least one interface module group is provided, the associated group clock _driver generating the interface clock (f _IF ). 12. Clock supply system for a microcomputer system after Claim 11 characterized in that the interface module group at least one of the elements Watchdog timer module, synchronous serial interface, asyn chronic serial interface, interrupt module, parallel In interface contains. 13. clock supply system for a microcomputer system according to one of claims 1 to 12, characterized in that the input clock (f _ON ) is generated by an oscillator and / or an external crystal. 14. Clock supply system for a microcomputer system after Claim 13, characterized in that the external quartz is a fundamental vibration quartz.