DE19702270C2 - Method for transmitting information in a system, in particular in a security system for motor vehicles - Google Patents

Description

The invention relates to a method for transmitting information in egg system, especially in a safety system for motor vehicles.

One method of transferring information in a system is can already be seen from US 5,222,107, in which a synchronization individual modules according to a clock transmitted on a network taking into account the delay time of the signal. In security systems in motor vehicles, in which a variety of in seat protection devices, such as airbags, belt tensioners and the like, controlled and switched off by a central control device solves, it is necessary that the central control unit one of the An number of protective devices on the corresponding number of output stages points.

With the increasing need for more safety in the motor vehicle who in addition to the driver airbag, passenger airbag, belt tensioners and roll bars other protective devices, such as side airbags and the like chen, desired. There is also a desire for airbag systems that in the event of deployment, adjust the airbag to the severity of the accident. Due to the additional protective devices and expanded options the best Protective devices increase the number of power amplifiers and the elec tronic circuit of the control device is getting bigger, so that derar circuits in a standard housing of a central control unit can no longer be accommodated.

It is therefore envisaged future security systems for motor vehicles to implement with decentralized control systems. Here the final stage fen directly at the location of the protective device as a peripheral module. The central unit of the control system captures and processes egg Accelerators supplied to one or more accelerometers signals in order to take the appropriate measures in the event of a dangerous accident  Trigger signals for the individual end modules designed as peripheral modules fen of the security system, so that the individual protective device operations are operated.

The individual peripheral modules are provided via a bus to connect the central unit in order to ver complex wiring avoid.

While it is known for the control of stepper motors (Motorola Semiconductor Application Note AN 475, 1993), a central processing unit with a to connect individual peripheral engine control modules via a bus which has only one single-wire line and is linear or ring-shaped, In the future, several modules should be in one for security systems Bus line or bus circuit can be summarized in which they are in series are arranged to be transferred from the central unit to the modules passed on or passed through from module to module be shot. With such a bus concept that in the not before published German patent application 196 19 117.3 is described, the reliability of the security system can be increased and the same reduce the driver power of the central unit at an early stage.

The invention has for its object a method for transmission of information in a system, especially in a security system to provide with the bus concept described, with which a reliable communication between a central unit and peripheral modules with freely selectable transmission speeds.

The object is achieved by the method according to claim 1.

According to the invention, the exchange of information between the central unit and the individual peripheral modules from the central unit a clock information and data information on each of the selected module and when receiving the response information will be a response delay specific to the selected module considered. In this way, problems with data transmission can be avoided Avoid between central unit and peripheral modules, since the central unit while waiting for the response information from the respective address  the relevant signal propagation times of the information does.

To change the signal propagation time caused by aging and environmental influences gene to be able to take into account, it is provided according to the invention that the response delay for each module during an initialization phase se, especially when the system is started up. There at conveniently a relatively small transmission speed used.

Since the response delay of a module only from its installation location in the Sy stem depends and on the transmission speed, i.e. on the Sen defrequency is independent, information transmission problems can Avoid when determining the response delay, so that this with the required reliability can be detected.

Appropriately, to determine the response delay for each of the module the individual modules one after the other from the central unit dials, then the clock and data information from the center sent to the selected module and the start of reception for the response information returned by the selected module is detected so that the response delay from the time interval received from the end of transmission and the beginning of reception.

Since the individual modules addressed after receiving the clock and Data information the required response information only after expiration send a predetermined transmission delay to the central unit, it is advantageous if the preparatory to the determination of the response delay agreed transmission delay of the peripheral module is taken into account.

It is particularly advantageous if the Ant Word delays remain saved even after the operating time has ended and if at the beginning of the next operating time, i.e. after switching on of the system, the response delays are determined anew and saved secured response delays are compared to the plausibility of the ensure determined response delays.  

By comparing the newly determined response delays with the corresponding response delays from a previous Be drive period can not only ensure that the new values are correct were found, but errors can also be found in the individual months and identify the bus transmission lines early.

The invention is described in the following, for example with reference to the drawing ago explained. In this shows:

Fig. 1 is a schematic block diagram of a system,

Fig. 2 is a simplified schematic block diagram of a peripheral module for the system of Fig. 1 and

Fig. 3 is a timing diagram for explaining the transmitted information tion.

In the different figures of the drawing are corresponding to each other Circuit elements with the same reference numerals.

Fig. 1 shows a decentralized system with a central unit 10 and a plurality of peripheral modules 11 , which are connected to each other and to the central unit via line sections 12 .

Each of the modules 11 has - as FIG. 2 shows - a transmit / receive circuit 13 , the input / output connections 14 of which form the input / output connections to the module 11 . The transmit / receive circuit 13 is connected in a manner not shown with an information processing circuit 15 which strikes a driver circuit 17 via a control line 16 . An output of the driver circuit 17 forms a control output 18 of the module 11 , via which a protective device can be actuated, for example in the case of a safety system for motor vehicles. In particular, the so-called squib of a gas generator for an airbag can be connected to the control output 18 .

In order to prevent faults or damage to the module 11 , protective circuits 19 are connected to the input / output connections 14 and are shown, for example, as a single capacitor. The protective circuits 19 form an RC circuit with an output resistor or an output impedance from the respective previous transmit / receive circuit 13 .

A received over one of the lead portions 12 on the right or left a transfer / output terminal 14 signal over the other, to continue forming thus the left and right input / output terminal 14 to the next Mo dul 11, the transmission / reception Circuit 13 a first and a second transmission driver 20 , 21 . In this case, an input of the first transmission driver 20 is connected to the input / output terminal 14 on the right in FIG. 2, while its output is connected to the left input / output terminal 14 . Conversely, the second transmission driver 21 is connected on the input side to the left and on the output side to the right input / output connection 14 of the transmission / reception circuit 13 or the module 11 .

To the central unit 10 bus strands 22 are thus connected, which are constructed from the individual line sections 12 and the sections between two cable sections 12 arranged transmit / receive circuits 13 of the modules 11 . Instead of the illustrated linear bus lines 22 , one or more ring-shaped bus lines can also be used in the system.

In order to send any of the modules 11 information, the central unit 10 transmits an information signal via the line section 12 to the first module 11 of the corresponding bus line 22 in which the selected module 11 is located. In the first module 11, the signal present at the left input / off transfer port 14 information signal 15 is fed and on the other hand I / O port 14 is further sent from the entspre sponding transmit driver 21 via the right input to the next module 11, in which the information signal on the one hand onsverarbeitungsschaltung the Informati processed in the same way.

The information signal sent out by the central processing unit 10 contains clock information, for example a synchronizing word (Synch-Info) S, and data information, for example a data word D. As shown in FIG. 3, for example, the synchronizing word S comprises eight bits, which alternate the Accept value "1" and "0". The synchronous word S thus has the structure 1-0-1-0- 1-0-1-0, and thus represents a pulse train from which in the individual modules 11 the current transmit clock, that is, the one selected by the central unit 10 Transmission or transmission frequency for the following data word D can be derived. The data word D shown for example in Fig. 3 includes z. B. also eight bits, of which the first four form a control information for the addressed module 11 , while the last four represent the module address. The length of the synchronous word S and the data word D must be firmly agreed for a system, but can vary from system to system. For example, a synchronous word can also be realized with four or six bits. The data word D can also have more or less than eight bits, the distribution of control and address information between the individual bits also being different. In particular, the number of bits required for the address depends on the number of modules 11 present in the system.

During a self-test to check the functionality of the system, the central unit 10 sends a synchronous word S and a data word D for communication with a selected module 11 . The selected module 11 derives from the synchronizing word S a takeover clock signal with the transmission frequency used by the central unit 10 and can thus recognize the following data word D in a trouble-free operation. The signal runtime from the central unit 10 to the selected module 11 does not matter here, since both the start of reception in module 11 and the respective takeover clock are controlled by the respective syn chronword S.

After a fixed transmission delay ΔS, the selected module 11 sends back a data word A in response to the central unit 10 , which is only received by the central unit 10 without significant additional delays if the module 11 returning the first module 11 in the corresponding bus line 22 is. However, if the data word A serving as an answer is sent back via further modules 11 , an additional delay delay ΔL occurs, which is shown in FIG. 3 in the lower two representations. The central unit 10 thus receives the data word A sent back from the respectively selected module 11 with a response delay ΔA which is composed of the transmission delay ΔS and the delay time ΔL. The response delay ΔA is made up of a constant system-related delay time and a variable construction-related delay time.

The transit time delay .DELTA.L takes into account the signal transit times from the central unit 10 to the module 11 and back, which are mainly caused by the RC circuits from the C protection circuit 19 and the preceding output impedance.

The size or duration of the transit time delay ΔL for a module 11 depends essentially on how many other modules are between the module 11 and the central unit 10 in the bus line 22 . For the second module 11 in one of the bus lines 22 , for example, there is a relatively small delay ΔL, as shown in the middle in FIG. 3, while for the fifth or sixth module 11 , as shown in FIG. 3 below, one significantly longer transit time delay ΔL must be taken into account.

The central unit 10 advantageously determines the response delay ΔA composed of the transmission delay ΔS and the transit time delay ΔL for each module 11 during an initialization phase each time the system is started up. As a result, tolerance-related un different signal delays in the individual modules 11 can be taken into account.

In order to determine the response delay ΔA for each module 11 , the central unit 10 sends a synchronous word and a corresponding data word D to the respectively selected module and determines the time interval between the end of transmission and the start of reception of the data word A sent back as a response by the module 11 Response delay ΔA is stored and taken into account in each subsequent communication with the corresponding module 11 .

Since the transit time delay ΔL is essentially independent of the over speed, that is the transmission frequency, the Er averaging the response delay ΔA with a relatively low transmission frequency.  

It is particularly advantageous if, after the end of an operating period of the system, the response delays ΔA determined for this operating period remain stored for the individual modules 11 in the system, so that when the system is restarted, that is to say at the beginning of the following operating period, the response delays then determined ΔA of the modules 11 with which from the previous operating period 11 can be compared. Hereby, age-related changes in the individual modules can be determined, so that possible errors and defects of the system resulting therefrom can be recognized at an early stage.

With the method according to the invention, communication problems between the central unit 10 and the individual modules can be avoided even at higher transmission frequencies of, for example, 1 MHz and many modules 11 arranged one behind the other in a bus line 22 , since the signal delay times, i.e. the delay time ΔL of the data, are taken into account , which are sequentially forwarded from module 11 to module 11 .

The runtime delays DL, which become greater for each module 11 , the more modules 11 are between it and the central unit 10 in the bus line 22 , have no effect on the transmission from the central unit 10 to the modules 11 , since each Module 11 synchronized itself with the transmit clock by means of the synchronous word S, so that a delay time as a result of the signal propagation time is eliminated in the result.

The signal propagation times from the individual modules 11 to the central unit 10 is determined according to the invention during an initialization phase of the system, for example during a self-test for each module 11 and then taken into account by the central unit 10 for each communication with the corresponding module 11 , so that the Inventional method can achieve reliable communication between the modules 11 and the central unit 10 . It is therefore possible to operate a system with different, freely selectable transmission speeds, which works reliably even with very high transmission frequencies.

Claims (6)

1. A method for transmitting information in a system, in particular in a special security system for motor vehicles, which has a central unit ( 10 ) and a plurality of peripheral modules ( 11 ) connected in series with the central unit ( 10 ) are, in order to communicate with a selected module ( 11 ) a clock information (S) and a data information (D) from the central unit ( 10 ) to the selected module ( 11 ) is sent, characterized in that

• a) during an initialization phase, in particular each time the system is started up, a response delay (ΔA) specific to the selected module ( 11 ) is determined, in which clock and data information from the central unit ( 10 ) to the respectively selected module ( 11 ) are sent, the start of reception for the response information (A) sent back by the selected module ( 11 ) is detected and the response delay (ΔA) is derived from the time interval between the end of transmission and the start of reception, and
• b) is subsequently taken into account when receiving response information (A) sent back by the selected module ( 11 ).

2. The method according to claim 1, characterized in that the response delay (ΔA) for each module ( 11 ) is determined with a relatively small transmission speed. 3. The method according to claim 1 or 2, characterized in that the response delay (ΔA) as a constant regardless of the ge currently selected transmission speed is taken into account.   4. The method according to claim 2 or 3, characterized in that for determining the response delay (ΔA) for each module ( 11 ), the individual modules ( 11 ) are selected one after the other by the central unit ( 10 ) that the clock and data information from the Central unit ( 10 ) are sent to the respectively selected module ( 11 ), that the reception start for the response information (A) sent back by the selected module ( 11 ) is detected and that the response delay (ΔA) is derived from the time interval between the end of transmission and the start of reception becomes. 5. The method according to claim 2 to 4, characterized in that a predetermined transmission delay (ΔS) of the module ( 11 ) is taken into account in the determination of the response delay (ΔA). 6. The method according to claim 2 to 5, characterized in that the response delays (ΔA) determined for an operating time also after At the end of the operating time remain saved that at the beginning of the next loading drive time the response delays (ΔA) determined again and with the ge stored response delays (ΔA) can be compared to the Ensure the plausibility of the determined response delays.