DE19640211A1 - Method for manufacturing barrier-free semiconductor memory devices - Google Patents

Abstract

This invention concerns a process for producing an integrated semiconductor storage assembly, particularly with the use of ferroelectric materials as storage dielectrics. To that effect, a conductive connection between an electrode of a storage capacitor and a selector transistor is only produced after depositing of the storage dielectric. This invention also concerns storage assemblies produced according to said production process.

Description

The invention relates to a method for producing a integrated semiconductor memory device and one after Processed semiconductor memory device.

Semiconductor-based memory devices usually exist se from a number of memory cells, each one off selection transistor and one connected to the selection transistor NEN storage capacitor. During a manufacturing driving such semiconductor memory devices are common Usually first electrodes over conductive connections brings, the conductive connections the first electrical connect it to one of the selection transistors. A The storage dielectric is applied over the first electrode brings, on which in turn a second electrode is brought so that the first and second electrodes and the intermediate storage dielectric a storage probe form sator, which is conductive with one of the selection transistors connected is.

The use of new ferroelectric materials as The storage dielectric of the storage capacitors enables Manufacture of semiconductor memories, their in the form of electrical charge stored information after elimination Do not lose the supply voltage or its memory content not at regular intervals due to occurring Leakage currents must be refreshed.

A deposition of most of the previously known ones ferroelectric materials takes place at high temperatures in an oxygen-containing atmosphere. This has to Consequence that the use of such ferroelectric mate  rialien in the process described above, in which the Storage dielectric applied over the first electrode which in turn is connected to a conductive connection the selection transistor, an oxidation of the conductive Compound causes oxygen during the deposition of the ferroelectric materials through the first electrode diffused through in the direction of the conductive connection. A Oxidation of the conductive connection means an interruption Connection between storage capacitor and off selection transistor, so that one from storage capacitor and off existing memory cell no longer works is capable.

Approaches to avoid oxidation of the conductive Connection during the deposition of a ferroelectric Storage dielectric provide barrier layers between to apply the conductive connection and the first electrode gene, the barrier layers being electrically conductive resistant to oxidation and diffusion through must be of oxygen. Disadvantageous when using Barrier layers is the difficult search for suitable ones Materials that are both electrically conductive and acidic are impermeable and resistant to oxidation and suitably on the conductive connections can be applied.

The aim of the invention is to provide a method for producing egg to provide ner semiconductor memory device, at the ferroelectric materials as storage dielectrics to be manufactured storage capacitors can be used and where between the use of barrier layers conductive connection and first electrode can be, so that in particular the above-mentioned Nachtei le do not result, as well as a manufactured according to the method Specify semiconductor memory device.  

This goal is achieved with a method of manufacturing a Semiconductor memory device achieved the following procedure steps:

• - Providing an arrangement of selection transistors;
• - depositing a first layer of electrode material on a first main surface of an insulation layer, over the array of selection transistors;
• - depositing a dielectric layer over the first Layer of electrode material;
• - Creation of contact holes over source areas of the Selection transistors;
• - Placing a second insulation layer on one freely placed edge of the first layer of electrode material al;
• - Deposition of a second layer of electrode material towards the first major surface;
• - Structuring the second layer of electrode material al.

In the inventive method for producing a Semiconductor memory device is manufactured conductive connection between one of the two electrodes, in in this case the second electrode and the selection transistor only after the storage dielectric has been deposited. The The method is suitable for the use of any floorboards trika as storage dielectric for the production of storage capacitors in semiconductor memory devices. It is particularly especially suitable for the use of ferroelectric mate rialien as storage dielectrics, because with this method above mentioned problems, such as the oxidation of the conductive connection  to the selection transistors during the deposition of the memory dielectric, cannot occur. The procedure is continue with previously known methods for the production of Semiconductor memory arrangements can be carried out easily.

Further developments of the invention are the subject of the Unteran claims.

The ferroelectric properties of most so far be knew ferroelectric materials, which after an out embodiment of the invention as a storage dielectric in question come are temperature dependent. This ferroelectric mate rialien behave below a characteristic for them temperature ferroelectric while they are above this characteristic temperature paraelectric behavior ten, the dielectric constant in the paraelectric State is significantly higher than the dielectric constant ten previously used memory dielectrics. The temperature, below which ferroelectric properties are established len is very low for some ferroelectric materials rig, so that from a technical point of view a use of this fer Roelectric materials only in the paraelectric state Question comes, with their dielectric constant in parae Electrical state each over 10, preferably over 100 be wearing.

One embodiment of the invention provides materials as To use storage dielectrics, the dielectric constant is always greater than 10, such materials for example ferroelectric materials mentioned above that can be above the characteristic tem temperature can be used.

One embodiment of the invention provides for the use of oxidic dielectrics as storage dielectrics. The class of these substances include, for example, SBTN SrBi₂ (Ta _1-x Nb _x ) ₂O₉, SBT SrBi₂Ta₂O₉, PZT (Pb, Zr) TiO₃, BST (Ba, Sr) TiO₃ or ST SrTiO₃. The formula (Pb, Zr) TiO₃ stands for Pb _x Zr _1-x TiO₃. The proportion of Pb and Zr in this substrate can vary, the ratio of Pb and Zr decisively determining the temperature behavior of this dielectric, ie determining the temperature below which the substrate has ro-electric properties or above which the substrate has paraelectric properties at a high level Dielectric constant. The formula (Ba, Sr) TiO₃ stands for Ba _x Sr _1-x TiO₃, whereby the temperature behavior on this substrate is largely determined by the ratio of Ba to Sr who can. The list of substances mentioned is by no means exhaustive. The selection of one of the substances as a storage dielectric depends to a large extent on processing factors during the manufacturing process, but also on factors during use, for example the ambient temperature of the semiconductor memory arrangement.

During the manufacturing process according to the invention, in which the second layer of electrode material after manufacture the contact holes are deposited over an arrangement, over which the first layer of electrode material and the Dielectric layer before the generation of the contact holes brought, it must be ensured that no leading Ver bond between the first layer of electrode material and the second layer of electrode material at edges of the Contact holes are formed on which the first layer of elec tread material exposed. To prevent such conductive connection between the first layer of electrodes material and second layer of electrode material is in Area of contact holes on exposed edges of the first Layer of electrode material a second insulation layer upset. The insulation layer can cover the side walls of the However, it can only completely cover the contact hole Parts of the side surfaces of the contact holes from the second Insulation layer are covered, for example what  the use of frustoconical contact holes or of contact holes in the area of the first electrodes layer have a larger diameter than in the area the first insulation layer can be achieved.

Semiconductor memory arrays which are produced by the method according to the invention are the subject of claims 7 to 12 .

The invention is hereinafter in connection with Ausfüh tion examples explained in more detail with reference to figures. It shows gene:

Fig. 1, a method according to the invention for producing an integrated semiconductor memory arrangement,

Fig. 2 shows an embodiment of a Halbleiterspeicheran order according to the invention,

Fig. 3 shows another embodiment of a semiconductor memory device according to the invention.

Designate in the following figures, unless otherwise indicated, same reference numerals, same parts with the same Meaning.

In Fig. 1, a method according to the invention for the produc- tion of a semiconductor memory device is explained using several method steps shown in FIGS . 1a to 1f.

Fig. 1a shows a cross section through a section of an arrangement of selection transistors, which has a semiconductor body 5 , over which an insulation layer 10 , for example se silicon dioxide SiO₂ is applied. A selection transistor 2 shown in the present figure has a source region 4 , a drain region 6 and a gate 8 , the source region 4 and the drain region 6 being located in a semiconductor body 5 while the Gate 8 is arranged in the insulating layer 10 above. The source and drain regions 4 , 6 can, for example, consist of regions of the semiconductor body 5 doped in a manner complementary to the conductivity type of the semiconductor body 5 , while the gate 8 can be made of polysilicon. Arrangements of this type from selection transistors 2 can be completely prefabricated and used for various methods for producing semiconductor memory arrangements with a wide variety of storage capacitor geometries.

For reasons of clarity, the semiconductor body 5 and the reference symbols for gate 8 and drain region 6 are omitted in the following figures. Furthermore, there is no further wiring of the arrangement of selection transistors, for example the word and bit lines, which usually connect several selection transistors to one another in such arrangements.

FIG. 1b shows the arrangement of selection transistors 2 according to a first method step, in which a first layer 12 was deposited electrode material on a first major surface 3 of the insulating layer 10, said layer over which it most layer 12 of electrode material, a dielectric was applied fourteenth Platinum, for example, can be used as the electrode material. To get a better on the dielectric layer 14 and the first layer 12 are liable to reach electrode material, can be between 14 and lektrikumsschicht The first layer 12 of electro denmaterial, an adhesive layer, eg. B. titanium dioxide TiO₂, are brought up.

Fig. 1c shows the arrangement after a further method step, in which a contact hole 18 over the source region 4 of the selection transistor 2 shown in the insulation layer 10 , the first layer 12 of electrode material and the dielectric layer 14 was generated. An edge 19 of the first seal 12 made of electrode material is thus exposed in the upper region of the contact hole 18 .

In a next step, a second insulation layer 20 is applied over the exposed edge 19 , as shown in Fig. 1d. In the example shown, the second insulation layer 20 completely covers side surfaces of the contact hole 18 and thus also the exposed edge 19 of the first layer 12 made of electrode material and the dielectric layer 14 in the region of the contact hole 18 . A suitable material for the second insulation layer 20 is, for example, silicon dioxide SiO₂ or silicon nitride Si₃N₄. The second insulation layer 20 is preferably produced by depositing a layer of insulation material in the direction of the first main surface 3 with subsequent anisotropic etching

Fig. 1e shows the arrangement after a next method step, in which a second layer 16 of electrode material was deposited in the direction of the first main surface 3 above the arrangement. The second layer 16 of electrode material covers the dielectric layer 14 in the areas outside the contact hole 18 , the second insulation layer 20 on the side surfaces of the contact hole 18 and the source region 4 of the selection transistor 2 at the bottom of the contact hole 18th

The second electrode layer 16 is in a next Ver structured method step, so that portions 16 'of the two-th layer 16 formed from electrode material, wherein the portions 16' of a second electrode 36 of the Speicherkonden catalysts of the resulting semiconductor memory device 1 speak ent and to the source Area 4 each one of the selection transistors are connected, as shown in Fig. 1f. The dielectric layer 14 corresponds to a storage dielectric 34 , the first layer 12 of electrode material of a first electrode 32 , the first electrode 32 in the example shown a plurality of storage capacitors of the half conductor memory arrangement 1 is common. In the example shown, the second electrode 36 simultaneously forms the conductive connection to the selection transistor 2 .

In FIG. 2, a further embodiment is a semiconductor produced by the production method of the invention, memory device 1 illustrated. In the present example, the contact hole 18 has a larger diameter in the region of the first electrode 32 and the storage dielectric 34 than in the region of the first insulation layer 10 . In the illustrated case, the second insulation layer 20 only covers the first electrode 32 and the storage dielectric 34 in the region of the contact hole 18 . The side surfaces of the contact hole 18 in the region of the first insulation layer 10 are not covered.

The further exemplary embodiment of a semiconductor memory arrangement 1 shown in FIG. 3, which was produced by means of the manufacturing method according to the invention, has a frustoconical contact hole 18 . In the example shown, the second insulation layer 20 covers the first electrode 32 and the storage dielectric 34 in the region of the contact hole 18 as well as parts of the first insulation layer 10 on the side surfaces of the contact hole 18 . The second insulation layer 20 has at least approximately perpendicular to the first main surface 3 , so that the thickness of the second insulation layer 20 increases in the case of a truncated conical contact hole 18 from the direction of the source region 4 in the direction of the first main surface 3 .

Reference list

1 semiconductor memory device
2 selection transistor
3 first main surface
4 Source area
6 drain area
8 gate
10 first insulation layer
12 first layer
14 dielectric layer
16 second layer
16 ′ section of the second layer
18 contact hole
19 edge of the first layer
20 second insulation layer
32 first electrode
34 storage dielectric
36 second electrode

Claims (12)

1. Method for producing an integrated semiconductor memory arrangement with the following method steps:

• - Providing an arrangement of selection transistors ( 2 );
• - Deposition of a first layer ( 12 ) of electrode material on a first main surface ( 3 ) of an insulation layer ( 10 ) over the arrangement of selection transistors ( 2 );
• - depositing a dielectric layer ( 14 ) over the first layer ( 12 ) of electrode material;
• - Generating contact holes ( 18 ) via source Ge ( 4 ) of the selection transistors ( 2 );
• - arranging a second insulation layer ( 20 ) on an exposed edge of the first layer ( 12 ) made of electrode material;
• - Deposition of a second layer ( 16 ) of electrode material in the direction of the first main surface ( 3 );
• - Structuring the second layer ( 16 ) made of electrode material.

2. The method according to claim 1, characterized in that the dielectric layer ( 14 ) is made of a material which has ferroelectric properties. 3. The method according to claim 1 or 2, characterized in that the dielectric layer ( 14 ) consists of a Ma material, whose dielectric constant is greater than 10. 4. The method according to any one of the preceding claims, characterized in that the material is an oxidic dielectric, in particular SBTN SrBi₂ (Ta _1-x Nb _x ) ₂O₉, SBT SrBi₂Ta₂O₉, PZT (Pb, Zr) TiO₃, BST (Ba, Sr) Is TiO₃ or ST SrTiO₃. 5. The method according to any one of the preceding claims, characterized in that the contact hole ( 15 ) in the loading area of the first layer ( 12 ) of electrode material has a larger diameter than in the area of the most insulating layer ( 10 ). 6. The method according to any one of the preceding claims, characterized in that the contact hole ( 15 ) is frustoconical. 7. Integrated semiconductor memory arrangement, consisting of a number of identical memory cells, each having the following features:

• 7.1. a selection transistor ( 2 ) having a source region ( 4 ), a drain region ( 6 ) and a gate ( 8 );
• 7.2. a first insulation layer ( 10 ) located over the source region ( 4 ) of the selection transistor ( 2 );
• 7.3. one on a first main surface ( 3 ) of the storage arrangement ( 1 ) arranged first electrode ( 30 ) with overlying storage dielectric ( 32 );

characterized by the following additional features:

• 7.4. a contact hole ( 18 ) over the source region ( 4 );
• 7.5. the first electrode ( 30 ) is covered in the area of the contact hole ( 18 ) by a second insulation layer ( 20 );
• 7.6. a second electrode ( 34 ) is located above the storage dielectric ( 32 ) and is conductively connected to the source region ( 4 ) of the selection transistor ( 2 ).

8. A semiconductor memory arrangement according to claim 7, characterized in that the storage dielectric ( 34 ) has ferro-electrical properties. 9. A semiconductor memory arrangement according to one of claims 7 or 8, characterized in that the storage dielectric ( 34 ) has a dielectric constant greater than 10. 10. A semiconductor memory device according to one of claims 7 to 9, characterized in that the storage dielectric is an oxide dielectric, in particular SBTN SrBi₂ (Ta _1-x Nb _x ) ₂O₉, SBT SrBi₂Ta₂O₉, PZT (Pb, Zr) TiO₃, BST (Ba, Sr) is TiO₃ or ST SrTiO₃. 11. A semiconductor memory arrangement according to one of claims 7 to 10, characterized in that the contact hole ( 18 ) in the region of the first electrode ( 32 ) has a larger diameter than in the region of the first insulation layer ( 10 )
12. Semiconductor memory arrangement according to one of claims 7 to 11, characterized in that the contact hole ( 18 ) is frustoconical.