DE19623480C1 - Method for generating an output clock signal that can be used to control a data output as a function of one of a plurality of input clock signals - Google Patents

Abstract

The invention describes a method for generating a suitable output clock signal for controlling data output. The signal is dependent on one of several input clock signals, which are produced by inputting data via several input channels (U1 to U8). The method is characterized in that the input clock signal used to generate the output clock signal is selectively changed whilst generating the output clock signal if the input clock signal is not suitable or becomes less suitable for generating the output clock signal.

Description

The present invention relates to a method according to the Preamble of claim 1, d. H. a process for Generation of one used to control a data output output clock signal depending on one of several input clock signals, which consist of several input data entry channels can be obtained.

Such a method is, for example, in an NT (net work termination) unit of an ISDN system. The usually NT-Ein installed at the ISDN subscriber unit forms the interface between the facilities (Communication terminals and / or private telephone systems) des ISDN subscriber and the facilities (network, Ver agency, etc.) of the ISDN operator.

The NT unit is able to operate from a central office or a so-called LT (line termination) unit of the ISDN operator over the same network, which at ISDN systems out as a so-called U interface is to receive data, then this within the NT unit via a so-called IOM interface (IOM inter face) to forward and further process and finally via an S or T interface (S or T interface) admit the ISDN subscriber facilities. Conversely, you can in the same way also data from the ISDN subscriber equipment to the ISDN operator facilities (and from there on to other participants).

For certain reasons, the knowledge of which is not available from Meaning, the IOM interface must be on the U-cut place to be synchronized; the NT unit, more precisely  their between the U interface and the IOM interface The intended transceiver is Clock slave of the U interface and clock master of the IOM cut Job. The transceiver of the NT unit must therefore for IOM interface generate output or relay clock signals conditions related to the data transfer rate (baud rate) and the Phase of the data entered via the U interface or adapted an input clock signal obtained therefrom or are synchronized with this.

For certain applications and / or areas of application, it can prove to be advantageous, multi-channel NT units, d. H. NT units with multiple U interface connections and several S or T interface connections the. In such cases, especially for cost reasons, Consider data for multiple U interfaces connections or from several U interface connections via to run a common (single) IOM interface.

By connecting the NT unit with several U-cuts the NT unit is connected to several clock masters the. Since the IOM section provided within the NT unit on the other hand, only provided in a simple version the question arises as to what is synchronized with whom that should.

One possibility is that one of the several Ren U interface connections of the NT unit as a master U interface connection is determined, and that the IOM interface is synchronized to an input clock signal which is obtained from the data stream, which over the the Master U interface assigned to master U interface connection is received.

This measure, however, only allows orderly as long proper synchronization of the IOM interface (an ord proper operation of the NT unit) as from the on the master U-section  incoming connection a suitable on output clock signal can be obtained. Coming on the master U-cut temporary or no long-term connection Data can no longer be used as a suitable input clock signal can be obtained more, and consequently it is difficult rig, the IOM interface with no interruptions and exactly to synchronize the U interfaces.

The present invention is therefore based on the object the method according to the preamble of claim 1 to develop in such a way that, for example, for the company output clock signal required by the IOM interface can be generated, which exactly at all times with example wise from data input over several U interfaces input clock signals is synchronized.

According to the invention, this object is characterized by the solved the part of claim 1 claimed features.

Accordingly, it is provided that this is to generate the output clock signal used input clock signal during the off Generation of clock pulse signal if not suitable or one Decrease in suitability for the output clock signal generation selectively changed.

The input clock signal does not become rigid as before a very specific input channel as the input clock signal determined depending on which the output Clock signal generation takes place, but it becomes dependent of the suitability of each for the output clock signal Generated input clock signal a dynamic Input clock signal selection performed.

As long as at least one input channel is active, is also at least one of the input clock signals for the output clock signal Generation suitable. It can therefore output a clock signal  generated, which exactly with one at all times suitable input clock signal is synchronized.

Advantageous developments of the invention are the subject of subclaims.

The invention is illustrated below with the aid of an embodiment game explained with reference to the drawing. It demonstrate

Fig. 1 is a block diagram of a circuit arrangement in which the inventive method is applicable, and

FIG. 2 shows a schematic illustration of the internal structure of transmitter / receiver devices 11 and 12 shown in FIG. 1.

The circuit arrangement shown in FIG. 1, in which the method according to the invention can be used, is an NT unit of an ISDN system. With regard to the function and arrangement of an NT unit within an ISDN system, reference is made to the introductory explanations.

It is expressly pointed out that the previous and designations used below for the respective Interfaces and units of the ISDN system each are common names; regarding their meaning if there are any doubts about this, in particular on the corresponding definitions, especially in the ETSI and ANSI standards referenced.

If in the present application of IOM interfaces or IOM data frame is mentioned, so this as abbreviated spelling of what is actually meant IOM-2 interfaces and IOM-2 data frames can be understood; the  IOM-2 definition is a mean created by the applicant but now well-known standard in the ISDN area.

Although the present invention is hereinafter referred to is described on an ISDN system, it is in their Applicability is not limited to this. The invention is rather, it can be used wherever there is an output clock generate signal with one of several input clock signals is synchronized.

The NT unit 1 shown in Fig. 1 comprises a total of four transmit / receive means (transceiver) 11, 12, 13, 14, of which a two (transceivers 11 and 12) each weils four U-interface terminals and of which the two of which (transceivers 13 and 14 ) are each equipped with four T interface connections. The U-interface connections of the transceiver 11 are connected via data transmission links in the form of U interfaces U1 to U4 to the LT units LT1 to LT4 (not shown in the figure), and the U interface connections of the transceiver 12 are connected via data transmission links in the form of U-cut places U5 to U8 connected to LT units LT5 to LT8, not shown in the figure. The T interface connections of the transceiver 13 are connected via data transmission links in the form of T interfaces T1 to T4 to communication terminals KE1 to KE4, not shown in the figure; the T interface connections of the transceiver 14 are connected via data transmission links in the form of T interfaces T5 to T8 to communication terminals KE5 to KE8, not shown in the figure. The transceivers 11 and 12 are connected to the transceivers 13 and 14 via a common single data transmission path in the form of an IOM interface IOM.

The transceivers 11 and 12 receive data from the connected LT units via the U interfaces in the form of so-called U data frames. The U data frames each consist of a predetermined number of bits, which are composed of the user data that is actually to be transmitted and control data for the receiving transceivers. The U data frames received by the transceivers 11 and 12 are converted there into so-called IOM data frames, which are processed further by subsequent units and / or are output from the NT unit via the IOM interface IOM to the transceivers 13 and 14 are passed on. Like the U data frames, the IOM data frames comprise a predetermined number of bits which are composed of the useful data to be transmitted and control data for the receiving transceivers.

With regard to the clock (frequency and phase position) of the data transmitted via the U interfaces, the respective U interfaces are the (clock) masters; the NT unit, more precisely its transceivers 11 and 12 can (not) influence this, but only react accordingly, are therefore the clock slave in this regard. The transfer of the data received via the U interfaces to the IOM interface has to take place under synchronization with the U interfaces, for which purpose the transceivers 11 and 12 provide a common output clock signal for all U interfaces and the transceivers 11 and 12 is produced.

For this, each of the transceivers has one to be more precise writing voting logic, with the respective voting logics are designed and interconnected, that to provide for the generation of the output clock signal lend input clock signal dynamically from multiple input clock signals can be selected, the selected input clock signal in response to a lack of suitability or a Deterioration of its suitability for the output clock signal genes selectively exchangeable or by a more suitable one is replaceable. The multiple input clock signals are derived from the via the connected U interfaces (in the present Embodiment from the U-U1  up to U8) incoming data streams obtained; more specifically is for each U interface from their incoming data current input synchronous to its data transfer clock clock signal obtained.

The tuning logic will now be described in more detail with reference to FIG. 2, which shows the internal structure and a circuit, not shown in FIG. 1 for reasons of clarity, of the transceivers 11 and 12 which are of particular interest here.

. As shown in Figure 2, the transceiver 11 consists of an analog unit 111 and a digital unit 112; the transceiver 12 consists of an analog unit 121 and a digital unit 122 .

In the (identically designed) analog units 111 and 121 , which can each be formed by a separate chip, analog signals are, as the name suggests, after any preprocessing that may be required (for example to compensate for the line echo etc.) into digital signals changed; In the (also identically designed) digital units 112 and 122 , which can also each be formed by a separate chip, digital signals, as the name suggests, are output to the IOM interface after a possibly necessary preprocessing.

Connections, not shown, are provided between the analog unit and the assigned digital unit of the respective transceivers, via which connections data and control signals can be exchanged. For the sake of clarity, only those connections are shown in FIG. 2 that are directly related to the synchronization of the IOM interface to the U interface.

In the exemplary embodiment shown, the output clock signal in question for synchronizing the IOM interface is formed in the analog unit 111 of the transceiver 11 under the control of the digital unit 112 of the transceiver 11 and to the digital unit 112 of the transceiver 11 and to the analog unit 121 and the digital unit 122 Transceivers 12 issued.

The control of the output clock signal generation by the analog unit 111 takes place in accordance with a control signal which is input into a dedicated input connection of the analog unit 111 , which is labeled "Ctl" in FIG. 2; the corresponding connection of the analog unit 121 of the transceiver 12 is connected to ground.

The said control signal is output by the digital unit 112 of the transceiver 11 , more precisely by a tuning logic L provided there and mentioned above.

The tuning logic L in the present exemplary embodiment has five input connections for input clock signals and one output connection for the control signal mentioned, which can in principle be directly one of the input clock signals or another signal formed on the basis thereof. In the present exemplary embodiment, the output signal of the tuning logic is one of the input clock signals; the tuning logic L can thus be implemented as a multiplexer that is particularly controlled. A tuning logic with an identical structure and an identical mode of operation is also provided in the digital unit 122 of the second transceiver 12 .

As already mentioned above, the respective input clock signals are obtained from the respective data streams which are input into the transceivers via the U interfaces. Accordingly, four input clock signals are formed in each of the transceivers 11 and 12 (in accordance with the number of U-interface connections) and input into the respective tuning logic L.

Each of the tuning logic L points, as already mentioned above was imagined, five and thus more input connections for On gave clock signals as at the transceiver in question U interface connections are provided.

This allows the tuning logic of a (first) transceiver additional input from outside the transceiver clock signal are supplied. One uses as another one output clock signal the output signal of a tuning logic (second) transceivers, so the number of inputs clock signals, under which the output signal of the vote logic of the first transceiver can be selected, except for one Increase value that is recognizable close to the sum of the input clock signal connections of the (cascaded ten) voting logic, whereby by connecting a third Voting logic to the second voting logic and / or another Ultimately, cascading any number for the output clock ready signal input clock signals ready can be put.

This initially generally described principle is implemented as follows in the circuit structure shown in FIG. 2:
Each of the transceivers 11 and 12 , more precisely each of their digital units 121 and 122, contains a tuning logic L.

The input signals of the tuning logic L of the digital unit 122 are four input clock signals which are obtained from the data streams arriving via the U interfaces U5 to U8. The fifth, externally assignable input connection from this voting logic is, as symbolically indicated in the figure, placed on ground potential.

The input signals applied to the tuning logic, at least however, this is output as the output signal from the tuning logic level input signal, are then by the tuning logic verifiable whether they are used to generate the IOM cut position control to be generated output clock signal. The criteria to be met for this can vary depending on the indi viduell demands of different nature be. In the present embodiment, the suitability criterion is that the output signal from the Tuning logic input clock signal output from a con continuous (uninterrupted) U-interface data current descends; a short or long lasting Interruption of the U-interface data stream from which the switched input clock signal could be obtained namely have the undesirable effect that forwarding from not using the output clock signal generation selected U interface interrupted incoming data streams or at least (due to the missing or only approximate Synchronization) is disturbed.

The said check by the voting logic L takes place in simplest case only at the respective to the exit of the respective input clock signal switched through the tuning logic, and for example by means of a finite state machine which is checked whether the corresponding U interface is active. If and as long as it is determined that the U-interface in question is active tete input clock signal so for the output clock signal generation suitable, this input clock signal can continue as an output signal from the voting logic. However, will found that the switched input clock signal not or no more or not as good at the output clock signal generation is suitable, so another will automatically Input clock signal out as the output signal of the tuning logic and henceforth its suitability for the output clock signal genes checked or monitored.  

There are, of course, many variations and variations lungs conceivable. For example, that always all or at least several of them in a respective Tuning logic input clock signals constantly on de suitability for the generation of output clock signals the. This required a bit more effort, but it would always be the most suitable one Switch through the output clock signal or at least at a requ the change in the input clock signal used Switching through one not or not well or not best prevent suitable input clock signal.

The input clock signal switched through by the tuning logic L of the digital unit 122 of the transceiver 12 (ie the output signal from this tuning logic) is applied as a fifth input clock signal to the tuning logic of the digital unit 112 of the transceiver 11 . The first four of the input clock signals input into this voting logic are obtained, similarly to the transceiver 12, from the data streams arriving via the connected U interfaces (U1 to U4).

The decision as to which of the input clock signals applied to the tuning logic is output as an output signal is also made dependent on a check in which the suitability of a particular input clock signal for outputting clock signal generation is checked. The check follows as with the tuning logic of the transceiver 12 .

In contrast to the tuning logic of the transceiver 12 , where an input clock signal could be selected from four input clock signals as the output signal, in the tuning logic of the transceiver 11, as a result of its cascading with the tuning logic of the transceiver 12, an input clock signal can be selected from eight input clock signals as the output signal.

In other words, the IOM interface Synchronization dynamically any of the (in the present based on the exemplary embodiment eight) U interfaces can be. By increasing the number of input connections for input clock signals to the respective tuning logic and / or a multi-level cascading of voting logic can ultimately be a suitable input clock signal Any number of input clock signals dynamically selected the.

The output signal from the tuning logic of the transceiver 11 is the control signal, taking into account the output clock signal to be generated ultimately by the arrangement described for IOM interface synchronization. This control signal is in the provided for this, in Fig. 2 with "Ctl" designated input terminal of the analog unit 111 of the transceiver 11 is entered and based there (using a PLL) output clock signal generation taking place there. The generated output clock signal is output from the analog unit 111 of the trans ceiver 11 as the signal “CLK” and all other units of the transceivers connected to the U interfaces, that is to say in the present exemplary embodiment the digital unit 112 of the transceiver 11 and the analog unit 121 and the digital unit 122 of the transceiver 12 supplied.

This (only) output clock signal is - at least as long at least one of the U interfaces is active - always with synchronized with a suitable input clock signal and results in an optimal, uninterrupted result Synchronization of the one IOM interface with the many U interfaces.

The data streams on the many U interfaces can counter each other a certain data transfer rate and phases have misalignment. To pass on this data no data losses flow to the one IOM interface  suffer, are sufficiently large for each U interface provide measured data buffers.

The forwarding of received via the U interfaces Data on the IOM interface can and must usually even accepting a certain amount of data transfer rate and phase shift. Behaves differently it is the opposite in data transmission Direction, i.e. from the IOM interface to the U-cut or from the ISDN subscriber to the LT unit of the ISDN operator. Here it must be ensured that the one data to be sent exactly the respective U interface have the same data transfer rate and phase position as that Data received via this U-interface (the U-cut are the clock master).

The respective digital units are associated with the Analog units are therefore connected in such a way that the digital ones in addition to the data to be sent, the respective data Time of transmission (in the form of a corresponding transmission clock) can assign the analog unit.

In single channel NT units, i.e. H. in NT units with only A U interface connection are for this between the Digital unit and the analog unit four connecting lines gene provided, namely a line for transmitting the Transmission time (transmission clock), and three lines to over averaging towards the U interface at this time giving data. In the considered four-channel NT unit would have retained this technique a significant number of connecting lines (four per channel) between the Digi valley unit and the analog unit. By after Modification of the previous procedure described below can be the number of connecting lines for the named Purpose to be reduced to one connecting line per channel.  

The com combination of two measures, namely

• 1) the transmission of the previously parallel over three lines data transmitted (to be sent) per channel summarized as a corresponding pulse width modulated signal on a single transmission line, and
• 2) Start transmission of each pulse width modulated Signals synchronized with the time of transmission at which the to transfer data transmitted thereby via the U interface are send, which means the transmission at the time of transmission a separate line can be dispensed with.

In other words, one for each U interface pulse width mod according to the respective transmission data lated transmission clock from the digital unit to the analog transfer unit.

One due to pulse width modulation and demodulation additionally occurring runtime can function in the Transceivers intended to avoid echo cancellers the line echo. To avoid who the from the U interface in the echo canceller level data by providing a correspondingly extended Runtime also entered with a delay.

The circuit arrangement described and its operation ma Chen the use of multi-channel NT units or - general mine expressed - the use of comparable device by which the same or a similar Synchroni due to the increased radio tion security extremely simplified at the same time attractive.

Claims (8)

1. A method for generating an output clock signal which can be used to control a data output as a function of one of a plurality of input clock signals which can be obtained from data inputs via a plurality of input channels (U1 to U8), characterized in that the input clock signal used to generate the output clock signal during the output clock signal Generation in the case of inadequate suitability or a deterioration in suitability for output clock signal generation is selectively changed. 2. The method according to claim 1, characterized, that the input clock signals from the input channels (U1 to U8) incoming data streams are obtained, that they syn. with respect to the respective data transmission clocks chron to these are. 3. The method according to claim 1 or 2, characterized, that that was used to generate the output clock signal Input clock signal entered by a tuning logic (L) from there input clock signals selected and as an output signal is issued from this. 4. The method according to claim 3, characterized, that in the tuning logic (L) an output signal of another Tuning logic can be entered as an input clock signal. 5. The method according to any one of the preceding claims, characterized, that the determination of the suitability of generating the Aus input clock signal used on the Er result of a review based on which found  whether the input corresponding to the input clock signal channel (U1 to U8) is active. 6. The method according to claim 5, characterized, that the review and the selection based on it for Output clock signal generation to use input clock signals is carried out by a finite state machine. 7. The method according to claim 3 or 4, characterized, that based on the selected input clock signal below Is generated using a PLL. 8. The method according to any one of the preceding claims, characterized, that a deterioration in the suitability of the selected one output clock signal for output clock signal generation is set if the selected input clock signal is not more, not as good or less good than another one output clock signal suitable for output clock signal generation is.