DE1911441A1 - High-speed data processing system - Google Patents

Description

High Speed Data Processing System The present invention relates to rely on a modular high-speed data processing system with a large number of functional modules, and in particular a modular data processing system with a high-speed main memory with an improved central processing module and an improved input / output control module.

It is known that arithmetic circles, in which the most advanced Logical elements are used, their functions in individual signal propagation pulses carry out and that afterwards you can either rely on the transmission of a Input / output information or the transfer of the next instruction from main memory of the system have to wait. These speed limits have been in place since the beginning the computer system development known and form a significant disadvantage.

Despite the advances in computer architecture and system design, the speed limit imposed by the duration of the main memory duty cycle caused is not acceptable. Since ferrite cores in most main storage applications large capacity cases have been used, many previous attempts have been made to increase the switching speeds. However, these efforts achieved at Far from the logical propagation speeds currently available stand. High-speed storage devices that use faster storage elements, such as superconducting ones Cells, magnetic separation crystals, magnetic thin films and ferrite plates, which a few years earlier were expected to have high storage rates Would replace capacity were slow to occur. Most attempts by yourself only generate memory with small capacity, in which these embodiments used at high speed were1 encountered a significant Difficulty. Solutions that were previously included to eliminate the problem, were no longer necessary. As a result, simplifications were immediate possible and earlier efforts to deviate from thought could now be applied to immediate Successes are judged.

In addition, the improved way of working that the advanced logical circuit structure and new components offered, which so far only partially realized could now be fully appreciated.

Thus, in addition to that, the present system includes a system is created that the speed limits that were previously in each main memory with large capacity were considered to be part of it, including a number of new ones Notions that these recently available capabilities more fully in terms of speed.

The invention is based on the object of an improved multi-computer module data processing system to create, the operating speed of the main memory being such that that it can meet storage and retrieval requests as quickly as they can the rest of the system can use; an improved computer module is also to be developed be created for such a system, the computer module processing and Control means comprising arithmetic, logic and thin film memory circuitry which is able to use the system main memory with a to use higher speed than the known data processing systems; furthermore, an improved input / output control module is intended for the present Data processing system can be created, each of the input / output control modules is able to make more efficient use of such a memory; after all, should a data processing system can be provided which has an improved automatic Possess the interrupt control system which has the means to further interrupt the-- Creates system operation during the period that the system is under a previous one Interruption condition is working.

The object on which the invention is based is achieved by at least a quick storage module, at least one input / output control module that individually is connected to each of the memory modules, at least one computing module that is individually connected to each of the memory modules, several peripheral devices with input / Output devices, each of the input / output-output control modules being a pair of Input / output control units, a memory connector and an input / output peripheral device interface unit each of the pairs of control units with the storage connection unit is connected, which in turn is connected to each memory module to the individual Connection with this to shcaffen, and whereby the input / output interface unit is connected between the control units and all peripheral devices In Figures 1 to 18 of the drawings - the subject matter of the invention with reference to FIG Embodiments shown, which are explained below. Show it: Fig. 1 is a pictorial representation of the proposed maximum system design; Fig. 2 is a block diagram of a typical system arrangement; 3 shows a simplified one Wiring diagram showing the basic inter-module connections of a typical Shows system arrangement; Fig. 4 is a functional block diagram showing the types of operations of the Arithmetic module when controlled by the interrupt signals; Fig. 5 is a table all system interruption signals from which their individual properties emerge; Figure 6 is a basic block diagram showing the path an interrupt signal may take travels during an input / output operation; 7 shows the various descriptor word formats, that of the I / O control modules to control the input / output operation Fig. 6 can be used; 8 shows an external wiring diagram of a computing module in the proposed system; 9 shows an external wiring diagram an input / output control module in the failed system; Fig. 10 an external Wiring diagram of a memory module in the proposed system; Fig. 11 a Wiring diagram of the input / output switching switch that connects the Figure 10 shows the I / O control module housings and peripheral devices; Figure 12 is a functional block diagram of a single computing module, its thin-film storage field, its arithmetic Field and its logic / control field; 13 including FIGS. 13A and Fig. 13B is a table showing the address locations of the thin film memory array of the computing module according to Figure 12; Figure 14 is a detailed block diagram of the arithmetic field of the computing module according to FIG. 11; 15 is a detailed block diagram of the logic / control field; which contains the program processing and memory control units; the thin film storage field is repeated for clarity; Fig. 16 including the Figures 16A, 16B, 16C and 16D in the arrangement shown, a detailed block diagram an I / O control module including the first and second I / O control units; 17 including FIGS. 17A and 17B is a detailed block diagram of a single main memory module as used in the present system will; 18, including FIGS. 18A and 18B, is a complete list of the existing commands used in the system.

The description discloses a modular data processing system, which is likely to be the first full-scale system to incorporate both magnetic core and Thin film magnetic storage devices as the basic storage elements of its Main memory used to create a system su its speed of operation is not limited by the cycle speed of a main memory.

The reference numbers in the figures are derived from those in FIG. 9. The computing modules, which are designated by 200 in FIG. 1, are shown in particular in FIG. 2 labeled 201, 202 and so on.

Fig. 1 shows an illustration of an embodiment of the present modular data processing system. The system is divided by dashed lines, to represent its main parts. The main memory 100 is through several separate connecting lines through a central switching switch 300 with the Processing or arithmetic part 200 connected. A peripheral device information becomes processed by an input / output control part 400 in a similar manner by the central interlocking switch 300 is connected to the main memory il 100 is.

An input / output switch 500 that is the central switch 300 is very similar, is between the control part 400 and the peripheral devices 6oo switched. The central switch 300 provides a means for concurrent Connection of each of the memory modules of the main memory 100 and one like it .Number of separate computation modules of the processing part 200 and of I / O control modules of the I / O control part 400.

Fig. 2 shows a block diagram of the module arrangement of the present Systems. Each of the modules is represented individually by a block. The four memory modules are labeled 101 to 104. The three computing modules 201, 202 and 203 and the ten input / output control modules 401-410 are all through the central switch 300 connected to each of these memory modules. Each of the I / O control modules is in divided into two control units, making a total of 20 I / O control units. All of the I / O controllers are through an input / output network 500 with a plurality of 64 peripheral devices 600 connected. These devices can accept 32 simple input and 32 simple output or 32 complex devices or combinations of simple and complex devices.

Fig. 3 is a wiring diagram of the central switch 300, the shows the modules of the system and their respective system connections. The ones in the Numbers in circles indicate the number of lines contained in the cable at. The data leaving the memory as information is transmitted through the 49-line cable which lead out of the lower part of each memory module 101-104. The connected group of cables are referred to as "information data from memory.

This group of four 49-line cables are more uniform in thick lines Width shown, successively with each of the remaining 13 modules 201 to 203, 401 to 410 are connected in the system. The initial connection is as one shown with the computing module 201; however, no special order is required.

Control of the flow of information data along these four 49-line cables is carried out by a group of four 13-wire cables, one being a cable comes from each of the four memory modules. These four cables are called "control data." from the memory ", and it is the signals along this group of cables, the information data flow from a particular one of the four memory modules 101 to 104 to a particular one of the 13 remaining system modules 201 to 203, 401 to 410 direct.

These remaining modules can therefore be referred to as non-tape modules because they are not part of main memory. -in another -expression could, Be memory consumer modules.

The 13-line control cable from each of the four control modules 101 to 104 is with the remaining modules in a completely different way connected as the 49 lead cable. Each memory module in the system is individual connected to each non-memory module by a single control line. One of the 13 lines of the memory module 101 is with the computing module 201, another connected to the computing module 202 and so on.

This continues until each of the 13 lines of the memory module 101 is connected to another separate non-storage module. This connection scheme is repeated for each of the remaining memory modules 101 to 104. The final result is a group of 13 cables with four wires. A 4-wire cable is included Each of the three computing modules 201 to 203 and with each of the 10 I / O module housings 401 through 410 (Fig. 3).

The input cables of the four memory modules shown in FIG. 3 are now shown considered. The information data to the memory is in turn provided by a 49-line cable transfer; in this case each of the 13 non-memory modules is by its own separate 49-line cable connected to the storage module 101. Each of these 13 modules 201 to 203, 401 to 410 are connected to the storage module through its own control cable 101 connected. The three control cables of the computing modules 201, 202 and 203 and the control cables of the ten I / O control modules 401-410 have two lines. There are 26 cables connected to the memory module 101, 13 of which are 49-line information data cables and 13 2-wire control data cable of the I / O control module housings 401 to 410 and the computing modules 201, 202 and 203 are. These 26 cables are sequential with each following one Memory module 102 to 104 connected. Since each memory module with the previous one is connected, this 26-line group is as well as the four 49-line information cable group and the four 13-line control cable groups of memory modules 101 to 104 are formed so as required by the size of the system. The central switch 300 (FIG. 1) becomes formed by the cables just described. It doesn't exist as a special one physical size, but it is created automatically by the module connection. It is automatically adapted to changes in size of the system when modules are added or be taken away.

Figure 4 illustrates the interrupt control system embodied in the data processing system This system not only detects faulty functions and one-off conditions and corrects or responds to these conditions, but also tries the data processing system to protect against total failure without stopping all processing. This is achieved in that the arithmetic module recognizes error interrupt signals, if the module is already operating in its interrupt mode. The system works not only in a normal and an interrupt mode, but also in another interrupt mode.

As used herein, the term "interruption" is not used in its usual way Sense is used to denote a suspension or interruption, rather it becomes used to describe a switchover or a transition.

It can be viewed as an instruction to the computing module, its To transfer attention from one program to another like this through the components of the interruption system are commanded. These commands can be internal (within each computing module) or external (from the other modules of the system) be initiated.

In Fig. 4, an interrupt signal selector receives 4-10 all interrupt signals and selects one for consideration by the computing module 4 to 12 off. Although this selector 4-1Q is shown separately, it is shown in FIG the arithmetic module 4-12 is built in and is shown for ease of explanation. Even though There are a number of computation modules in Fig. 4, they only represent the different ones Operating modes. They are not physically different modules, but rather the same module in different operating modes.

A computing module 4-12 responds to the receipt of an interrupt signal by switching its type of operation. A calculation module, i.e. in the normal type of operation executed, executes the steps of a translated program. Receiving one selected interrupt signal at this point in time will cause the arithmetic module to be. Äufmerksamk.it (its operation) on a control instruction to judge. This mode switching is called a switching from the normal operation referred to in the control operation. The first type of control operation is used in the present Description as control operation type A (4-16) different from the second control operation type B (4-20).

The selection of an interrupt signal by the device 4-10, when the arithmetic module 4-12 is operating in the normal operation mode (N) ika to perform an operation type switchover to the control operation type "A" (4-16). In this state, the computing module executes a program from a group of suitable ones Control programs associated with each interrupt condition. These programs are located in special places in the main memory.

They are collectively referred to as the A tax type interrupt table. In addition, see the remedial and control programs, usually with the expression "Interrupt" are connected, additional programs are included for all control functions, required by the system.

All I / O operations are accomplished through the use of an interrupt control signal and the completion of such an operation is achieved by using it recognized.

For all signals, the arithmetic module is activated on the basis of the interrupt signal operates and then returns to its N mode of operation by sending an interrupt return signal IRR generated. After returning to the normal type of operation, he receives from his its own thin-film memory stores the information that has been received after the interruption signal saved became. This information stored in this way contains the all of the information necessary to resave the program up to that point is when the interruption occurred.

If the control module while it is in control operation type A (4-16) is operating, receives an interrupt signal indicating that an error has occurred is, it switches to another type of operation that is control operation type B is called. This is shown symbolically (Fig. 4) by the block 4-20. In this the latter type of control operation, the control module executes programs that are in a other table. This table is called the B control mode interrupt table denotes and only contains programs that are used to remedy the situation, as only an error interruption can initiate such an operational switchover. The computing module returns from its B operation type (4-20) back to its N operation type (4-12) if the executions the appropriate remedial program have been completed. if the computing module while it is in the B operation mode (4-20), receives another interrupt signal, This indicates that an error occurred while running the remedy or that commands the control module to interrupt processing, then responds the module accordingly and interrupts processing (4-22). The advantage of this Property becomes apparent when it is taken into account that without mie the computing module continues to run the remedial program even though the given errors are incorrect would be.

If the arithmetic module, while it is in operation type A.

(4-16) is operating, receives an interrupt signal instructing him to to interrupt the processing, he will comply in a similar manner and immediately go to the halt state 4-22 instead of switching to operation type B (4-20).

The components that are necessary to achieve this interruption property are created by two registers of the local thin film memory, contained in every computing module of the system. Fig. 13 shows a list of the local thin film storage register locations. There are two interrupt reason address registers in it IARA and IARB, which are listed as registers 063 and 067, respectively. Both Registers contain the base address of the interrupt tables that are in main memories 100 of Fig. 1 are stored. This basic address information is used to determine the start address of the interrupt maintenance program. The A tax type interrupt table is not in the same main memory module as the B control type interrupt table. This prevents both tables from being inaccessible when a single main memory module fails.

Fig. 5 shows. the 14 interruption conditions that exist in the system be used. Usually the arrival of one of these interrupt signals causes the computation module that receives it from the execution of a translated program to switch to the execution of a control program.

The particular control program that is selected depends from the received interrupt condition; There are suitable control programs in the main memory associated with each of the interruption conditions.

Because the occurrence of certain conditions a quicker attention than the others required, the 14 conditions were given a predetermined priority, which is indicated by its sequence of digits. Corresponding interruption conditions are listed in the second column next to their respective positions. Everyone who Compute module contains a 12-bit interrupt register, with one of the bits corresponding is assigned to a special interruption condition. This register becomes the Temporary storage of the interrupt signals of the 12 interruption conditions used with lower precedence until maintenance is done. In a similar way Way, each arithmetic module contains a register that corresponds to the interrupt register is connected and that is operated in conjunction with this in order to activate to control certain bits of the interrupt register. The latter register will referred to as a mask register. Its main function is to make certain of the computing modules from responding to certain of the interruption conditions. It supplies the system with means to keep all computing modules from running at the same time to respond to a single tax request.

The individual bits of the interrupt register are in the third Column in Fig. 5 listed. The two interruption conditions, the first and second priority designation have none. Position under the Interrupt register bits of column 3. These two conditions are the only two of the 14 interruption conditions, which must have an effect on all computation modules without a bit in the 12-bit interrupt register included in each computing module. They are according to theirs Priority primarily energy interruption and timer. Any of the remaining 12 interruption conditions operates in conjunction with a bit of the 12-bit interrupt register, which is located in each computing module. Of the 12 listed bits (third column in Fig. 5) four interrupt registers can be hidden from an active operation.

This prevents a special computing module on the selected one hidden interrupt replies. The bits of the 48-bit data word that the hide register loads, corresponds to the bits of the interrupt register. These are at neighboring Place the row listed in the column that starts with "Fade-out bits of the special loading register (LSRpOperanden ". The data words biX 1-20 are assigned to bit 3 of the interrupt register used while bits 21-36 to bit 2 or the external request bit of the Interrupt register. Bit 5 of the interrupt register can be activated by activating can be hidden by bit 41 of the data word and bits 43-45 can be used to block the activation of bit 9 of the interrupt register. The fourth column indicates on which of the computation modules each of the interruption conditions acts. The presence of the primary energy interruption signal is recognized by all Modules in the system answered, since all take precautions for the operational failure have to. In the event of a real-time interruption, those at her Occurrence affects all computing modules, each one responds individually to their command. Only three of the 14 listed conditions can be recognized while using a computing module operates in interrupt mode A to cause the module to move into the To toggle interrupt operation type B. They are called, "No access to Memory "," Parity Errors and n Illegal Instruction. "The bits of the interrupt register can be listed in any of the columns labeled "Bit Session Type" Kind be set.

In the two columns, namely the "Response control type" and the column "Normal type of answer" contains the respective answers from a computing module listed in each of these modes of operation considering each who operates 14 interruptions. The computing module automatically saves the information which it has just processed after receiving a primary power failure "interrupt signal, ? regardless of its current mode of operation. The answer to a real-time encoder interrupt is the same in the normal and control operation modes as the timer is in both is increased by one.

Figure 6 shows I / O system operation using appropriate ones Interrupt signals to initiate and terminate the operation. A basic one System is shown housing only a single memory module 101, an input / output control module 401 with two I / O submodules or units 401-1 and 401-2 and a computing module 201 is used. A single block, commonly called "connecting devices." 6Q0 "is included to represent a group of peripheral devices. The particular type of device that is used is not relevant to the discussion, as long as at least one of the aforementioned external command interrupt signals is produced.

Each of the two I / O controllers 401-1 and 401-2 is a small one Fixed program computer, the data depending on the 48-bit word commands that Descriptors are called, received, transmitted and reformed. It's fundamental four types of such descriptors exist, each of which has its own distinctive character Bit format and function, i.e.

the set, release, command and result descriptors.

The first three are and will be housed in main memory sent here to one or more of the I / O control modules. The result descriptor content is generated in the I / O control module and sent back to a location in memory, as determined in the control module.

The sequence in which these four descriptors are used is that same for every B / A operation. After receiving an I / O completion interrupt signal the arithmetic module 201 commands the memory module 101, the list of descriptors includes sending a release descriptor to the I / O unit 401-1 or 401-2, which outputs the I / O completion interrupt signal. After that there is a set descriptor auP command for all I / O units in a selected group sent. After that, another release descriptor becomes the selected I / O controller sent. A command descriptor is then sent to the selected unit and Finally, a result descriptor for the unit of the memory module 101.

The arithmetic module 201 initially operates in its N-type of operation (201-N). Upon receipt of an I / O completion interrupt signal from either the I / O control unit 401-1 or 401-2 switches the control module 201 from the N operation type (201-N) to the control operation mode (201-C). In this type of operation, the send Computing modules send an IORL command to the thin film storage module 101 and initiate it, a release descriptor stored therein, to the I / O controllers 401-1 or

401-2 of the selected group to send the completion interrupt sent out. When this is done, the computing module 201-C next sends one Command to memory module 101 and commands it to assign a programming descriptor to all units in the same selected I / O group. The enable-set-enable cycle is not always necessary; after the completion interruption signal, another may Command to be sent to the I / O units. When an order is issued without prior knowledge If a completion interruption is to be sent out, it is recommended that a Release is sent out before a command descriptor is sent out. A setting descriptor is only sent out if the program changes the basic address of the descriptor list want. Thereon Another IORL command follows to take the first step to repeat, Finally, the computing module 201-C commands (IOC) the memory module 101 a command descriptor to the selected I / O control unit 401-1 or 401-2 transferred to. In this 48-bit word instruction descriptor is all of the program information necessary to perform the I / O operation. When the operation is desired as an input operation, the unit acts on a controller and Transfer of the information data from one of the selected input devices of the in the connection devices 600 contained devices to the memory module. In the same way an output operation would be handled except that the information flow in a reverse direction through the peripheral interface 401-10 and the storage connection means 401-12 of the I / O control module 401 takes place.

The bit format of each of the items associated with the E / K operation four descriptors is shown in FIG. The programming descriptor contains in the Bit 17-20 is the address of the selected I / O controller that received the descriptor target. The enable and control descriptors can also be sent to a special I / O unit or to all ten units of a particular group by using the the same four bits 17, 18, 19 and 20 of the 48-bit descriptor word are encoded.

A 4-bit bin address corresponding to this number is then sent to the Bits 17 to 20 are set. When all four bits are one, the descriptor becomes all Control modules or units of a particular I / O module group sent. For every other Combination of bits, the descriptor goes to a special module. The memory address, which is used by the I / O module to retransmit a result descriptor, is contained in the first 11 bits of the programming descriptor word and is called denotes the descriptor base address. This address is in a single 11-bit register stored in each I / O control module and provides the base address of a 32-word list in high-speed main memory known as the descriptor list. Both I / O modules or units in the housing use this address as a basic number to get from this from determining their particular memory address in the descriptor list. This 3 determination is achieved by adding the unit number plus twice to the base number address 1 is added. The storage address for unit 5 is 2 x 5 plus 1 or 11.

All I / O units that have successfully completed a programming descriptor received, confirm this receipt; the units that are not in use become put into operation and return a result descriptor.

The format of the release descriptor is immediately in FIG under the programming descriptor. This descriptor enables the system to change an I / O control unit from the operational state to the idle state.

This change ends the active operation of the I / O base. bit 43 of the descriptor is used to inform the control unit when it end the operation 8011. If bit 43 is a binary one, the I / O control unit displayed to return when the last character of the memory word that is currently is transferred, is completed. When bit 43 is a binary zero, the I / O control unit is running indicated to reply immediately, even if she intends to provide an instantaneous prematurely To end the transfer operation.

A release descriptor with correct parity is held by an idle located control unit is not observed. A release descriptor is provided by a operating unit is only recognized if the unit is recognized by the descriptor specifically addressed or if the operating unit included is when the descriptor is general to all units of a selected group is sent.

The release descriptor, like all other descriptors, becomes individual for the correct parity from all I / O control modules in the selected group controlled. If any of the modules detects incorrect parity, the descriptor is treated like a command or setting descriptor, the one is not has correct parity addressed to all modules, in which case, when one of the devices in the I / O cage is idle, the device becomes one Activates the result descriptor and causes it to be returned to memory will. This descriptor contains status information, which is the parity error indicates. If both units in the marked housing are in operation, the release descriptor disregarded and those in operation Units continue their current tasks.

The I / O control unit that successfully receives a release descriptor thus shows the successful completion of the descriptor transfer by signal delivery to the computer that initiated the operation. This display is not an interruption signal, since an I / O completion interruption never occurs when the I / O operation is through a release descriptor has ended. The display and the interruption are different Signals from the I / O module to the computer.

All I / O control units are set to the operational state when the system is switched on and remains in the operating state until the first successful one Transfer of a release descriptor to this unit.

All operations of the peripheral devices are carried out with a command descriptor initiated. Its format is immediately below the release descriptor in FIG. 7 shown. This descriptor can, for all units of a selected group or sent to a special I / O device.

When sent to a special unit in the group, will the addressed unit can record it, provided that the descriptor is the correct one Has parity and assuming that the unit was the previous peripheral operation has completed.

As in the case of the programming descriptor, the command descriptor addressed to all I / O units in the group if bits 17-20 are all binary 1, i.e. 1111.

When the programmer chooses to address all units in a group and more than one is out of service, all of those will be out of service Units try to carry out the order. All idle units go into the operating state and forward a result descriptor to the memory, when incorrect parity is found in the instruction descriptor.

As indicated in Fig. 7, the instruction descriptor is used to denote the type of peripheral device to be used. Around To simplify the term, these are the types of peripheral devices used by the system are initially classified as simple and complex devices. An easy Device is defined as a device that has a single trunk of an input / output switch needed.

There are two types of simple devices, namely a simple input and a simple output device. In this specification is a peripheral input device defined as a device that receives information for transmission into the system, while an output device is defined as a device that provides information for transmission prepared by the system. An example of the former is a card scanner and an example ür the latter a printer. A complex peripheral Device is a bi-directional device that has more than a multiple line an I / O switch is required. It can be referred to as a pair of simple devices will.

In the instruction descriptor (Fig. 7), bit 45 is used to denote a complex To designate device. If bit 45 is set to a binary 1, it is a complex one Device required to execute the command while if a binary 0 is determined is, a simple device is given. Bits 39-40 of the descriptor word designate the selected peripheral device. Since there are six bits in this group, the total number of possible choices is 64.

Two bits, 37 and 38, of the instruction descriptor are used to the operation of an I / O control unit in its execution of an input operation to redirect. For example, if bit 37 is a binary 1, the I / O control unit will which uses this descriptor does not terminate the operation on a parity error, which is determined during the transfer of information from the connecting device, how she usually does this. She will complete the. Transfer from the Wait for the device before registering the error. If bit 38 is set, wait the control I / O channel that owns this descriptor does not have its turn and gain access to the link buffer stage of the I / O control module housing but it becomes him the priority over his Twin unit in given the same I / O chassis.

Again, if that enclosure is on a storage trunk, which has priority in the memory module, it accesses and the I / O unit wins immediate access to their storage definition. A suggested use for this reversal is given if a channel of an I / O control module with a peripheral device that has an operation speed of 1 MHz and the other channel is connected to a peripheral device that has an operation speed of 100 KHz. It would be desirable for the fast device to take precedence over to have the slow device. During one of both devices in a control module priority can be given, both units cannot be in it at the same time Control operations that require this precedence bit to be set.

The first 12 bits (1-12) of the command descriptor become the word count field called. This field indicates the number of words that will be included in the I / O operation are. A maximum of 4096 words can be specified, and so with a command descriptor be transmitted. Bits 13-16 are referred to as the sentence count field. It contains the number of sentences, up to 16, that an input operation comprises. Where a single Sentence, as indicated by the word count field, up to 4096 Words are transferred. If the example included multiple sentences, each would Sentence contains 256 words, with the possible exception of the first. The 16-bit field includes bits 21-36 and gives the lead-in memory address to be used by the I / O control unit; it is accordingly in of the figure.

Three bits of the command descriptor form the command code that goes with the I / O control units are sent for transmission to the peripheral devices. this are bits 46, 47 and 48. In the case of a simple input device there will be two of the eight possible command codes reserved for the enable and set descriptors and only three of the remaining six instruction codes are used.

These are: 010, 011 and 100. The other three codes (101, 110 and 111), even if they are sent, are evaluated by the device in the same way, as if they were the code 010.

These three command code bits (46-48) are also used to define various Commands to the simple output devices as well as to any complex device to deliver. In both cases there are also the four additional bits of the record count field, namely bits 13, 14, 15 and 16 are available. Bit 46 is from the I / O control module used to notify a complex device that is performing an output operation that the last identifier in the transmission is sent, and that the eight least significant bits of the 12-bit word count field are 0.

The format of the result descriptor is shown in Figure 7 below. It is the only one of the four shown descriptors whose direction of propagation is from to the I / O control unit the memory runs. Its main function is to provide the system with information regarding the status of an I / O operation regards.

Its first 12 bits indicate the number of remaining words, which are to be transferred. The next four bits (13-16) indicate the number of remaining sentences to be read. There are six bits in this descriptor available that the system provides particularly with information about the condition or the Supply the status of an I / O operation. Three of the bits are for the I / O control module and three allocated to the peripheral device. Bits 17 to 19 transmit status information, related to the I / O control module. The following eight codes can be accessed using these three bits are communicated to the SXtem regarding certain status conditions of the I / O control module. They are: Bit 17 18 19 O 0 O A programming descriptor was received correctly from an idle I / O base.

O 0 1 The peripheral device identified by the command descriptor is not available.

0 1 0 The peripheral device operation in progress has been prematurely terminated by a release descriptor that is under program control to transferred to this I / O control unit.

Bit 17 18 19 0 1 1 The word count field that is defined by bits 1-12 in dm Control descriptor is set to 0, it indicates that the designated data transfer has taken place.

10 0 The command to the memory has a time limit of 3.75 microseconds exceeded (5 memory cycles) 1 0 1 An AC power failure occurred.

110 A tag assigned to the I / O base from an input device was transmitted, was received with even parity and bit 37 (parity override) was not set in the command descriptor.

111 Was made in an issue operation or descriptor transfer detected a parity error on the word from memory. For an input operation the word count field has become 0; Bit 37 (parity override) was in the command descriptor is set and the I / O device encountered a parity error in at least one input tag received from the peripheral device.

The remaining three bits 20, 37 and 38 are allocated to one To provide status information relating to the peripheral devices. That Field made up of these three bits and the field made up of the previous ones three status bits are formed are mutually exclusive. If both at the same time are present in the returning descriptor, the system gives the status information the preference that relates to the peripheral device. As a number of different peripheral devices is present, the status information must relate to the particular Obtain device that is being used. A general set of status codes becomes not shown, as was done with bits 17, 18 and 19. To a special one To illustrate this case, the following state pattern can be obtained from an I / O control unit which controls a peripheral card punch device.

Bit 20 37 38 0 1 0 No response to state control 0 1 1 Unit failure 1 0 0 Illegal instruction 1 0 1 Punch error 1 1 0 Data too slow 1 1 1 Parity error The 16-bit address identified by bits 21-36 of the result descriptor their determination gives way Return to main memory. This address is always one greater than the address of the last memory word, that was transferred from memory.

Bits 39-44 of the result descriptor provide the identifying one Number of peripheral device that performed the operation while the bits 45-48 almost invariable copies of the corresponding bits of the instruction descriptor are. There is an exception, namely if the connection unit used is a is a simple input device. In this case the returned descriptor can be different Contains bits to indicate how the operation was initiated.

Figures 8, 9 and 10 each represent external wiring diagrams of the computer, the I / O and the memory modules. In each case is a simplified one A block diagram of the inner part of the module is shown to provide a trace of the signal flow through the module. The computing module 201 (Fig. 8) shows the four main parts of each such module. These are the program processing units 201-40, the arithmetic unit 201-20, the memory control unit 201-30 and the local Thin film storage 201-10. The memory control unit 201-30 routes control information to all memory modules 201-22, and requires that memory information be sent to a special memory location is read from the memory. It also indicates where this information should be sent. The control unit -201-30 performs this operation under the command of the togram processing unit 201-40 by, that carries out the steps of a special program. This processing unit 201-40 is the control unit of the control module 201. It is the only unit that Connects in two directions to all of the remaining three main parts. she can not only information about the thin film storage unit .201-10, the arithmetic Unit 201-20 and the memory control unit 201-30, but it can also command these units to transmit information to them.

Information and control data enter the computing module through the Connections shown above in Fig. 8 are sin, while such data passes the module through the leave lower connections. Input and output connections can be cables from and to all other modules in the data processing system. Storage information enters the computation module via a 49-line cable, that of a group. selected from cables containing one cable from each memory module. Tax data enter through a group of wires that have a control connection from each Memory module included.

Memory information leaves the computation module (Fig. 8) via a single one 49-wire cable that is commonly connected to all memory modules in the system is. Control information is sent from the module in a single 2-wire cable, which is connected together with all memory modules.

Fig. 9 \ is an external wiring diagram showing the wiring of a Input / output control module shows. All such modules have the same connections and only one will be described. The wiring connections of the control module are unique in the system modules in that they are in addition to input and output connections to all memory modules input and output connections to all peripheral devices included in the system. Their connections to all memory modules are shown above Fig. 9, while the peripheral device connections are shown below. The I / O control module 401 shown in Fig. 9 includes two identical I / O controllers 401-1 and 401-2. These units share the common interface switch assembly 401-12, 401-100, 401-101 on the main memory and the peripheral devices. The main memory interface circuitry 401-12 receives information data from main memory through a group of 49-line cables 9-30 and a group of control lines 9-40. With that in mind, this one is Module similar to the computation module shown in FIG. The information return cable 9-20 to memory is similar in that it also contains 49 lines as well the control cable 9-10 with its two return lines.

Referring to the lower part of FIG. 9, the interface contains between an I / O control module and the multitude of peripheral devices the control and data lines necessary to establish the connection between any of the to establish and maintain peripheral devices and one of the two I / O units en. The input interface Switching arrangement 401-101 receives one Multiple cable connection 9-50, which consists of 32 input cables with 12 lines each. Each input cable can enable a simple input device with a I / O unit to connect. The output interface switch assembly 401-100 is connected to a similar plurality of cables 9-60 to a corresponding one Ability to create for any simple output device. Each of the output cables has also 12 lines. There are 5 control and 7 information lines in each cable. Six of the information lines give a sign of information at the same time and the seventh line supplies a parity signal. All input and output cables can can be used by one of the two I / O units 401-1 and 401-2 included in the Module are included. Five control lines are included with each cable that goes into the multiple cable connection 9-50 and 9-60 is included. These are a start / stop line, a character request line, a unit available line, a label evaluation line, a device status line. A complex device requires two cables, one for the input and another one for the output. The input cable number is always around one greater than the number of output cables.

In the memory module 101, with its external wiring diagram As shown in Fig. 1Q, a memory 101-20 is between an input information selector 101-110 and the output information drivers 101-130 are switched. In the voting facility Enter 49-wire cables leading from each of the three compute and each of the ten I / O control modules are coming. A control cable from each also enters the memory module of these other 13 modules. These control cables are from all computing modules and I / O control modules identical.

These cables provide the necessary control information for access to request a special memory module.

Each requirement includes an additional 19 control lines, those on the most significant three bits and the least significant 16 bits of the 49-line information cables available. The three most significant bits designate the operation code to the memory. These codes differ depending on whether they are from an I / O module or a Arithmetic module come. Both modules can have either a read and a write opcode send out. In addition to these two codes, the computation module can issue a command for send out a descriptor to a particular group of I / O control modules should be sent. The least significant 16 bits of the 49-line information cable contain the memory module address and the word address in the module. As each of the Memory module contains 16 384 addresses, 14 of these lines determine the word address 0 The remaining two bits are used to determine the memory module address. A single memory module can only make one request at any given time meet, whereby it makes a priority decision that is necessary in each memory module is. The decision is made by the priority determination circuit 101-142 If there is no consequence int, the access command is preserved (101-150) and the requesting module is thus indicated by one of the output control lines that come from the lower part of Fig.1. The selected word is then used by the Memory 101-120 is transferred and to the requesting module by the memory output drivers 101-130 forwarded in a single simultaneous 49-bit transmission.

Fig. 11 shows the connection between the I / O control modules and the A variety of 64 peripheral devices.

This connection is shown more generally in Fig. 2, where it starts with 500 and in Figure 1 where it is referred to as the input / output switch is. Reference was also made earlier to the central exchange 300 shown taken and it has been featured in the same figures. From each of the 10 I / O control modules 401-410 are identical cable groups to each of the 64 peripheral Devices 600 paired.

Each group of 64 cables is divided into 32 input and 32 output cables. The figure includes only a representative number of these cables and their corresponding ones Devices. Any input cable connected to each of the ten I / A control modules contains a total of 12 lines. Ten of these lines carry information from the Device to the module and are thus signal lines relative to the module as input viewed. The remaining two lines of the input cable transmit information in an opposite direction and has been used by the module for such purposes, e.g. to start or stop the device or to request information from a peripheral input device. Any of the output cables that come with each the output parts of the ten I / O control modules are connected, contains 12 lines. These lines are divided roughly differently. Nine lines of each of the 32 output cables carry information from the I / O control module to the peripheral ones Devices while the remaining three wires of each cable are used, to get information in the opposite direction, i.e. from the devices to the I / O control modules to transfer.

Figure 11 shows that an I / O switch or network has been created is when 32 input and output cables from each of the ten I / O control modules with a Group of 32 peripheral input and 32 output devices is connected.

The creation of such a network does not just enable anyone of the ten I / O control modules, with any of the available peripheral Devices to connect, it also allows a number of such connections is established at the same time.

Fig. 12 is a block diagram of a computation module 201 which is the Function field sr shows. Three such computation modules can be in a maximum system be used.

A fourth computing module can replace the tenth I / O control module be used. The computing modules are housed in individual housings and basically have three function fields, a logic field and a control field arithmetic field and a storage lt. The logic and control field is used to execute instructions, for indexing, for relative and indirect addressing and to Interrupt processing used. The arithmetic field performs arithmetic operations Offsets and comparisons. The control field supplies a local thin film memory, that is easily available and quickly accessible.

Figures 13, 14 and 15 relate individually to the same three function fields of the computing module shown in FIG. Fig. 13 contains the Figures 13A and 13B which together form a complete plan of the thin film storage unit 201-10, while Figs. 14 and 15 each show separate block diagrams of the arithmetic Of the field and the control field.

The computing module works like a changeable 3-address machine, whose program instructions are treated like sequences of syllables. A program word consists of four 12-bit syllables plus a parity bit. There are four different ones possible types of syllables in a program word: the operator, the variant, the address and the index syllable. The operator syllable consists of a 6-bit instruction code and three 2-bit address indicators. The command code indicates which command of the possible 61 the calculator will run. The address indicator shows how many syllables are required are to complete the instruction. The commands can range from one to be seven syllables long. The variant syllable consists of a 12-hit instruction reversal variable. An address syllable consists of 11 bits of a literal address and one bit for an indirect address indicator. The index syllables consist of three fields of four bits each. The address and index syllables can be connected, to effect direct and indirect addressing. An infinite number of levels of indirect addressing is by indexing on the last level possible.

The logic and control field (Fig. 12) contains a program processing unit (PPU) 201-40 and a memory control unit (MCU) 201-30. The circuit arrangement of this Field is used for indexing, indirect addressing, and address calculation and perform other logical operations. The program processing unit (PPU) 201-40 is the central control system of the computing module. All data and program words are handled in this unit before being passed through the lockout switch 300 to the main memory or the arithmetic unit 201-20.

The program processing unit prepared data and instructions. She reads the program from the local thin film memory 201-10, one syllable at a time, calculates the data search address, performs the indexing and starts the artithmetic Kinheit 201-20 or the memory control unit 201-30 (MOU). They then processed the next syllable while the other units perform their functions. These Ability to process successive program syllables at the same time is a special characteristic of the machine, known as "program overlap". This is done during the operation of the arithmetic unit 201-20 (or the memory control unit 201-30), at what time the PPU processes the next program word, the memory or branch address calculated and begins the next instruction for the arithmetic unit. It follows that the time that required for the program pick-up can be regarded as negligible.

Includes PPU 201-40. the mask register and the memory edge register, which are used together with the Lada special register (LSR) instruction. In no other program is accessible.

The PPU waits for all program interruptions by storing them all pertinent control information in thin film registers of the thin film memory 201-10 upon receipt of an interrupt status signal. The information is required to re-save the program up to the point of interruption later. she then control branches to an interrupt routine and sets the interrupt register selectively zurück0 The memory control unit (MCU) 201-30 is controlled by the program processing unit (PPU) used The storage control unit 201-30 establishes control and waits access to main memory if it is set with an address from the PPU. After it has gained access, it enters the resulting data into the W register of the 3PUO The PPU then brings the data into the arithmetic unit processing (or in the program control register (PSR) in the local thin-film memory 201-10, in the case of a program branching or program overlapping).

In the case of a main memory control operation, the memory control unit controls 201-30 the received. Address to determine if it is within the given Border lies. It then waits for the resulting data word of the arithmetic Unit before access to the main memory and the transfer of data. When a Access to a memory module is requested but not granted after An interrupt condition is created for 10 milliseconds and the command is terminated.

The edge registers X and Y are the only parts of the MCU that are program accessible are.

The arithmetic field of the arithmetic module shown in Fig. 12 exists from an arithmetic unit 201-20.

This unit contains the three arithmetic working registers A, B and C and their associated controls. Registers A and B carry the actual ones arithmetic calculations. All of these three registers are called shift registers used for fixed and floating point operations. The arithmetic unit registers are not accessible to the program.

The thin-film storage field of the computing module has a magnetic one Thin film storage unit 201-10. This local thin film storage unit consists of 128 thin film 50-bit registers. As shown, it works in conjunction with the program processing unit 201-40 to provide a high-speed storage facility that keeps track of the numbers of data accesses to the main memory modules.

Fig. 13 shows that all 128 thin film registers by an octal code number (E.g. 057) can be addressed. You can also use a name (Indxreg 10) or by a group of uppercase letters acting as a thin film address identifier is known (e.g., PCR identifies thin film register address 057). The thin film list thus identifies the thin film registers and register groups by numbers as well like by a name.

Five operand registers are the four contained in the thin film field Stack registers having octalkedec numbers 104, 144, 150, and 154, and the thin film C (TFC) register with the octal code number 124. The TFC register holds the least significant part of the data for an instruction with double length (DDV), a sliding partial instruction (FDV) and a double-length shift instruction (SHF). It also saves the least significant half of a product with twice the length of a multiplication operation and the remainder of a division operation and the result of the shift instruction double length.

The two program memory registers (PSR1 and PSR2) that contain the octal numbers 100 and 104, store eight instruction syllables and allow one to overlap Instructions pick-up during long commands.

The base address register (BAR) at 055 contains the base address of the data address field. The base program register (BRP) at 034 contains the base address of the two program address field. The program counter register (PCR) at 057 holds the address of the last value (the shortly before the memory was fetched) in the program control registers.

15 index registers and 19 comparison limit registers are with the rst 30 octal code numbers (000 to 037) in local memory in each index address syllable and can be used to modify any operand address. The index registers can be increased, decreased and in six different ways will compare the limit registers. The index increment register (XIR) is used by of the logic used during the execution of the index increase instruction. Index register 0 and limit register 0 are special registers that are used in comparison operations will. Both always contain 0. Information can be stored in limit register 0 but it always contains 0 when performing comparison operations. Information can be stored in a different way in limit register O at octal digit 020 but never in index register O at position 000.

The 24-bit content of the real-time encoder (BTC) register at position 114 is read out automatically and increased once every 10 milliseconds. The real-time encoder can be checked and set by the program. An interruption is initiated if an overflow count occurs when the mask bit is set.

The character count register (CCR) at location 123 is used by the character searcher (CSE) instruction used to change the character position that was last specified for the Character has been checked.

If a repeat instruction is used, the repeat program register takes care of it elsewhere 041 (BPR) for a storage of four syllables of the program word, the is repeated; the repeat counting register (RCR) contains at position 120 the Number of itarations that still have to be executed while the repetition increment register (RIR) at location 130 contains the increment that corresponds to the addresses that in the three repeat address registers (RAR) at positions 144-, 143 and 146 of the Repeat instruction are included.

The subroutine base address register (SS) at position 060 contains the base address of a list of subroutine addresses. When a subroutine is executed the subroutine storage registers (SSR, SSA, SSP, SSC) hold subroutine information, i.e. the previous contents of the BAR, BTR and PCR. The interrupt program register (IPR) at the.

Position 110 ensures that the last PSR addressed is stored during the interruption, whereas the interruption release register (IDR) is on the location 070 holds the PSR and retry controls for the interrupt return. The power failure discard register (PDR) on the Stolle 064 holds the contents of the control flip-flop and the flop of the interrupt register in the event of a power failure.

The program field from which the last branch was made is contained in a register (BRR). The effective address registers BAR 1 and EAR 2 preserve the history of all memory addresses (with the exception of Wioderhel operation ),until a storage connection error is made.

They remain unchanged until this error condition is corrected.

The interruption system handles interrupts, those of such Conditions arise as arithmetic overflow, real-time encoder overflow, Invalid instruction, parity number, external input / output request and Input / output result states. Each computation module has an interrupt register, which is set by the interrupt mask register. If a special condition a binary 1 has caused it to be placed in any bit in the interrupt register an interrupt routine occurs. This interruption stops the program being executed stores sufficient inertia in the thin film registers, to allow the interrupted program to be continued at a later point in time, and transfers control to a single program to correct the error. If an error occurs during the control operation mode, the control will issue a Transfer another one-time program to fix the error. The return duroh the Interrupt Return (IRR) instruction is always to the initial normal operation mode. The unused thin film registers that are included in the plan of FIG. 13 of this local Memory contained are for use by the execution control program reserved.

FIG. 14 relates to the arithmetic field shown in FIG and provides a block diagram of the arithmetic unit contained therein 201-20. A portion of the transmission trunk line 201-50 of Figure 12 is in the left Part of Fig. 14 shown. The arithmetic unit contains the three arithmetic units Working register of the computing module together with the associated controls. There are this is the A register 201-20-16, the B register 201-20-12 and the register 201-20-10. The A and B registers 201-20-16 and 201-20-12 hold the actual arithmetic Operations through and all three are used as shift registers for fixed operations and used for floating point operations.

The adder 201-20-14 included in this arithmetic unit is able to add two 48-bit numbers in a single cycle time. Since the system works with a clock speed of 4 NHz, a full Su-ie received in 250 nsec. This Su-e is then entered into the A register 201-20-16 and arranged according to the type of instruction. A full 48-bit shift is also in a clock time just like a 48-bit transfer from a register carried out to another. This leads to a significantly reduced execution time for the respective repeat instructions, such as multiply and divide.

A characteristic of this arithmetic unit is its ability to do that Put the word in the correct position in the A register. This setting up of the word is made by shifting the result to the left or to the right achieved by transferring it to logic switch 201-20-18. The logical one Switch comprises a large number of switch positions that can be changed, so that any quantity of information can be switched, whereby he is able to is put to toggle each value of the logical information contained in a single Cycle time is desired. Register D 201-20-22 in turn provides the necessary shift information to R and L decoders 201-20-24, which decode the shift information, and causes accordingly that the information contained in the logical switch 201-20-18 is oriented in the appropriate manner.

The S-Register 201-20-26 contains the variant syllable that contains the Shift information accompanies and controls the type of shift: right or left, end-away or end-around, arithmetic or logical, single or double are executed. A single shift is performed on a 48-3it word. The double shift is performed on two 48-bit words, whichever is the least significant Part in the TFC register is contained in the local thin film.

A shift is also used in the instructions that normalize Need to become. A non-standardized result an arithmetic The instruction is the command CBF (recoding from binary to floating point). These instructions cause the 48-bit word to shift left and set the exponent will. - This process is known as Adjustment 201-20-20 and continues until a binary 1 is present at the most significant digit of the mantissa.

The character selector 201-20-30 and the field shift decoder 201-20-28 answer signals of the S register 201-20-26. The output of the character dialer is placed on the A, B and C registers to enable them to be selective indicate one of the characters contained in each of these working registers.

The field shift decoder puts its output on the D register 201-20-22 to assign a move operation similar to the above positioning operation cause, with the exception that the shift that is to be achieved acts on an information field instead of on a particular bit. The field can be a Be a multiple of 6 to a maximum of 48 bits.

In the right part of Fig. 14 is the clock distributor 201-20-50, the arithmetic unit is assigned, together with a general block diagram shown showing the path of the clock control signals used in this operation will shows. The program processing unit 201-40 is shown to have activated the clock distributor and at the same time di. Data processing control device 201-20-52 of this introduction. These Control device in turn, causes a group of subroutines to be issued. The F register 201-40-24 (Fig. 15 in the PPU part of the drawing) is also called the 6-bit K register 201-20-56 shown activating to cause the instruction decoders 201-20-54 to of the data processing control device 201-20-52 of the during this clock sequence to report the instruction to be executed.

Fig. 15 shows the logic and control field of the computing module.

This field contains the program processing unit (PPU) and memory control unit (MCU).

The thin-film storage area 201-10 is also shown to its To specify the relationship to the PPU of the module. Since the program processing unit uses the central control system is the computing module, it is used to run the program to read, to start the arithmetic and memory control unit and to start the thin film memory part of the module to be addressed and activated. The 50-bit information drivers 201-40-18 in the PPU are determined by the content of the 48-bit W register or the 16-bit M register activated to the 48 information lines of the local thin film memory during to drive a write operation. The remaining two bits are used by the Parity generator driven by the W register or the M register. The 48-bit word is taken as two separate 24-bit registers for parity generation. the first 24 bits that always come from the W register and the W and M registers another one assigned to them Parity bit. Both bits are generated to make the overall parity odd.

Alternatively, the 50-bit R register 201-40-20 receives the 50-bit output of local memory when performing a read operation. During one Read, the 50-bit R register is checked to ensure that the Overall parity is odd. When an error is detected, i.e. even partition one of the two halves will be the central clock in the computer and the processing stopped. The address of the thin film and the content of this register are displayed. The output information of the R register is returned to the information drivers, to perform the regenerative rewriting operation required for this species of memory is required. A multiplexer 201-40-22 operates to to create a simultaneous transmission path for several functions.

It receives the output information of the R register as well as the W register, the adder 201-40-42 and the index multiplexing device 201-40-30, the necessary indexing of the tax information and the necessary additional changes to be carried out in control instructions.

The output information of the multiplex device 201-40-22 is with connected to a number of registers which carry out the necessary decoding and encoding operations perform for the multiple functions in the singular content of the multiplex device are included. The F register 201-40-24 is a 12-bit register that contains the function information receives, which is contained in the multiplex device. This information is decoded (201-40-28) to identify the function and will access the necessary control devices coupled for the data processing control and its accompanying address calculation control 201-40-32 are included. The N register 201-40-26 is another 12-bit register, which is connected to receive the output information of the multiplex device and that provides information that needs to be encoded.

The interrupt register 201-40-12 and its mask register 201-40-10 also operate to provide information that needs to be encoded. The interrupt encoder 201-40-13 provides such information, which is appropriately indexed (201-40-30) must be multiplexed before going to the thin film address encoder 201-40-34 is given to form an address in the local thin film memory. This address is then stored in the address register 201-40-36 for subsequent addressing given to the memory location in the thin film memory that is to be activated.

The 16-bit M register 201-40-38 is also associated with the multiplexer connected to receive information requiring mathematical treatment. It receives information that needs to be sent to adder 201-40-42 where it is combined with the content of the E register 201-40-40. She also receives Information from the multiplexing device which is sent to the register of the arithmetic Unit must be sent to provide the information for some shifting function to deliver that is to be executed.

The input control information for the arithmetic module is placed in the 48-bit W register 201-40-16 as well as the input data of the memory module. The save data is coming first in several receivers 201-40-14, which are able to receive 49 bits of such data to treat.

In a similar way, the data then pass through a mathematical Treatment in the arithmetic unit must or must be subjected to the W register via the internal transmission trunk line 201-50 of the computing module.

The memory control unit (MCU) handles the control and transmission assignments, given by the program processing unit. This unit 201-30 is contained in the lower right part of FIG. 15 in dashed lines. It contains and controls the 51-bit line drivers 201-30-18, the address and data to the memory modules transfer. It also contains the memory clock device 201-30-10, which does the synchronization between the memory module and the computing module connected to it. All sub-commands that affect this transfer are handled by this memory clock 201-30-10 issued and controlled.

The 19iBit-G register 201-30-12 receives and contains information to be conveyed to the line drivers 201-30-18 after having undergone address handling has been subjected to the program control unit (PPU) by the adder 201-40-42. In addition to the addressing information, it also receives switching commands from the adder, indicating the function to be performed and data information of the W register. Parity information, which is dependent on the parity generator 201-30-14 is created by an enable signal from the W register also becomes the Sent to line drivers.

A pair of 8-bit registers, labeled separately as X and Register and are denoted together with 20-30-16, form the control device the address to see if it is within set limits. this is reached by a comparator 201-30-20 which compares the address that searched from the content of the G register with the upper and lower address limits contained in the 8-bit registers 201-30-16.

The representations in Figures 13, 14 and 15 are considered a complete Representation of the computing module viewed, and they are all mentioned. The registers in the local thin-film memory are described by using "identifiers", i.e. BAR, BPR etc.

After an interrupt condition occurs, the computing module must detect the interruption as soon as possible and process. Each interrupt condition sets a special bit in the interrupt register 201-40-12.

When the instruction being carried out (when the interruption occurs), is completed, the computing module confirms the interruption status Entry into the control operation mode. The transition from the normal type of operation becomes the control operation mode by receiving a signal from the control flip-flop (ITE) triggered. The detection of an interruption condition triggers a sequence, the steps of which are described in the following sections.

The contents of the thin film storage registers BAR, BPR and POR are respectively stored in the ISA, ISP and ISC. The value stored by the PCR is the address of the program word that will be used after returning to the normal type of operation should be executed, or by one less than the word to be executed; therefore depends the execution of the interrupted program depends on the syllable at the time the interruption is being processed. If an overlap has occurred, it is the address in the PCR has been automatically corrected.

The contents of the appropriate program storage registers PSR1 and PSR2 is stored in the Interrupt Program Register (IPR). The content of the control flip-flops, which is necessary to restore the operation on the correct syllable in the program is recorded in the least significant 16 bits of the IDR (Interrupt Discharge Register) saved. The characteristic that each bit of the IDR receives is listed in the following paragraphs.

Bit 1, 2 and 3: These bits give the address of the next PSR syllable at. This is an operational syllable, as the transition to control mode is only at the end the instruction can occur. The syllables in PSR1 are from the most significant ending of the register numbered 3-2-1-0; the syllables in PSR2 are similar numbered 7-6-5-4.

Bit 4: If this bit is one, a repeated instruction has been made interrupted.

Bit 5: If this bit is one, a repeated instruction has been made interrupted before executing the first iteration.

Bit 6t A one in this position indicates that the PSR1 still has information after executing the last instruction before processing the interrupt became. If bits 6 and 7 are both one due to an overlap fill, one of these bits will be reset when it is saved because of an overlap is lost after returning to normal mode of operation.

Bit 72 A one here indicates that the PSR1 still needs information Includes execution of the last instruction before processing the interrupt became. If bits 6 and 7 are both one due to an overlap fill, will one of these bits is reset when it is saved because of the overlap will be lost.

Bit 8: A one in this bit position indicates that the POV (overflow) flip-flop is set and its corresponding indicator is illuminated.

Bit 9: A one here indicates that the PUN (underflow) flip-flop is set. and illuminates its corresponding indicator.

Bit 10: A one at this point indicates that the PNN (non-standardized) flip-flop is set and its indicator is lit.

Bits 11 and 12s These bits relate to the content of the batch counter and indicate which register of the stack is on top: 0,1,2 or 3 (respectively corresponding positions 1 to 4).

Bit 13: A one here indicates that the memory module is in control operation mode operated.

Bit 14s A one here indicates that the current interruption condition is a primary power failure.

Bit 15s A one at this point indicates an inverse ~ operation of the Batch counter.

Bit 16s A one here indicates that the memory module in the Control operation type B operated.

The control operation mode flip-flop is set to transition to the Indicate control operation type, this allows the use of certain instructions, which are not available when operating in the normal type of operation and temporarily prevents other interruption conditions from being processed with the exception of two interruptions with the highest priority: primary power failure and counting hole timer.

The contents of the IAR (Interrupt Address Register) are stored in the BAR and BPR entered. The IAR can only be loaded in the control operation mode and contains the base address of a table of 12 data words, which are the start addresses Specify the programs that type the 12 interruption conditions. this table is set up by the programmer in such a way that every interruption condition by the appropriate program is being maintained. The programmer is responsible for ensuring that these maintenance programs are written, except when the program is under control an execution program should run. Interrupt maintenance programs are similar a group of subroutines, each of which performs a series of operations, to either (a) b @ time the reason for the interrupt condition and bypass it, or (b) bridge the portion of the program that was interrupted, or (c) that Restart the program and try to repeat the suspected faulty part, or (d) express an identification of the interruption and halt.

The memory address of the first digit of the interrupt maintenance program for a special. The interruption condition is created by adding the number of interruptions from the table (Fig. 5) plus 1 to the contents of the interrupt base address register (IAR) calculated.

The bit in interrupt register 201-40-12 that corresponds to the interrupt condition to be processed is reset 0 The POV, PUN, PNN and all other necessary control flip-flops are reset so that the control operation program, running can use them without first being reset have to.

If the interruption is caused by a faulty condition such as 3. POV, PUN or PNN, these flip-flops are causing the interruption cause, not reset. The content of the other is saved and they are reset so that they can be re-stored when the IRR instruction is executed. These flip-flops that are associated with the conditions that cause the interruption cause are reset when the IRR instruction is executed, when they have not been previously reset.

The activity of the control program as a function of an interruption therefore usually occurs (unlike the first two interruptions, the are given in Fig. 3) in the form of a maintenance program, which the necessary activities directs that must be carried out. These maintenance programs are in a table housed in the main memory modules and each of the listed Interruption conditions is assigned to one of the programs that is part of a corresponding special address is arranged in the stored list.

When no program activity in response to an interrupt signal is necessary, an IRR instruction can be coded at this point in the table. The following table shows typical activities for the maintenance of the specified Interruptions are used, primary power failure (PFF) restart any Input / output operation affected by a power failure External Requirements (EXR) External requirements maintenance for the computer to observe Dingabe / Ausgabe-Besndigung (IOT) Test of the state in the result descriptor for the appropriate Completion of an input / output operation Computer interruption (INTC) See in the activity table according to the task to be performed Real-time encoder overflow (RTC) Performing an operation when a prescribed time interval has elapsed is overriding the limits (WOB) attempt to determine why the effective Address outside of memory limits Illegal instruction (ILIN) startup an input / output operation if an unused numeric code causes an interruption causes No Access to Memory (NOAM) Trying to discover why a Operand address sioh to a memory location not in d.

the system refers to anermales requirement (ABCN) correction of the data value due to overflow or

Underflow Halt (HLT) Perform a type of control operation such as E.g.

Change of memory limits Blunt bit (SNAG) implementation a program activity when there is a lockout from the memory word or table occurs parity error (PER) regeneration of the data risk an error in the memory word The execution of an instruction containing the external memory request (SER) instruction is called, causes the contents of the interrupt register 201-40-12 is stored in bits 21-32 of the SER instruction storage address. This indicates the interrupt signals waiting to be processed.

The four Figures 16A, 16B, 16C and 16D are connected (Figure 16) to collectively, a detailed block diagram of a complete input / output control module housing to show that two completely separate I / O control units (No. 1 and No. 2) or channels. In this explanation, a module means a housing and these terms are used interchangeably. Each of the two binary units in a module is also referred to as a channel module or a submodule. In the previous description 6, the I / O control module housings 401 have been described and the channels or Units were designated 401-1 and 401-2. Di. peripheral interface and the memory connector parts of the module were identified with 401-10 and 401-12, respectively designated. These basic characters are used in this description of the I / O control module housing with additional reference switch parts which are appended for a description of the additional details shown in FIG.

As all of the ten I / O control module housings are disclosed in the present System are identical, it is only necessary to describe a single housing0 Each housing allows input / output operations to be carried out simultaneously with data processing to execute. Bie also controls the transition and format of the data between the peripheral devices and the main memory modules. Input / output activities become initiated by the control module, but the operation is once initiated is under the control of the I / O control module. After the data transfer has been completed all devices automatically return to a state of readiness for new requirements and inform the execution program of the system interruption the completion of the input / output operation.

The connection between system memory and each of the I / O control modules is maintained by the memory connection portion of the I / O module shown in Fig. 16 is shown above. This module part is generally divided into two I / O units, as well as the peripheral device intarface part shown in the lower part of the figure is. Since both control units are able to operate in both directions ind, each description of the signal flow path through the module must be given by a special one Operation, i.e. an input or output operation. One Output operation involves transitioning memory information data in 48-bit sections or Words through the central switch to intermediate connection register 401-12-18 of the I / O control module.

From here they become TO the unit's information register 401-2-12 No. 2 sent in both cases, the 48-bit word is sent afterwards in a serial sequence of 6-bit character segments to a peripheral output device under the control of the Transfer device0 Conversely, an input operation occurs when these characters the information sequentially from a peripheral input device to a 48-bit word put together in one of the information registers 401-1-12 of one or the other of the I / O controllers and then to the intermediate connection register 401-12-18 for transmission on the central switch lines to a special be sent to a ren storage location. Since both operations started in the same way i.e. through a descriptor transition from system memory to an I / O module under the orders of an arithmetic module, all operations are performed in the same way initiated and therefore follow the same pattern.

All input / output unit operations are dependent on an r m / A instruction initiated by a computing module that is in the A control operation mode works0 This instruction is called "Transfer of a descriptor to the I / O -" (TIO) designated. This results in the following: The computing module requests access to a Memory module. If granted, the transfer of the contents of the memory word location will be (a descriptor) to the I / O control unit causes the in the command code that accompanies the memory request. The introductory word arrives into the scriptor register 401-1-Z6 via the intermediate connection register 401-12-18.

Entry into the generally shared intermediate connection register is achieved by a selective gate control device shown in FIG. 16 as a one-way entry device 401-12-16. By selectively gating information into the Intermediate connection register 401-12-18.

allows single side entry device 401-12-t6 that the Intermediate register accepts the information that comes from the memory when a Output operation is specified, or that it is a character compound word from one of the information registers 401-1-12, 401-2-12 when an input operation is specified. The storage information data stored in the intermediate register 401-12-18 enter from single-sided input device 401-12-16 during an output operation, in turn become one or the other of the information registers 401-1-12 or 401-2-12 transferred. If the transfer from memory includes control data, i. a descriptter, then the transition from the intermediate register takes place za or the other of the descriptor registers 401-1-26, 401-2-26, regardless of whether it is an input or an output operation.

Data that enter the intermediate register, be it that it is infermation data or tax data related to the Memory to be returned, i.e., input information data or result descriptors, do not just lay a different one Because of leaving the intermediate register, but will be just as different treated The different path that is covered runs from the intermediate register to a group of line drivers. One set of such drivers includes 401-12-38 a total of 29 line drivers, while a second group 401-12-32 19 such drivers contains. A parity driver 401-12-36 is also included and comes with a Parity signal supplied by parity generator 401-12-34 during the drivers 401-12-38 receive their data directly from the dual register, this is the case with the 19 line drivers 401-12-32 not the case 16 of these drivers are from a second selective pilot control device, which also includes binary page inputs 401-12-26 while the remaining three drivers are called by a read / write switch 401-12-30, which indicates the operation performed by the controller which is assigned to each unit (No. 1 and No. 2).

These 16 line drivers are obtained from single-ended inputs 401-12-26 alternately supplied with information and control data. The one-sided input 401-12-26 can selectively receive information on all 16 drivers from intermediate register 401-12-18 steer. This happens when the 16-bit memory address is in the 48-bit content of the Intermediate memory register 401-12-18 is included. Information, diodes 11-bit contents of descriptor base address register 401-12-20 and the five Connects bits that identify the peripheral device that requires setting or release maintenance 401-12-22 can also be delivered to these 16 cable drivers The instructions contained in the descriptor word contained in each of the descriptor registers 401-1-26 and 401-2-26 are only indicated symbolically in Fig. 16, as they are in the previous part of the description dealing with the types of descriptors and their functions have been explained in more detail0 Contains the descriptor word the serial number of the peripheral device, the operation code of the external device, the number of records to be processed, the memory location that is used and the I / O operation status field. The descriptor decoding facility 401-1-28 and an appropriate logic controller 401-1-36 are in the descriptor register assigned, as well as the instruction register in the control module previously described. The peripheral device to be used for this operation is determined by the Device line pair selector 401-1-30 as a function of the 5-bit identification signal of the descriptor register 401-1-26 is selected. Status information ESL from the peripheral Input and output devices enter the unit through the LRX receiver mixer 401-1-32, as well as information from both types of devices regarding availability (UA) concern the unit.

Since the unit must determine this information of the devices, are means required to give certain control signals the characters sent to such devices For peripheral input devices, this control is from the mixer 401-1-34 carried out, while the mixer 401-1-22 for the output devices Need met.

The I / O control module is connected to the terminal equipment (a peripheral Device) through an input and output interface circuit. This output interface circuit consists of several mixers / drivers 401-10-1, which are the decoding, mixing and driver elements for all lines from the I / O module to the peripheral devices. These Output circuit also requires a receiver for the character request signal of the Device, The input interface circuit does not only consist of several receivers 401-10-2, but also requires an input driver 401-10-8 and an input selector 401-10-6. These input signals are multiplexed into the I / O controllers transmitted through the receiver mixer 401-10-2, where it is selectively transmitted by the data mixer 401-10-4 and then into the 2-character intermediate register for the appropriate control character 1 can be controlled.

This 2-character intermediate register 401-1-10 is in an additional 2-character register, which is coupled with the information agister to provide intermediate storage for to supply the last two characters of the 8-character value. The 2-character regiser 401-1-10 operates during an output operation as follows: If the sixth character of the Register has been transferred, a parallel Transfer of the seventh and eighth characters to the 2-character intermediate register causes. At this point is the information register for the next word transfer available from intermediate link registers 401-12-18 even if the seventh and eighth characters after it has not been transmitted to the peripheral devices. Every I / O control unit has the ability to overlap operations between the Information that is being transmitted and the information that is currently in use to accomplish.

This 2-character intermediate register also operates during an input sequence. In this way, os9 operates the first two characters of the next one after the other Suppose word that was transmitted from the peripheral device during the time period in which the previously put together. Word in the information register the intermediate link register is moved to main memory. During this Period of time, the I / O unit performs two functions at the same time to avoid the overlap of operations to accomplish.

The input / output device interface parts shown in the lower part of the 16 each contain a connecting cable having 224 leads and dls data is denoted. This compound consists of 32 groups of seven Lines that each supply the 6-bit characters and the one parity bit. Each 7-line group together with one 5-line group of control lines forms a separate cable. The signals on these lines are now described, since they refer to the three basic types of peripheral devices, namely the simple input, the simple output, and the complex peripheral.

The simple input device delivers di. the following ten output signals. Although they are specified as the output signals of the device, they are input signals for the I / O base of Fig. 16. In the previous description, these were Signals given directly with reference to the device itself. In the following These signals are described immediately below in the description of each peripheral device With reference to the device itself.

le unit available (UA) A binary 1-level signal on this line indicates that the device is able to transmit information and that sio is not connected to any I / O device.

The device transmits a 0 level whenever it is not transmitting any data can or within 1.0 microseconds of the I / O base attempting a Operation with either the read start / stop or read character request lines wants to initiate that come from the input mixed drivers 401-10-8.

2. Character evaluation (CS) The occurrence of a 1-rule signal from A simple peripheral input device is a command for an I / O device, the data lines query for a data character. This signal (CS) enters the I / O base through the LR-X receiver / mixer 401-1-32, the evaluation character does not allow data to be entered into the I / O base. The input device generates a character evaluation signal like this as soon as possible after receiving a 1-level signal on the read start / stop signal line. The device then generates a character evaluation signal as soon as possible after receipt of 1 level on the character request line O The character evaluation signal becomes held at the 1 level for a minimum of 9.39 microseconds on the I / O base. If it is at the 0 level, this becomes a minimum of 0.39 microseconds at the I / O base held. The maximum repetition frequency of the evaluation signal is 0.75 mega-pulses per Seconds 3. Data (7 lines in total, 6 data, 1 parity) The input device generates 7 data output signals, 6 of which represent the character, and the 7th becomes generated to make the overall parity odd. Data signals are at the beginning of the binary 1-level of the character evaluation signal is present, they remain for a minimum of 0.75 Microseconds thereafter for an I / O unit with high priority and a minimum of 1.10 microseconds for the other unit in the module housing. Data signals can be any time after to the Transition of the read start / stop signal from the 0 to the 1 level and then after receiving a drawing request signal within the time limit which is prescribed for the character evaluation signal 0 The data lines are numbered from 1 to 7 *, where 1 is the most significant data bit and 7 is the parity bit is.

4. Status The status signal is functionally identical to the line evaluation signal. The presence of either the status signal or the character evaluation signal indicates indicates that there are valid signal levels on the data lines. The timings which are given for the character evaluation signal apply in the same way to the Status evaluation signalO If the status signal is at the 1 level, the contain Data lines carrying information to the I / O base from a simple input device conduct a special status code that indicates the occurrence of a valid operation indicates. The status signal levels appear on the data lines at the beginning of the 1 level on the status line.

They stay there for a minimum of 1.1 microseconds for either of the two I / O units. The clock control for the status signal level assumes that the peripheral devices do not have their character evaluation and status evaluation signals at the same time produce. The signals are considered to be simultaneous when the leading edges of the two pulses are not separated by more than 0.38 microseconds0 the The following status codes are used by the peripheral devices of this system used. These codes appear on 7 data lines No. 1 and No. 2, as further shown and set below.

Status code signals on data lines 123-456-7 KOC to 000 to 1: This state is used by a simple input device that has a 1 level on its character request line and an O-P gel on its read start line detects to determine whether the device is performing a read or start operation target. For a read operation, the I / O binary becomes within 2.67 microseconds respond with a 1 level on the Les - Start line and the descriptor command code field, Set bits 46-48 through 101. If the simple input device does not have a 1 level on the Receives read start line within 2.67 microseconds, it becomes a completion state to the I / O base and perform the specified control operation.

XOO-OOO-Xs This status code is used by an input device that transmits data to cause the I / O unit to transmit a subword of at least to store a character in memory. The multi-valued character positions of the partial word will contain extinguishing teeth (all 1). if the I / O unit that last word processed, receipt of this status will cause the I / O unit to store the partial word in memory and then with the word end status (011-000) conclude in the status register.

X01-000-X: This status code is used by the input device to disable a partial word sent to the I / O base. if If the I / O unit detects this condition, it puts delete characters in its Data intermediate register and resets its character counter.

X10-000-X: This status code causes the I / O unit to read the word and address fields of the descriptor to be counted in reverse order.

X11-000-X: This state has the same effect; he will obtained by successive transmission of the two previous status codes.

XOO-001-X: This state is used by a device that uses sentence-wise reads to query the record count field in the I / O base. After receiving this status code signal the I / O unit will be like a 'word of at least one character in memory save as described above, reset the character counter to 0 and the sentence counter to decrease. When the I / O unit has processed the last word or when the status caused the record counter to go to 0, the I / O unit ends with diq operation with a set condition (000-001) in the status field.

X00-X1X-X, 000-1XX-X: These status codes are used by the device to indicate an error or an end-of-operation condition, and are called exit state conditions designated. The interpretation of this code is unique for each device. In all cases the I / O unit with leading delete characters will delete the contents of its intermediate data register transferred to the memory and the operation with codes from the device data lines 4, 5 and 6 set in the result descriptor status field (bits 20, 37 and 38), finish, The simple input device takes the following as input signals two output signals from the input mixer / writer 401-10-8. The two lines, that carry these signals are also identified by their designation abbreviations 1. Read start / stop (RSS) s The signal transition from 0 to 1 level on this line shall indicate that the input device has been connected to the I / O base and that the I / O base is ready to accept the first character0 The transition to the 1-level will only occur at the beginning of the operation if the device has a 1-level on its Unit Available (UA) line. The transition to the 1-Pogel will depend on the read start line within 2.67 microseconds from the status code signal X00-000X. This signal transition from 1 to 0 level indicates that the input device has been disconnected from the I / O base 0 This transition always occurs when a status code is inserted in the status field.

2. Bookmark Request (RCR) The signal transition to the 1 level indicates that the device is querying the I / O unit with the status code signal X00-00X should to determine if the requested input operation is a read operation or is a control operation.

If the requested operation is a read operation, the I / O device returns a 1 level on the read start / stop line within 2.67 microseconds. Data transfer then takes place 0 If the I / O unit does not have a 1 level the read start / stop line transmits within 2.67 microseconds becomes a Control operation performed 0 The device must then transmit a completion status code, to confirm the instruction. Realization exhausts the simple binary Coding options for the two lines, the information from the I / O unit the input device for device instruction changes.

If the signal level on the read start line is already on the binary 1 level when the character request line level is shifted shows this indicates that the I / O base has received a character one after the other and is ready to accept the next character. When the data transfer, as from the word count of the second command descriptor prescribed by the transmission of a character is complete, the I / O base confirms the successful transfer of the character with a 1 level on the character request line, but terminates the operation only if the bookmark request signal in the I / O base for a minimum of 0.333 Microseconds is held. The normal answer of the Character request signal is on the input device for devices that have a high priority with the I / O unit of the I / O control module with less than 15 m of cable in 0.49 microseconds after the 0- occur on the 1-transition of the character evaluation line at the input device. The devices, those with the remaining unit or the unit with lower priority with less than 15 m of cable are connected, the normal response of the sign request occurs ignals on the input device in 0.49 to 1.67 microseconds after the 0 to 1 transition the character evaluation line on the input device. The I / O base holds a 1 pagel on the character request line until the transition to the 0 level on the character evaluation line upright. The answer to the character evaluation signal with a 0 to 1 transition of the Character evaluation line of the I / O unit takes place in a not defined time. That The device is therefore prepared to wait for this answer. The input device is used the draw request signal as an indication that the I / O device is the character has accepted and to transmit the next character evaluation signal.

The signal transition of the drawing request line to the 1 level occurs as a function of a non-compliant status signal to 0 This signal occurs when the character request line is at the 0 level. The normal answer the request line to a non-completion status signal occurs on the input device for devices that use either I / O units with less than 15 m of cable are connected. It occurs in 0.49 to 1.67 microseconds after the 0 to 1 transition the character evaluation line on the input device.

Similarly, there are 32 cables that make up the peripheral output devices connect to the output interface part of each I / O control module, from the same Variety of lines that are able to transmit identical signals between them respectively. The following description applies to each of these signals and theirs Relationship to a peripheral output device.

To start a peripheral output device, the I / O base must a 1 level must be present on the unit-available line from the device comes. The I / O module begins the operation by transmitting an instruction character to the connecting device via the 7 data lines that lead to the device. At the same Time she requests a word from memory. The peripheral output device answers to the transmission of the instruction symbol by changing the binary signal on its device-available line from 1 to 0. If the I / O device is the first Word receives from memory, the I / O base becomes the output device with a 1 level signal on the write start / stop line, the I / O module continues with the transfer of the instruction line6 via -di. Data bit lines up to a receipt of a 1 level on the data request line from the device. As soon as a draw request signal is received, the I / O unit puts a data character on the data lines and notifies the output device of the transition via the character evaluation line. The I / O module continues to respond to any character request from the output device until the binary signal on the sahreib- Start / Stop (WSS) line from the Output / mixers 401-10-1 goes to a 0 level.

The simple output device provides the following three input signals to the I / O base. For the peripheral device, these signals are output signals.

1st unit available A 1 level on the unit available line of the simple output device, the I / O device indicates that the device is capable is to accept information and that it is not connected to any other I / O base is. A device that transmits a 0 level on the unit available line is either connected to another I / O base or is not eligible for data transition ready. After the I / O device tries to communicate with the peripheral device through transmission of the instruction mark becomes the unit available signal fall to 0 level within 1.0 microseconds. The unity available signal remains at the O level until the I / O unit transmits an O level on the write start / stop line and. the peripheral device is ready to accept information.

2. Character request: The transition to the 1 level on the character request line always occurs when the write start line from the I / O base is at the 1 level and when the device is ready to receive a 6-bit character from the I / O base is. The character request line stays on the 1-P-g-l for a minimum of 0.39 microseconds at the I / O base. After receiving a signal on the character request line the I / O module with a signal on its character evaluation line and with permissible Reply to data on its data lines 0 The 0 level of the character request line is maintained on the I / O base for a minimum of 0.39 microseconds.

The maximum repetition rate of the character request signal is 0.75 mega-pulses per second.

3rd state: A binary 1-level signal on the state line shows indicates that either a parity error was found on a character used by the I / O device was received, or that the device has experienced some type of failure. This binary 1-level signal on the status line lasts for a minimum of 0.39 seconds held in the I / O modules. The command code 000-010 is written to the status register given and the I / O module terminates the operation and transmits a binary O level signal on the write start / stop line. The presence of a binary O level the status line indicates that the operation is proceeding normally.

The I / O base provides the following input signals at a simple one peripheral output device. Although they are referred to as input signals to the peripheral device they are output signals from system 1. Less-Start / Stop A binary 1-level on the write start / stop line is sent to a simple output device, after the I / O module is connected to the device via the instruction sign and the I / O base that first word received from memory that to be transmitted to the device, the receipt of a binary 1 level on the Read start / stop line causes the device to send out character request signals to begin the I / O unit. A binary 1 level remains on the read start / stop line, until a termination condition occurs in the I / O base or from the connecting device The occurrence of a status code in the status field of the descriptor causes the I / O unit to be disconnected from the peripheral device by transmission of a binary 0 level on the read start / stop line.

2- Character evaluation: The I / O unit sends a record to the character evaluation line for a minimum of 0.33 microsecond in the I / O unit as a function of a binary 1-level signal on the character request line from the device, within 20 ns after this signal transition of the character evaluation line is a valid data line present on the 6 data lines at the I / O unit. For those devices that use If the I / O module is connected with less than 15 m of cable, this response usually occurs on the output device between 0.49 and 1.33 microseconds after the time after which the character request signal transitions to a binary 1 level. The peripheral device does not wait for a character evaluation response in a defined manner. After their arrival remains the character evaluation signal at the binary 1 level until the signal on the character evaluation line changes to the binary 0 level. The peripheral device then becomes its next character request signal transferred and the above process will be repeated. A connection between the peripheral output device and the I / O unit via the character request and character scoring lines only occurs when the character start / stop line occurs is a binary 1 level.

3. Data: The operational I / O unit will be a 7-bit data character the peripheral output device within 20 ns of the transition of the signal the write character evaluation line is transmitted to a binary 1 level. The 6-bit data character remains valid for a minimum of 1.33 microseconds. The duration of time depends of course on the Transmission speed of the character request signals from the peripheral output device away. The data character is transmitted on lines numbered 1 to 6, where the signal on line 1 is the most significant bit. The bit on the line 7 is generated so that the overall parity is odd.

For at least 1.5 microseconds before the signal transition from one binary zero to a binary one level on the write start / stop line the data lines for transmitting special bits of the command descriptor to the peripheral device is used as the instruction mark. The peripheral device is in use this 7-bit instruction to change its operations. The sentence count field that Bits 13-16 of the descriptor are carried on data lines 7, -1, 2 and 3. That Command code field, bits 46-48 of the descriptor, is displayed on data lines 4, 5 and 6th transfer. The transmission of this instruction will be carried out after Maintain signal transition to the binary O level on the read start / stop line, until the I / O unit has a 0 level on the read character request line from the Device receives.

A complex peripheral device is started and in the following Operated wisely.

First, the I / O base will try to only include the complex devices in To bring gear, whose unit-available line has a binary signal at the 1 level owns. After that, the I / O base will try to transfer to the device an instruction mark on the data lines to the complex peripheral device establish a connection in the manner described for a simple output device.

The device will respond to the transmission of the instruction character Lower - answer his device-available line.

After the complex peripheral device received the instruction from the I / O unit one of the following three operations can be performed. These are: 1. A complex input operation that requires only one instruction character.

2. A complex input operation that requires more than one instruction character needed.

3. A complex output operation.

An example of a complex peripheral device is a unit, known in data processing technology as a flexo writer. she is also an example of a device whose input operation is just an instruction character requires. Within 0.67 microseconds of the instruction mark on the data lines were given to the device, the I / O unit transmits a binary 1-level signal on the read start / stop line. The instruction mark in the Command descriptor is contained, remains on the data lines for the duration the operation. The data transfer progresses in for a simple peripheral Input device, with the exception that for the last character of the last word as from the character count and word count fields in the command descriptor determines the I / O module will indicate to the device that it accepted this last character Has. This is done by transmitting a binary 1-level signal to its read character request and write character evaluation lines. It holds a binary 1-level signal on the start / stop line upright until the device either produces a binary 0 level signal on the read character evaluation line for that last character returns or a completion state condition in the Enters the status of the result descriptor.

A magnetic tape is an example of a complex peripheral device, whose input operation requires more than one instruction character. The operation this device is initiated and expires in the same way as for the simple one Output operation previously described. When the device received the required number of instruction characters it sends a status signal 100-000-X to the I / O base.

The I / O unit responds to this status signal by transmission a binary 0 level signal on the write start / stop line, a binary 1 level signal on the read start / stop line and by entering the instruction character, the contained in the descriptor on the 7-data lines. If the device accepts the binary Detects 1 level on the read start / stop line, the operation continues as it does now for a complex input device, continue.

The third operation listed above takes place when a complex peripheral device such as a simple output device is set in motion. This operation can go in two different ways depending on whether Bit 46 in the 48-bit descriptor word is a binary 1 or a binary 0. If that Bit 46 of the command descriptor word is a binary 0, data transfer is in progress as with a simple output device with the exception of the last character of the last Data word that is to be transmitted.

This is determined by the character and word counting fields of the command descriptor word certainly. The I / O base will indicate to the peripheral that it is the last one Character is transferred by entering a binary 1-level signal to the write character evaluation and the read character request lines. The I / O module becomes a binary 1-level signal maintained on the read start / stop line until the perphere device a binary 0 level signal on the read character request line for the last one Character-transmits or until a completion status condition in the status field of the Descriptor is entered. If bit 46 of the command descriptor is a 1, then run the data transfer as with a simple output device. When the last character of the word is transmitted and the least significant 8 bits of the word count field in the descriptor word are 0, the sequence is slightly different. When the I / O base transmits this last character, signals it to the complex peripheral device by transmitting a 1 level on the read character evaluation and read character request lines. The peripheral device can determine whether this simultaneous reception of a binary A level 1 signal indicates that the I / O base is just finishing the last character of the word by returning a status signal OOO-000-x to the I / O unit. If the I / O base does not process that last word (i.e. the word counter does not equals 0), the read character request line will transition to the binary 0 level and the operation will continue. When the I / O base is processing the last word (i.e. when the word counter is 0) the read character request line becomes stay at the binary 1 level.

When this happens, the peripheral device terminates the operation either by entering a 0 level on the read character request line, or by transmitting a completion status code to the I / O base.

The following three output signals from the complex peripheral device are supplied as input signals to the I / O module. They are: 1. Unit available: A binary 1 level signal on the unit available line from the complex peripheral Device states that it is ready to be used and that it is not currently connected to another unit. Conversely, if the peripheral device is a delivers a binary 0-level signal on the unit-available line, it is either connected to another device or it is not yet ready for data transfer ready. When the I / O base tries to connect to the peripheral device by transferring the Turning the instruction sign on will turn the binary 1-level signal on the unit-available line will drop to a binary 0 level signal within 1.0 microseconds. After that remains the unit available signal at the binary O level until the I / O unit has a binary Transmits an O signal on the write start / stop or read start / stop line.

2. Write character request / read character request (WCR / RCS) a complex input device, where the line carries this signal, carries the same Function like the line that sends the character evaluation signal for a simple output device leads. For a complex output device, this line function is the same as that of the line, which is usually the sign request line for a simple one Output device leads.

Whenever a complex device has a binary 1 level on the write character evaluation line and the read character request line from the I / O module determines the device must be prepared to maintain a binary 1-level signal on the WCR / RCS line, until it connects to the I / O base. If the device doesn't have a Has sent completion state while it is holding the WCR / RCS line at the 1 level, the I / O base will continue after receiving an O level on the WCR / RCS line, Process words as long as the word counter is not 0. However, it will stop when the word counter reaches 0.

3. Status line: The description and use of the status signal for a simple input device also applies to a complex device. For a complex Device that is switched for an input operation, practically all of the status codes apply, that were previously set for a simple input operation, including the complex one Input operation.

When a complex device is switched for an output operation, the status codes are transmitted to the I / O unit on the data lines and Their meaning is as follows: Complex device status code for output operations Signal on data lines 123-456-7 OOO-OOO-X: This condition code is used by the complex peripheral devices whose command descriptor is a has binary 1 signal in bit 46 to between the end of the operation and the end of the sentence to be distinguished. If the device simultaneously has the presence of a 1 level on the write character evaluate and read character request lines detects it maintains the 1 level on the write character request line and in the meantime signals to the I / O unit on the status line the code OOO-OOO-X on the data lines to distinguish whether the competing Signals mean end of operation or end of sentence. When the read character request line transitions to the 0 level within 2.0 microseconds and stays there until the Status line has a corresponding binary signal, then prepares the peripheral Device proposes the acceptance of a different sentence. When the read character request line remains at the 1 level instead of going to the 0 level, the peripheral device prepares the operation ends before. When this occurs, the I / O module is being used by the device in 1.0 microsecond disconnected after the signal on the write character request line was shifted to the binary O level.

001-000-X: this code is used to identify the existing contents of the Reject I / O device intermediate data levels and access to the next storage location to demand.

The content of this new memory location is then transferred to the intermediate data levels given, the number of characters returned to "O" and the output transmission again recorded.

010-000-X: This code is used by the complex peripheral device around the word count and address count fields of the descriptor in reverse order to count.

011-000-X: This status code accomplishes the same tasks like those obtained by successive transmission of the two previous status codes be achieved.

100-000-X: This status code is used to control the I / O module cause to communicate with the complex device for an input operation step. The receipt of this status code signal causes the I / O unit to be binary 0 level signal in the read start / stop line and a binary 1 level on the read start / stop line to the device and then continue like an input device.

11X-OOQ-X: This code is not used.

1X1-000-Xt This code is not used.

XXX-XXl-X; XXX-X1X-X, XXX-1XX-Xs These status codes are used by the Device used to indicate an error or end of operation condition; they are Completion state conditions for the complex output operation. In all cases the I / O unit will do the operation with the code from the data lines 4, 5 and 6 completed in the result descriptor status field, bits 20, 37 and 38, set are. The characters used in the I / O unit data intermediate levels remain when this status code occurs are not transmitted to the device. The interpretation of the status code is unique for each device.

4. Data: The description and use of the data lines to the I / O unit for a simple input device also applies to the complex device, if one is connected to the I / O base for an input operation. That for one Output operation switched complex device uses the data lines only for Transfer of status conditions to the I / O base.

A complex peripheral device receives the following group of five Signals as output signals from the data processing system.

1. Write start / stop: The I / O unit puts an n 1 tt on the write start / stop line to the peripheral device whether the operation to be performed is a complex one Output operation or a complex input operation is that further instruction characters needed.

This latter operation occurs whenever the I / O module is with the device by transmitting the instruction character contained in the descriptor is connected and when the first word is received from memory has been. The write start / stop line is at the 1 level during all data transfers and stays there until a completion status signal or a Reverse-to-input operation status signal is sent out from the complex peripheral device or in the I / O unit Condition occurs that changes the state of the unit. The appearance of one Completion signal, a reverse signal or a status condition signal the I / O unit to transmit a 0 level on the write start / stop line.

2. Read start / stop: A signal transition on this line from the binary 0 to the binary 1 level indicates to the peripheral device that the I / O unit is connected as a complex input device and that the I / O unit is ready to receive the first daton character 0 This signal transition to the 1-Pogol occurs within 0.67 microseconds after the instruction character occurs the data lines have been given, provided that the unit-available line of the device is at the 1 level, or depending on the status code 100-000-X from a complex device that is connected to the I / O unit as an output device is. The signal transition from 1- to O-Pagel indicates that the complex device from the I / O base has been disconnected. The transition to the 0 level is made by a Condition condition generated in the I / O unit or by a Termination status transmitted from the device to the I / O unit.

3. Write character evaluation: The use and description of the Write character evaluation signal for a simple «+ output device also applies to the complex device that connects to the I / O unit for an output operation or for a Input operation that requires further instruction characters. Additionally to the function described for a simple output device if the I / O base is connected to a complex device in the manner described above, the Write character evaluation signal used to ensure a successful response from the I / O base to indicate a non-completion or control state from the complex device. The timing of this response of the read character request to a status signal for a simple input operation also applies to the response of the write character evaluation signal on a state signal.

If the complex device is switched as an input device, that is Transition from the 1 level on the Schrelb character evaluation line a signal for the Device that the I / O unit accepted the last character for the data transition determined by the digit count and word count fields of the descriptor. The I / O unit will transition to the 1 level within 20 ns of the transition to the 1 level on the read character request line occurring to the device confirms the successful transfer of the last character. The write character evaluation line remains at the 1 level until the read character evaluation line from the device to the O-P-gel passes over or

until the operation is terminated by a termination unconditional.

40 Bookmark Request: The Use and Description of the Bookmark Request for a simple input device also applies to the complex device, the one with the I / O unit connected for an input operation.

When the I / O unit and the complex device for one output operation are connected, the transition of the read character request to the 1 level becomes occur at different times, depending on whether bit 46 of the descriptor is a Is 1 or bine 0 or not. When bit 46 of the descriptor is 0, this transition will be always occur when the last character of the last word, as indicated by the character counter and the word counter is determined to be transmitted to the device. If bit 46 of the counter Is 1, this transition occurs every time the last character of the transmitted word occurs occur when the least significant 8 bits of the pre-counting folder are in the descriptor O are. In both cases, the transition to the 1 level occurs within the I / O unit of 20 ns after the transition to the 1 level of the Schr-ib-Z-ich-nauswertleltung for this sign. In both cases, the read character request remains at the 1 level until the write character evaluation goes to the 0 level. If the word count field doesn't Is 0, the read character request goes to the 0 level for the duration of the status level, if the device transmits the status code 000-000-1.

3. Data: The use and description of the data lines for a simple output device also applies to the data lines from the I / O unit to the complex device switched for an output operation.

When the complex device is dead for an input operation, becomes the instruction character of the command descriptor via the output data lines transmitted for the duration of the operation. If the device is for an output or Input operation is activated that requires additional instructions, becomes the instruction character contained in the descriptor via the output file lines transmitted until the first character request is received from the complex device. In the latter case, after the additional characters have been received and the state sent by the complex device to reverse the operation for an input operation is, the instruction character contained in the descriptor is put on the output data lines given for the rest of the operation.

Fig. 17 contains Figs. 17A and 173. It shows a logical one A block diagram of the memory module used in the present system. Four such modules are included in the arrangement disclosed. Every module consists of a core memory 101-17-10 with a capacity of 16 384 words owns. Each word is 49 bits long including one parity bit and each word can be addressed separately. This selection is made by the memory word selector 101-17-108 hit.

In the upper left-hand part of FIG. 17, several 40-wire cabal appear into the module. One of these input information cables comes from each of the rest 13 module of the Systems. The group of three 49-wire cables that comes from each of the three computing modules is directly connected to the logic receivers 101-17-12 connected0 However, the group of ten 49-line I / O data cables that coming from each of the I / O control modules, first with I / O receivers 101-17-14 connected before they come to one of these in logic receivers 101-17-12 The selection of the special cable from the ten cables for connection to the logic receiver is achieved by request resolution logic 101-17-28. Into this logic circuit several of the 4-wire cables enter. One of these 4 ° lines-cables is with connected to the memory module of each of the ten I / O control modules. Each of these cables contains two pairs of line groups. One of these pairs in each cable is called I / O data and the remaining pair is marked as I / O request. These markings are self-explanatory by the fact that the respective groups just specify that data is being supplied to the memory by the respective I / O control modules or that one of the modules requests access to the memory module.

The cables in the upper right part of the figure show the conflict resolution device, which provides the determination of the particular module, access to these memory modules should be granted.

In the case of the compute module access conflict, an e becomes something different Explosion scheme generated. In this case it becomes the cross point dissolution connection accomplished by a 21-wire cable from each of the three compute modules. Two Lines in each of these three cables denote the compute module request line, while the remaining 19 lines of the 21-line cable are referred to as arithmetic data are. The three 21-line cables enter the crosspoint receiver and resolution logic 101-17-30 from the computing modules. A fourth 21 lead cable also occurs Put in this circuit 0 This fourth cable consists of four wires from the I / O receivers and the request resolution logic 101-17-28 and 17 lines from the I / O receivers 101-17-14. The control panel and test register 101-17-26 generate a test signal, to test the crosspoint receivers 101-17-30.

From this resolution circuit 101-17-30 is a 6-line cable connected to the logic receivers to provide the necessary gate control signals for the data input to deliver.

A separate group of 13 lines is with the 13 line drivers 101-17-36 connected, the outputs of which are applied, at the wheel (intersection) information to deliver to the grate of the system.

A cable with 24 wires is connected to the address counter 101-17-32, to deliver the address of the selected word into core memory 101-17-10. This address information is checked by the memory word selector before it is used 101-17-105 first stored in address register 101-17-34.

A separate 49-lead output cable is with multiple output register indicators 101-17-18 connected by core memory 101-17-100 Similarly, is a special one tes 14-wire cable connected to several memory address indicators 101-17-20, for an indication of the particular ren word addressed in the memory deliver.

The actually selected word output becomes TO several of the 49-line drivers 101-17-22, the output of which is given to the system data lines.

The same word output is also given to a comparator 101-17-24, in which it is compared to a word stored in test register 101-17-26 can be.

A memory clock and control circuit 101-17-16 is also included, to provide the necessary clock control associated with core memory. She receives signal.

from and liefort signals to core memory 101-17-10 and its word selector 101-17-108.

Figures 18A and 18B table the complete list of instructions of this machine, the table lists the device set language mnemonics and alphabetically the machine language syllable formats.

These syllable program (machine language) instructions derived from the Fitter generated are composed of sequences of 1 to 7 syllables depending on of the instruction being carried out. The sequence of syllables that make up an instruction represents, the last syllable of the preceding instruction follows, which is a usage which allows program memory fields with maximum efficiency. Every program word contains four syllables; a 7-syllable construction with a maximum length can have up to three Cover program words.

Knowledge of syllable programming is essential for the system programmer necessary to change the compound programs, the equipment set listing to read and analyze the memory dumps.

A list of the symbol names appears in Fig. 18B for understanding of the instructions shown in the table.

Claims (15)

- Expectations 1. Modular data processing system, characterized by at least a quick save module (101-104), at least one input / output control module (400), which is individually connected to each of the memory modules (100), at least a computing module (200) individually connected to each of the memory modules (100) is-t, multiple peripherals (600) with input / output devices, each of the input / output control modules (400) a pair of input / output control units (401-1, 401-2), a memory connector (401-12) and an input / output peripheral device interface unit (401-10), each of the pairs of control units (401-1,401-2) with the storage connection unit (40-1-12) is connected, which in turn is connected to each memory module (100), to create the single connection with this, and where the input / output interface unit (401-10) between the control units (401-1,401-2) and all peripheral devices (600) is switched. 2. System according to claim 1, characterized by several quick storage modules (100), multiple input / output control modules (400) that are individually associated with each memory module (101-104) are connected, several cabinet modules (200), which are individually connected to each storage module (101-104) are connected and several peripheral devices (600), the input and output devices contain. The system of claim 2, characterized in that the plurality of peripheral devices (600) are connected to the input / output control modules (400), the pairs of input / output control units (401-1,401-2) and the memory connection unit (401-12) selectively connected to each pair of control units (401-1,401-2) to enable each of the units (401-1,401-2), individually with each the memory modules (301-104) connect on an alternate basis, while the pairs of units (401-1,401-2) simultaneously with the pairs of several Peripherals (600) are linked. 4. System according to claim 2 or 3 with a plurality of central processing modules' characterized in that each central processing module (201) and each input / output congestion module (400) is connected to each memory module (100) to individual selective connections establish between these that each central processing module (201) one Program processing unit (201-40), an arithmetic unit (201-20), a Storage control unit (201-30) and a thin film storage unit (201-10), that the program processing unit (201-40) to act in two directions Connection to each of the remaining units in the processing module (201) is, and that the program processing unit (6201-40) and the Memory control unit (201-30) with each memory module (100) in the system for in two directions acting connection are connected0 5. System according to one of the claims 1 to 4, characterized in that each input / output control module (400) has a Input peripheral device interface (401-101) and an output peripheral device interface (401-100), which together with both input / output control units (401-1,401-2) are connected. 6. System according to one of claims 1 to 5, characterized in that that each memory module (101-104) has a fast magnetic core matrix block organized by words (10122) and contains several connection cables, di. between the storage media (101-104) and Spe remaining modules of the system are connected, and that the number of several Cable equal to the number of input / output control modules (400) and computing modules (200) is. 7. System according to claim 4, 5 or 6 with a main memory, characterized characterized in that the processing module (201) also has a first connection device (Fig. 8) for information data transmission acting in two directions between the main memory (100) with the processing module (201) and a second connection device (Fig. 8) for two-way control data transfer between the memory and the module. 8. System according to claim 4, 5, 6 or 7, characterized in that the program processing unit (201) contains means for receiving and transmitting of data while performing various processing operations at the same time Data to allow successive programs to overlap. 9. System according to one of claims 1 to 8, characterized in that that the multiple peripheral devices (600), which contain input and output devices, connected to the input / output control modules (400) that each of the computing modules (201) Means for interrupting (Fig0 4, 4-10) the normal processing operation mode (4-12) of the control modules and further means (4-14) to cause that the computation modules operate in a first interrupt control mode (4-16), and others Means (4-18) for interrupting the first interrupt control type (4-16) in order to cause the arithmetic modules to start in a second interrupt mode (4-20) work. 10. System according to claim 9, characterized by means in each of the Input / output control modules (400) and each of the computing modules (201) for activation the interruption means (4-10) contained in each computing module (201), to cause the interrupted computation module in the first and in the second Interrupt control type (4-16 or 4-20) is working. 11. System according to claim 9 or 10, characterized by further means to interrupt the first interrupt control type (4-16) to cause that the computing module (201) works in a second interrupt control mode, which depends only on signals associated with errors that occurred during its O, perations execution occur in the first interruption type. 12. System according to claim 2, 3 or 4 with several connected function modules, characterized in that each pair of signal / output control units (401-1,401-2) consists of a first and a second input / output control unit that the Input / output peripheral device interface unit (401) from an input peripheral device interface unit (401-101) and an output peripheral device interface unit (401-100) that the memory connection unit (401-12) having the first and second input / output control units (401-1,401-2) is connected to a bidirectional connection with and from each of the control units (401-1,401-2) to enable the input peripheral device interface unit (401-101) between the input peripheral devices and the first and second input / output control units (401-1,401-2) is switched to provide a selective connection between an input peripheral device and an input / output control unit (401-1T401-2), and that the Output Peripheral Interface Unit (401-100) in the same way between the output peripherals and the first and second input / output controls in units (401-1,401-2) is connected to an equal selective connection between to manufacture this. 13. System according to claim 1 with a main memory, characterized in that that the input / output control module (400) is a main memory connection unit (300) contains the two-way data transfer with the main memory connected between these, a first B / O control unit, a second I / O control unit, which are able to selectively with the connection unit for bidirectional Acting data transmission between these to connect, an input peripheral device interface unit (500) between all input devices (600) and the first and second input / output control unit is switched, and an output peripheral device interface unit, which in the same Way between all output peripheral devices and both input / output control units is switched. 14. System according to claim 1 or 13, characterized by at least a main memory module (100), at least one central processing module (201), each central processing module (201) and each I / O control module (400) having each main memory module (100) is connected, each central processing module (201) contains several separate operation units, namely a program processing unit (201-40), a memory control unit (201-30), a arithmetic Unit (201-20) and a thin film storage unit (201-10), wherein the program processing unit (201-40) connected to each of the remaining units in the processing module (201) each input / output control module (400) having several separate operational units comprises, namely a memory connection unit (401-12), a first and a second kingangs / output control unit (401-1, 401-2), one input peripheral device interface unit (401-101) and an output peripheral device interface unit (401-100), each I / O control unit (400) is connected to the memory connection unit (401-12) and each interface unit (401-100, 401-101) with each input / output control unit in the input / output module (400). 15. System according to claim 1, 13 or 14 with functional modules, at least a central processing module, characterized in that at least one Input / output control module (400) several input and several associated therewith Output peripheral devices (600) have that each central processing module (200) also a program processing unit (201-40), a magnetic thin film storage unit (201-10), an arithmetic processing unit (201-20) and a memory control unit (201-30) has that the program processing unit (201-40) with each of the remaining units in the central processing module (200) into two active connection is connected that the Program processing unit (201-40) and the memory controller (201-30) continue with each memory module (100) is connected to form a two-way connection between them, that each input / output control module (400) further includes a memory connection unit (401-12), first and second input / output control units (401-1, 401-2), one Input peripheral device interface unit (401-100) and an output peripheral device interface unit (401-101) that the memory connection unit (401-12) between the memory module (100) and the first and second input / output control units 3n (401-1,401-2) are switched is to provide a bi-directional link between each control unit and the memory module to enable the input peripheral device interface unit between the input peripheral devices and the first and second input / output control units is connected to a selective connection between an input peripheral device and an input / output control unit, and that the output peripheral device interface unit in the same way between the output peripherals and the first and second Input / output control unit is switched to an equal. selective connection to allow between these. L e r s e i t e