DE1499200B2 - DATA PROCESSING SYSTEM WITH PRIORITY CONTROLLED PROGRAM INTERRUPTION - Google Patents

Abstract

1,061,361. Editing data. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 11, 1965 [April 6, 1964], No. 5906/65. Heading G4A. In an electronic data processing system, data characters to be edited are transferred selectively and successively under partial control of a bi-stable device from a first (" source ") storage field to a second (" pattern ") storage field initially containing control and data characters (e.g. decimal point), whereby at the conclusion of an editing operation the second field contains selected characters from the first field selectively interspersed with data characters of the second field. Bytes each have 8 bits and comprise two binary-coded decimal digits or one such and a sign (" packed " format), or one such digit plus 4 zone bits (" unpacked " format). Provision is made for interchanging the two halves of a byte in a register to simplify test on a half, testing being done generally by subtracting a constant from the number and seeing if the result is zero. The bi-stable device referred to above is a " significance trigger " which is 0 if the next " source " character is presumed non-significant and 1 if significant. The trigger is set to 1 if the " source " character is non-zero, or when a " significance start " control character is detected in the " pattern " field, and set to 0 when a " field separation " control character is detected. The characters of the " pattern " field are accessed from memory in turn. Those not control characters are retained in the " pattern " field if the "significance trigger " is at 1 but replaced by fill characters if at .0. " Field separation " control characters are replaced by fill characters. Detection of a " significance start " control character or a " digit select " control character results in the accessing of the. corresponding " source " character. If this is non-zero or if the "significance trigger " is at 1, it replaces the control character in the "pattern " field after being " unpacked " by insertion of zone bits 1111. Otherwise the control character is replaced by a fill character. The editing operation is initiated by an instruction word containing an OP code specifying either normal, editing as above or the latter plus the additional feature of storing the address in the "pattern " field of the highest significant character in the "source" field when this is detected through switching of the " significance trigger ". This facilitates later insertion of e.g. a currency symbol. The editing instruction word also specifies the number of bytes in the " pattern " field and the addresses of the highest order bytes of the " source " and " pattern " fields. These addresses are each specified by specifying a number and a register, the contents of the register being added to the number to get the address. Detection of a sign character in the " source " field sets to 1 a trigger to indicate that a sign is present, and if the sign is negative sets a further trigger to 1 to indicate this. This will cause the " significance trigger " to be set to 1. The second sign trigger and another trigger set to 1 in the presence of a non-zero " source " digit can be used to control subsequent (unspecified) operations. Reference has been directed by the Comptroller to Specification 954,801.

Description

1 2

The invention relates to a program status word assigned to a data processing program in the position with priority-controlled program interruption, active PSW registers transferred,
with an active program status word register If a (PSW register) is provided for each available subroutine for the recording of the data describing the current register pair for recording the program status program (program status 5 words, one of which is an empty word) and with a Control circuit for controlling and the program status word of the program sequence to be interrupted and for receiving the program and from which the other interrupt requests. the program status word of the interrupting program

During the execution of the various ope- grams, a ration, the program-controlled data processing io exchange of the program status words and the transition management systems are executed, certain loads can be changed from a running program to a subcondition occur that interrupt the program. Results in the following normal currently running problem program check that an interrupt request is required. Such conditions can be present with varying degrees of urgency occur in parts of the system; you can enter program status input via 15 active PSW registers and output units are now called into the empty register of the register, ζ. B. when an input or output operation pair higher for the interrupting program should be started or ended; they can also be urgency. This process can be repeated occur in so-called external units, so in An embodiment of the invention the console, in a time data processing system used in the system, is based on the signal generator or explained in other connections connected to the system. It shows

Units that can be immediately referred to on request

require viewing; also detected errors in the data processing system in which the inventive

The machine or the program can use an undersized interruption system

make refraction necessary. Usually it is 25 can,

if an interrupt condition occurs, F i g. 2 a schematic representation of a prorichend, the currently running problem program of the program status word,

to interrupt, an interrupt subroutine F i g. 3 is a diagram showing when the

and then run the problem program into various types of interruption conditions

to continue. 30 can occur with respect to the problem program

It is known that in multi-channel transmissions each and at what times the interruption sub-channel is assigned its own control word, which programs are started,
the properties and the state of this channel for FIG. 4, a diagram which indicates an information transmission in the case of several. simultaneous interruption conditions

It is also known to indicate to each input and output 35 the order in which the problem device is assigned a bistable memory element which is set during the program and the various interruptions of an interrupt request for this device subroutines assigned to the program status; these feature elements will be completed and stored in words,
cyclically after the presence of an interruption Fig. 5 is a block diagram of the circuit, queried with request. A priority between the 4 ° whose help is determined whether a requested request is not taken into account. Interruption according to the one currently in use

The object of the present invention is to determine which program status word can take place or not, and to select the one with the highest urgency different interruptions determined,
1 shows a block diagram of a machine, requests of different urgency, in which the above-mentioned interruption system can be used starting with the request of the lowest urgency. This diagram shows the ability to continuously check whether a request block 1 represents a core memory that is of a higher priority, and only when this is no longer the case, the request of the currently other one Control words and data, all of which have to be dealt with under the highest urgency and can then be of different lengths, and work one after the other in reverse order which the processing memory 3 has, which transfer the function of registers for the processing of the remaining requirements to be carried out arithmetic operations. 55 takes. The 8-bit storage locations are addressed

In the case of a data processing system, the input from the address register 5; the stored 8 bits

mentioned type, the task at hand is achieved by forming one byte at a time and entering them in parallel into the

several PSW registers for the same data register 19 read out if necessary. The registered mail from

Timely inclusion of data ready for description- data takes place under the control of the memory standing subroutines or interrupted 6 ° assigned locking circuit 4 in accordance

Programs; through from the control circuit to with the content of the register 19. Block 6 represents a

known introduction of a read-only memory subroutine in which microinstructions are

control devices which can be excited at different priorities are stored. The microinstructions will be off

lines, which in a known manner each to a subpro- by the address register 7 determined memory program are assigned and which also set in sense amplifier latch circuits 8 when energized 65

add the active program status word to the read out. After decoding, they will be

relevant subroutine assigned inactive for controlling the operations of the computer system

Save l'SW register and use this sub-. The control circuits are through block 9

I 499 2Ö0

3. 4th

shown, among other things they ymfassen the switching of all programs by a superordinate gene 10 and 11, which are used to control the interruption program, which are used in the following as a monitor program. The latter circuits and their working called is monitored. If several methods are used in connection with FIG. 5, grams, each of which is a sequence of and 6, are explained in detail. The blocks 12 represent the 5 macro instructions, parts of the system are carried out, one of which is to be interrupted, this monitor program determines the series request can proceed. Arithmetic and logically their implementation; It also controls the Untergische Operations are programmed in the arithmetic unit 18 which are interrupted when an interruption occurs. The two operands with which the arithmetic conditions are required in the system are.
Metic and logical links are to be carried out. During the execution of problem programs, the computer system works under the control of a ß (14) and the buffer registers A (16) and B (17) are pulled from the monitor program via lines A (13) _: provided control word, and from there to the arithmetic unit, which is referred to as the program status word (PSW). The signals for the various interruption programs, which represent the results, are sent to line Z (15), from where they 15 grams are also determined by the type of subroutine in one or more of the registers 19 to 25 via programs. PSW used. Which are led into the. These registers are used for various information contained in PSW and for the respective purposes: Register 19 is used, as already explained, as the status of the programs and the main memory data register in the system: Register 20 reflects existing relationships and conditions, serves as an instruction counter, which is 21 For this purpose it is continuously corrected and saved values are stored in the address register 5 that is overcompleteL · In addition to other information, it contains carry; Register 21 is as an intermediate address register _example: address of the next Makröbenutzt that stored therein values serve on instruction. For the direct control of a currently running address register 5 for calling up the memory program, the currently used location of the main memory 1 or via the address 25 or active PSW is contained in a register 7 provided for this purpose for addressing the read-only memory 6 ; Be ^ The remaining registers 22 to 25 are used to temporarily store certain parts of the PSW are also used in the rain storage of the operation code, the condition, interlocking circuits or similar for the supply codes, the length code and status bits, temporary storage serving devices part addresses or , other information given in the 30th. Inactive PSWs, which are currently not related to the connection with the program execution in each case, are important to the program. The number of registers in the fixed positions provided for this purpose in the main is of course not included in the number in the memory 2. As well as a program. Signing specified restricted. The PSWV assigned to it will be able to register the values stored as registers, as entered in the main memory and shown in the diagram, the various lines and a "new" PSW that is used to control the following -Address registers are supplied; so can z. B. the operations is used, transferred to the work from the main memory 2 in the data register 19 aus- memory. These PSW contain for each read data via the line 13, the buffer time, which are passed for an interruption and subsequent re-register 16 and the arithmetic unit 10 to each other information register required to record a program. _r type. . . . .

In the system shown in Fig. 1, the following is a detailed description

Execution of problem learning programs through a sequence of the funjction of the PSW and the "working method" controlled by macroinstructions; each of these. interrupt system given.
Macro instructions determine a 45 in Fig. 1 to be executed. Figure 2 is the PSW operation used in the plant, shown schematically under the direct control of a 26; It consists of the bit sequence of macro instructions for execution. Positions 0 to 63, which are in fields 26 ^ 1 to 26K . The opcode of each macroinstruct are grouped. The following is an explanation of the function governing this operation, but the bits of the macro information and instructions stored in these fields are not used directly to control the control functions performed by them on the circuitry of the system; however give.

causes the operation stored in one of the registers _{Fdd 26A} - _{Bks 0 to 7} _ SYSTEM MASK

ration code in cooperation with the tax. .-.

circuits 9 the reading of a first micro- When a request for an input occurs

instruction from read-only memory 6. Address 55 would be / output or an "external" interruption The bits of the system mask are at least partially used for the next micro-instruction in each case the preceding microinstruction indicates whether such an interruption is present hold that to. Completion of the address can take place, i.e. is allowed or not. the Required bits depend on the at the time in the .. · Bit positions 0 to 6 correspond to seven different System existing conditions and from the open channels through which the input / output input code the macro instruction. After executions are connected to the computer system; Bit position 7 corresponding to a macro instruction is assigned to the units which have an ex sequence of microinstructions that make the next internal interrupt program necessary Macro instruction from the memory level of the main can. An "O" bit in one of these bit positions Memory read out, which by the Instruktipnsr 65 causes the execution of the corresponding counter 20 is determined and the problem program subroutine is reset; a "1" bit continues, indicates that the subroutine is ready to be executed

In the computer system described, the can be achieved. The purpose of these interruptions

and the processes caused by them will be explained in more detail later.

The system mask of the active PSW is stored in the main memory and also in interlocking circuits.

Field 26 B - Bits 8 through 11 - MEMORY PROTECTION CODE

This 4-bit code defines the areas of the main memory, which are accessible for the instructions of the current program. Is that true? Memory protection code with the one contained in an address used to address the main memory If the memory code does not match, the program must be interrupted.

The memory protection code of the active PSW is in the main memory and in a register of the computer system contain

Field 26C - Bit 12 - Not used
Field 26 D - Bit 13 - MACHINE TEST MASK

This bit is used to determine whether a Machine test interruption may or may not take place. Such an interruption is requested who has found an error in the operation of the computer system. If this bit is a "1", then the interruption is initiated; however, if this bit is a "0", the program currently running becomes continued.

Field 26E - Bit 14 - RUN / WAIT

If this bit is a "0", the computer is executing instructions, it is "running". Will this bit on the other hand to "1", the execution of instructions is interrupted and the system waits until the program is interrupted.

Field 26 F - Bit 15 - MONITOR / PROBLEM

If this bit is a "1", the computer is located in problem program status, the programs run normally. Will this bit to »0« j the computer is in monitor status, in which only special functions can be carried out, all other functions lead to an error display.

Bits 13, 14 and 15 of the active PSW are stored in memory, bits 13 and 14 are above also included in interlocking circuits.

Field 26G - Bits 16 to 31 - SUB-

REFRACTION CODE

This 16-bit code is used to indicate the reason used, which caused an interruption; it determines the various types of interruption both the entity that requested an interrupt program and the reason or condition which made the interruption necessary.

The interrupt code is not included in the active PSW; this information will only be sent to the PSW then supplied when it is transferred to the main memory as an old PSW in the event of an interruption. other storage locations included. The instruction length code is generated by the monitor program in the case of a machine test interruption or a program test interruption used to get the address of the first byte of the instruction that caused the interrupt determine. Bits 32 and 33 are used to determine the length of the instruction that is currently being executed or is just finished. They are used by every macro instruction whose bit positions 0 and 1 are the Identify the length of the instruction inserted into the PSW so that the memory address of the first byte the instruction can be determined.

Field 26 / - Bit 34 and 35 - CONDITION CODE

This code identifies one of several conditions that existed when executing the previous Instructions have occurred in the computer system. In the active PSW this code is in decoded form contained in the main memory:

Bits 34 and 35 4-bit code of the active PSW 00
01
10
11th 1000
0100
0010
0001

When executing an instruction, in the course of which a code is entered in the condition register of the system is brought, the 4-bit code contained in the PSW is changed to the result of the to mark performed operations. The code then remains unchanged until a another instruction causes a change in the condition register.

Field 26 / - Bits 36 to 39 - PROGRAM CHECK MASK

These bits are used to determine whether a Program Check Interrupt has been requested may or may not take place; such an interruption becomes necessary after in the program an error was detected.

Each of the 4 bits corresponds to one of four interruption conditions, which can occur in the computer system. When such a condition occurs if the corresponding bit is considered, if it is a "1", then a program check interruption occurs initiated, but if it is a "0", the current program is continued.

The program test mask is part of the active PSW and is therefore contained in the working memory.

Field 26 H - Bits 32 and 33 - INSTRUCTION LENGTH CODE

Macro instructions of various lengths are used in the system. The 8-bit bytes that make up an instruction are in aufein-Field 26 K - bits 40 to 63 - INSTRUCTION ADDRESS

These bits define the address of the next macro instruction in the course of the current one Program is to be executed.

After a macro instruction has been executed, it is the address of the next instruction in the current program both in the instruction counter of the system and in bit positions 40 to 63 of the active PSW contain. During the execution of each instruction this address becomes in agreement incremented with the instruction length code included in each instruction; the address will be

sets when the normal instruction order by controlling a sequence of microinstructions 1 to η

a branch instruction is interrupted. executed by the respective macro instruction

That is determined in the data processing described (columns 30, 4 and 30S).
The interrupt system used allows arrows in the "Interrupt requested" column to interrupt running programs and the 5 (30C) indicate for each type of interruption when interrupt subroutines are to be executed, rather time, with reference to the sequence of microinstructions required by conditions, which can be requested in an interruption,
external units of the system, in I / O units, requirements for machine testing (MASCH or occurring in the computer system itself. A TEST), program test (PROGPRUF), interruption consists in the storage of the io output / output (E / A) - and external (EXT) underactive PSW as "old" PSW and the provisioning breaks can take place at any time, as with a "new" PSW. The upper arrow and the large brackets then begin, the program determined by the new PSW The monitor call (MON RUF) interruption is carried out under the conditions and at the point by a macro provided by the programmer the new PSW to be defined. 15 instruction initiated and can therefore only follow

Five different types of sequence of microinstructions can be run in the system, such as

of interruption conditions occur: by the arrow marked with MON RUF

specified.

1. MACHINE TEST Arrows in the column "Interruption occurred" (30D)

20 indicate for each type of interruption to which

A machine test interruption is given a time, with reference to the microinstruction sequence, which, as soon as an error in the machine has been detected, will allow execution of the interruption subroutine, if it has been requested and if 2 PROCRAMM PRi ¹ IFT JNC by the corresponding mask bits certainly

25 that the interruption can take place.

A program check break is activated. As shown, MACH CHECK and PROG

routed as soon as an error is detected in the program PRUF interruptions initiated immediately. The Mi

was, e.g. an invalid operation code, a sequence of instructions is interrupted because a

wrong memory address or an overflow condition. Continuation of the program with incorrect results

1 cmrADc / ATicPADc ³ ° could lead ^nits.

ό. bUNOrAüt / AUbOABt _{I / O. and} EXT interruptions are after

An input / output interruption is initiated. The sequence of microinstructions is initiated. the

directs as soon as an input / output unit serves such a sequence during the last microinstruction

of the operations performed by it always has a point to determine whether during the execution reached, at which the monitor program for determining the 35 microinstruction sequence requirements for I / O

the further work process of the system or EXT interruptions have occurred,

must be drawn. A MON RUF interruption will, as already

. _pv mentioned, after the sequence of microinstructions

4. üAiüKiN headed.

An external interruption is initiated, as soon as 40 The use of the PSW makes it possible to

soon the computer system of external units, whose multiple interruptions occurring at the same time

Operations do not allow postponement to be used to process requests that interrupt interruption

the must. Execute the highest urgency program first

5 MONITOR ^{CALL unc} * ^ ^e I ^{n forrnat} i ° ^{nen to} save the for the

45 less urgency interrupt programs

A monitor call interruption is required by one. Step into the described special monitor call instruction initiated. The interruption system multiple, one interruption Main purpose of this interruption requiring conditions at the same time, so will it says, the computer system from the problem status in the old problem program PSW in one after the other switch the monitor status; this is required to have 50 main memories stored, which is a first sub-if a PSW is to be replaced or changed. refraction (lowest urgency) appropriate

As already mentioned, machine test, new PSW can be transferred to the main memory, this Program checking, input / output and external first new PSW after it according to the Interrupt subroutines are only initiated and interrupt conditions are changed and completed, when the corresponding mask bits of the 55 have been set, reactivate the main memory PSW represent a "1"; if, on the other hand, the saves, the next new PSW, which is the one in the If the corresponding bit is a »0«, a sub-urgency sequence cannot take place in the next interrupt interruption until the program bit has been changed in the working memory to "l". A monitor call interruption is carried out by, etc. The execution of instructions a macro instruction is initiated and requires that 60 is resumed under the control of the no mask bit in the PSW. PSW, which is the last from the main memory to the

The in Fig. 3 shows the diagram to which main memory was transferred, that is to say the Untercher time, with reference to the problem program, the break program of highest urgency according to the requirements for the various types of speaks; the order of execution of the sub-interrupts occur and at what time the 65 interrupt programs is opposite to that at which interrupts can be made. in which the PSW were transferred.
As already mentioned, the operations defined by macroinstructions are permanently assigned to the various PSWs under the direct 64 bits in the main memory ten storage locations.

, '109 516/273

The PSW for which these positions are intended are designated as follows:

I. Old EXT PSW
II. New EXT PSW

III. Old I / O PSW

IV. New I / O PSW

V. Old MASCH PRUEF PSW
VI. New MASCH PRUEF PSW
VII. Old PROG PRUEF PSW
VIII. New PROG PRUEF PSW
IX. Old MON RUF PSW
X. New MON RUF PSW

When an interrupt is initiated, the active problem program PSW after it becomes appropriate the interruption conditions was changed and completed as the old PSW in the corresponding Main memory location saved. For a PROG CHECK interruption, the old PSW is stored in memory location VII »old, for example PROG PRÜF-PSW «entered. Most of the bits of the PSW are left unchanged; H. the way she's in RAM were included, transferred to the main memory; the condition code however must, as already explained, be decoded beforehand.

When storing an old PSW, the interrupt code is in bit positions 16, respectively to 31 included. This code defines the reasons for the interruption as follows:

1. For an EXT interrupt, the code defines which external unit caused the interrupt.

2. For a MON RUF interruption, the code forms the information that the MON PROG decoded, determines the reason for the MON RUF instruction.

3. For a PROG CHECK interruption, the code defines that caused by a faulty program resulting condition that requires an interruption.

4. The code is always »0« for a MASCH CHECK interruption.

5. For an I / O interruption, the code defines the channel and unit that the interruption occurs requested.

After the old PSW is completely in the memory location determined by the type of interruption of the main memory has been entered, the new PSW is stored in the one provided for the currently active PSW Memory location of the main memory transferred. If z. B. an old PSW in the memory location IV "old PROG CHECK PSW" has been saved, the new PSW that is used to control the PROG CHECK interrupt program, taken from storage location VIII "new PROG CHECK PSW". The new PSW does not require the interrupt code and is therefore not included in the Working memory taken over; the 2-bit condition code is decoded into 4-bit form as before explained. The new PSW now contains the start address and the start conditions for the monitor program, under whose control the interrupt program is running and the computer system begins executing instructions until the interrupt routine has ended. At that time, the PSW, under whose control the Interrupt program was executed in the memory location assigned to it in the main memory returned. Then the old PSW, which is used to control the interrupted problem program served, entered into the working memory, and the computer sets the problem program to the Resume where it left off.

The diagram of Fig. 4 shows the application of the PSW in the event that two interruptions, EXT and I / O can be requested at the same time. It

ίο it is assumed that both interruptions to At the time of the request, the corresponding mask bits were determined to be "allowed", the corresponding Subroutines are to be executed in the order of their urgency.

The numbers given in column 4 (M correspond the various operational steps required for the example adopted. In columns 40 # and 4OC show which program or subroutine is used during each Steps are carried out in each case and which PSW is contained in the main memory as the active PSW. the various programs, problem program, EXT interrupt, and I / O interrupt, are through different hatchings in accordance with those indicated for blocks 41, 42 and 43 Explanations shown. The double columns 4OD to 40/7 represent the pairs of the different ones Types of interruptions are permanently assigned storage locations in the main memory that are used for storage serve the non-active PSW. Such a pair of storage locations I to X is for the old and new PSW of one type of interruption are planned, such as I and II for EXT interruptions, III and IV for I / O interruptions etc. The storage of a PSW in the "old" storage location of a pair follows automatically reading out the associated "new" memory location. A detailed description follows of operation steps 1 to 12.

Step 1

Execution of a problem program under the control of a problem program PSW contained in the RAM is included. The "old" PSW storage locations in the main memory (odd numbers I, III etc.) are empty, while the "new" PSW storage locations (even numbers II, IV etc.). the different Interrupt subroutines included corresponding PSW.

step 2

During the execution of the problem program, two interruptions are permitted at the same time different urgency required: an EXT interrupt (lower urgency) and

an I / O interruption (higher priority). The problem program PSW is transferred to the Storage location I transferred; this is the location for the lower priority interrupt of the two requested interruptions.

step 3

The new EXT interruption PSW is taken from memory location II and into the working memory convicted. There is another interruption (higher urgency) to the execution waits, does not begin executing the EXT interrupt routine.

Step 5

The EXT interruption PSW is transferred to storage location III as the old PSW; This is the memory location corresponding to the higher priority interrupt.

Step 5

The new I / O PSW is read out from memory location IV and stored in the main memory. Since no more interrupts are requested, execution of the I / O interrupt routine begins.

Step 6

15th

Execution of the I / O interrupt routine under control of what is in memory I / O PSW.

Step 7

20th

Upon completion of the I / O interrupt routine, the I / O interrupt routine becomes the I / O PSW is returned to the memory location IV assigned to it.

Step 8

The EXT-PSW is automatically read from memory location III and into the working memory stored. Start of the EXT interrupt program.

Step 9

Execution of the EXT interrupt routine under the control of what is in memory EXT-PSW.

Step 10

After the EXT interrupt routine has been completed, the EXT-PSW becomes the one assigned to it Location II returned.

Step 11

The problem program PSW is read from memory location I and into the main memory stored. Execution of the problem program will resume at the point at which it was interrupted by step 2.

Step 12

Execution of the problem program under the control of the problem program PSW contained in memory.

The mode of operation of the different PSWs was designed for the case of two simultaneous interruption requests described.

Cases in which only a single interruption is required or in which an interruption is already in progress Interrupt program is to be interrupted are treated accordingly and therefore not here further explained. The same applies to other types of interruptions than those selected in the example.

F i g. 5 shows a block diagram of the FIG. 1 , circuit 11 , which is used for the mask operation which is used to determine whether or not a requested interrupt can take place at the present time, ie is allowed. The circuit shown is limited to handling I / O and EXT interrupts requested by the I / O units on channels 120-126 and requested by the external units on channel 127.

As noted, the system mask bits of the active PSW 26 are used to determine whether a requested I / O or EXT interrupt is allowed. If the bit corresponding to the channel requesting the interruption (bit 0 for channel 120, bit 1 for channel 121, etc.) is "1", it means that the interruption is allowed; a "0" would indicate that the interruption must be postponed at least temporarily.

The active PSW 26 is completely stored in the main memory 3. The bits of the system mask are also contained in the associated locking circuits 500 to 507, these circuits being in the on state when the corresponding mask bit is "1" and in the off state when the bit is "0". One of the AND circuits 530 to 537 is provided for each mask bit or for each of the interruption channels 120 to 127. The inputs of these AND circuits are connected to the corresponding interlock circuits via lines 510 to 517 and to the corresponding interrupt channels via lines 520 to 527. An interlock circuit in the on state applies a potential to one input line of the associated AND circuit, which prepares the AND circuit in such a way that a signal coming from the corresponding interrupt channel via the other input line passes the AND circuit. These signals appearing on the output lines 540 to 547 of the AND circuits are used to indicate permitted interrupt requests. The in F i g. The circuit shown in FIG. 5 also supplies signals "interruption requested" (UNT ANGEF) and "external interruption requested" (EXT AN-GEF) on the output lines 57 and 58, respectively, which the circuit shown in FIG. 6 and serve to indicate that an interrupt request of some kind or a request for an external interrupt is present. The signal UNT ANGEF appears at the output of the OR circuit 56, the input lines of which are connected to lines 540 to 547.

Since a plurality of I / O channels 120 to 126 are connected, several I / O interrupt requests can therefore occur simultaneously, a priority order of these channels must be determined, if not all channels with only one exception by the mask bits 0 to 6 of the active one PSW can be defined as unauthorized. However, the circuitry required for this priority determination is no longer described since it does not constitute an essential part of the present invention.

The F i g. 6 shows a block diagram of the FIG. 1 with 10 designated control circuit, which is used to control the various PSW operations required when several interrupt requests occur simultaneously. This circuit determines the order of priority given by the structure of the system in which the various types of interruption programs are executed.

13 14

Block 60 represents the circuits that were requested under the 1st no interruption,

direct control of a sequence of micro-instruction ₂ . A single interrupt request,

the programs to be processed. This ~ ,,,. . , ... ... , _T,. ,

Operations are either ^{terminated by a 3} " \ more simultaneous interruption

of a problem program on line 61.

initiated signal or by a signal on the ". · Ι ι

Line 62; the latter appears after the complete e ι s ρ ι e

Execution of a macro instruction if none Assume that during a macro interrupt request is present, or at the beginning instruction that corresponds to one under the control of Interrupt program. The sequence of microinstructions carried out by the io in the Circuit 60 controlled operations also include plant no interruption conditions occurred the ongoing changes and completions and thus no interruption requests of the active PSW. was presented.

When signals on lines 63 or 64 since no MASCH PRUEF or PROG PRUEF requests for allowed MASCH PRUEF 15 interrupt requests have been made, wel or PROG PRUEF interrupts are indicated before an immediate termination of the microinstruction, circuit 60 causes the would have caused immediate consequences, the last microinstruction ending of the microinstructions being executed in the sequence is used to determine whether there is a request sequence and provides signals on the output lines for an I / O or EXT interruption before -65 or 66. These signals are related to the ones through the 20. The interrogation blocks 80D and 80E shown on the line 68 are sent to the circuit 70. This circuit, which introduces the appropriate interruptions, conducts the already mentioned simple logic function. If an instruction is provided by the programmer to generate one of the output signals YES or NO, a MON-RUF interrupt on lines 71 or 62, respectively. Since initiated, a signal appears on the output 25 that no interrupt request line 67, which is routed to circuit 80C, is present, has caused an interruption required on the input line UNT AN. GEF 57 no signal present, and the circuit 70

The respectively last instruction of a microinstruction sends a signal to the NO output line 62.

tion sequence generates a signal on the output line. This signal is passed to control circuit 60

68, which is used to determine whether during the training 30 and here causes the execution of the next measure

Execution of the micro-instruction sequence a request instruction of the current program,

tion set for an I / O or EXT interruption ". . , '

became. Example 2

Blocks 70 "Interrupt?" And 72 Assume that during execution

"External?" Represent simple logic circuits 35 of a program belonging to a problem program.

represents an I / O interruption from the channel after a signal has been received on the line unrecognized instruction

gen 68 or 71 exercise the following function: 121 (see Fig. 5) was requested and that the

if a UNT ANGEF- or an EXT ANGEF-Si-Bit 1 of the system mask of the active PSW, this

gnal on the input lines 57 or 58 corresponds to channel present, a "1" is and thus the sub-

If this is the case, a signal on the YES output line 40 is defined as being allowed to be broken.

71 and 73 given; if no request signal Since no MASCH PRUEF or PROG PRUEF

is present, a signal is set to the NO-off interrupt requests that

Transit line 62 and 74 generated. an immediate termination of the microinstruction sequence

With 80A to 80E circuits are identified, the last microinstruction of the net, the 45 sequence for the various interrupt types, is used to determine whether a request is EXT, I / O, MON RUF, PROG PRUEF and for an I / O or there is an EXT interruption. MASCH PRUEF under the control of microin- The interrogation signal on line 68 is used to control the following operations: processing 70. Since it was assumed that a completion of the active PSW with information, a request for a permitted interruption was made which the requesting unit and the reason for the 50 were made and this was defined by a signal on the interruption line; Transmission of the active 57 is indicated, the circuit 70 on the PSW from the main memory into one of the "old" PSW-YES output line 71 generates a pulse which is sent to the switching memory locations, this memory location being passed through the device 72. This circuit, which is determined by the on-type of interruption: Storage location occurs when a request for an EXT interruption "old EXT PSW" for circuit 80 A "old I / O 55 receives a signal on line 58, the PSW exercises «For 8OB, » old MON RUF PSW «for 8OC, mentioned function, which the circuit 70 contains» old PROG PRUEF PSW «for 8OD and» old, and delivers a YES or NO-Aus-MASCH PRUEF PSW «For 80 E; Reading out the output signal on lines 73 or 74. Since the new PSW was taken from the memory location of the main memory, there is no I / O interruption that corresponds to the location in which the old PSW was requested Signal on the line chert has been assigned, and transfer of the 58 and an output signal appears on the new PSW in the working memory. After completion, NO line 74. For those shown in FIG. In these operations shown in Fig. 6, an output signal appears in order, this signal means that an I / wire line 68 A, interruption corresponding to circuit 80 has been requested; this becomes clear at 68 B, 68 C, 68 D or 68 E. 65 Hand of the following consideration: a signal on

The operation of the in F i g. 6 shown switching line 57 indicates that a request for a

processing orders is made below on the basis of interruption of any kind, and

three examples explained: since in the present arrangement shown in FIG.

15 16

There are only two different types of interruption, since there are no requirements for MASCH TEST

and further or PROG PRUEF-L interruptions occurred

the absence of a signal on line 58 indicating an immediate termination of the microin-

indicates that the request at hand would not have affected the instruction sequence, the last one is used

refers to an EXT interrupt, it must not- 5 microinstruction of the sequence to determine whether a

maneuverable around a request for an I / O request for an I / O or an EXT sub-

Act interruption. there is a refraction. The query signal on the line

The interrogation of the various types of communication 68 is passed to circuit 70, which, as explained in the order of example 2 in the break request, develops a YES output signal on the increasing urgency of the interruptions on line 71. Executed on the two entrances. In the in F i g. 6 shown arrangement lines 58 and 71 of the circuit 72 signals are only two different levels of urgency available, so that this circuit can also be considered a YES, without the principle output signal on the line 73 to change the method , a further subdivided circuit 8OA is forwarded. This circuit urgency scheme can be used; so could 15 causes the storage of the active PSW in the z. B. the different I / O channels - main memory location "al | es EXT PSW" and the priorities are assigned to which by subsequent transfer of the new PSW, which is required for additional query circuits (corresponding to the circuits 70 and 72 required for executing the EXfr program ) Must be taken into account, from the main memory location »new EXT PSW« can be used. 30 to the main memory. After completing this transfer

Returning to the assumed example: the transmission is carried out, the Si-NO signal developed on line 68 A on line 74 is fed to the gnal circuit of circuit 70 and passed the query operation 805 which repeats the completion of the active ration. Since a second interrupt PSW controls and the transfer of the subrequest is available, there is an old PSW assigned to the program interrupted from the 25 on line 57, and the circuit 70 supplies a YES ^ Alr working memory in the main memory location »old I / O output signal on line 71. As the request for PSW «initiated. Since the query for EXT and the EXT interruption is already taking place through the transfer of the I / O interruption requests at the end of a corresponding PSW to the main memory, contains the active PSW has been taken into account, there is no longer a signal that contains all the information at this time , which leads to the restart 30 line 58, and the circuit 72 develops the interrupted program after a NO output signal on the line 74. This termination of the interrupt program required indicates, as already explained, that a request is made. In addition to the storage of the active PSW for an I / O interruption, and the old PSW in the main memory are no expansion 80 B controls the storage of the old PSW ren data transfer or storage operations in the main memory location »old I / O PSW «. It will be necessary. It is then further pointed out that this old PSW is the new PSW YQn of the control word assigned to the program, which is controlled by the circuit 80 B , the new PSW YQn is the control word required for the I / O not yet executed EXT interruption protocol subroutine. This PSW main storage location "new I / O PSW" read out contains all the information that is required to be transferred to and from the main memory. 40 the execution of the EXT interrupt routine

After these PSW transmissions have been carried out, an initiation is made as soon as the output signal on line 685 is transferred to the main memory again. This is done, as directed further below by device 70 and as explained above, is repeated after the I / O operation has been completed. Since it has been assumed, the interrupt program which, compared to the EXT, is that no further interrupt requests are made. An interruption of higher urgency.
After the old (EXT) PSW has been stored, output line 62 is generated and the new one for the I / O interruption program is passed on to circuit 60, which in turn requires the execution of the I / O PSW from the main memory location »initiates a new interrupt program. I / O PSW «read out and into the working memory

After completion of this subroutine, 59 is transferred.

If no further interrupt is requested After this operation has been completed on the line, the active PSW, which is the signal appearing on I / O 685, is given to the PSW associated with the circuit interrupt program in 70, and the query operation again becomes the main memory location "New I / O PSW" repeated. Since it was assumed that no further storage was made, and the PSW, which the interrupt requests for the resumption were made, would take the interrupted problem program, a signal appears on the NO output line contains necessary information , routed to circuit 60, read out the "old I / O PSW" execution and initiate that of the I / AT interrupt program.
Working memory transferred, then after the completion of the I / O interrupt pro execution of the problem program is continued. 6q gramms and assuming that no further. Interrupt requests have occurred, will ^B ? I ^s Vl? ¹ 3 the active (I / O) PSW in the main memory location

It. Assume that "new I / O PSW" is stored during execution and the PSW for a measure belonging to a problem program - the EXTr interrupt program from the memory instruction read out two requests for interrupter 65 “old I / O PSW” and the different urgency, namely working memory supplied. This is followed by the execution an I / O and for an EXT interruption, execution of the second interrupt program,

entered and were determined to be allowed. After completing this program and again

deruin assuming that no further interrupt requests occurred, the now active (EXT) PSW is stored in the main memory location »new EXT PSW «and the PSW that is required for resuming the interrupted problem program contains the required information, taken from the "old EXT PSW" storage location and entered into the working memory. The interrupted problem program is then executed continued.

In the case of the method described, several interrupt requests are made at the same time the corresponding PSW occur in the order of increasing urgency of the subroutines stored, the PSW with the lowest priority is taken into account first; however, the Execution of the subroutines in the opposite order, d. H. the subroutine Urgency is carried out first.

With the help of the specified procedure, it is also possible to take interruption requests into account, which occur during the execution of another type of interrupt routine. if the requested second interruption has been determined to be allowed, the system enables the interruption of the running first interrupt program.

From the foregoing it can be seen that as soon as the monitor program executes a Interrupt program initiated and started, this subprogram is not carried out by a subprogram of the same type may be interrupted. If this were allowed, then all information would be get lost via the interrupted, originally running problem program because the PSW assigned to the first interrupt program would be entered into the "old" PSW memory location that already had the PSW of the original Contains problem program. This situation can be avoided by suitable application of the mask bits PSW can be prevented: this is, for example, the interruption requests that occur one after the other in order to I / O interruptions, the system mask of the new I / O PSW corresponding to the first interruption program must all of Define interruptions requested by other I / O channels as not permitted. That way you can no further I / O interrupt can be initiated before the currently executing I / O subroutine has been completed.

MASCH PRUEF and PROG PRUEF interruptions are activated immediately after the occurrence of the Interruptions requiring conditions initiated. Again, this becomes the control of what is to be interrupted The old PSW serving the program is transferred to the main memory and the new one for the Execution of the interrupt program required PSW entered into the working memory. The same applies to the MON RUF interruptions, which only differ in that they are through macro instructions provided by the programmer are initiated.

The by the in F i g. 6 shown structure of the system predetermined order of priority can easily can be changed by using the options given by the masks contained in the PSW exploits. Should z. B. an interrupt program that has a lower priority according to the circuit has, as a second, simultaneously requested interrupt program, before this second Interrupt program of higher priority get to be executed, you can use the mask bits of the PSW corresponding to the lower priority subroutine, which is the first in the working memory is entered, select the channel corresponding to the channel requesting the higher priority interrupt Mask bit is made "0", which defines this interruption as not allowed will. This gives a very versatile and easily variable interruption method that Interruptions of varying urgency in one determined by the programmer or the program Order allowed to execute.

Claims (2)

Patent claims: 1. Data processing system with priority-controlled program interruption, with a Active program status word register (PSW register) for the inclusion of the current program descriptive data (program status word) and with a control circuit for control of the program sequence and for receiving interrupt requests through several inactive PSW registers for the simultaneous recording of data available for description if necessary Subroutines or interrupted programs by the control circuit (60) excitable to initiate a subroutine of different priority, known per se Control devices (80) which are each assigned to a subroutine in a known manner and which also supplement the active program status word when excited, in the relevant Save the inactive PSW registers assigned to the subroutine and this subroutine Transfer the assigned program status word to the active PSW register. 2. Data processing system according to claim 1, characterized in that each available subroutine is assigned a pair of registers (4OD to 40 /?), One of which registers (z. B. 40DI) is provided for receiving the program status word associated with the program to be interrupted and the other (e.g. 40 DII) contains the program status word belonging to the interrupting subroutine and to be transferred to the active PSW register, with the program status word of the subroutine initially considered from the active PSW register again if another higher priority interrupt request is present and entered into one register (e.g. 40 £ 111) of the register pair assigned to the second subprogram (e.g. 40E) and from the other register (e.g. 40 £ IV) of the second register pair that of the second subprogram associated program status word is transferred to the active PSW register and that further simultaneous interrupt requests orders are treated in the same way and the requirements are broken down in the reverse order. For this purpose 2 sheets of drawings