DE1437187C - Method and circuit arrangement for decoding binary pulse signals - Google Patents

Description

1 2

The invention relates to a method and one of the only ones provided by the output signal Circuit arrangement for decoding binary bistable one-pulse signals influenced by the transmission line at the output of a transmission multivibrator in a specific, as a sampling block line is determined with the aid of a bistable designated number of scanning cycles on the receiving side, Input flip-flop. 5 where each of the impulses entered on the transmitter side

The cause of the loss of data when an odd number of data is transmitted on the receiving end from a transmitter about one convinced sampling cycles, and that the am The transmission channel to a receiver can in the rough position most frequently occurring in a sampling block see or glitches detected on the transmission line of a bistable input multivibrator or in the event of a loss or failure of the synchronization io and the binary value corresponding to this position between the clocks on the send and receive is stored.

catcher side exist. The last case can occur, a circuit arrangement for implementing the

if either the clock is not initially syn- the method according to the invention is thereby marked or if one of the clocks records that a single one, under control of a runs faster than the other. 15 clock generator standing bistable input multivibrator

Considerable efforts are being made, which are undertaken on the input side to reduce the noise and interference voltages on the transmission line and on the output side via a logical transmission channels, but switching with a first counter for the "ON" - will be impossible , evaluate all these interfering influences and switch them on with a second counter for the »OFF«. A sensible solution to this problem is connected with 20 values, and that output pulses of the is to be seen in a device at the receiving counter via a decoder and the logic switch, which the data pulses from processing at a first certain amount (n + 1) in Differentiates between noise and interference pulses. one of the counters in the bistable input

It has already been proposed that the data signal, multivibrator, indicated by their position in binary Allow disturbances in the form of undesired short-term values to be transferred to an accumulator and Temporary level changes or level jumps in that when a second certain impairment is reached or · contains several bit intervals, with a sluggish one for the sum of the counter readings (2 «+ 1) of the Sampling frequency to be sampled, the resetting of the counter to zero by the duration of the two counters Disturbance and the data speed or data occurs.

repetition frequency is determined. The resulting 30 further refinements of the invention are shown in FIG Samples are then stored and subsequently included in the subclaims. The procedure ßend in a logic gate circuit to a pre- according to the invention and an arrangement for the transmitted Character grouping examined, the conduct of the procedure will now be on hand The presence of a fault is displayed. of the drawings. It shows

The synchronization of the clock in the transmitter 35 F i g. 1 a simplified block diagram of the recipient and recipient before the start of a data transmission order on the recipient side,
Generation is often carried out by transmitting certain im- Figs. 2A and 2B a diagram of the function pulses or pulse combinations. The processes,

Data transmission must then be determined in accordance with FIGS. 3A to 3C, a detailed block diagram

th periods of time are interrupted to allow additional 40 of the arrangement,

to transmit borrowed synchronization pulses and F i g. 4 a block diagram of the clock generator,

to re-synchronize the clocks. Another fig. 5 a pulse diagram of the required cycle

The solution is to add an additional transmission pulse and

supply channel available via the clock F i g. 6 pulse diagrams of the data pulses

impulses are transmitted. All of these measures 45 the transmission line at too fast and too are uneconomical and expensive. slow clock on the sending side.

It is the object of the invention to provide a device from FIG. 1 it can be seen that input data for receivers of data pulses is created, the pulses on the transmission line 10 as a setting is able to keep the value of the data pulses despite the input signal of the input multivibrator (LBT) 12 to the relatively high noise voltage and despite interference pulses 50 . If the pulse level on the over on the transmission channel can be determined properly. transmission line 10 is high, LBT12 is brought into the ON-The provision of a special synchronizing state, and if the pulse level on channel or special synchronizing combinations, line 10 is low, LBT12 is in the OFF-the before and during the actual messages - Condition brought. LBT12 will be in the transmission OFF state, should be avoided 55 reset by a clock pulse that will be the clock. Furthermore, the device 90 should also be in the scanning state at a suitable point in time in the event of reception level disturbances which are fed to the line 14 during the cycle. The point in time of the application of this clock pulse, which extends over more than one or two sampling cycles, and the manner in which it is applied based on a majority decision with more certainty are described below. The probability base still finding the correct 60 output line 16 of the LBT12 leads to an in-received signal value. In contrast to a logic circuit 18 and as information about the state of the art, it is particularly advantageous to have a mation input to AND circuits 20 and 22. That, according to the method according to the present signals on line 16, data pulses still correctly show the state of the invention off- LBT12 on. The logic circuit 18 is a goal that can be rated in its time length 65 circuit, the output signals are disturbed to one or more to almost 50%. reren output lines generated when different

The method according to the invention solves the predetermined settings of the switching toggle positions Task in that the respective position steps and counters are determined, which the switching

device can be supplied as input signals. A gate circuit suitable for this purpose is shown in FIG. 3B shown and will be described later.

An excitation pulse for the AND circuit 20 is a clock pulse from the clock generator 90 on line 24, and the second excitation pulse for this AND circuit is the output line 26 of the logic circuit 18. The output line 28 of the AND circuit 20 brings the "earlier sample" «Flip-flop (PST) 30 in the same state as the LBT 12. The output line 32 of the PST 30 is connected to the logic circuit 18 as a second input.

An excitation pulse for the AND circuit 22 is a clock pulse from the clock generator 90 on line 34. The second excitation pulse for this AND circuit comes via the output line 36 from the logic circuit 18. The output line 38 of the AND circuit 22 is an adjustment input line the “earlier bit” flip-flop (PBT) 40 and connected to the accumulator 42 as an adjustment and shift input line. Therefore, when the AND circuit 22 is fully energized, the contents of the LBT are inserted into the PBT40 and into the first digit of the accumulator 42, and the remaining bits in the accumulator 42 are shifted one place to the left. The accumulator 42 is a common digit shift register. The output line 44 of the PBT 40 leads as a third input to the logic circuit 18. The content of the accumulator 42 is fed to a decoder 48 via lines 46. The decoder 48 is connected in such a way that it recognizes the various characters contained in the accumulator 42 and generates output signals on the lines 49 which indicate which characters are involved.

A fourth flip-flop in the circuit is the cycle control flip-flop (CCT) 50. This flip-flop is turned ON by a signal on line 52 and reset by a signal on line 54. Line 52 is the output line of AND circuit 56, the inputs of which are clock pulse line 58 and output line 60 of logic circuit 18. The reset line 54 is the output line of the AND circuit 62, the inputs of which are the clock pulse line 64 and the output line 66 of the logic circuit 18. The output line 67 \ 5 of the OUT side of the CCT50 leads as a fourth input * |; to the logic circuit 18.-

The output line 68 of the logic circuit 18 is the clear line for the I. counter 70 and for the II. Counter 72. The counter I counts the "up" sampling pulses obtained during a sampling cycle, and the counter II counts the "up" sampling pulses received during the same sampling cycle. Low "sampling pulses. The output lines 74 and 76 of the first and second counters are connected to the logic circuit 18 via the decoder 78 and the line 80 as the fifth input. The decoder 78 is a gate circuit which generates output pulses at predetermined counts in the I. and II. Counters 70 and 72. A suitable decoder shown in Figure 3C is discussed further below. The output line 82 of the logic circuit 18 is the relay line for the I. counter 70, the II. Counter 72 and the III. Counter 84. Counter III counts the successive equal sampling pulses derived from the signal on transmission line 10. By means of a signal fed to line 82, one or more of the counters are incremented after each sampling of the input pulse stored in LBT12. The output line 86 of the logic circuit 18 is the setting line for the counters 70, 72 and 84. When a signal is fed to this line, either the counter I or the counter II is brought to the count 4 or the counter III to the count 1 . The output line 88 of the counter III leads as the last input to the logic circuit 18. A signal on line 88 means that the counter III has the count 4.

The various used to control the setting of the multivibrators and counters in the circuit Clock pulses are generated by the clock circuit 90. This circuit produces six independent clock pulses and a clock pulse that is the length of three of the independent clock pulses has during each scan cycle. Seven sampling cycles run for each data pulse cycle. the The duration of a data pulse cycle is equal to the duration of a normal data pulse. One to generate The circuit suitable for the required clock pulses is shown in FIG. 4 and will be explained later.

Figs. 2A and 2B form a logic flow diagram; this shows how the circuit shown in Fig. 1 operates to determine the value of a binary input pulse to determine and how the circuit itself remains capable of receiving these input pulses detect when the clocks in the transmitter and receiver are out of phase.

The sequence of operations shown in Figs. 2A and 2B expires during a single scan cycle, and seven such duty cycles find normal for each Data pulse instead. The duration of a normal data pulse is hereinafter referred to as the data pulse cycle designated.

Looking at FIGS. 1 and 2A together, it can be seen that the first clock pulse T1 from the clock generator 90 is used to control the pulse on line 10 into the LBTV1 . Therefore, at the beginning of each sampling cycle, the LBT12 is set according to the current value of the signal on the transmission line 10. When the line level is high, the LBT 12 is brought into the ON state, and when it is low, the LBT12 remains in the OFF state. Between clock pulses 1 and 2, logic circuit 18 performs several different tests. From the loop on the left in FIG. 2A it can be seen that the logic circuit checks whether the counter I or the counter II has the count 4. If one of these counters has a count of 4, the value of the data pulse has already been determined and the remaining samples are only taken to complete the data pulse cycle. The logic circuit recognizes the end of a data pulse cycle when the sum of the counts in counters I and II is equal to 7. In order to simplify the required detection circuit, a 7 is only recognized if one counter is set to 4 and the other counter is set to 3. Therefore, looking at the circuit loop on the left in Fig. 2A, it must be remembered that if either counter is at 4, then the value of the data pulse has already been determined and that if either counter I or counter II has exceeded a count 4, the circuit for detecting the end of the data pulse cycle does not operate. Hence

the counter II is incremented by 1 at time Γ 2 when the counter I is at 4 and thus indicates that the data pulse on line 10 has a high level. Likewise, the counter I is incremented by 1 at time T 2 when the counter II is at 4 and thereby indicates that the data pulse has a low level. If no 4 is stored in either counter I or II, the value of the data pulse currently being sampled has not yet been determined, and at time T 2 the counter I is incremented when LBT12 is turned ON, and the counter II is incremented when LBT12 is in the OFF state.

Simultaneously with performing the above checks, logic circuit 18 also checks whether the setting of LBT12 is equal to the setting of PST 30. If the previous sampling and the current sampling coincide (that is, if the contents of PST and LBT are the same), the counter III is incremented by 1 at time Γ2. If, on the other hand, the current and previous samples are different (ie, if LBT and PST do not match), counter III is reset to count 1 at time 7 * 2. In addition, if LBT and PST do not match, a signal is applied to line 26 at time T3, as a result of which AND circuit 20 is fully energized and enables PST to be set to the value of LBT . The meaning of both of the above operations is to indicate that a continuous scan of the value now stored in PST (the value of the scan just performed) has taken place.

As far as the “yes” output of the “ LBT test equals PSTÄ circuit” is concerned, after the counter III has been advanced at time T2, the logic circuit 18 checks whether a 4 is stored in counter III. If the counter III is at 4 at this point in time and CCTSQ is in the OFF state, and it is determined that LBT is not equal to PBT , then at time T3 the logic circuit 18 generates a signal on line 68 which the counters I and II resets to 0. After counter I and II have been cleared, the state of LBT12 is checked, and if this flip-flop is in the ON state, counter I is set to 4 at time Γ 4. If, on the other hand, LBT is in the OFF state, the counter II is set to 4 at time T 4.

The operations described above enable the circuit to correctly identify the value of input data pulses even when the transmitter and receiver clocks are out of phase. At the end of each data pulse cycle, counters I and II are cleared. Thus, if the transmitter's clock is running faster than the receiver's clock (the receiver's clock being the reference clock) so that part of a second data pulse is received during the data pulse cycle of the previous data pulse, one or more of the later samples of the previous data pulse cycle will occur actually in relation to the new data pulse. These samples are lost when counters I and II are cleared. The counter III, however, determines the number of consecutive samples of a given value and is not reset at the end of a data pulse cycle. Therefore, if one or more samples of the new data pulse that have taken place during the previous data pulse cycle are the same and the first samples during the new pulse's own sampling time are the same as those taken during the previous sample pulse cycle, the counter III indicates that four consecutive Samples of the same value have been obtained. If the previous bit is the same as the new bit, this check is irrelevant because all samples are the same. Therefore this test is only carried out if the new bit and the previously sampled bit are different; a necessary precondition for this test is therefore a mismatch between LBT and PBT. When the counter I or the counter II is 4, the value of the new data pulse has already been determined by the normal means used by the circuit and the above-described operation is unnecessary. This check is therefore only carried out if CCT, the flip-flop that is set when either counter I or counter II is set to 4, is in the OFF state.

If the right conditions exist, the circuit clears counters I and II and then sets the counter corresponding to the value stored in LBT to 4. This makes the circuit inevitable synchronized by assuming that the first sample of the detected by the counter III consecutive samples is the first sample for a new data pulse.

Between time T4 and T5, the logic circuit 18 checks whether the counter I or the counter II is at 4. If it has already been established.

that one of these counters was at 4 during the same data pulse cycle, CCT5Q is in the ON state, and since the three operations which, as explained above, are to be carried out at time T5 , have already been carried out, they do not need to be carried out again. At time T5 , the three operations are therefore only carried out if CCTSQ is in the OFF state and either counter I or counter II is at 4. To perform the first operation, a signal appears on line 36 (FIG. 1) which fully energizes AND gate 22 and produces an output signal on line 38 which sets the value of LBT 12 in PBT 4Q . In addition, the signal on line 38 inserts the value in LBT12 into accumulator 42 and causes the remaining data in the accumulator to be shifted one place to the right. Eventually, logic circuit 18 produces an output on line 60 that fully energizes AND gate 56 so that it produces an output on line 52 that brings CCT 50 ON. The above operations are carried out regardless of how the count 4 got into the counters I and II. They are therefore executed when the counter has been switched on by successive switching signals on lines 82 to 4 or the counter has been set to 4 by a signal on line 86 as a result of the determination of count 4 in counter III.

The last test to be carried out in each sampling cycle takes place between T4 and Γ6, when the sum of counters I and II is fed to logic circuit 18 via line 80 from decoder 78 and it is determined whether the sum is equal to 7

is. When this sum is equal to 7, a signal is generated on line 68 (FIG. 1) at time T 6 which clears counters I and II, and a signal is generated on line 66 to full AND gate 62 energized so that it generates a reset signal on line 54 which resets the CCTSO to the OFF state. The above sequence of operations terminates the data pulse cycle and initiates the next.

At time T 6 of each sample pulse cycle, clock 90 (FIG. 1) puts a clock pulse on line 14 which resets LBT12 to the OFF state. In order to further illustrate the operation of the circuit of FIG. 1, it is assumed that with synchronized transmitter and receiver clocks and without noise signals on the line, the received signal corresponds to that shown on line (a) of FIG. It is also assumed that the transmitter's clock is running faster than that of the receiver and that noise signals are on the line, so that the received signal corresponds to that on line (b) of FIG. 6 corresponds to that shown.

It is assumed that a sample taken on a pulse transition will cause the LBT12 to be set to the value of the pulse which is about to terminate. Therefore, the first sample is taken from the first in FIG. 6 at time 51.

In the following description, the term "time Si" means the time for the / th sample cycle when seven sample cycles elapse for each normal data pulse cycle, and time Ti is the time at which the clock pulse generates / from the clock 90 during one sample cycle will. There are six Tz times for every Si time.

At the time 51, a high level is on the transmission line 10. Therefore, the LBT12 the time Tl in the ON state is provided. If it is assumed that at the beginning of the 51-sampling cycle all flip-flops are in the OFF state and all counters are cleared, all tests which are carried out before time T2 (FIG. 2A) of sampling time S1 give negative results. Therefore, at time T 2, the counter I is incremented by 1 and the counter III is reset to the value 1. At time T 3 there is a signal on line 26 which energizes AND circuit 20 to set the PST to the value of the LBT (ie, ON). Nothing else happens during the scan cycle. Only after the time T 4 is checked whether the counter I or the counter II is 4. Since none of these counters is 4 and since the sum of the counts in them is not equal to 7, nothing further happens during the 51 cycle until time Γ 6 when the clock generator 90 gives a signal on line 14 to switch LBT OFF - Reset the condition. Since LBT is reset to the OFF state at time T6 of each sampling cycle, it is believed that this operation is taking place. It is no longer specifically mentioned in this section.

A spike of smoke now occurs causing the sample to hit a low level at time 52. Therefore, LBT12 remains in the OFF state at the beginning of this sampling cycle. Even now, neither counter I nor counter II is set to 4, so that the counter corresponding to the setting of LBT12 is incremented. In this case, the counter II is switched to level 1. Since the previous sample was a high level and the current sample is a low level, the settings of LBT and PST are different and therefore the counter III is reset to 1 at time Γ 2 and PST is OFF at time Γ 3 - Condition brought. Here, too, all further tests fail and no further operations are carried out during this sampling time.

The 53 scan will now find the received signal high and cause LBT12 to be turned ON. As a result ίο the counter I is switched to the level 2, the counter III remains at the level 1, and Ρ5Γ30 is brought into the ON state.

At the 54 scan, the received signal is high again and therefore LBT12 is turned ON. As a result, the counter I is incremented to 3 and the counter III to 2. All further tests fail and no further operations are performed during this scan cycle.

As already indicated, sampling that occurs on a transition causes LBT12 to be set to the value of the previous pulse instead of the value of the new pulse. Therefore, a scan performed at time 55 will cause LBT12 to go ON. Therefore, the counter 1 is incremented to 4 at time T2 , and the counter III is incremented to 3. Since CCTSO is OFF when the counters are checked after the time Γ 4 and it is found that the counter I is at 4, output signals on lines 36 (FIG. 1) and 60 from the logic Circuit 18 generated. At time T 5, the signal on line 36 fully energizes AND circuit 22, so that the contents of LBT 12, a high voltage level, are fed to PBT 40 via line 38 and are also stored in accumulator 42. The signal on line 60 brings the CCTSO to the ON state via AND circuit 56 and line 52. Therefore, the first pulse was correctly recognized, although it is more than 28% shorter than it should be and also contains a noise spike. At time S 6 , the transmission line 10 is low, and therefore the LBT12 is brought into the OFF state. Since the sum of the numbers in counters I and II does not equal 7, these counters have not been cleared. Therefore, before time T 2, a test indicates that counter 1 is at 4, and therefore counter II is incremented from 1 to 2 at time Γ 2. In addition, before time T 2, a check indicates that the contents of LBT12 and PST 30 do not match, so that counter III is reset to 1 at time T 2. At time T3, a signal appears on line 26 ( Fig . 1) which energizes AND gate 20 to transfer the contents of LBT12 to PST30. The PST30 is therefore brought into the OFF state. After the time T 4, the counter I is checked and it is found that it is 4; but since CCT is now in the ON state, no operations are taking place at time T 5. Since the sum of the numbers in counters I and II is only equal to 6 during this sampling cycle, counters I and II and the CCT are not reset at time Γ 6.

At time 57, the transmission line 10 is low, and therefore the LBT is returned to the OFF state. Since the counter I is still at 4, the counter II is switched to the next at time T2, and so is the previous one

009 552/97

Sampling was a low level, the counter III is switched to 2. Since the counter III is only 2, no operation takes place at time T 3. However, if the sum of the numbers in counters I and II is checked now before time T 6, it is found to be equal to seven. Therefore, at time T 6, logic circuit 18 produces an output on line 68 which clears counters I and II, and also produces an output on line 66 which fully energizes AND gate 62 so that it has an output on line 54 is generated which resets the CCT50 to the OFF state. At the end of the first data pulse cycle, two scanning cycles of the second data pulse have already passed. In the course of the description of the mode of operation it will be seen that this does not cause a problem in the correct determination of the data pulses supplied via transmission line 10.

The scanning carried out at time 58 brings the LBT12 back into the OFF state. Since none of the counters is now at 4, counter II is incremented to 1 at time T 2, and since LBT is equal to PST , counter III is incremented to 3. All further tests fail during this scan cycle and no further operations are performed.

At time S9 , the LBT is brought back into the OFF state at time Π. Therefore, the counter II is switched to 2 and the counter III to 4 at time T1. Between time 2 and time 3, the counter III is checked and the count 4 is determined. Since the CCT is in the OFF state and LBT is not equal to PBT (because LBT is in the OFF state and PBT is in the ON state), at time T2> a signal is given by the logic circuit 18 on the line 68 to the counters I and II to delete. Since the LBT is in the OFF state, a signal is sent to line 86 at time T4 , which advances counter II to 4. It is then determined by a test that the counter II is at 4, and since the CCT is still in the OFF state, signals are again sent from the logic circuit 18 to the lines 36 and 60 at the time T5. The signal on line 36 causes the PBT40 to be brought into the state of the LBT12 (OFF state) and that the OFF level is applied to the lowest digit in the accumulator 42, while the remaining data in the accumulator is shifted to the left. Eventually, the signal on line 60 through AND gate 56 and line 52 brings the CCTSO to the ON state. The second data pulse is therefore correctly recognized as an OFF level.

At time TX of sample cycle 510, the LBT 12 is again set to the OFF state, the transition being recognized as the value of the expiring pulse. Since the counter II is now at 4, the counter I is switched to 1 at time Γ 2. Since the CCT 50 is ON, no further operations are performed during this scan cycle.

At time 511, the signal on transmission line 10 has gone ON, and therefore the LBT is turned ON at time T1. Since the counter II is still at 4, the counter I is switched to 2. Since LBT is now not equal to PST , the counter III is also reset to 1 at time T1, and the PST is set to the value of LBT , namely brought into the ON state at time T3. These are the only operations performed during scan cycle 511. At time T1 of 512, the LBT is switched back to the ON state, and since counter II is still at 4, counter I is switched to 3 at time T1. Since LBT is now equal to PST , counter III is switched to 2 at the same time. Before the time T 6 , it is determined by a test of the counters I and II that their sum is now equal to 7.

Therefore, at time T 6, these counters are cleared as described above, and the CCT is reset to the OFF state. This ends the data pulse cycle for the second data pulse. As before, this termination takes place after two sampling pulse times of the next data pulse have elapsed. However, it can be seen that the circuit is no further "OFF" as it was at the end of the previous data pulse cycle and that the circuit operates so that even if the clocks are out of phase, the sampling pulses are never out of phase by more than two sampling pulses, as many Data pulses are also sent.

At the end of sampling time 12, counter III is at 2. This reading becomes 13 during sampling time increased to 3 and increased to 4 during sampling time 14. The circuit therefore recognizes the third data pulse correct as the ON level during the 14th sampling time and corrects the counts in counters I and II to trying to re-synchronize the signals sent and received.

The detection of further impulses is carried out in the same way as has been described above. While for that on line (b) of FIG. 6 can tolerate very little noise in order to still get accurate results, remember that in this example the transmitter and receiver clocks are almost 30% out of phase. This is an enormous phase error that is very unlikely to occur in a normal transmission system. Phase errors of 2 or 3% are usually encountered.

Line (c) of FIG. 6 shows the received signal when the clock generators of the transmitter and receiver are again about 30% out of phase, but now the clock generator of the transmitter is running more slowly. According to FIG. 2 and 6, the sampling carried out at time 51 has the effect that counters I and III are incremented to 1. The scans carried out at times 52 and 53 cause these counters to increase equally, so that at the end of time 53 counters I and III are each set to 3. The noise spike at time 54 causes counter II to increment by 1 and reset counter III to 1. At time S 5 , the signal on the transmission line has again reached the high level, and therefore counter I is incremented to 4 and the counter III leave at 1. The advancement of the counter I to the level 4 has the effect that at time 75 the PBT goes into the ON state, an ON level is shifted into the accumulator42, with the remaining data in the accumulator being shifted one place to the left, and the CCT goes into the ON state. The result of these operations is the correct identification of the first data pulse as an ON value. Since counter I is at 4 at time T1 of S 6 , counter II is incremented to 2, and counter III is also incremented to 2. At time 57, counter II and counter III are each set to 3

forwarded. Since the sum of the numbers in counters I and II is now 7, these counters are cleared and the CCT is reset to the OFF state. This ends the first data pulse cycle. Its termination therefore takes place two sampling cycles before the end of the first data pulse. However, this does not prevent the later data pulses from being correctly recognized.

At time 58 the LBT is again in the ON-Zuder counter III to 4, the CCT is in the OFF state, and the LBT is not the same as the PBT. Counters I and II are therefore cleared during time T3 of this sampling cycle, and counter I is set to 4 during time T4. This allows the third data pulse to be recognized as an ON voltage level and causes the circuit to be resynchronized. More data pulses on line (c) in FIG. 6 are recognized in the same way as it was above for the first

stood brought; therefore the counter I is set to 1 and ao three data pulses has been explained.

the counter III switched to 4. Between times Γ 2 and Γ 3 of this sampling cycle, the counter III is at 4, and the CCT is in the OFF state. However, the LBT and the PBT are both in the ON state. Therefore, at the time T3, neither the counter reset to 0, nor the counter I is brought to the state 4 at time T 4th At time 59 the counter I is switched to 2 and the counter III to 5. At time 510, the signal on the transmission line 10 has reached the low level so that the LBT goes into the OFF state. Therefore counter II is incremented to 1 and counter III is reset to 1. During the sampling cycles at time 511 and 512, counters II and III are each incremented, so that at the end of time 512, counters II and III both have count 3. At time 513, counters II and III are both switched to 4. Between time Γ 2 and T 3 of the sampling cycle 513, the counter III is at 4, the CCT is in the OFF state, and the LBT is different from the PBT. Therefore, at time T 3, counters I and II are cleared, and at time Γ 4, counter II is brought to count 4. This operation causes the reading 2 previously stored in counter I to be recorded. 3 A and 3 B form a detailed circuit diagram of the selected exemplary embodiment of the invention. The same elements are shown in FIG. 1 and 3 A to 3 C are denoted by the same reference numerals, and the circuit arrangements for the logic circuit 18 and the decoder 78 in FIG. 3 B and 3 C are bordered with dashed lines in order to facilitate the mutual assignment of these two figures.

According to FIG. 3 A are the data pulses on the transmission line 10 via a voltage level adjuster 100 and the line 102 are fed to the pulse driver 104. The level adjuster 100 must in general the voltage values of the transmitted signal to those for the setting of the multivibrators in bring the required voltage level to the circuit. The pulse driver 104 and the other pulse drivers in the arrangement are AND circuits that have an output signal only on the leading edge of the Generate impulses which fully excite them. Therefore, these circuits generate an output voltage spike, which is ideally suited for setting a flip-flop and prevent certain timing problems from occurring

lifted. The currently executed data pulse cycle 35 th, if not such pulses for setting the is therefore initiated at time 510, the point in time when flip-flops would be used. Such a circuit at which the first sample counted by counter III occurred. Since the first sample of the

second data pulse actually at time 510 the PBT is set to the value of the LBT , ie brought into the OFF state, a low level is fed into the accumulator, and the CCT becomes

can be formed by connecting a coil in series with at least one of the inputs of a conventional AND circuit. The following is, at this point the circuit is correct 40 output line 106 of the pulse driver 104 is synchronized on. At time Γ5 of sampling cycle 513, the ON input of the input flip-flop (LBT) 12

connected. The other input of the pulse driver 104 is the T1 clock pulse line IOS. Line 108 is one of the seven outputs of the clock switched to the ON state. Therefore the 45 encoder recognizes 90. Its other outputs are a Tl circuit, the second data pulse correctly as an OFF clock pulse line 109, a JS clock pulse line voltage level. HO, a r4 clock pulse line III, a T5 clock

Since the counter is at 4 II, is pulse circuit 112 during the time, a Tö clock pulse line 113 the scanning cycles Tl 514.515 and 516, the counter I, and a T4-r6 clock pulse line 114th
switched from 0 to 3. Before time Γ 6 of the down 50 The r6 clock pulse line 113 represents a keying cycle 516, it is determined that the sum of the j *> outputs for the pulse drivers 118 and 120 is. The on counts in counters I and II equals 7 , and i ',. The input of the pulse driver 118 is a signal which is continuously interrupted at time T 6 and has an ON voltage level which is deleted and the CCT is reset to the OFF state. i. £ l source 122 generates on line 123. Therefore, the In-The second data pulse cycle thus is two sample 55 pulse driver 118, an output signal on line 124 cycles, before the end of the second data pulse, the LBT always loading in the OFF State ends. It is known that the first data pulse is also switched when a clock pulse on line 113 has been terminated two sampling cycles too early. to be led. The output line 16 a of the EIN-side therefore keeps the circuit a good synchronization of the LBTIl is as an information input to the AND upright, even if the clock of the transmitter and 60 circuits 128, 130, 132, 134 (Fig. 3 B), 136, 138 recipients are nearly 30% out of phase.

During the sampling cycles 517 and 518, the counters II and III are incremented to two. During scan cycle 519, counter I is incremented to 1 and counter III is reset to 1. During the sampling cycles 520, 521 and 522, the counters I and III are incremented from 1 to 4. Therefore, after the time T1 of the sampling cycle 522 and 140 is connected. The output line 16 b of the OUT side of the LBTlI is connected as an information input to the AND circuits 144, 146 (FIG. 4B), 150, 152 and 154. .

The output line 67 of the OFF side of the cycle control multivibrator (CCT) 50 is connected as an input to the AND circuits 158 (FIG. 3B) and 160.

13 14

The output line 32α of the IN-side of the AND circuit 140 is connected as an excitation input to the earlier sampling flip-flop (PST) 30 is connected as a two-pulse driver 226 (FIG. 3C). The Auster input to AND gate 136 (Fig. 3B) output line 228 of AND gate 154 is connected as Er. The output line 326 of the OFF excitation input is connected to the pulse driver 230. Side of the PST 30 is connected as a second input to the AND- 5 The other input for the pulse driver 226 and circuit 150 (Fig. 3B). The output 230 forms the r4 pulse line 111. The output output lines 166 and 168 of the AND circuit line 232 of the pulse driver 226 is connected to the counter 136 and 150 as inputs to the OR switch I that a Pulse on line device 170 connected. The output line 172 of the 232 brings the counter I to the level 4, and the OR circuit 170 is connected as an excitation input to the io output line 234 of the pulse driver 230 so that the pulse driver 174 (FIG. 3 C) is connected. How to connect to the counter II, that the counter II will still be seen, this is the onward switching line can be switched from to the state 4, the logic circuit for the counter III. The other The output line 236 of the IN side of the 1-

The input of the pulse driver 174 forms the T2 clock flip-flop 238 of the counter I is as an input to the pulse line 109. Line 109 is also connected as a 15 AND circuit 240. The output input to the pulse drivers 176, 180 and 184 instructions 242 of the IN side of the 2-flip-flop 244 of the closed. The output line 188 of the pulse driver counter I is the second input to the AND switch 174 the relay line for the counter III, 84th device 240 is connected. An output signal appears The OR circuit output line 172 is simultaneously on lines 236 and 242 when im 170 (Fig. 3B) is also at the input of the inverter 20 counter I a 3 is stored. The third entrance ters 190 connected. The output line 192 of the AND circuit 240 forms the output line Inverter ISO splits up and forms the lines 246 of the IN side of the 4-flip-flop 248 of the counter 194 and 26. The line 194 is the second input lers II. Therefore, the AND circuit 240 is energized, connected to pulse driver 176 (Fig. 3C). to generate an output on line 250, The output line 196 of the pulse driver 176 is 25 when the counter I is at 3 and the counter II is at 4 so connected to the counter III that there is a pulse. The output lines 252 and 254 of the IN-on this line sets the counter to the count 1 side of the 1-flip-flop 256 or the 2-flip-flop 258 brings. Therefore the line 194 is the »Counter III on the counter II lead to two inputs of the AND-1 «Output line of the logic circuit 18. Circuit 260, the third input of which is the output

The line 26 is connected as an excitation input to the Im- 3 ° line 262 of the 4-flip-flop 264 of the counter I, pulse driver 186 (Fig. 3A). The AND circuit 260 is therefore energized in order to generate another input of this pulse driver, which forms the T3-Lei signal on line 266 when the counting 110 stand on 4. The last bers 186 is connected as an excitation input to the AND switch input to the AND circuits 240 and 260 biltungen 130 and 144. The output 35 det the r4-T6 clock pulse line 114. The lines 200 of the AND circuit 130 is connected to the IN 250 and 266 lead to the inputs of the OR side of the PST30 , while the output circuit 268.

line 202 of AND circuit 144 to the OFF The OR circuit 268 therefore generates a Si

Input of this flip-flop is connected. Therefore, on the output line 270, if the sum is the line 26 the »PST on the value of LBT one 40 of the counts in the counters I and II 3 + 4 = 7. output line of logic circuit 18. Line 270 splits into line 272. Output line 44a of the IN side of (FIG. 3B), which is the second input of OR earlier bit flip-flop (PBT) 40 forms the second on-circuit 222, and the line 66, which connects the output to the AND circuit 152 (FIG. 3 B), the excitation input of the pulse driver 120 (FIG. 3 A). The output line 44 b of the OFF side 45 forms. The output line 68 of the OR circuit of the PBT '40 is connected as a second input to the AND 222 is connected as an excitation input to the pulse driver 274 circuit 138. The output lines (FIG. 3 C) connected, the other input of which 210 and 212 of the AND circuits 138 and 152, the output line 276 of the OR circuit 278 are connected as inputs to the OR circuit 214. The inputs of the OR circuit 278 are the closed ones. The output line 216 of the OR 5 ° T3 line 110 and the J6 line 113. The off circuit 214 is connected to circuit 158 as a second input to the AND output line 280 of the pulse driver 274. The third input closed, that it forms all flip-flops in the counters I of the AND circuit 158, the output line and II resets to the OFF state or, on the other hand, the ON side of the 4-flip-flop 218 (FIG. 3 C) the ren words that clears counters I and II. Counter III. The AND circuits 138 and 152 55 The output line 282 of the pulse driver and the OR circuit 214 form an OR (Fig. 3A) is connected to the OUT side input of the but circuit which generates an output signal, CCTSO . As already indicated, form when PBT and LBT are not the same. Therefore, the inputs of the pulse driver 120 produce the line, the AND circuit 158 produces an output signal and the 2 "6 line 113.

on line 220 when CCT50 is OFF, 60 The output line 246 of the IN side which counter III is at 4 and LBT is not equal to PBT 4 flip-flop 248 (Fig. 3C ) of counter II is both. According to FIG. 2A, these are known to be the three as an input to the AND circuit 240 and as conditions for initiating a resynchronization input to the OR circuits 284 and operation. (Fig. 3 B) connected. The exit line

The output line 220 of the AND circuit 158 65 is the IN side of the 4-flip-flop 264 of the counter I is a second input to AND circuits 140 as well as an input to the AND circuit and 154 and as an input to the OR circuit and as a second input to the OR circuit 222 connected. The output line 224 of the device 284 and as an input to the OR circuit

15 16

device 288 (Fig. 3 B) is connected. Therefore, the frequency of the oscillator II generated at least the OR circuit 284 must have an output signal at least seven times as high as that of the oscillator I line 290, if either the counter I or the circuit. The output signal of oscillator I is set to 4 via counter II. The line 290 forms the line 354, one input of the pulse driver, the second input of the AND circuit 160 (FIG. 3B). 5 356 supplied. The other input of the pulse output line 292 of the AND circuit 160 driver 356 forms the line 358, which divides into lines 36 and 60. The line source 359 is an uninterrupted ON voltage 36 is connected to the excitation input of the Pulse driver level is fed. Therefore, the pulse train 294 (FIG. 3 A) connected, the line 60 is connected as via 356 a pulse peak at the beginning of each output excitation input to the pulse driver 296 connected pulses of the oscillator 350. The output pulse sen. The other input of the pulse driver of the pulse driver 356 on line 360 is the 294 and 296 forms the T5 line 112. The off-ON-side input of the flip-flop 362 is fed, output line 298 of the pulse driver 296 leads to the output line 364 of the IN- Side of the toggle-ON side input of the CCT 50. The output stage 362 is connected as an input to the pulse driver device 300 of the pulse driver 294 forms an input 15 366, the other input of which is the output of the AND circuits 128, 132 and 146 and output line 368 of oscillator 352. The pulse driver 366 therefore generates the shift pulse line for the accumulator 42. At the beginning of each output pulse of the oscillator 352, the output line 302 of the AND circuit 128 generates a pulse peak which supplies the accumulator 42 with new data. As in FIG. 3 on output line 370, if at the same time FIG. 1, the information in accumulator 42 20 run flip-flop 362 is in the ON state. The cable is fed to the decoder 48 via lines 46. device 370 forms an input for the AND switch This shows on the output lines 49 the through lines 372, 374, 376, 378, 380, 382, 384, 386 the combination of bits in the accumulator and 388. The output line 390 of the AND switch information on. The output line 304 of the device 372 is connected to the OUT-side input of the toggle AND circuit 132 is connected to the IN-side input 25 stage 362. Since the other input is that of the PBT40 and the output line 306 of the AND- AND circuit 372 is the T6 line 113, circuit 146 at the OUT side input of this means that the flip-flop 362 passes through the first of the flip-flops connected. Pulse driver 366 generated pulse spike during

The output line 308 is switched off from the OFF side of the time Γ 6.

4-flip-flop 264 (Fig. 3C) of counter I is connected to 30. Output lines 392, 394, 396 and 398 of the

an input of AND circuit 310 (Fig. 3B) AND circuits 374, 378, 382 and 386, respectively, are on

connected. The OUT-side output line 312 represents the respective IN-side inputs of the flip-flops

the 4-flip-flop 248 of the counter II is connected to the other 401 to 404. The output lines

Ren input of AND circuit 310 is connected. The 406, 408, 410 and 412 of the AND circuits 376,

Output line 314 of AND circuit 310 is as 35 380, 384 and 388 are connected to the respective OUT side

second input to AND circuits 134 and th inputs of flip-flops 401 to 404

148 connected. The output line 316 of the closed. The IN side output line 414

AND circuit 134 leads as a second input to that of flip-flop 401 forms the second input of

OR circuit 286, and the output line 318 AND circuit 378 and one input of the AND

the AND circuit 148 leads circuits 416 and 418 as a second input 40

to the OR circuit 288. The output line 320 of the IN side of the flip-flop 402 forms the second

the OR circuit 286 is an excitation input at the input of the AND circuit 382 and one each

the pulse driver 184 (Fig. 3C) is connected. The inputs of AND circuits 422 and 424. The

Output line 322 of pulse driver 184 is as output line 426 of the ON side of flip-flop 403

Switching input connected to counter I. 45 forms the second input of the AND circuits

The output line 324 of the OR circuit 288 376, 386 and 418 as well as an input of the AND

(F i g. 3 B) leads as the excitation input to the pulse train circuit 428. The output line 114 of the input

over 180 (Fig. 3C). The output line 326 of the flip-flop 404 side forms an input of the

Pulse driver ISO is connected to the switching input AND circuit 432 and the T4-T6 output

of the meter II connected. 5th line of the clock generator 90. The output line 434

The flip-flops in counters I, II and III can be the OFF side of flip-flop 401 forms the second nen in any normal way with input of AND circuits 380 and 424. The are connected to each other that the desired output line 436 of the OFF side of the flip-flop Results are achieved. 402 forms the second input of the AND circuit these connections are not shown 55 to 384, 416 and 428. The output line 438 of FIG but are shown schematically by the dashed OFF side of the flip-flop 403 forming the second line indicated between the flip-flops. The AND gates 374, 388, 422 and 432 switch. The output lines of the AND circuits 416, are shown closed, these lines lead tat- 422, 418, 424, 428 and 432 are the Tl-r6 lines to connecting gates in the meters. 60 gen 108 to 113.

An embodiment of the process shown in FIG. 1 Fig. 5 is a timing diagram showing how to and FIG. 3B, the clock circuit 90 shown explains the desired sequence of clock pulses from the circuit shown in FIG tert. According to FIG. 4, the clock consists of a F i g. 4 includes the circuit shown. after the Oscillator I (350) and an oscillator II (352). Like run-flip-flop 362 through the leading flank of the Ausin F i g. 5 is the frequency of the oscillator 65 input pulse of the oscillator I in the ON state tors I seven times the data frequency and has been switched, the leading edge causes each the frequency of the oscillator II in turn is essentially the output pulse of the oscillator II that a step higher than that of the oscillator I. The switching pulse shown here is applied to line 370. the

Flip-flops 401 to 404 are connected to one another in such a way that flip-flop 401 is switched on first and the other flip-flops are switched on one after the other by subsequent pulses supplied via line 370, the pulse switching on flip-flop 404 also serving to switch off flip-flop 401. The remaining three flip-flops are then switched off one after the other by further pulses on line 370, the pulse that switches off flip-flop 404 also switching flip-flop 401 on again. The outputs of these flip-flops are then linked in an AND-shaped manner in an explained manner in order to form the desired pulse train. The pulse on line 370, which turns flip-flop 404 off and thereby terminates the T6 pulse on line 113, is also passed through energized AND gate 372 to switch run flip-flop 362 to the OFF state. Then no further pulses are fed via line 370 until a new pulse is given from oscillator I on line 354. Since oscillator I generates seven pulses for each data pulse, there are seven sample pulse cycles for each data pulse.

In order to illustrate the operation of the circuit shown in FIGS. 3A to 3C, it is assumed that the clock generator of the transmitter runs almost 30% faster than the clock generator of the receiver. B. the one on line (a) of FIG. 6, the received signal shown in line (b) of FIG. 6 has the shape shown. Since the same logic is used in the circuits of Figures 1 and 3A-3C, the flowchart of Figures 2A and 2B applies to both circuits. Therefore, a glance at the flowchart of Figures 2A and 2B will assist in understanding the following description of the operation of the circuit of Figure 2B. 3 A to 3 C at.

As shown in FIG. 3 A, the ON voltage level on the transmission line 10 is fed to one input of the pulse driver 104 via the voltage level adjuster 100 and the line 102 at the beginning of the sampling cycle 51. When the clock pulse T1 is applied to the line 108, the pulse driver 104 sends a pulse peak via the line 106, which brings the LBT12 into the ON state. Since neither counter I nor counter II is now at 4, signals appear on lines 308 and 312 which fully energize AND gate 310 (FIG. 3B) so that it generates an output signal on line 314 which indicates the AND Circuit 134 energized. Since there is a signal on the output line 16 α of the IN side of the LBT , the AND circuit 134 generates an output signal on line 316 which is fed to line 320 via the OR circuit 286. The signal on line 320 is applied to pulse driver 184 (Fig. 3C) and energizes it. At time Γ 2, a signal appears on line 109 which fully excites pulse driver 184 so that it generates a pulse peak on line 322 which advances counter I to one.

Since the PST30 (Fig. 3A) is now in the OFF state, a signal appears on the output line 32b, which prepares the AND circuit 150 (Fig. 3B). Since LBT12 is in the ON state, a signal also appears on line 16 a, which the AND circuit 136 prepares. Since neither AND circuit 136 nor AND circuit 150 is fully energized at this point, OR circuit 170 produces no output on line 172, and therefore inverter 190 produces an output on line 192 which, on line 26, provides the pulse driver 186 (FIG. 3 A) and via line 194 the pulse driver 176 (FIG. 3C) is prepared. At time Γ2, a pulse arrives on line 109 which fully excites pulse driver 176 so that it generates an output voltage spike on line 196, which is fed to counter III and sets it to one. At time T 3, a signal is placed on line 110 which fully energizes pulse driver 186 (FIG. 3A) so that it generates a voltage spike on line 198 which fully energizes AND gate 130 so that it A signal on line 200 switches the Ρ5Γ30 to the ON state. As noted, all tests fail during this scan cycle and therefore no further operations are performed until time T 6 when a signal through pulse driver 118 (FIG. 3A) and line 124 resets the LBT12 to the OFF state.

At time 5 2 , the voltage on the transmission line 10 has dropped to the OFF level due to a noise voltage spike. Any deviation of this level from the normal value is compensated in the level adjuster 100. Therefore, when the ri clock pulse is applied to line 108, the pulse driver 104 is switched off and the LBT 12 is still in the OFF state. Since neither counter I nor counter II is now at 4, signals still appear on lines 308 and 312, which are fed to AND circuit 148 via AND circuit 310 (FIG. 3B) and line 314. Since the LBT12 is in the OFF state, there is a signal on the output line 166 of the OFF side which fully energizes the AND gate 148 so that it produces an output signal on line 318 which is passed through the OR gate 288 and line 324 energizes the pulse driver 180 (Fig. 3C). At time Γ2, a signal appears on line 109, the leading edge of which advances counter II to 1 via pulse driver 180 and line 326.

Since the PSJ30 is ON, there is also a signal on line 32a which prepares the AND circuit 136 (Fig. 3B). The signal on line 16 b prepares the AND circuit 150. Therefore, none of these AND circuits are fully energized and OR circuit 170 does not produce an output on line 172. Inverter ISO therefore produces an output on line 192 which is applied to lines 26 and 194. As already mentioned, the counter III is reset to 1 at time T 2 and the contents of the LBT are entered into the PST at time 7 "3. No further operations are carried out during this cycle until a signal on the line at time T 6 113, which energizes the pulse driver 118 (FIG. 3A). This brings about a signal on the line 124 which forces the LBT 12 into the OFF state. Since the LBT is already in the OFF state, this pulse is of course without Effect.

At time 53 insists on the transmission line 10 returns to an ON voltage level and the same sequence of operations takes place as for the Time 51 has been written, with the only difference that now the counter I after the further switching has the count 2.

At time 54, the transmission line 10 is still at its ON voltage level so that

the LBT12 goes into the ON state at time Π. Since the counters I and II are now both not at 4, the counter I is incremented to 3 in the manner described above. Since the Ρ5Γ30 is in the ON state, there is a signal on line 32 a, which is supplied as an excitation input signal to the AND circuit 136 (FIG. 3B), the other excitation signal of which is the signal on the output line 16 a from the ON side of the LBT12 is. Therefore, AND gate 136 is now fully energized producing an output on line 166 which via OR gate 170 and line 172 energizes pulse driver 174 (FIG. 3C). At time Γ2, the leading edge of the clock pulse on line 109 from pulse driver 174 to line 188 and causes counter III to be advanced to level 2. During this sampling cycle, no further operations are carried out until time T6, a signal via line 113 and the Pulse driver 118 comes on line 124 to reset LBT 12 to the OFF state.

At time 55, the received signal on the transmission line 10 is recognized as the ON voltage level, thereby bringing the LBT12 into the ON state at time Π. As a result, the counters I and III are incremented in the manner described above, and the counter I is now at 4 and the counter III at 3. Since the counter I has the count 4, an output signal appears on the output line 262 of the IN side of the 4-flip-flop 264 (FIG. 3 C), which is fed via the OR circuit 284 and the line 290 to one input of the AND circuit 160 (FIG. 3B). Since CCT 50 is OFF, there is now a signal on line 67 which fully energizes AND gate 160 to produce an output on line 292 which is applied to lines 36 and 60. The signal on line 36 prepares pulse driver 294 (FIG. 3A) and the signal on line 60 prepares pulse driver 296. At time Γ 5, a signal appears on line 112 which fully energizes pulse drivers 294 and 296. The output on line 298 of pulse driver 296 turns the CCT 50 ON. The output of pulse driver 294 on line 300 switches the PBTAQ to the ON state via AND circuit 132 and line 304 and causes an ON voltage level to be input to accumulator 42 via AND circuit 128 and line 302 . The signal on line 300 also causes the contents of accumulator 42 to be shifted one place to the left. In this way, the first pulse of data is properly stored as an ON value. At time Γ 6 of this same data sampling cycle, the LBT12 is reset to the OFF state.

At time 56 there is an OFF voltage level on the transmission line 10, so that the pulse driver 104 is absent at time T1. Therefore, the LBT 12 remains in the OFF state. Since the counter I is at 4, a signal is produced on the output line 262 of the IN side of the 4-flip-flop 264 of the counter I. This signal is fed via the OR circuit 288 (FIG. 3B) and the line 324 to the pulse driver 180 ( Fig. 3 C) supplied. Since the counter I is at 4, there is now no signal on line 308, whereby the AND circuit 310 (FIG. 3B) is blocked and the application of a signal on line 314 is prevented. At time Γ 2, a signal arrives on line 109, which fully excites the pulse driver 180 so that it generates a further pulse for the counter II and thus advances it to 2.

The PST is now in the ON state, and therefore an output signal is on line 32 a, which the AND circuit 136 prepares. The signal on the output line 16 b of the OFF side of the LB T 12 prepares the AND circuit 150. Since none of these AND circuits are fully energized, OR circuit 170 will not produce an output on line 172 and therefore inverter 190 will send a signal on line 192 causing counter III to reset to 1 at time Γ 2 and PST at time Γ3 is reset to the OFF state, the state of the LBT . These operations take place in the manner described above. No further operations occur during sampling cycle S 6.

During time Γ1 of sampling cycle 57, the LBT12 remains in the OFF state, and during time Γ2 of the same sampling cycle, counter II is incremented to 3 and counter III to 2 in the manner already described. The counter I is now at 4, so that the flip-flop 264 is in the ON state, and because the counter II is at 3, the flip-flops 256 and 258 are also in the ON state. Hence de-. there are output signals on lines 262, 252 and 254 which prepare the AND circuit 260. During times 4-Γ6, a signal appears on output line 114 of clock 90 which fully energizes AND gate 260 to produce an output signal on line 266 which is fed through OR gate 268 and line 270 to lines 66 and 272 is supplied.

The signal on line 272 passes through OR circuit 222 (FIG. 3C) and line 68 as an excitation input signal to pulse driver 274 (FIG. 3C). At time T6 , the clock generator 90 outputs a signal on line 113, which is likewise fed to the pulse driver 274 via the OR circuit 278 and the line 276. The resulting output of pulse driver 274 on line 280 is applied to the OFF side input of each of the flip-flops of counters I and II to clear both of those counters. The signal on line 66 partially energizes pulse driver 120 (FIG. 3A). The signal on line 113 at time T 6 is also fed to this pulse driver and fully energizes it so that it generates a pulse on line 282 which resets the CCT 50 to the OFF state. By resetting the CCT and the counters I and II, the first data pulse cycle is ended, namely it is ended two sampling pulse times after the end of the first data pulse. However, as already mentioned, the circuit is designed to compensate for this error so that the circuit can accurately determine the value of the subsequent data pulses without the need to resynchronize the clocks in the transmitter and receiver.

At the time Tl of the scan 58, the transmission line 10 has still an OFF voltage level, so that the LBT12 remains in the OFF state. At time T 2 of this cycle, the counter II is set to 1 and the counter III is set to 3, as described above.

At time Π of scan cycle 59, the transmission line 10 is still at the OFF voltage level, and therefore LBT 12 remains in OFF-Z> *

was standing. At time Γ 2 of the same cycle, counter II is switched to 2 and counter III to 4. As a result of the advancement of the counter III to 4, the flip-flop 218 of this counter is switched to the ON state. The resulting output signal 5 on line 88 is fed to one input of AND circuit 158 (FIG. 3B). Since CCT 50 is in the OFF state, a signal arrives from the OFF side of this flip-flop on the output line 67, which is fed to the second input of the AND circuit 158. Since PBT 40 are in the ON state and LB T 12 in the OFF state, there are further signals on lines 44 α and 16 b , which fully energize AND circuit 152, so that they receive a signal on line 212, OR Circuit 214 and line 216 to the third input of AND circuit 158 sends. This is therefore fully excited and generates an output signal on line 220 which is fed to AND circuit 154 and, via OR circuit 222 and line 68, to pulse driver 274 (FIG. 3 C). At time T 3, clock generator 90 generates a signal on line 110 which, through OR circuit 278 and line 276, fully energizes pulse driver 274 so that it generates a pulse on line 280 which clears counters I and II. The signal on the output line 16 b of the OFF side of the LBTIl the "becomes full AND circuit excited 154 (Fig. 3B) supplied. The resulting output signal on line 228 prepares the pulse driver 230 (Figure 3C) in front. Currently Γ4 generated the clock generator 90 sends a signal on line 111 which fully energizes the pulse driver 230 so that it generates a pulse on line 234 which brings the counter II to the count 4.

Since the counter II is at 4, an output signal appears on the output line 246 of the IN side of the 4-flip-flop 248 of the counter IL. The signal is fed via the OR circuit 284 and the line 290 to one input of the AND circuit 160 (Fig 3B) supplied. Since the CCT 50 is now in the OFF state, a signal is on line 67 which fully energizes AND gate 160 so that it generates an output signal on line 292 which is fed to lines 36 and 60. The signal on line 36 is fed to the excitation input of the pulse driver 294 (FIG. 3 A) and the signal on line 60 is fed to the excitation input of the pulse driver 296. At time Γ 5, clock 90 generates a signal on line 112 which fully energizes pulse driver 294 to produce an output signal on line 300 and which fully energizes pulse driver 296 to produce an output pulse on line 298. The output pulse on line 298 turns the CCT 50 ON. The output pulse on line 300 energizes the AND circuit 146 so that the signal on line 16 b on the PBT40 via line 306 in the OFF state. In addition, the pulse on line 3CO shifts the data in accumulator 42 one place to the left and prepares AND circuit 128. Since there is no signal on line 16 «, the AND circuit 128 is not switched on and no pulse reaches the lowest digit of the accumulator 42. The result of this operation is correctly indicated that the second data pulse has an OFF value.

In the manner indicated, the circuit continues to operate to properly evaluate the remaining pulses in the pulse train. How the circuit would work to generate pulses in the line (c) of FIG. 6 to evaluate the pulse train shown with a slow clock generator in the transmitter, can easily be derived from the above description of the mode of operation with regard to the pulse train shown in line (b) and from the description of the decoding of this pulse train in the general description section.

While in the example explained, seven sampling cycles are assumed for each data pulse cycle have been, the invention is not limited thereby. As the number of Sampling cycles per data pulse cycle increases the ability of the circuit to produce accurate results at higher rates Generate noise and phase error components in the received signals, and vice versa decreases the tolerable noise and phase error rate with a decreasing number of sampling cycles per data pulse cycle. With seven sampling cycles per data pulse cycle, there is a theoretical maximum of almost 43% noise signals are permitted, whereby exact results can still be achieved. When you consider the number of Increased sampling cycles per data pulse cycle to eleven, the theoretical maximum would be more tolerable Errors only rise to a little over 45%, while reducing the number of sampling cycles per data ' pulse cycles to five, the tolerable theoretical maximum noise component would drop to 40%. The tolerable theoretical noise maximum approaches 50% with increasing number of sampling cycles per Data pulse cycle. Therefore, the choice of the number of sampling cycles per data pulse cycle depends on the designer's choice between the cost of additional components and the meter size in relation to the required degree of accuracy. In most applications, you will get satisfactory results with five or seven sampling cycles per data pulse cycle.

As illustrated, the circuit receives information from a given transmitting station. Since the circuit elements and the oscillators I and II (Fig. 4) with a much higher frequency As the data pulse frequency can work, however, it is possible to send the signals from transmitters different To process data frequency with the circuit according to the invention.

Furthermore, in the examples described above, the pulses alternate with high and low voltage levels; with the normal phase error of a few percent between the The circuit would also provide clock generators with exact results for long sequences of high and low frequencies Voltage levels as well as the alternating high and low levels shown in the examples.

Claims (4)

Patent claims: 1. Method of decoding binary pulse signals at the output of a transmission line with the help of a receiving-side bistable input flip-flop, characterized in that that the respective position of this single provided by the output signal the transmission line influenced bistable input flip-flop (12) in a certain, number of scan cycles referred to as the scan block is determined, with each the impulses entered in the correct corresponds to even number of sampling cycles generated on the receiver side, and that the most frequent The position of the one bistable input multivibrator (12) occurring in a sampling block is determined and the binary value corresponding to this position is stored. 2. Circuit arrangement for performing the method according to claim 1, characterized in that a single, under control of a clock (90) standing bistable input flip-flop (12) is provided, the input side with a transmission line (10) and the output side via a logic circuit (18) is connected to a first counter (70) for the ON values and to a second counter (72) for the OFF values, and that output pulses of the counters (70, 72) via a decoder (78) and the logic Circuit (18) at a first specific amount (n + 1) in one of the counters (70, 72) can transfer the binary value indicated by its position in the bistable input flip-flop (12) to an accumulator (42) and that when it is reached a second particular Amount for the sum of the counter readings (2 n + 1) of the two counters (70, 72) the counter (70, 72) is reset to zero. 3. Circuit arrangement according to claim 2, characterized in that the counting of all successive binary values that are determined when the count of the second (2 n + 1) the resetting of the first and second counter (70, 72) caused to zero, regardless of the binary ON or OFF position of the input multivibrator (12) takes place, which increment the first counter (70) or the second counter (72). 4. Circuit arrangement according to one of claims 2 or 3, characterized in that the decoder (78) consists of two AND circuits (240, 260), whose inputs each with the IN outputs of the first or the second stage of one counter (70 or 72) and with the IN output of the third stage of the other counter (72 or 70) are connected and their outputs are combined by an OR circuit (268). For this purpose 3 sheets of drawings 009 552/97