DE131054T1 - ERROR REDUCTION CIRCUIT IN A DATA RECEIVER. - Google Patents

Claims (1)

DIPL-INQ. KVRT KAHLER * - * '^ IUO Η _89j1 walkertshofen nr.ijs PATENT ADVOCATE TEL.08i39-341 February 5, 1985 3392 / EPC European patent application 84 900 670.5 NCR Corporation Circuit for reducing errors in a data receiver Claims 1. Data receiver with a circuit arrangement for compensating for transmission disturbances in a carrier-modulated transmission system, which circuit arrangement includes a correction circuit (17) for correcting a previously equalized received signal (* _n ) / and a decision circuit (19) which responds to the corrected received signal (y_) responds to output data signals (S), a difference determination circuit (21) which is coupled to an input and an output of the decision circuit (19) and a correction factor determination circuit (23) having an output of the difference determination circuit (21) and an input the correction circuit (17), characterized in that the difference determination circuit (21) is responsive to complex signals representing the corrected received signals (y _n ) and the output data signals (ä) to output complex residual error signals (d), and that the correction factor determining circuit (23) responds to the complex residual error signals (d) and to a gain factor control signal (w, / Λ * ₂ '^ n' ^ ι ^ to vary in a time-dependent manner of an initial signal value, when the receiver initially begins to receive transmitted data, up to an end signal value that differs from the initial value, whereby the correction factor determining circuit (23) outputs a complex reference signal (v) which, during operation, is sent to the correction circuit (17 ) is applied to compensate for phase and amplitude errors in the data receiver. 2. Data receiver according to claim 1, characterized in that the correction factor determining circuit (23) has: a first compensation circuit (45, 47, 51, 53, 55, 57) which is based on 90 ° phase-shifted components of the complex residual error signal (d) and responsive to the gain control signal ty ,, ^ ₂ '* η'® I to provide a compensated output signal which is compensated for a frequency shift, and a second compensation circuit (27, 29, 31, 35) which is responsive to in-phase components of the complex residual error signal (d) responds to the gain factor control signal 'f ι f 4 ^ τ' ^ 0 '^ 1' ^{Un (} ^ ^au ^ ^ ^aS compensated output signal and is suitable for emitting the complex reference signal (v). Data receiver according to Claim 2, characterized in that the gain control signal represents a plurality of gain control factors UJ-, / Vt ' ^ Q'& I ^ clarify and that the first compensation circuit comprises a first adder circuit (47) with a first and second input, a delay element (51), which has an input with the first input and an output with a first multiplier circuit (53) for multiplying cation to a first of the gain control factors (^ ₀ ), wherein an output of the first multiplier circuit is coupled to a first input of a second adder circuit (57) which has a second input coupled to an output of a second multiplier circuit (55) which is suitable is to multiply the 90 ° phase-shifted component of the complex residual error signal (d) by a second of the gain control factors (άι), an output of the second adding circuit (57) with an input of the delay element (51) and with the first input of the first adding circuit (47), the second input of the first adder circuit (47) being coupled to an input of a third multiplier circuit (45) which is suitable for converting the 90 ° phase-shifted component of the complex residual error signal (d) to a third of the gain control factors ( ¹ J *? ^ ^To multiply. 4. Data receiver according to claim 3, characterized in that the second compensation circuit comprises: a fourth multiplier circuit (29) which has a first complex input which is suitable for receiving an output signal of the first adding circuit (47) as a 90 ° phase-shifted component and to receive as an in-phase component an output signal of a fifth multiplier circuit (35) which is suitable for multiplying the in-phase component of the complex residual error signal (d) by a fourth of the gain control factors (^ ₁ ), the fourth multiplier circuit (29) having a second complex input coupled to an output of a further delay element (27), a third adding circuit (31) which has its inputs connected to an output of the fourth multiplier circuit (29) and to the output of the further delay element (27) and an output to an input of the further Has delay element (27) coupled and is suitable to output the complex reference signal (v). 5. Data receiver according to claim 4, characterized by Correlation circuit means (61, 63, 65, 67, 69, 71) based on the 90 ° phase shifted component of the responds to complex residual error signal (d) and is suitable for outputting averaged correlation signals (q), which are arranged to modify the third of the gain control actuators U *), the third multiplier circuit (45) is arranged to the 90 ° phase-shifted component of the complex To multiply residual error signal (d) by the modified third of the gain control factors. 6. Data receiver according to claim 5, characterized by a fourth adding circuit (73) which has inputs which are suitable for receiving the averaged correlation signal (q) and the third of the gain control factors W><y) , and an output which is connected to a Input of the third multiplier circuit (45) is coupled. 7. Data receiver according to claim 6, characterized by a gain factor generation circuit (24) which is suitable to generate the first, second, third and fourth gain control ^{factor 4 /} * l '^ 2'"0'^ I ^ <3 ^en » wherein the gain generation circuit comprises a feedback loop (75, 77, 79) and is responsive to a plurality of predetermined factors (r _Q to r), whereby each of the gain control factors is 4 * 1'V * 2 '■ 0' ^ I ^ dependent is from an output of the feedback loop (75, 77, 79) and at least one of the predetermined factors (r _n to r _c ). U b 8. Data receiver according to claim 7, characterized in that the first of the gain control factors φ «) is arranged is to increase towards a value close to 1 and that is the second of the gain control factors (d-,) is arranged to decrease towards a value close to zero.