DE1151961B - Circuit arrangement for comparing decimal numbers - Google Patents

Description

GERMAN

PATENT OFFICE

REGISTRATION DATE: MAY 6, 1960

NOTICE THE REGISTRATION AND ISSUE OF EDITORIAL: JULY 25, 1963

The invention relates to a circuit arrangement for comparing two multi-digit decimal numbers in partially binary encrypted form for use in electronic data processing systems. It is assumed that the decimal numbers appear in series-parallel representation, i. H. the individual binary digits of a character group representing a decimal digit at the same time, the different However, groups of characters consecutively in time. Furthermore, with the present Circuit arrangement only such a code into consideration that has a spatial or temporal arrangement both of the binary digits within a character group as well as the individual groups of characters one after the other in ascending order of importance and in which, furthermore, the unit of each place value is the greatest possible sum of the preceding ones Exceeds significance.

Devices are already known with the help of which the relationship between two occurring in parallel representation Groups of characters, e.g. B. tetrads, is displayed in the form of signals representing the statements "Greater", "smaller" or "equal to" correspond. From these statements z. B. for a data processing Required commands or decisions can be derived from the system.

A circuit principle for parallel comparators of the aforementioned type is also known which is particularly favorable in terms of the required expenditure on circuit means. According to this circuit principle, the parallel comparator contains for corresponding binary digits of the digits of the pair of digits to be compared a comparator stage each with a bistable circuit for receiving the code bits of the two digits to be compared. The outputs of the bistable switching elements for one digit are connected directly for the other comparison digit, however, to the respective comparator AND circuits belonging to the stage, which - apart from the comparator stage of the lowest order - are each connected to an inverter via an OR circuit and which - with the exception of the comparator stage of the highest order - are connected to two blocking AND circuits connected to the inverters of all previous stages. Finally, in this circuit, the corresponding locking AND circuits of the highest order level are connected via associated OR circuits to the output terminals of the parallel comparator for intermediate result signals "A >B","A<B" .

Such a circuit arrangement is, however, a circuit arrangement for comparison
of decimal numbers

Applicant:
Olympia Werke AG, Wilhelmshaven

Dipl.-Ing. Hugo Reichert, Wilhelmshaven,
has been named as the inventor

not yet to carry out a comparison of two decimal numbers in series-parallel representation suitable. This is because a group appears at the outputs of the parallel comparator after processing of binary digits, e.g. B. a tetrad, always only the comparison result of the pair of digits concerned. However, this result does not agree with the comparison result of the digit sums from the first

-5 match up to the last compared position, if the last compared pair of digits is the same, a previous one Pair of digits is not the same. Accordingly, after the last pair of digits has been processed, the decimal numbers to be compared not the overall comparison result, only the comparison result of the highest decimal place is displayed.

The object of the invention is therefore to create a circuit arrangement for comparing decimal numbers in binary-encrypted parallel-series representation 211 using the circuit principle mentioned. The inventive solution to this problem is essentially that the output terminals of the parallel comparator for the intermediate result signals "A >ß" and "A <CB" are connected on the one hand via a common OR circuit to the normal input of a first bistable output element, the complement input only before At the beginning of each total count comparison, a start pulse producing the result state "A = B" is applied and, on the other hand, each is individually connected to an input of a further bistable output element. As a result, the result signal "equal" as the initial state is deleted when the first comparison result "not equal" occurs in the order of the pairs of digits running through. The result signal "same" can then only be returned when the

309 648/211

3 4

whole number comparison connected by a new start- the decimal digit A , the right inputs

impulse can be produced. In this way, the flip-hops FF ₅ to FF ₈ with input terminals B _{1 provide}

when running through the digit pair with the highest digit g to B ₄ for the tetrad of the decimal digit B. The

obtained comparison result also the total binary digit L may in a known manner by a

the same result of the pair of numbers. 5 signal, represented for example by a pulse

The advantages and features of the invention will be made possible by the absence of this binary digit

by describing an embodiment signal. An input signal at the input terminal

explained on the basis of the drawings. In the figures A ₁ to A ₄ and B ₁ to B ₄ , the connected

nungen shows the appropriate flip-flop in its "L" position; these

FIG. 1 shows the block diagram of a parallel comparison position in the present example in FIG. 1

circuit according to the known circuit principle, marked by hatching on the right partial area

2 shows the block diagram of a series comparison network. The left inputs of the flip-flops FF ₁ to FF ₈

circuit according to the invention and in Fig. 1 are with an input terminal A ₁ for a

3 shows a block diagram of the reset signal according to the invention. After each later loading

Overall circuit. ¹⁵ described comparison process are carried out by this

In the overall circuit according to FIG. 3, the PV reset signal denotes the flip-flops FF ₁ to FF _e in their

the switching "O" position described later with reference to FIG. 1 is switched if it does not have this position

management arrangement for the comparison of in parallel-binary-have already taken. The "O" position of the

decimal flip-flops represented by decimal encryption by hatching the left sub-area

digits, with an ^{ao of} the flip-flops specified in this embodiment.

Encryption in parallel tetrads is selected. As is known with a flip-flop, the

The four input terminals for parallel input of the signals on the output lines of the individual

Decimal digits A are complementary with A ₁ to A ₄ , the four one-on flip-flops. If, for example, the

input terminals for parallel input of the decimal flip-flop FF ₁ considered, the one shown in the drawing

Numbers B denoted by B ₁ to B ₄ . The terminals ^a 5 position after the above embodies a zero, so

A > B and A < B represent the result once executes the output line on the left side of FF ₁

outputs of the parallel comparison circuit PV (Fig. 1) no signal corresponding to the binary digit 0, since in

on the other hand, the corresponding input this embodiment is assumed that the

clamp a circuit SV (Fig. 2) to compare binary digit 0 the absence of an output pulse

speaks of binary coded information presented in series. The exit line on the right side of

options. The series comparison circuit SV has Er- FF ₁ , however, carries a signal corresponding to the

Result outputsΛ —Β, A> B and A <B, at which, the complement of the digit 0, it appears on it

as will be described later, the end result of that is an output pulse. Flip-flop FF ₂ on the other hand

Comparison of the two decimal numbers is displayed. represents an "L" in the position shown, so that its

In the following, the circuit output on the left-hand side first emits a pulse

construction and the mode of operation of execution with its exit on the right side, however, corresponds

the comparison circuit PV and SV do not play an impulse given the complementary value to "L"

and then the mode of action of the overall appearance. It is therefore the left exit in the following

arrangement according to the invention explained. all flip-flops in Fig. 1 with normal output and the

Fig. 1 shows as an exemplary embodiment a 4 ° right output referred to as a complement output, equal circuit for comparing two decimal digits, the pairings of the flip-flops FF ₁ and FF _& , FF ₂ in parallel tetrads, i.e. by four binary and FF ₆ , FF ₃ and FF ₁ , FF ₄ and FF ₈ are with the digits, are shown. The encryption of the associated switching element decimal numbers to be described later must be chosen so that the th in each case is assigned to a binary digit of the binary digits to be compared with the decimal digit in ascending order and form the comparator seats, i.e., for example, the coding in stages, namely from right to left in Fig. 1 in Dreiexeßkey. increasing order.

The tetrads to be compared of the two deci As FIG. 1 shows, the normal output of one of the binary digits FF ₁ to FF ₄ (digit Λ) and FF _n to FF ₈ 50 are assigned within a comparator digit in a bistable switching stage Flip-flops are saved with the appropriate (digit B). The bistable switching elements complement output of the second to be compared may be designed, for example, as flip-flops. The flip-flops assigned to the binary digit via a flip-flops In Fig. 1, the flip-flops FF ₁ to FF _{8 are connected} as a right AND circuit. For example, corner shown and can be constructed in a known manner from the normal output of the two electronic switches, such as tubes or Tran- 55 flip-flops FF ₁ and the complement output of the transistor, in the highest binary digit, of which flip-flops in one construction FF ₅ to the inputs of the AND circuit, for example from transistors in a known manner in each M _n , the complement output of FF ₁ and the norstable state of the flip-flop a transistor lei- mal output of FF. on the AND circuit h _1? . tend, the other is locked. This is indicated in the drawing. The same applies to the flip-flop pairs FF ₂ with voltage Fig. 1 indicated that the rectangles 6o FF ₆ , FF ^ with FF. and FF ₄ with FF _g and their are divided into two equal halves. The respective subordinate pairs of AND circuits M ₂₁ with M ₂₂ , M ₃₁ side of a flip-flop, the transistor of which is conductive with H ₃₂ and M ₄₁ with M ₄₂ . In this way, the state that is located is indicated by hatching of the partial signals on the output lines of the area mentioned. All inputs of the switching elements, first pairs of AND circuits, respectively, the Er _r of FIGS. 1 to 2 are identified by an arrow pointing to the switching results of the comparison of two binary digits within elements. a binary digit. As above, the right inputs of the flip-flops FF ₁ to FF ₄ in the flip-flops FF ₁ to FF ₄ shown decimals are with input terminals A ₁ to A ₄ for the tetrad digit with A and in the Flip-flops FF ₅ to FF ₈

shown decimal digit with B, it is easy to see from Fig. 1 after the above that signals on the output lines of the AND circuits U _n , u., _V U ₃₁ , M ₄₁ mean that the binary digit of the decimal digit in the corresponding binary digit Λ is greater than that of the decimal number B , but that signals on the output lines of the AND circuits M ₁₂ . ii.,. ,, M ₃₂ , M ₄₂ indicate that the binary digit of the decimal digit A is smaller than that of the decimal digit B in the corresponding binary parts.

The output lines of the first AND circuit pair M ₁₁ M _1., The highest order comparator are o directly via OR circuits. And o _ti associated with the result outputs A ~> B and A <iB, as shown in FIG. 1, M ₁₁ via o. with A ~> B and U _1. , over o _d with A <B.

The Äusgangsleitungen the first AND circuit couples u. _N m.,. "M ₃₁ M ₃₂ and M ₄₁ M ₄₂ are shown in FIG. 1 associated with the first inputs of second AND circuit couples M ₂₃ M ₂₄ M ₃₃ M ₃₄ and M ₄₃ M ₄₄ connected, namely M ₂₁ with M ₂₃ , M ₂₂ with M ₂₄ and M ₃₁ with M ₃₃ , M _3. , With M ₃₄ and M ₄₁ with M ₄₃ , M ₄₂ with M ₄₄ . The output lines of the AND circuits M ₂₃ , M ₃₃ and M ₄₃ lead via the OR circuit ο _δ to the result output A> B, the output lines of the AND circuits M ₂₄ , M ₃₄ and M ₄₄ via the OR circuit o ₆ on the result output A <LB.

To achieve a parallel comparison of all binary digits of the decimal digits and a statement about The individual comparator stages are used to obtain the relationship between the decimal digits to be compared linked in the following way:

The output lines of the first AND circuit pair of each comparator stage up to the lowest order stage are each combined via an OR circuit, as shown in FIG. 1, M ₁₁ M ₁₂ via O ₁ , M ₂₁ M ₂₂ via O ₂ and M ₃₁ M ₃₂ about o ₃ .

The output lines of the OR circuits O ₁ to O ₃ are each connected to the input of an inverter stage I ₁ to I ₃ . As can also be seen from FIG. 1, the output line of the inverter stage of each comparator stage is connected to corresponding inputs of the AND circuits of the second AND circuit pairs of all comparator stages of the lower order. For example, the output line of inverter I _{1 leads} to inputs of AND circuits M ₂₃ and M ₂₄ , M ₃₃ and M ₃₄ and M ₄₃ and U ₄₄ , and the output line of inverter I _{2 leads} to inputs of AND circuits M ₃₃ and M ₃₄ as well as M ₄₃ and M ₄₄ etc.

As will be described later using a numerical example, this ensures that that when the inequality of the compared binary digits is determined in a comparator stage is, all result outputs of the comparator stages of the lower order for the delivery of their Signals representing results are blocked.

The result outputs A > B, A <iB are routed via an OR circuit o on an inverter stage / ₄ . The output line of the inverter stage / ₄ is connected to the result output A = B.

The mode of operation of the comparison circuit according to the invention will be described using a numerical example. The decimal digits A = 2, which is represented in the three-process key by the tetrad OLOL , and the decimal digit B - O, which is represented in the three-process key by the tetrad OO LL , are to be compared. As indicated in Fig. 1 by the hatching of the flip-flops FF ₁ to FF ₈ , the number A = 2 is stored in the flip-flops FF ₁ to FF ₄ , the number B = O in the flip-flops FF. to FF _H. The comparison results of the comparator stages may now be considered in the order from higher to lower order of the binary digits. In the comparator stage of the highest order with FF ₁ and FF ₅ , both decimal digits to be compared have the binary digit O. Due to the above-described linking of the normal and complement outputs of the flip-flops with the associated AND circuits, neither appear on the output line of the AND circuit M ₁₁ still on the output line of the AND circuit M ₁₂ output

signals. The lack of an output signal is converted into an output signal by the inverter stage I ₁ , thereby enabling the comparator stages of the lower order to output their comparison results by applying the output _{from the inverter Z 1}

Output signal to the associated inputs of the AND circuits of the second pair of AND circuits is prepared. In the comparator stage of the second highest order, the binary digit L in flip-flop FF ₂ must be compared according to the decimal

digit A = 2 and the binary digit O in the flip-flop FF ₀ according to the decimal digit B = O. Due to the above-mentioned linking of the flip-flops with their first AND circuit pair, an output signal _{appears on the output line of the AND circuit M 21,}

on the output line of the AND circuit M ₂₂ no output signal. The AND circuits // _{2: J} and u _{24 are} prepared for the output of signals by the output signal of the inverter I _{1 generated as described above.} In this way, the output signal of the AND circuit m. _M leads to an output signal at the AND circuit M ₂₃ and thus to the display of the result “A > β” at the result output A ~> B. At the same time, the output signal of the AND circuit M _{21 is passed} through the OR circuit o ₂ to the inverter / ₂ , so that no more signal occurs at the output of /. In this way, the inputs of the second AND circuit pairs of the comparator stages of the lower order, namely the inputs of the AND circuits M ₃₃ , M ₃₄ , M ₄₃ and M ₄₄ , connected to the output of the inverter /., Are blocked for outputting output signals . The comparison results of the comparator stages with FF ₁ and FF ₁ as well as FF ₄ and FF _H are not conclusive in this way. Thus, the comparison result in the comparator stage from FF ₉ and FFe indicates the result of the comparison of the two "decimal digits A = 2 and B = O , namely " A > ß ".

It can be seen from the above that in general each of all binary digits is the result of the inequality of their binary digits, the one with the highest order is used to represent the comparison result of the compared decimal digits will.

With that shown in Fig. 1 and described above Comparison circuit according to the invention, a comparison of two decimal digits is made. In order to make this circuit arrangement usable for comparing multi-digit decimal numbers, wherein the individual decimal digits are supplied in increasing order in series, the comparison circuit 1 with a comparison circuit for comparing binary digits shown in series Fig. 2 connected.

For this purpose, the terminals A > B and A <iB of the parallel comparator are used as intermediate result outputs and are connected to the input terminals of the series comparator according to FIG. 2, which are designated in the same way. In order to prevent the effect of Siörsignalen it is useful between the circuits Fig. I and Fig. Insert 2 AND gates, the second inputs of the later-described AND circuits H ₅₁ and H are acted upon ₅₂ in Fig. 2 with a Ausblendtakt similar. To simplify the drawing, this known arrangement has not been shown. In this way, the result of the comparison of two decimal digits of the parallel comparison circuit in bistable switching elements, for example in flip-flops FF _n and FF ₁₀ , is set. Corresponding to the flip-flops FF ₁ to FF ₈ described above, the upper output line of the flip-flops FF _n and FF ₁₀ represents the normal output, the lower output line represents the complement output. As described there, the hatching of the partial areas of FF ₉ and FF _w indicates the switching status of the flip-flops, hatching on the upper sub-area corresponds to information “0”, hatching on the lower sub-area corresponds to information “L”.

A pulse at the input terminals A *> B and A <i B switches the corresponding flip-flop to its "L" position, and an output signal appears on the corresponding normal output. A signal at terminal R, which is connected to the upper inputs of FF ₉ and FF ₁₀ , is used to reset the flip-flops after the comparison operation has taken place. As FIG. 2 shows, the normal output of FF ₉ and the complement output of FF _n , with the inputs of an AND circuit M ₅₁ , the normal output of FF _1n and the complement output of FF, with the inputs of an AND circuit H ₅ , tied together. To avoid false displays, for example due to interference pulses, a test clock signal from terminal P is applied to third inputs of the AND circuits M ₅₁ and « _v> . The output of the AND circuit M, j is via an OR circuit o ,, with the left input of a bistable switching element FF ₁₂ , for example a flip-flop, the output of the AND circuit H ₅ , with the reclv th input of FF , ₂ connected. Furthermore, the outputs of both AND circuits M ₅₁ and M _{52 are combined} via an OR circuit o _{; <} and connected to the right input of a bistable switching element FF ₁₁ , for example a flip-flop.

The flip-flops FF ₁₁ and FF _vi are constructed according to the description of FF ₁ to FF ₁₀ with regard to their switching position and outputs. The left input of both flip-flops FF _V and FF ₁₂ is connected to a terminal S to which a start pulse is given. The right output of FF _n leads to a result output A = B ', the left output of FF ₁ to a result output A <£?'. The left output of FF ₁ and the right output of FF _V y are connected to the inputs of an AND circuit u ,. _n connected, the output of which leads to a result output A > - B ' .

The mode of operation of the circuit according to FIG. 2 in connection with the comparison circuit of FIG. 1 will be described using a numerical example. The decimal numbers A = 533 and B = 443 are to be compared.As is customary in electronic data processing systems, the decimal numbers are processed digit by digit in increasing order; shown (i.e. parallel to series in increasing order). First, a start pulse at terminal S switches the flip-flops FF ₁₁ and FF ₁₂ into the position shown. The result signal ίο »A = ß« appears at output A = B ' as the original result signal due to the switch position of FF _n. FF ₉ and FF ₁₀ are also in the position shown due to the last reset pulse occurring at R _2.

The ones place

Compare two digits 3. At the result outputs A > B and A < B in Fig. 1 and at the corresponding input terminals in Fig. 2, no output or input signal appears, the circuit remains in the position shown, the result remains » / 4 = ß «at A = B '.

The tens digit

To compare the number is from number A 3 by the numeral 4 in number B. As a result of the comparison described above, in the parallel comparison circuit Fig. 1 gives a result signal "AKB" in the result output AKB that appears at the corresponding input terminal in Fig. 2 . Flip-flop FF ₁₀ is switched from the one shown to its second, the "L" position. FF ₉ retains its position. In this way, signals appear at the associated inputs of the AND circuit H ₅₂ , this AND circuit emits an output signal at terminal P at the time of the test tract. This signal switches the flip-flop FF _n via the OR circuit o _s from ier drawn into its second stable position, so that no more signal occurs at A = B ' . At the same time, the output signal from M _{53 appears} at the right input

gang from FF ₁₂ . Flip-flop FF ₁₂ is switched from the drawn to its second stable position, whereby the AND circuit u _m is blocked by the lack of the output signal at the right output of FF ₁₉ , and a result signal is output at the result output A <C B ' will.

The last and highest decimal place

As before each comparison process, the flip-flops FFy and FF _{10 are} reset to the position shown. The number 5 from number A is to be compared with the number 4 from number B. As a result of the number comparison in FIG. 1, a result signal appears at the result output A ^> B and a corresponding input signal appears at the flip-flop FF ₉ . The latter is switched from the drawn to its second stable position, FF ₁₀ remains in the drawn position. As a result, a signal appears at the associated inputs of the AND circuit M ₅₁ ; when the test pulse occurs at terminal P , M ₅₁ therefore emits an output signal. There is no longer a signal at the result output A-B ' , but the left output of FF _{11 sends} a signal to an input of the AND circuit H ₆₀ . At the same time, the output signal from U ₅₁ reaches the left input via the OR circuit o ₉

from FF ₁₂ and switches FF _{12 back} to the position shown. There is also no longer any signal at output A <LB '. However, it is now due to the second

output of the AND circuit U ₀₀ a signal so that « _{6U outputs} a result signal at the result output A ~> B ' .

After processing the last, highest decimal place, the final result of the comparison of the decimal numbers can be read at the result outputs A = B \ A> B ' or A <B' of the series comparator, for example by a query circuit, not shown, which works with a test cycle, similar to realized on the AND circuits H ₅₁ and M _52.

Claims (2)

PATENT CLAIMS: 1. Circuit arrangement for comparing decimal numbers A, B in binary-coded parallel series representation with output terminals for result signals "A >ß","A<Cß" and "A = B" and a parallel comparator, the corresponding binary digits of the digits of the pair of numbers to be compared each contains a comparator stage with a bistable switching element each to receive the code bits of the two digits to be compared, the outputs of the bistable switching elements for one digit directly, for the other comparison digit, on the other hand, crosswise to the comparator belonging to the stage-AND- Circuits are connected which are connected to an inverter (up to the lowest order comparator stage) via an OR circuit each and which (up to the highest order comparator stage) are connected to two locking-ANDs connected to the inverters of all the preceding stages Circuits are connected and wherein corresponding locking AND circuits of the stage highest order are connected via associated OR circuits to output terminals of the parallel comparator for intermediate result signals "A ^>B" and "A <CB" , characterized in that the output terminals of the parallel comparator for the intermediate result signals "A ^>B". and "A <CB" on the one hand via a common OR circuit (o _s ) are connected to the normal input of a first bistable output element (Ff ₁₁ ) whose complement input only before the beginning of each total number comparison with a start pulse producing the result state "A = B" is acted upon, and on the other hand are individually connected to one input each of a further bistable output element (FF ₁₂ ) . 2. Parallel-series comparator according to claim 1, characterized in that the complement output of the first bistable output element (FF _n ) of the series comparator (5F) to an output terminal (A - B ') for the result signal "A = ß", the normal output of the second bistable output element (FF ₁₂ ) to a second output terminal (A <B ') for the result signal "A <CB" and the normal output of the first output element (FF ₁₁ ) and the complement output of the second output element (FF ₁₂ ) via an AND Circuit (w ₆₀ ) are connected to a third output terminal (A > B) for the result signal. Considered publications: U.S. Patent Nos. 2,885,655, 2,889,534. 1 sheet of drawings © 309 648/211 7.