DE112018000230T5 - System and method for speculative instruction execution using the control memory buffer - Google Patents

Abstract

Disclosed are systems and methods for speculative instruction execution using the control storage buffer. NVM Express (NVMe) implements a paired delivery queue and termination queue mechanism whereby host software on the host device places commands in the delivery queue and then notifies the storage device of the instructions in the delivery queue. The delivery queue may reside in the storage device, such as in a control storage buffer. Prior to notification by the host device, the storage device may determine that the instructions are placed in the delivery queue and that instructions can be speculatively executed.

Description

REFER TO RELATED APPLICATIONS

This application claims the priority of U.S. Patent Application No. 15/468620 , filed on March 24, 2017, and the U.S. Patent Application No. 15/585827 , filed on Wednesday, 3 May 2017, both of which are hereby incorporated by reference in their entirety.

BACKGROUND

NVM Express (NVMe) is a standard for accessing non-volatile storage media connected via a PCI Express bus (PCIe bus). NVMe can be used with a variety of non-volatile storage media, such as Solid State Drives (SSDs). One focus of NVMe is on I / O communication between a host device (which can access and / or write to the nonvolatile storage medium) and a storage device (which includes the nonvolatile storage medium). In this regard, NVMe implements a paired delivery queue and completion queue mechanism wherein the host software on the host device places commands in the delivery queue. The terminations are placed in the associated completion queue by the storage device controller.

list of figures

• 1A ist ein Blockdiagramm eines beispielhaften nichtflüchtigen Speichersystems.
• 1B ist ein Blockdiagramm eines Speichermoduls, das eine Vielzahl von nichtflüchtigen Speichersystemen und einen Host einschließt.
• 1C ist ein Blockdiagramm eines hierarchischen Speichersystems.
• 2A ist ein Blockdiagramm beispielhafter Komponenten einer Steuerung des nichtflüchtigen Speichersystems aus 1A.
• 2B ist ein Blockdiagramm beispielhafter Komponenten eines nichtflüchtigen Speicherchips des nichtflüchtigen Speichersystems aus 1A.
• 3 ist ein Blockdiagramm der Hostvorrichtung und der NVMe-Steuerung, das eine Sequenz für eine Hostvorrichtung und eine Speichervorrichtung zum Anfordern und Verarbeiten eines NVMe-Befehls veranschaulicht.
• 4 ist ein Blockdiagramm mit weiteren beispielhaften Komponenten einer Hostvorrichtung und einer Speichervorrichtung.
• 5 ist ein Flussdiagramm zur spekulativen Ausführung eines Befehls in der Übermittlungswarteschlange.
• 6 ist ein Flussdiagramm zur spekulativen Ausführung eines Lesebefehls in der Übermittlungswarteschlange.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the invention and, together with the description, serve to explain its principles. Wherever appropriate, the same reference numbers will be used throughout the drawings to refer to the same or similar elements.

• 1A FIG. 10 is a block diagram of an exemplary nonvolatile memory system. FIG.
• 1B Figure 10 is a block diagram of a memory module including a plurality of nonvolatile memory systems and a host.
• 1C is a block diagram of a hierarchical storage system.
• 2A FIG. 12 is a block diagram of exemplary components of a controller of the nonvolatile memory system 1A ,
• 2 B FIG. 12 is a block diagram of exemplary components of a nonvolatile memory chip of the nonvolatile memory system 1A ,
• 3 Figure 10 is a block diagram of the host device and the NVMe controller illustrating a sequence for a host device and a memory device for requesting and processing an NVMe command.
• 4 FIG. 10 is a block diagram showing further exemplary components of a host device and a memory device. FIG.
• 5 Figure 4 is a flowchart for speculatively executing a command in the delivery queue.
• 6 Figure 4 is a flow chart for speculatively executing a read command in the submit queue.

DETAILED DESCRIPTION OF THE EMBODIMENTS

overview

NVMe is based on paired delivery queues (SQ) and completion queues (CQ). Using software, the host device places commands in a respective submission queue. The storage device places entries in the associated completion queue through the storage device controller, the entries indicating complete command execution. In one implementation, delivery and completion queues are allocated to the memory of the host device. The allocation of the queues in the host memory buffer may be physically contiguous or non-contiguous. Thus, the storage device controller performs a PCI Express (PCIe) to transfer queues residing in the host memory, which is read from the host memory to retrieve the queue entries.

Alternatively, the delivery queues and completion queues may be stored in the storage device. For example, the controller memory buffer (CMB) allows the host device to place the delivery queues and completion queues in the controller storage. Thus, a memory control based queue is used in the same way as a host memory based queue, with the difference that the memory address is within the memory device (eg, rather within the memory controller's own memory than in the host memory ). In particular, the admin and / or I / O queues may be placed in the CMB, as discussed in greater detail below. Therefore, in an implementation for a particular queue, all of the memory that the server has assigned to a particular queue, completely in either the CMB or in the host memory. Delivery queues in the control store allow the host software to write the entire delivery queue entry directly into the storage device controller's internal memory, thereby avoiding reading from the storage device controller into the host device.

Example types of queues include admin queues and I / O queues. The admin queue, such as the admin submission queues and queuing queues, is an administrative submission queue that includes administrative commands to the storage device. Exemplary administrative commands include, but are not limited to: retrieving an exhaust page (e.g., an NVMe exhaust page is retrieved from an NVMe device and provides the retumed structure); Identification (e.g., returning a data buffer describing information about the NVMe subsystem, control or namespaces), function fetching (e.g., retrieving properties of the specified function) / and function setting (e.g., specifying the properties of the displayed function). The listed administrative commands are for illustrative purposes only. I / O commands may refer to data transmission, such as read commands (e.g., reading data from the flash memory) and write commands (e.g., writing data to the flash memory).

Typically, the host device first writes commands to the delivery queue and then notifies the storage device by updating the end-doorbell register of the delivery queue, as discussed in greater detail below. In response to the notification by the host device about a command in the delivery queue, the storage device controller begins to process the command. In one implementation, the memory write request to the end-Doorbell register of the transmit queue may not have the RO (Relaxed Ordering) bit to ensure that it arrives at the memory device controller after everything has been written to the CMB.

In one implementation, the storage device controller begins to process a command prior to notification by the host device via the command in the delivery queue (e.g., prior to notification via the end-Doorbell register of the delivery queue). For example, the storage device may determine if the host device has written a command to the delivery queue. This can be done in one of several ways. In one way, the storage device may monitor the NVMe delivery queues that are physically located in the control storage buffer, thereby allowing the storage device to begin the speculative command execution itself before receiving the corresponding notification from the host device (e.g., Doorbell write transfers). In another way, the storage device may monitor a communication interface between the host device and the storage device (e.g., the PCIe bus input) to determine if the host device has sent any communications indicating a write of a command to a delivery queue.

In response to the determination of the storage device that the host device has written command (s) into the delivery queue (s), the storage device may parse the command (s), and in response to the determination that one or more new commands in the submission queue are to begin speculatively with the execution of the one or more new commands.

Various instructions may be subjected to speculative execution. For example, a read command may be subjected to a speculative read command execution that triggers a Rad Look Ahead (RLA) algorithm. In particular, the relevant data subject to the read command may be retrieved from the flash memory to a temporary cache. When the host device notifies the storage device of the command (e.g., enqueues the relevant command by issuing a write to the corresponding doorbell register of the submission queue), the data can be retrieved immediately from the temporary cache and provided to the host device. In this regard, the RLA hit may result in better latency of the flash memory (e.g., period of capture and transmission) and thereby better performance. In another case, a write command may be subjected to a speculative write command execution. For example, one or more steps to perform the write command, such as fetching the Flash Translation Layer (FTL) table, may be performed before the host device queues the command. Thus, the overall performance of the storage device can be improved.

In one implementation, the storage device selectively performs a speculative execution of instructions. In a first specific Implementation, the storage device may parse the command and may determine, based on the nature of the command, whether speculatively the execution of the command should commence prior to notifying the host device of the Doorbell register by placing the command in the delivery queue. As discussed herein, there are various types of commands, such as read commands, write commands, and the like. For example, a read command may include a pointer to a PRP list, where the PRP list indicates the portions in the host memory where the memory device is to write the data read from the flash memory. Similarly, the write command includes a pointer to a PRP list indicating the portions in the host memory where the data is located for writing to the flash (ie, the memory device uses the PRP list to read host locations for data, where the read data is written to the flash memory).

In a second specific implementation, in at least one embodiment of the instruction, such as the priority of the instruction, the storage device may determine whether (or when) the speculative instruction execution prior to notifying the host device of the Doorbell register by placing the instruction in the delivery queue should be started. As noted in co-pending US Application No. (Ref. No. 10519-3193 (SDA-2985-US Patent), incorporated herein by reference in its entirety, the memory device may prioritize a command (or perform one or more phases) based on one or more criteria, including any or any combination or all of the following: ( 1 ) Priority of the respective command; ( 2 ) Internals of the memory device (eg, the state of the chip or the processing capability of the memory device as set forth below); ( 3 ) Power consumption; ( 4 State of the communication interface between the host device and the storage device (eg, the status of the input and / or output path); and ( 5 ) the phases of the instructions that are subject to execution. Depending on the priority assigned to the instruction, the storage device may determine whether an instruction is subject to speculative execution. In one example, the memory device determines the priority of a first command and a second command, wherein the priority assigned to the first command is higher than the priority assigned to the second command. Based on the determined priorities, the storage device performs a speculative execution of the first instruction before or instead of the speculative execution of the second instruction. Alternatively, in the case that the storage device performs the speculative execution of the second instruction, the storage device may stop performing the speculative execution of the second instruction and begin speculative execution of the first instruction in response to the determination that the host device is the first instruction has placed in the delivery queue and in response to the determination that the priority assigned to the first instruction is higher than the priority assigned to the second instruction.

Thus, in the first and second specific implementations, the storage device performs speculative execution only on threads within the storage device, but not on threads that include the host device (eg, that are external to the host device or in communication with the host Stand device). In this regard, any flow associated with the host device, such as reading a PRP list on the host device, is not speculatively performed. However, an internal process, such as reading from flash memory, performing error correction or encryption / decryption, may be performed speculatively. In this regard, in a specific implementation, the storage device may perform a speculative execution of a read command, but not a speculative execution of a write command. Specifically, prior to receiving the Doorbell notification from the host device, the storage device speculatively performs certain operations in the execution of the read command, such as reading from the flash memory, performing error correction and encryption, but does not perform other operations by communication with the host device, such as by reading the PRP list located on the host device.

One measure of the performance of the NVME command execution is the period between the issuance of the Doorbell write to a submission queue by the host device and the delivery of a completion message to the submission queue by the storage device. Using speculative execution, this time can be reduced. In this regard, speculative execution may improve performance for certain instructions, such as read and write instructions, especially at low queue depths. Furthermore, instruction execution latency, which can be measured on the PCIe bus, can be improved for different types of instructions (e.g., read, write, and admin commands). Finally, the speculative implementation may be implemented in both hardware and firmware, thereby simplifying integration within the storage device.

Typically, when the host device writes a command to the delivery queue, the host device notifies the storage device of the command (eg, the command is optionally queued from the host device for writing to the corresponding doorbell register end). It is atypical that the host device can write one instruction to the delivery queue and then override the instruction with another instruction and then queue the other instruction. Regardless, speculative execution may affect this atypical situation.

embodiments

The following embodiments describe nonvolatile memory devices and associated methods for processing instructions. Before referring to these and other embodiments, the following paragraphs provide a discussion of exemplary non-volatile memory devices and memory modules that may be used with these embodiments. Of course, these are only examples and other suitable types of nonvolatile memory devices and / or memory modules may be used.

1A FIG. 10 is a block diagram illustrating a nonvolatile memory device. FIG 100 illustrated. The nonvolatile storage device 100 can be a controller 102 and a non-volatile memory consisting of one or more non-volatile memory chips 104 can exist. As used herein, the term element refers to the set of nonvolatile memory cells and associated circuitry for managing the physical operation of these nonvolatile memory cells formed on a single semiconductor substrate. The control 102 may interface with a host device or host system and transmit instruction sequences for read, program and erase operations to the non-volatile memory chip (s) 104. As explained below, the instructions may include logical and / or physical addresses.

The control 102 (which may be a flash memory controller) may take the form of a processing circuit, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (eg, software or firmware) provided by the (micro) processor, logic gate, Switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. The control 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts. In addition, some of the components shown as being within the controller may also be stored outside the controller, and other components may be used. In addition, the term "operatively in communication with" could mean directly in communication with or indirectly (wired or wireless) in communication with one or more components, which may or may not be shown or described herein.

As used herein, the flash memory controller is a device that manages data stored in the flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller may have various functions in addition to the specific functionality described herein. For example, the flash memory controller may format the flash memory to ensure that the memory is operating properly to isolate bad flash memory cells and allocate spare cells to replace defective cells in the future. Some parts of the spare cells can be used to capture firmware, operate the flash memory controller, and implement other features. An example of the firmware is a flash translation layer. If a host device needs to read data from flash memory during operation or write data to it, the host communicates with the flash memory controller. When the host provides a logical address to which to read / write data, the flash memory controller may convert the logical address received from the host to a physical address in the flash memory controller. The flash memory controller may also perform various memory management functions, such as memory management. For example, but not limited to, wear leveling (distributing writes to avoid wearing down specific memory blocks that would otherwise be written to repeatedly) and garbage collection (after a block is full, shifting only the valid data pages to a new block such that the full block can be deleted and reused).

The interface between the controller 102 and the nonvolatile memory chip 104 can be any suitable flash interface, such as. As the toggle mode 200 . 400 or 800 , In one embodiment, the storage device 100 be a card-based system, such. As a secure digital (SD) or a secure digital micro-card (micro-SD). In an alternative embodiment, the system 100 Be part of an embedded storage device.

Although the non-volatile memory device 100 in the 1A illustrate a single channel between the controller 102 and the non-volatile memory chip (s) 104 may include, the subject matter described herein is not limited to a single memory channel. For example, in some NAND memory device architectures 2 . 4 . 8th or more NAND channels between the controller and the NAND memory chip (s) 104 depending on the capabilities of the controller. In each of the embodiments described herein, more than a single channel may exist between the controller and the memory chip (s) 104, even though a single channel is shown in the drawings.

1B illustrates a memory module 200 containing several non-volatile memory devices 100 includes. As such, the memory module 200 a memory controller 202 Include that with a host 220 and with a storage system 204 connected to a variety of non-volatile memory devices 100 includes. The interface between the memory controller 202 and the nonvolatile memory devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interface Express (PCIe) interface, an embedded MultiMediaCard (eMMC) interface, an SD interface, or a Universal Serial Port (USB) interface Bus). The storage system 200 For example, in one embodiment, it may be a solid state drive (SSD) such as found in portable computing devices such as laptop computers, tablet computers, and cell phones.

1C is a block diagram illustrating a hierarchical storage system 250 illustrated. The hierarchical storage system 250 can be a variety of storage controllers 202 each of which includes a corresponding storage system 204 controls. The host systems 252 can access memory within the hierarchical storage system via a bus interface 250 access. Example bus interfaces may include, for example, an NVMe interface (non-volatile memory express), a FCoE interface (Fiber Channel over Ethernet), an SD interface, a USB interface, a SATA interface, a PCIe interface or an eMMC interface lock in. In one embodiment, the in 1C illustrated hierarchical storage system 250 a frame mountable mass storage system that can be accessed by multiple host computers, such as found in a data center or other location where mass storage is required. In one embodiment, the host systems 252 which in host 220 include described functionality.

2A is a block diagram illustrating example components of the controller 102 illustrated in more detail. The control 102 can be a frontend module 108 that is paired with a host, a backend module 110 which is coupled to the nonvolatile memory chip (s) 104 and various other modules that include various functions of the nonvolatile memory device 100 carry out. In general, a module may be hardware or a combination of hardware and software. For example, each module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other Type of hardware or combination thereof. Additionally or alternatively, each module may include memory hardware that includes instructions that are executable with a processor or processor circuitry to implement one or more of the features of the module. If one of the modules includes the portion of the memory that includes instructions that are executable with the processor, the module may or may not include the processor. In some examples, each module may be only that portion of the memory that includes instructions that are executable with the processor to implement the features of the corresponding module without the module including any other hardware. Because each module includes at least some hardware, even if the included hardware includes software, each module can be interchangeably referred to as a hardware module.

The control 102 may be a buffer manager / bus control module 114 Include the Buffer in Random Access Memory (RAM) 116 managed and the internal bus allocation for communication on an internal communication bus 117 the controller 102 controls. A read-only memory (ROM) 118 can save and / or access the boot code of the system. Although she is in 2A as from the controller 102 can be shown separated, in other embodiments, either the RAM 116 or the ROM 118 or both within the controller 102 be arranged. In still other embodiments, portions of the RAM may become 116 and the ROM 118 both within the controller 102 as well as outside the controller 102 are located. Further, in some implementations, the controller may 102 , the RAM 116 and the ROM 118 be arranged on separate semiconductor elements. As explained below, in one implementation, the delivery queues and completion queues may be in the Control memory buffer stored in the RAM 116 can be accommodated.

Additionally, the frontend module 108 a host interface 120 and a physical layer interface (PHY) 122 which provide the electrical interface to the host or the next level storage controller. The choice of the type of host interface 120 may depend on the type of memory used. Example types of the host interface 120 These include, but are not limited to, SATA, SATA Express, SAS, Fiber Channel, USB, PCle, and NVMe. The host interface 120 usually allows the transmission of data, control signals and time signals.

The backend module 110 Can An ECC Engine (Error Correction Controller) 124 that encodes the bytes of data received from the host and that is sent from the nonvolatile memory chip (s). 104 data bytes decoded and errors corrected. As further explained below, the ECC engine may be tunable to generate, for example, different amounts of ECC data based on the mode (eg, generate normal mode ECC data in normal programming mode and burst mode ECC data in burst mode). Generate programming mode, where the burst mode ECC data is greater than the normal mode ECC data). The backend module 110 can also use a command sequencer 126 which generates instruction sequences such as program, read and erase instruction sequences to be transmitted to the nonvolatile memory die 104 (s) 104. In addition, the backend module 110 a RAID module (Redundant Array of Independent Drives) 128 which manages the generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data entering the nonvolatile storage device 100 to be written. In some cases, the RAID module 128 Part of the ECC engine 124 his. A memory interface 130 returns the command sequences to the nonvolatile memory die (s) 104 and receive status information from the nonvolatile memory die (s) 104 , In addition to the command sequences and status information, data to be programmed into and read from the nonvolatile memory chip (s) 104 may be provided via the memory interface 130 be communicated. In one embodiment, the memory interface 130 a DDR interface (Double Date Rate) and / or a toggle mode 200 . 400 , or 800 Be interface. A flash control layer 132 can the overall operation of the backend module 110 control.

Thus, the controller 102 One or more management tables for managing operations of the storage system 100 lock in. One type of management table includes a logical-to-physical address mapping table. The size of the logical-to-physical mapping table can grow with memory size. In this regard, the logical-to-physical address mapping table for high performance memory devices (e.g., greater than 32G ) To be too large to store in the SRAM, it can be stored in non-volatile memory 104 stored together with user and host data. Therefore, accesses to the non-volatile memory 104 First, read the logical-to-physical address map from the nonvolatile memory 104 require.

Additional modules of in 2A illustrated storage device 100 can be a media management layer 138 for wear compensation of memory cells of the nonvolatile memory chip 104 lock in. The nonvolatile storage device 100 can also have other discrete components 140 included, such as external electrical interfaces, external RAM, resistors, capacitors or other components that come with the controller 102 can be connected. In alternative embodiments, one or more of the components are RAID module 128 , Media Management Layer 138 and buffer management / bus control 114 optional components included in the controller 102 may not be necessary.

Other modules of the nonvolatile memory device 100 , in the 2A can be a host command writing module 111 , an execution module of speculative instructions 112 and a host override determination module 113 lock in. As shown, these modules are from the other modules of the nonvolatile memory device 100 although in other configurations one or more of them may be part of one of the other modules.

As discussed in greater detail below, the storage device may determine whether the host device has written to the delivery queue before the host device accesses the storage device using the host command writing module 111 formally notified. Further, in response to the storage device determining that the host has written a command to the delivery queue, the execution module may issue speculative instructions 112 begin to execute the command before a formal notification from the host device. In addition, the host override determination module may 113 determine if the host device is the command which subject to speculative execution, as will be explained in greater detail below.

2 B FIG. 10 is a block diagram illustrating example components of a nonvolatile memory chip. FIG 104 represents more detailed. The non-volatile memory chip 104 can be a nonvolatile storage array 142 lock in. The nonvolatile storage array 142 may include a plurality of nonvolatile memory elements or cells, each of which is arranged to store one or more bits of data. The nonvolatile memory elements or cells may be any suitable nonvolatile memory cells, including NAND flash memory cells and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The memory cells may take the form of solid-state (eg, flash) memory cells and may be one-time programmable, multi-programmable, or multi-programmable. In addition, the storage elements or cells may be set up as single-level cells (SLCs) that store a single data bit per cell, multi-level cells (MLCs) that store multiple bits of data per cell, or combinations thereof. For some example configurations, the multi-level cells (MLCs) may include triple-level cells (TLCs) that store three bits of data per cell.

Additionally, a flash memory cell may be in the array 142 a floating gate transistor (FGT) having a floating gate and a control gate. The floating gate is surrounded by an insulator or insulating material that helps hold charge in the floating gate. The presence or absence of charges within the floating gate can cause a shift in a threshold voltage of the FGT that is used to distinguish logic levels. That is, the FGT threshold voltage may indicate the data stored in the memory cell. In the following, FGT, memory element and memory cell can be used interchangeably to refer to the same physical unit.

The memory cells may be in the memory array 142 be arranged in accordance with a matrix-like structure of rows and columns of memory cells. At the intersection of a row and a column is an FGT (or memory cell). A column of FGTs can be called a string. FGTs in a string or column can be electrically connected in series. One line of FGTs can be called a page. Control gates of FGTs in a page or row can be electrically connected together.

The storage array 142 may also include wordlines and bitlines connected to the FGTs. Each side of FGTs is connected to a wordline. In particular, each wordline may be coupled to the control gates of FGTs in a page. In addition, each string of FGTs may be coupled to a bitline. Further, a single string may span multiple wordlines, and the number of FGTs in a string may equal the number of pages in a block.

The non-volatile memory chip 104 may also include a page buffer or data cache 144 which caches data from the storage array 142 sampled and / or programmed for this. The non-volatile memory chip 104 can also use a row address decoder 146 and a column address decoder 148 lock in. The row address decoder 146 may decode a row address and a particular wordline in the memory array 142 Select if data in the memory cells of the memory array 142 written or read from these. The column address decoder 148 may decode a column address to a particular group of bitlines in the memory array 142 for electrical coupling to the data cache 144 select.

In addition, the non-volatile memory chip 104 a peripheral circuit 150 lock in. The peripheral circuit 150 can be a state machine 151 Include the status information to the controller 102 supplies. Other functionalities of the state machine 151 are described in more detail below.

3 illustrates a sequence of steps for processing a command over the NVMe standard. As shown, the host device completes 300 a host memory 302 and the storage device includes control, such as an NVMe controller 310. In one implementation, the host memory completes 302 a delivery queue 304 and a termination queue 306 on. In practice, the host device generates 300 in the initialization phase, one or more delivery queues and one or more corresponding completion queues. As discussed above, in one implementation, the delivery queues and completion queues may have a one-to-one mapping, and in another implementation, the delivery queues and completion queues do not have a one-to-one mapping.

Input can be the host device 300 informing the storage device of the delivery queue (s) and completion queue (s) by providing information such as the base address for each queue the storage device sends. In this regard, each submission queue has a corresponding completion queue. When the delivery queue and the completion queue are in the host device, the host device sends information to the storage device to allow the storage device to determine the locations of the delivery queue and the completion queue in the host device. In a specific implementation, the host device sends a command indicating the generation of the delivery queue and the completion queue. The instruction may include a PRP1 pointer which is a pointer to a list on the host device indicating the storage locations of the specific delivery queue or specific completion queue. In practice, the storage device sends a TLP read request using the PRP1 to obtain the PRP list and stores the PRP list in the storage device to determine the locations within the host device that will be used in future commands to read from the specific delivery queue or used to write to the specific completion queue. Alternatively, the host device 300 instruct the storage device, the delivery queue (s), and the corresponding completion queue (s) in a memory located in the storage device, such as a storage device. A control memory buffer.

The delivery queue 304 can be based on a ring buffer, as in 3 illustrated with an initial pointer and an end pointer. After generating the delivery queue (s) and notifying the storage device of the generated delivery queue (s), the host device may 300 Write a command (or multiple commands) to the submission queue. This is in 3 as a step 1 specified, named "Queue Command". In particular, illustrated 3 that four commands were written to the submission queue. In one implementation, the storage device is not aware of the host device 300 the delivery queue 304 has updated with four commands, since the host device 300 their own host storage 302 has updated. In another implementation (eg, when the delivery queue (s) and the completion queue (s) are in the control storage buffer), the storage device may provide a communication interface between the host device 300 and the storage device for certain communications monitor such. For example, writing to the transfer queue (s) on the storage device. For example, the storage device may monitor the transport layer packets (TLPs) on the PCI Express bus to determine whether the host device 300 has sent a TLP that results in an update of the delivery queue present in the control storage buffer. In this regard, the storage device may identify one or more entries written to the delivery queue (s).

In step 2 writes the host device 300 into an end-Doorbell register of the delivery queue 312 in the storage device. This write to the end-Doorbell register of the delivery queue 312 indicates to the storage device that the host device has one or more commands in that specific delivery queue 304 (eg 4 commands, as in 3 illustrated). Writing to the end-Doorbell register of the delivery queue 312 can take one of several forms. On the one hand shows the host device 300 a new end for the delivery queue 304 , which indicates the number of commands that are in the submission queue 304 were written. Thus, the storage device is the base address for the delivery queue 304 The storage device only needs to know the end address to indicate the number of new instructions that will be in the delivery queue 304 were written. After a command (or set of commands) has been processed, the storage device then places the new beginning of the delivery queue 304 accordingly. So that the tail pointer can represent an "offset" from the start pointer. On the other hand, the host device gives 300 a number of commands that are in the submission queue 304 were written. In practice, each submission queue points 304 a corresponding end Doorbell register of the transmission queue in the memory device, so that when the host device 300 updated a particular Doorbell register (that with a specific delivery queue 304 The storage device may determine which particular delivery queue based on the Doorbell register 304 was updated.

After step 2 (where the storage device is one or more command (s) on the delivery queue 304 informed) and before step 3 (With the storage device retrieving the command (s)) the storage device is aware that in the delivery queue 304 one / more command (s) pending. In general, there can be multiple delivery queues (with potentially many pending commands in the different delivery queues). Thus, the storage device controller may perform prior to performing the step 3 between the different delivery queues to select the particular delivery queue from which to retrieve the command (s).

In response to determining which particular delivery queue 304 the command (s) are to be retrieved, the storage device calls in step 3 the command (s) from the particular delivery queue 304 from. In practice, the storage device may access the base address of the particular delivery queue 304 and access the pointer on the current header pointer in the host device 300 is implemented.

As explained above, the transmission queue or the completion queue may be allocated a memory area (such as in the host device or in the control memory buffer in the memory device). The delivery queue and the completion queue may include multiple entries, each associated with a specific instruction. The size of each entry may be a predetermined size, such as 64 Kb. In this regard, entries within the delivery queue may be based on the base address for the delivery queue and offsetting the base address against the number of entries multiplied by the size of each entry (e.g. Kb) are determined.

As discussed above, the storage device has knowledge of the tail pointer that it used in step 2 was notified. Thus, the storage device can receive all new commands from the delivery queue 304 receive. In a delivery queue located on the host device, the storage device may send a TLP request to receive the command (s) from the delivery queue 304 to obtain. In response to receiving the TLP request, the host device sends 300 a TLP completion message with the instructions in the submission queue 304 , In this connection, the memory device receives at the end of step 3 the command (s) from the delivery queue 304 ,

At step 4 the storage device processes the command. In one implementation, the storage device analyzes the instructions and determines the steps to execute the instructions (eg, read / write / etc.). For example, the command may include a read command. In response to receiving the read command, the storage device analyzes the read command, implements the address translation, and accesses the flash to receive the data. After receiving the data, the storage device causes the data to be stored on the host device based on information in the command (e.g., the PRP file discussed below). 1 ). As another example, the command may include a write command. In response to receipt of the write command, the storage device analyzes the write command, determines the location of the data on the host device being written, reads the data from the location on the host device, and writes the data into the flash memory.

In particular, the memory device may receive a read command or a write command with a PRP1 pointer. For example, a read command in which the host device requests the memory device to read from the flash memory includes a PRP1 pointer pointing to a PRP list. The storage device obtains the PRP list to determine the locations within the host device to write the data read from the flash memory. As another example, a write command in which the host device requests the memory device to write data to the flash memory includes a PRP1 pointer pointing to a PRP list. The storage device receives the PRP list to determine the locations within the host device from which to read the data from the flash memory (and thereafter store the read data on the flash memory).

Each entry in the PRP list may be associated with a particular section in the host device memory and may have a predetermined size, such as 4 Kb. Thus it can be in a 1 Mb transmission 250 Give references in the PRP list, each 4 Kb in size. In practice, the storage device may retrieve data outside the sequence. This may be because the data to be retrieved is on multiple flash chips, with the chips being available for retrieval at different times. For example, the memory device may retrieve the data corresponding to 100-200 Kb of the 1 Mb transmission before retrieving the data corresponding to 0-100 Kb of the 1 Mb transmission. Nevertheless, since the storage device has the PRP list (and therefore knows the storage locations where host device expects the 100-200 Kb to be stored therein), the storage device can transfer the data corresponding to 100-200 Kb of the 1 Mb transfer, without having first retrieved the data corresponding to 0-100 Kb of 1 Mb transmission.

In NVMe, there may be a plurality of PCI-e TLPs to transfer the data from the storage device to the host device 300 transferred to. In general, the data transferred in the host memory 302 the host device 300 stored on the basis of a hint in the command (eg, the command includes an address to store the requested data).

After completion of the data transfer, in step 5 The storage device controller sends a termination message to the relevant completion queue 306 , As mentioned above, the host device allocates 300 in the initialization phase, the delivery queues to the completion queues. The host device knows this 300 which commands in the delivery queue have been terminated based on which termination queue the storage device is writing to. The completion message may include information related to the processing of the instruction (s), such as whether the instruction has completed successfully or an error has occurred in the execution of the instruction.

After the step 5 knows the host device 300 not that the storage device is in the termination queue 306 has set. This is because the storage device causes data to be in the completion queue 306 to be written. In this connection, the storage device notifies the host device 300 in step 6 in that an update of the completion queue 306 took place. In particular, the memory device sends an interrupt to the host device 300 (For example, in NVMe the host device can 300 use an MSIe interrupt).

In response to receipt of the interrupt, the host device determines 300 in that one or more completion entries in the termination queue 306 for the host device 300 pending. In step 7 processes the host device 300 then the entries in the termination queue 306 ,

After the host deletes the entries from the termination queue 306 has processed, notifies the host device 300 in step 8th the storage device via the entries that the host device 300 from the termination queue 306 has processed. This can be done by updating a start Doorbell register 314 the termination queue indicating to the storage device that the host device 300 one or more entries from the termination queue 306 has processed. In response to updating the start Doorbell register 314 the termination queue updates the memory device the beginning of the completion queue 306 , With the new beginning, the storage device knows which entries in the termination queue 306 already from the host device 300 have been processed and can be overwritten.

4 FIG. 10 is a block diagram of other exemplary components of a host device. FIG 400 and a storage device 420 , The host device 400 closes the host memory 402 a, the Physical Region Page (PRP) 404 , Data buffer 406 and other stores 408 can have.

4 further illustrates a communication interface between the host device 400 and the storage device 420 , In a first implementation (in 4 not shown), the communication interface between the host device and the storage device is implemented as a simplex interface, with communications to and communications from the storage device on the same path. In a second implementation (in 4 illustrated) is the communication interface between the host device 400 and the storage device 420 designed as a duplex interface, with a separate input path and a separate output path. The input path contains from the perspective of the storage device 420 incoming requests from the host device 400 to the storage device 420 , Conversely, the output path contains from the perspective of the storage device 420 outbound requests from the storage device 420 to the host device 400 ,

The incoming requests (requests from the host device 400 to the storage device 420 ) can be segmented in several ways, such as incoming read requests and incoming write requests. Similarly, the storage device 400 via the input path, a read request to a memory section in the memory device 420 or a write request for writing to a memory section in the memory device 420 send. Similarly, the storage device 420 via the output path, a read request to a portion of the memory in the host device 400 or a write request for writing to a portion of the memory in the host device 400 send.

In practice, using MVMe, there may be a series of read requests (a request from the host device to read data resident on the storage device, and vice versa) and a series of write requests (a request from the host device to write data to one the storage device resident location, and vice versa). In particular, the storage device and the host device communicate with each other in NVMe TLP requirements (Transaction Layer Packet), such as: For example, TLP read requests to perform a read on the other device, or TLP write requests to perform a write on the other device. In one example (with the SQ and CQ on the host device), the memory device uses the Doorbell register on the memory device in response to a TLP write request (sent via the input path) by the host device (writing to the Doorbell device). Register indicates that a command is present in the SQ) a TLP read request (sent over the output path) to fetch the write command from the SQ (located on the host device). Thus, the write command is a request for the memory device to write data to the nonvolatile memory. The storage device then analyzes the write command for information, such as an indication of a PRP pointer (eg, PRP1) to a PRP list. The PRP list is a set of information, such as pointers or addresses, that indicate the location of the data in the host device. The storage device then uses another TLP read request to read data from the pointers or addresses in the PRP list. Thereafter, the storage device performs the writing operation by storing the data in a nonvolatile memory (eg, a flash memory) on the storage device. After storing the data, the storage device uses a TLP write request to write an entry to the CQ (indicating that the write command has been completed). Finally, the memory device uses a TLP write request to generate an interrupt to the host device, which interrupt signals the host device that an entry exists in the CQ. In response to the interruption, the host device reads the entry in the CQ and then issues a TLP write request to a CQ Doorbell write register indicating that the host device has checked the entry in the CQ.

In another example (with the SQ and the CQ residing on the host device), the storage device uses the Doorbell register on the storage device (in which writing to the Doorbell register indicates that a write request is made by the host in response to a TLP write request from the host Command on the SQ) is a TLP read request to fetch the read command from the SQ (located on the host device). Thus, the read command is a request for the memory device to read data from the nonvolatile memory and send the read data to the host device. The storage device then reads the nonvolatile memory (eg, flash memory) to read out the data. The memory device may perform a number of operations on the data, such as error correction, encoding / decoding, etc., with memory buffers interspersed between each of the serial operations. The storage device may then analyze the read command for information, such as an indication of a PRP pointer (eg, PRP1) to a PRP list. The PRP list is a set of information, such as: Pointers or addresses indicating the location in the host device to store the data read from the non-volatile memory (and optionally error-corrected, encrypted, etc.). The storage device then uses a TLP read request to read data from the pointers or addresses in the PRP list. Thereafter, the storage device uses a TLP write request to write the data read from the nonvolatile memory. After writing the data to the host device, the storage device uses a TLP write request to write an entry to the CQ (indicating that the read command has ended). Finally, the memory device uses a TLP write request to generate an interrupt to the host device, which interrupt signals the host device that there is an entry in the CQ. In response to the interruption, the host device reads the entry in the CQ and then issues a TLP write request to a CQ Doorbell write register indicating that the host device has checked the entry in the CQ.

Optionally, the CQ and SQ may reside in the memory device, such as in the Control Memory Buffer (CMB). In this case, the host device may send a TLP write request (sent over the input path) to the storage device to write to the termination queue. Likewise, the memory device may send a TLP write request (sent over the output path) to generate an interrupt for the host device.

The storage device 420 closes the storage device control 422 and the storage arrays 446 on. The storage array 446 can be segmented in several ways, such as in 10 Sections, as in 4 illustrated. The storage device controller 422 can use any or all of a PCIe MAC and PHY interface 424 contain. The storage device controller 422 can also have one or more processors 450 lock in.

The storage device controller 422 also closes the Control Memory Buffer (CMB) 426 which is the host device 400 is assigned. As discussed above, the various queues, including the Delivery queues and completion queues residing in the host device or in the storage device. As in 4 shown, the queues are in CMB 426 in the storage device 420 , such as the delivery queues 428 , Additionally, CMB 426 other data 430 lock in.

The command parser 432 is set up to one or more internal buses, such as the bus of the PCle MAC and PHY interface 424 to CMB 426 to monitor. command parser 432 is still for parsing by the host device 400 real-time written NVMe commands (or if the commands are sent internally within the storage device 420 and to select the commands that are candidates for speculative execution. command parser 432 can use these commands in the performing unit for speculative commands 434 rows that can be implemented both in hardware and in firmware. As will be explained in more detail below, the speculative instructions execution unit may 434 based on resources within the storage device 420 the execution phase of these commands even before a formal notification of the commands from the host device 400 start.

The flash interface module 440 is set up to the storage arrays 446 to control and access them. For example, the flash interface module 440 with the storage arrays 446 interact, mainly during read and write operations. planner 440 is for controlling the data transfer during the activation of the control path 436 for retrieving the PRPs, the completion message (eg, step 5 in 3 ) and the interruptions (eg step 6 in 3 ) as well as the activation of the DMAs 438 for the actual data transfer between the host device 400 and the storage device 420 set up. The error correction engine 442 is set up by the storage arrays 446 to correct retrieved data.

In one implementation, speculative instruction execution does not speculatively expose any process that relates to the host device 400 refers to. Rather, the completion message may be executed only after the queue command, which may be a write to the corresponding Doorbell register (see step 3 in 3 ).

Even though 4 Includes queues, such as the delivery queue 428 in CMB 426 in the storage device 420 , the speculative execution may be performed when the queues, such as sequential queues, in the host device 400 are located. In this case, sequential queues may be stored in the DRAM host. In some applications, it may be advantageous to pre-fetch commands from the next slots in the sequential queues even before the host device 400 the storage device 420 notified (eg in step 2 from 3 in the Doorbell register writes). In such implementations, the storage device internally holds the previous commands received from the host device in the past 400 in the same slots were ranked. When the commands are prefetched, the storage device may 420 First, be aware of any new commands in these slots by the host device 400 are set, or if the previous commands still exist. If there are new commands available, the storage device can 420 The speculative execution will start even before the host device 400 Issue the Doorbell write. Thus, the storage device 420 communicate via the PCIe MAC PHY interface 424 to the new commands residing in the submission queues on the host device 400 are to be prefetched.

5 is a flowchart 500 to speculatively execute a command in the delivery queue. In 502 writes the host device 400 a command in the submission queue 428 that are in CMB 426 located. In 504 parses the command parser 432 the command in real time while the command in CMB 426 is written. In 506 determines the command parser 432 whether the command is speculative or not. In particular, the command parser 432 Analyze one or more aspects to determine if speculative execution is to be performed. In one implementation, the command parser parses 432 the instruction itself (eg, the type of instruction) to determine whether to perform a speculative execution. In an example, in response to the determination of the command parser 432 in that the command is a read command, the speculative execution is performed. In this case, the memory device may be connected to the memory array in 510 446 and prefetch some (or all) data in response to the read command and prepare for entry into a particular state or database. Conversely, there are certain NVMe commands where there is no added value for a speculative execution. In this regard, in 508, execution of these certain NVMe instructions will not begin until the host device has notified of the command (eg, step 2 from 3 ).

In another implementation, the command parser parses 432 the available internal resources of the storage device 420 to determine if speculative execution is to be performed. In one example, the command parser determines 432 in response to the determination of the command parser 432 that storage device 420 has sufficient internal resources to perform the speculative execution to perform the speculative execution. Conversely, if at some point there are no available resources in the storage device required to execute the command, the command can be executed later, and even after the host command queue. In yet another implementation, the command parser parses 432 both the instruction and the internal resources of the storage device by determining whether to perform a speculative execution. Thus, if there are available resources and if the instruction is a candidate for speculative execution, the storage device starts the speculative execution phase.

There are cases where the host device 400 can overwrite a command after the command enters the submit queue 428 has been set. Thus, the storage device determines in 512 whether the host device 400 overwritten the commands before they were ranked. If this is the case, in 514 canceled the speculative execution of the overwritten command. Otherwise it will be in 516 determines if the host device 400 by placing the command in the queue by writing to the corresponding Doorbell register (eg, step 2 from 3 ). If not, the flowchart jumps 500 back to 512 and wait to determine if overwriting has occurred. If so, the storage device may 420 in 518 continue the command execution normally while using speculative execution. As an example, speculative execution of a read command may involve reading data from the memory arrays 446 and storing the read data into temporary memory buffers as described with reference to 6 explained.

6 is a flowchart 600 for the speculative execution of a read command in the submission queue. As described above, when the host device 400 writes a command into the delivery queue requiring read access to the flash memory array, the read may begin at this point in a speculative manner (eg, a wheel look ahead). Thus, in 602 determines whether the host device has written a command that requires a read access. If this is the case, in 604 the storage device controller 422 on the storage arrays 446 in 606 access, read the appropriate pages and in 608 Save the read relevant pages in a temporary buffer. As discussed above, from the memory array 446 read data (such as the flash memory) undergo a read, such as error correction and / or encryption / decryption. For example, the read data may first be analyzed for errors and using the ECC controller 124 Errors in the read data are corrected. The corrected data may then be subject to encryption or decryption and eventually stored in the temporary buffer.

In 610 determines the storage device control 422 whether the host device 400 queued the command. If the host device 400 the command in 612 determines whether the command has been overwritten. If not, can in 614 retrieve the data from the temporary buffer instead of fetching it from the flash memory arrays. In this regard, in one implementation, the data stored in the temporary buffer is transmitted to the host only when the host device 400 the order lines up. In a more specific implementation, the storage device may retrieve corrected decrypted data from the temporary buffer for transmission to the host device. In this way, the storage device may perform the fetch, error correction, and encryption or decryption functions before the instruction is fetched by the host device (eg, the host device will perform step 2 in 3 by).

Conversely, during the time the data is stored in the temporary buffer, the host device may 400 overwrite the command. In this case, in 614 provided the new data for the corresponding read command.

Due to the speculative implementation, the memory device may access the temporary memory buffers to transmit the read data to the host device when the host device 400 the order lines up. This is in contrast to conventional instruction execution in which the data is read from the memory array in response to the instruction string. Therefore, with respect to read commands, the speculative execution may be faster because reading the data from the temporary buffer is faster than reading the data from the memory arrays 446 he follows. The benefit in this case could be significant as the read performance of low depth queues can be increased slightly.

Commands other than read commands may be speculative execution candidates. For example, write commands may be speculative. In particular, the speculative execution for flash writes may include retrieval of the Flash Translation Layer (FTL) table used for address translations (eg, logical block into a physical block translation table). In another example Power management commands are executed speculatively. In particular, the host device 400 prompt the storage device to enter a specific NVMe power state using the function setting command. The speculative execution in this case may include flushing all internal caches into the flash memory array and other preparations related to that particular state. In yet another example, flush commands may be performed speculatively. In particular, the host device 400 Send flush commands. In response, the storage device flutters 420 put their temporary buffer on the medium and then put the host device 400 a completion message too. For a speculative flush, the storage device may 420 start the flushing process as usual. In the worst case, the host device may override the command (eg, will not order the command). Nonetheless, even if the storage device has 420 executing flushes, the storage device 420 no rule disregarded.

Finally, as mentioned above, any suitable storage type can be used. Semiconductor memory devices include volatile memory devices, such as "Dynamic Random Access Memory (DRAM) memory devices, or Static Random Access Memory (SRAM) memory devices, nonvolatile memory such as Resistive Random Access Memory (ReRAM) memories." Electrically Erasable Programmable Read Only Memory, Flash Memory (which may also be considered a subset of an EEPROM), Ferroelectric Random Access Memory (FRAM), and Magnetoresistive Random Access Memory (MRAM) memory ) and other semiconductor elements that can store information. Each type of storage device may have different configurations. For example, flash memory devices may be configured in a NAND or NOR configuration.

The memory devices may be formed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory devices include ReRAM device elements, in some embodiments a resistive memory element such as an anti-fuse, phase change material, etc., and optionally a steering element such as a diode, etc. , contain. Further, by way of non-limiting example, semiconductor active memory elements include EEPROM and flash memory device elements, which in some embodiments include elements having a charge storage region, such as a floating gate, conductive nanoparticles, or a charge-storing dielectric material.

Multiple storage elements can be set up in series or each item can be accessed individually. As a non-limiting example, flash memory devices in NAND (NAND) configuration typically include memory elements connected in series. A NAND memory array may be arranged such that the array is composed of a plurality of memory chains in which a chain is composed of a plurality of memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g. B. a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.

The semiconductor memory elements disposed within and / or over a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (eg, in an x-z direction plane) that extends substantially parallel to a major surface of a substrate carrying the memory elements. The substrate may be a wafer over or in which the layer of memory elements is formed, or it may be a carrier substrate attached to the memory elements after formation. As a non-limiting example, the substrate may include a semiconductor such as silicon.

The storage elements may be arranged on the single storage device level in an ordered array, such as in a plurality of rows and / or columns. However, the memory elements may be arranged in non-regular or non-orthogonal configurations. The memory elements may each comprise two or more electrodes or contact lines, such as bit lines and word lines.

A three-dimensional memory array is arranged such that memory elements occupy multiple levels or multiple memory device levels, thereby forming a structure in three dimensions (ie, in the x, y, and z directions, where the y-direction is substantially perpendicular and the x and z-directions are substantially parallel to the main surface of the substrate).

As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of a plurality of two-dimensional storage device layers. As a further non-limiting example, a three-dimensional memory array may be arranged as a plurality of vertical columns (eg, columns extending substantially perpendicular to the main surface of the substrate, ie, in the y-direction), each column having a plurality of memory elements in each column. The columns may be arranged in a two-dimensional configuration, e.g. In an xz plane, resulting in a three-dimensional array of storage elements with elements on multiple vertically stacked storage levels. Other configurations of storage elements in three dimensions may also form a three-dimensional storage array.

As a non-limiting example, in a three-dimensional NAND memory array, the memory elements may be coupled together to form a NAND chain within a single horizontal (eg, x-y) memory device levels. Alternatively, the storage elements may be coupled together to form a vertical NAND chain that extends across a plurality of horizontal storage device levels. Other three-dimensional configurations may be considered, with some NAND chains containing memory elements in a single memory plane, while other chains include memory elements extending across multiple memory planes. Three-dimensional memory arrays may also be configured as a NOR configuration and as a ReRAM configuration.

Typically, in a monolithic three-dimensional memory array, one or more storage device layers are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also include one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers that make up each storage device plane of the array are typically formed on the layers of the underlying storage device layers of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or may have intermediate layers between memory device levels.

Then, again, two-dimensional arrays may be separately formed and then packaged together to form a non-monolithic memory device having a plurality of memory layers. For example, non-monolithic stacked memories can be constructed by forming memory layers on separate substrates and then stacking them one on top of the other. The substrates may be thinned out or removed from the storage device planes before stacking, but since the storage device layers are initially formed over separate substrates, the resulting storage arrays are not monolithic three-dimensional storage arrays. Furthermore, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

Associated circuits are usually required for the operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may include circuits used to control and drive memory elements to perform functions such as programming and reading. This associated circuit may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for read / write operations of the memory may be disposed on a separate control chip and / or on the same substrate as the memory elements.

It is intended that the foregoing detailed description be interpreted as illustrative of selected forms that the invention may and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the claimed invention. Finally, it should be understood that each aspect of each of the preferred embodiments described herein may be used alone or in combination with each other.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 15468620 [0001]
• US 15585827 [0001]

Claims (20)

Method, comprising before a host device notifies a storage device that a command is being delivered in a delivery queue, the storage device causes: Reading the command from the delivery queue; and Processing the command; Determining if the host device has notified the storage device that the command has been delivered to the delivery queue; and in response to determining that the host device has notified the storage device that the command has been delivered to the delivery queue, notifying the host device of completion of the termination queue command. Method according to Claim 1 , further comprising determining whether the host device has overridden the command that was delivered to the delivery queue. Method according to Claim 2 , further comprising in response to the determination that the host device has overridden the command delivered at the delivery queue, revoking the command processing. Method according to Claim 1 wherein: the instruction comprises a read instruction; and processing the command before the host device notifies the storage device that the command is delivered to the delivery queue, reads data from the nonvolatile memory, and stores the read data in volatile memory. Method according to Claim 4 wherein the instruction processing further comprises error correction of the read data. Method according to Claim 1 wherein: the instruction comprises a flush instruction indicating to the memory device that it is to flush internal caches to non-volatile memory; and processing the command before the host device notifies the storage device that the command is delivered to the delivery queue to write at least a portion of the data in the internal caches to the nonvolatile memory. Method according to Claim 6 , further comprising: determining that the host device has overwritten the flush command; and in response to the determination that the host device has overridden the flush command, revoking the writing of the at least a portion of the data in the internal caches to the nonvolatile memory. Method according to Claim 1 , further comprising: after reading the instruction from the delivery queue, determining whether to begin processing the instruction before the host device notifies the storage device that the instruction is delivered to the delivery queue; in response to the determination to begin processing the command before the host device notifies the storage device that the command is delivered to the delivery queue to process the command before the host device notifies the storage device that the command is being delivered to the delivery queue; and in response to the determination not to begin processing the command before the host device notifies the storage device that the command is delivered to the delivery queue, wait until the host device notifies the storage device that the command is delivered to the delivery queue, to start the command processing. Method according to Claim 8 wherein determining whether to start processing the command before the host device notifies the storage device that the command is being delivered to the delivery queue is based on a command type. Method according to Claim 9 , further comprising: in response to the determination that the type of command is a read command, determining to begin command processing before the host device notifies the storage device that the command is being delivered to the delivery queue; and, in response to the determination that the type of command is a read command, to determine to wait with the command processing until the host device notifies the storage device that the command is being delivered to the delivery queue. A nonvolatile memory device comprising: a nonvolatile memory; an interface adapted to communicate with a host device for the host device to create one or more instructions for storage in a delivery queue; and a controller in communication with the nonvolatile memory and the interface, wherein the controller is configured: before the host device is notified that the one or more instructions are stored in the transmission queue: reading the one or more instructions; determine a flow within the storage device to be performed to process the one or more instructions; and at least partially performing the flow within the storage device; and after the host device notifies that the one or more instructions are stored in the transmission queue: to determine a procedure outside the memory device to be performed to process the one or more instructions; and performing the procedure outside the storage device. The nonvolatile memory device according to Claim 11 wherein: the one or more instructions comprise read commands; and the flow within the memory device comprises reading data from the nonvolatile memory. The nonvolatile memory device according to Claim 11 further comprising a control storage buffer configured to store the delivery queue; wherein the controller is further configured to: determine, before the host device notifies that the one or more instructions are stored in the transmission queue, that the host device has stored the one or more instructions in the transmission queue in the control memory buffer; and in response to the controller determining that the host device has stored the one or more instructions in the delivery queue in the control storage buffer, reading the one or more instructions from the delivery queue in the control storage buffer and at least partially completing the flow within the storage device perform. The nonvolatile memory device according to Claim 11 wherein the flow outside the storage device comprises the communication via the communication interface with the host device. The nonvolatile memory device according to Claim 14 wherein the flow outside the storage device comprises transmitting a transmission layer packet read request to read a portion of the host memory. The nonvolatile memory device according to Claim 14 wherein the flow outside the storage device comprises transmitting a transmission layer packet write request for writing to a portion of the host memory. A non-volatile memory device comprising: a non-volatile memory: a communication interface configured to communicate with a host device for the host device to create one or more instructions for storage in a delivery queue; Means for determining, before the host device notifies that the one or more instructions are stored in the transmission queue, that the one or more instructions are stored in the transmission queue; Means for determining whether the one or more instructions stored in the submission queue are to be speculatively processed; and in response to the determination to speculatively process the one or more instructions stored in the transmission queue, means for speculatively processing the one or more instructions. Storage system according to Claim 17 wherein the means for determining whether the one or more instructions stored in the transmission queue are to be speculatively processed are based on a type of instruction. Storage system according to Claim 17 wherein the means for determining whether the one or more instructions stored in the transmission queue are to be speculatively processed is based on whether the instruction is a read command or a write command. Storage system according to Claim 17 , further comprising: means for determining that the host device has overwritten a command delivered to the delivery queue; and in response to the determination that the host device has overwritten the command delivered to the delivery queue, means for suspending the speculative processing of the command.

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