DE10345475A1 - Non-volatile integrated semiconductor memory - Google Patents

Non-volatile integrated semiconductor memory Download PDF

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Publication number
DE10345475A1
DE10345475A1 DE10345475A DE10345475A DE10345475A1 DE 10345475 A1 DE10345475 A1 DE 10345475A1 DE 10345475 A DE10345475 A DE 10345475A DE 10345475 A DE10345475 A DE 10345475A DE 10345475 A1 DE10345475 A1 DE 10345475A1
Authority
DE
Germany
Prior art keywords
charge
storing plane
tunnel barrier
barrier layer
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10345475A
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German (de)
Other versions
DE10345475B4 (en
Inventor
Harald Seidl
Thomas Happ
Cay-Uwe Pinnow
Martin Gutsche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345475A priority Critical patent/DE10345475B4/en
Priority to US10/950,477 priority patent/US7084454B2/en
Publication of DE10345475A1 publication Critical patent/DE10345475A1/en
Application granted granted Critical
Publication of DE10345475B4 publication Critical patent/DE10345475B4/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/954—Making oxide-nitride-oxide device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Die Erfindung betrifft einen nichtflüchtigen integrierten Halbleiterspeicher, der eine Schichtenfolge (10) mit einer Tunnelbarriereschicht (12) und einer ladungsspeichernden Ebene (11) aufweist. Die ladungsspeichernde Ebene (11) besteht aus einem dielektrischen Material, das eingestreute Ladungsträger (21) in räumlich fixierter Position speichert. Die Tunnelbarriereschicht (12) besteht aus einem durch hochenergetische Ladungsträger (21) durchtunnelbaren Material. Erfindungsgemäß besitzt mindestens eine Grenzfläche (11a; 11b) der ladungsspeichernden Ebene (11) eine größere mikroskopische Rauhigkeit als die der ladungsspeichernden Ebene (11) abgewandte Grenzfläche (12a) der Tunnelbarriereschicht (12), wobei in ersten Bereichen (I) die ladungsspeichernde Ebene (11) eine größere Schichtdicke besitzt als in zweiten Bereichen (II). Dadurch wird eine identische Verteilung und Lokalisierung positiver wie auch negativer Ladungsträger in lateraler Richtung erzeugt; in die ladungsspeichernde Ebene (11) eingestreute Ladungsträger (21) rekombinieren daher vollständig, wodurch die Gefahr eines unvorhergesehenen Datenverlusts beim Langzeitbetrieb nichtflüchtiger Speicher reduziert wird.The invention relates to a nonvolatile integrated semiconductor memory which has a layer sequence (10) with a tunnel barrier layer (12) and a charge-storing plane (11). The charge-storing plane (11) consists of a dielectric material which stores scattered charge carriers (21) in a spatially fixed position. The tunnel barrier layer (12) consists of a through high-energy carrier (21) durchtunnelbaren material. According to the invention, at least one interface (11a; 11b) of the charge-storing plane (11) has a greater microscopic roughness than the charge-storing plane (11) facing away from the interface (12a) of the tunnel barrier layer (12), wherein in first regions (I) the charge-storing plane ( 11) has a greater layer thickness than in second regions (II). This produces an identical distribution and localization of positive and negative charge carriers in the lateral direction; charge carriers (21) interspersed in the charge-storing plane (11) therefore recombine completely, thereby reducing the risk of unforeseen data loss in the long-term operation of non-volatile memories.

DE10345475A 2003-09-30 2003-09-30 Non-volatile integrated semiconductor memory Expired - Fee Related DE10345475B4 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10345475A DE10345475B4 (en) 2003-09-30 2003-09-30 Non-volatile integrated semiconductor memory
US10/950,477 US7084454B2 (en) 2003-09-30 2004-09-28 Nonvolatile integrated semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345475A DE10345475B4 (en) 2003-09-30 2003-09-30 Non-volatile integrated semiconductor memory

Publications (2)

Publication Number Publication Date
DE10345475A1 true DE10345475A1 (en) 2005-05-04
DE10345475B4 DE10345475B4 (en) 2008-04-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE10345475A Expired - Fee Related DE10345475B4 (en) 2003-09-30 2003-09-30 Non-volatile integrated semiconductor memory

Country Status (2)

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US (1) US7084454B2 (en)
DE (1) DE10345475B4 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113586A1 (en) * 2004-11-29 2006-06-01 Macronix International Co., Ltd. Charge trapping dielectric structure for non-volatile memory
US7746694B2 (en) * 2006-07-10 2010-06-29 Macronix International Co., Ltd. Nonvolatile memory array having modified channel region interface
US7646637B2 (en) * 2006-07-10 2010-01-12 Macronix International Co., Ltd. Nonvolatile memory having modified channel region interface
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
KR102005845B1 (en) * 2015-03-07 2019-08-01 에스케이하이닉스 주식회사 Non-volatile memory device and method of driving the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017505A (en) * 1986-07-18 1991-05-21 Nippondenso Co., Ltd. Method of making a nonvolatile semiconductor memory apparatus with a floating gate
US5504022A (en) * 1993-01-07 1996-04-02 Fujitsu Limited Method of making a semiconductor memory device having a floating gate
US5999444A (en) * 1997-09-02 1999-12-07 Sony Corporation Nonvolatile semiconductor memory device and writing and erasing method of the same
US6319775B1 (en) * 1999-10-25 2001-11-20 Advanced Micro Devices, Inc. Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
US6331465B1 (en) * 1998-05-29 2001-12-18 Micron Technology, Inc. Alternate method and structure for improved floating gate tunneling devices using textured surface
US6451713B1 (en) * 2000-04-17 2002-09-17 Mattson Technology, Inc. UV pretreatment process for ultra-thin oxynitride formation
US6455372B1 (en) * 2000-08-14 2002-09-24 Micron Technology, Inc. Nucleation for improved flash erase characteristics

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4335391A (en) * 1978-12-11 1982-06-15 Texas Instruments Incorporated Non-volatile semiconductor memory elements and methods of making

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017505A (en) * 1986-07-18 1991-05-21 Nippondenso Co., Ltd. Method of making a nonvolatile semiconductor memory apparatus with a floating gate
US5504022A (en) * 1993-01-07 1996-04-02 Fujitsu Limited Method of making a semiconductor memory device having a floating gate
US5999444A (en) * 1997-09-02 1999-12-07 Sony Corporation Nonvolatile semiconductor memory device and writing and erasing method of the same
US6331465B1 (en) * 1998-05-29 2001-12-18 Micron Technology, Inc. Alternate method and structure for improved floating gate tunneling devices using textured surface
US6319775B1 (en) * 1999-10-25 2001-11-20 Advanced Micro Devices, Inc. Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
US6451713B1 (en) * 2000-04-17 2002-09-17 Mattson Technology, Inc. UV pretreatment process for ultra-thin oxynitride formation
US6455372B1 (en) * 2000-08-14 2002-09-24 Micron Technology, Inc. Nucleation for improved flash erase characteristics

Also Published As

Publication number Publication date
DE10345475B4 (en) 2008-04-17
US20050067634A1 (en) 2005-03-31
US7084454B2 (en) 2006-08-01

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee