DE10341836B4 - Test device for testing electrical circuits and method for parallel testing of electrical circuits - Google Patents

Abstract

Test device (2) for testing electrical circuits (21, 22, 23), wherein the test device (2) has the following features: - at least two input contacts (211, 221, 231) which are adapted for connection to the electrical circuits (21-, 22). 23), wherein at the input contacts (211, 221, 231) different electrical circuits can be connected, - for each input contact (211, 221, 231) is ever an electrical short-circuit protection circuit (506, 516, 526) available, - the output of each electrical short-circuit protection circuit (506, 516, 526) is connected to the associated input contact (211, 221, 231), - a signal generator (201) which is intended to generate a test signal and which is connected via a connecting line (409 ) is connected to each input of the electrical short circuit protection circuits (506, 516, 526), - through each short circuit protection circuit (506, 516, 526) is the respective input contact (211, 221, 231) of the front of the input The electrical short-circuit protection circuit (506, 516, 526) lying connection line (409) decoupled, each electrical short-circuit protection circuit (506, 516, 526) via a circuit breaker (51) and via a parallel to the circuit breaker (51) connected isolation amplifier ( 52), the inputs of the isolating switch (51) and the isolating amplifier (52) being connected to the signal generator (201) and the outputs of the isolating switch (51) and isolating amplifier (52) to the respective input contact (211, 221, 231) are.

Description

The invention relates to a test device for testing electrical circuits and to a method for parallel testing of electrical circuits, in particular integrated circuits.

The production test of integrated circuits represents a significant cost factor in the production of such integrated circuits. In order to optimize the costs incurred in the production test of integrated circuits, it is often attempted to make the best possible use of the available test systems. By optimizing the test algorithm that tests the integrated circuits to a minimum of test time, this approach has already exhausted all cost reduction opportunities.

Another approach to testing integrated circuits is to simultaneously test multiple integrated circuits on a single tester. For this it is necessary to convert the used tester accordingly, in particular to adapt the load board to accommodate multiple integrated circuits. A load board is understood to be a socket used in such a test, which is capable of accommodating one or more integrated circuits to be tested.

In such parallel tests of integrated circuits, the problem often arises that because of a single defective integrated circuit, all integrated circuits of the respective parallel test run are reported as faulty and therefore rejected. This reduces the yield and increases the unit cost of the defect-free integrated circuits.

The US Pat. No. 6,441,637 B1 shows a test for a plurality of devices to be tested simultaneously, wherein between a central voltage source and the individual devices each have a temperature-dependent resistor is provided, which increases its resistance value in the event of a short circuit and thus reduces the current flow through the shorted device.

The JP 11295394 shows an AD converter being tested by a tester. To improve the accuracy of the output voltage of the tester, the result of the AD converter is returned. The data sheet for the LM324 operational amplifier from Fairchild Semiconductor Corp., 2002, shows a semiconductor device with four operational amplifiers. In the short circuit protection circuit of US 4,544,981 In the case of a short circuit, the output of a driver is switched to high impedance. The DE 101 50 404 shows an apparatus and a method for testing a semiconductor integrated circuit having an AD converter. An output channel selector at the output of the testing circuit may select one of several integrated circuits to be tested.

It is an object of the present invention to provide an apparatus and a method by which a parallel test of integrated circuits can be performed and in which the faulty of faultless integrated circuits can be reliably distinguished.

This object is achieved with the subject matter of the independent claims. Advantageous developments of the invention will become apparent from the respective dependent claims.

• – wenigstens zwei Eingangskontakte, die zum Anschluss an die elektrischen Schaltungen bestimmt sind, wobei an den Eingangskontakten verschiedene elektrische Schaltungen anschließbar sind,
• – für jeden Eingangskontakt ist je eine elektrische Kurzschlussschutz-Schaltung vorhanden,
• – der Ausgang jeder elektrischen Kurzschlussschutz-Schaltung ist mit dem zugehörigen Eingangskontakt verbunden,
• – einen Signalgenerator, der zum Generieren eines Testsignals bestimmt ist und der über je eine Anschlussleitung mit jedem Eingang der elektrischen Kurzschlussschutz-Schaltungen verbunden ist,
• – durch jede Kurzschlussschutz-Schaltung ist der jeweilige Eingangskontakt von der vor dem Eingang der elektrischen Kurzschlussschutz-Schaltung liegenden Anschlussleitung entkoppelbar,

wobei jede elektrische Kurzschlussschutz-Schaltung über einen Trennschalter sowie über einen parallel zum Trennschalter geschalteten Trennverstärker verfügt, wobei die Eingänge des Trennschalters und des Trennverstärkers an den Signalgenerator und die Ausgänge des Trennschalters und des Trennverstärkers an den jeweiligen Eingangskontakt angeschlossen sind.The invention relates to a test device for testing electrical circuits, the test device having the following features:

• At least two input contacts intended for connection to the electrical circuits, it being possible to connect different electrical circuits to the input contacts,
• - there is an electrical short-circuit protection circuit for each input contact,
• The output of each electrical short-circuit protection circuit is connected to the associated input contact,
• A signal generator which is intended to generate a test signal and which is connected via a respective connecting line to each input of the electrical short-circuit protection circuits,
• By each short-circuit protection circuit, the respective input contact can be decoupled from the connection line lying in front of the input of the electrical short-circuit protection circuit,

wherein each electrical short-circuit protection circuit has a disconnect switch and an isolation amplifier connected in parallel with the disconnect switch, wherein the inputs of the disconnector and the isolation amplifier are connected to the signal generator and the outputs of the disconnector and the isolation amplifier to the respective input contact.

In accordance with one aspect of the invention, the additional provision of a short circuit protection circuit for each input contact ensures that short circuits generated by defective integrated circuits to be tested do not affect other input contacts. This ensures that only the actually faulty integrated circuits are detected as defective and sorted out, whereas the remaining error-free integrated circuits further tested and leave the test process properly in the event of further testing. This increases the yield during testing while ensuring that n integrated circuits can be tested simultaneously. This reduces the total test time, with the equipment of the used tester remains the same. Only the load board needs to be adapted to accommodate multiple integrated circuits and such additional cost-effective short circuit protection circuits must be provided.

Such an electrical short-circuit protection circuit can be arranged directly at the input contact, wherein it is advantageous that the signal values considered by the short-circuit protection circuit correspond very accurately to the actual signal values applied to the input contacts.

The simplest realization of such a decoupling according to the invention can be achieved by an isolating amplifier, which has to meet relatively high requirements with regard to the frequency response and the linearity. In this embodiment of the invention, no further measures must be taken to decouple the signal inputs. Several signal inputs or several integrated circuits connected to these signal inputs can be checked at the same time, resulting in considerable cost and time savings.

According to a further embodiment of the invention, an input contact is only decoupled if the test signal applied to the input contact assumes an impermissible value, in particular has a short circuit.

For this, the electrical short-circuit protection circuit can be designed as a current-controlled disconnecting switch. In this embodiment of the invention, an ammeter is additionally provided, which is arranged in particular in a signal generator. The connection between the signal generator and the input contact is interrupted when a current value detected by the ammeter and applied to the input contact deviates from an expected current value. In addition, a control line between the current-controlled disconnector and the ammeter must be provided, by means of which the current-controlled disconnecting switch is switchable. By means of this embodiment of the invention, defective components to be tested can be accurately recognized and disconnected individually. The test procedure is carried out sequentially for all components connected in parallel.

In an alternative embodiment, the electrical short-circuit protection circuit has a disconnect switch and an isolation amplifier connected in parallel to the disconnect switch. The inputs of the isolating switch and of the isolating amplifier are connected to a signal generator and the outputs of the isolating switch and isolating amplifier to an input contact. This embodiment of the invention represents a precise working and cost-effective decoupling possibility for parallel input contacts, in which the input contacts checked at the same time and possibly decoupled. No additional external control lines are needed. The isolation amplifier is only active during the initial short-circuit test and serves only to decouple the inputs. There are only low demands on the frequency response, the gain and the linearity of the isolation amplifier. The isolation amplifier only has to pass on the amplitude of the short-circuit test voltage emitted by the signal generator approximately in amplitude.

The electrical short-circuit protection circuit may be monolithically integrated on the integrated circuit under test in any of the embodiments described above.

The invention relates to a test device for testing integrated circuits, in particular dynamic AD converters. This test device comprises at least one input contact for connection to an integrated circuit, for each input contact depending on an electrical short circuit protection circuit described above, the outputs of which is connected to the associated input contact and a signal generator for generating a test signal, each via a connecting line to each input of electrical short-circuit protection circuit (s) is connected. With such a test device, multiple integrated circuits can be tested simultaneously and short-circuit protected.

In a first embodiment, the test device also includes a respective comparator unit for each input contact and at least one reference signal generator. This comparator unit is connected to the input or to the output of the electrical short-circuit protection circuit. Whether the comparator unit is connected to the input or to the output in each case depends on the type of realization of the short-circuit protection circuit. The reference signal generator for generating a reference signal is connected to each comparator unit by means of at least one line, in particular by means of a reference line and by means of a calibration line. It is particularly advantageous that the test signals are validated by the comparator units against the reference signals and the Comparator units can be precisely calibrated. This results in particularly reliable test results.

Each comparator unit may be operated in a test mode in which the test signal of the relevant input contact is compared with the reference signal and in which the signal generator is turned off by the comparator unit when the test signal exceeds or falls below the reference signal. This ensures that the test signals are within a desired, precisely adjustable interval.

Further, if a decision logic unit is provided which is connected to the comparator units and which can generate control signals for the precision signal generator from the output signals of the comparator units, the comparator units or the comparators can be calibrated in parallel prior to the start of a test cycle. This will allow further acceleration of the test.

According to a further embodiment of the invention, the test device comprises two reference signal generators. The first reference signal generator generates a lower reference signal and the second reference signal generator generates an upper reference signal. In this embodiment, each input contact has two comparator units, via a first comparator unit connected to the first reference signal generator and via a second comparator unit connected to the second reference signal generator.

This ensures that the integrated circuits are tested only with test signals located within the test interval spanned by the lower and upper reference signals. The test signal values actually applied to the input contacts of the integrated circuits can thus be reliably controlled.

In an easily implementable embodiment of the test device according to the invention, each comparator unit each comprises a comparator. It is particularly simple and cost-effective if the test device each comprises a comparator with two inputs and one output. The first input of each comparator is connected to the reference line of the respective reference signal generator, the second input of each comparator is switchable to the calibration line of the relevant reference signal generator and to the input or the output of the electrical short circuit protection circuit. The output of each comparator is switchable to its calibration unit and to the precision signal generator. The switching properties, in particular the offset and the hysteresis of the comparator are adjustable by the calibration unit.

According to a further embodiment of the invention, two lines, namely a calibration line and a reference line, are supplied to the comparator unit (s) by the reference signal generator or by the reference signal generators. Furthermore, each comparator unit also comprises a calibration unit, to whose control input the output of the comparator unit is respectively guided. The calibration line and the reference line are routed as close together as possible to the signal line, so that all these lines experience the same external disturbances. The comparator unit can also be operated in a calibration mode in which the switching characteristics of the comparator unit, in particular the offset / deviation from the zero value and the hysteresis / after-effect of the test signal after shutdown are set by the calibration on the reference and the reference Calibration unit applied signal values are compared.

Due to external disturbances or the influence of the different signal paths, it is possible that the test mode starts and ends at the different integrated circuits at slightly offset times. In order to prevent this, the evaluation logic of the tester is informed of the valid time window. For each a validation signal line is provided, which leads from each comparator unit to the relevant output line, which attaches to the output contact of the integrated circuit under test. Via this validation signal line, a validation signal is fed to the respective output line, in particular to an AND gate arranged behind the output contact, where it is linked to the digital output of each integrated circuit.

If the electrical short-circuit protection circuit is designed as a current-controlled disconnecting switch, then the electrical short-circuit protection circuit can be operated in a short circuit test mode. In this short-circuit test mode, the current-controlled disconnect switch is switched so that the connection between the signal generator and the input contact is closed and the current meter can determine whether the current value produced by the signal generator and located at the input contact lies within a defined permissible standby range. The current-controlled disconnector is then opened by the ammeter when the current value applied by the signal generator and applied to the input contact is not within the defined permissible range of values. Otherwise it stays closed for the rest of the test. With this short-circuit test mode, faulty integrated circuits can be accurately detected and selectively disconnected.

Such an advantageous short-circuit test mode can also be carried out in the case of an electrical short-circuit protection circuit designed as a parallel circuit breaker and isolating amplifier. In this case, a respective control line is provided between a respective disconnector and the associated comparator unit, and the respective input contact can be switched so that it is connected to the comparator unit. In the short-circuit test mode, the short-circuit protection circuit is initially switched so that the connection between the signal generator and the input contact only passes through the isolation amplifier and the disconnect switch interrupts. Furthermore, the input contact is switched so that the test signal applied to the input contact is connected to the comparator unit.

If there is no short circuit or if the test signal applied to the input contact assumes a permissible value, the disconnecting switch is switched by the comparator unit in such a way that the connection between the signal generator and the input contact passes through the disconnecting switch.

However, if there is a short circuit or if the test signal applied to the input contact assumes an impermissible value, the circuit breaker is switched by the comparator unit so that the circuit breaker interrupts and the connection between the signal generator and the input contact only passes through the isolating amplifier.

To ensure high functionality of the test device, the comparator units and the short circuit protection circuits can be switched between the short circuit test mode, the calibration mode and the test mode.

The test device according to the invention described above can be realized in various ways. The different characteristics of the test device according to the invention differ only in the partitioning or in the arrangement of the individual elements of the test device according to the invention. Depending on the availability of circuit area on the integrated circuits, individual or even all elements of the described test device may be incorporated into the integrated circuits as a BIST / Built-In Self-Test Circuit. depending on how many elements of the test device according to the invention can be accommodated on the integrated circuit, different cost savings can be achieved.

The invention relates to an integrated circuit having an electrical short-circuit protection circuit as described above or a test device as described above. In this case, the short-circuit protection circuit or the test device is monolithically integrated on this integrated circuit and formed in addition to the actual circuit of the integrated circuit. It is possible to replace the common precision signal generator by local digital signal sources formed in the integrated circuits. This on-chip solution is particularly cost-effective.

In this embodiment, either only the short-circuit protection circuit or even the entire arrangement of the described test device with the precision signal generator, with the short-circuit protection circuit, with the comparator unit or with the comparator and with the calibration unit and with the reference signal generators can be placed on the integrated circuit , However, a prerequisite for this is that the additional chip area required for this is available. In particular, in integrated circuits, in which the button is limited only by the number of applied connection contacts, i. d. R. enough chip area available. In this embodiment of the invention, a filter, in particular a low-pass filter, which is able to convert a generated test signal into a desired analog signal, is additionally required on the loadboard for each integrated circuit. The reference voltage sources can be realized, for example, by highly stable and temperature-compensated band gaps. This embodiment of the test device according to the invention is particularly cost-optimal, especially since it no longer requires any special tester properties and is particularly versatile.

The above-described short-circuit protection circuit and test device may further be formed on a load board for receiving at least one probe card for testing integrated circuit and / or at least one test socket for testing integrated circuit and / or for connecting a handler to an integrated circuit tester , In this case, all elements of the short-circuit protection circuit or test device described above can be placed on the loadboard.

Alternatively, it is also possible in the training of the test device on the loadboard to replace the central precision signal generator of the tester by locally recorded in the integrated circuits digital signal sources. The comparator units or the comparators are included This arrangement placed on the loadboard and can control the internal precision signal generators. This assumes that the integrated circuit has an external control interface / external control interface, such as bpsw. over an I ² C bus. This is the case with many mixed-signal components. These are therefore particularly suitable for this solution.

The invention also relates to a tester for testing integrated circuits, which has a plurality of instruments for generating signals or data streams and a plurality of measuring sensors, in particular for currents and voltages. The tester further comprises a loadboard as described above and a short-circuit protection circuit or test device also described above. Therein, the precision signal generator and the reference signal generator (s) on the tester and the comparators with the calibration units on the loadboard are respectively disposed adjacent to the input contacts for the integrated circuits. A tester with a test device arranged in this way can test an almost any number of integrated circuits in parallel, whereby it is ensured by the test device according to the invention that the test results obtained are reliable and only the actually faulty integrated circuits are sorted out. The invention also relates to a method for parallel testing of integrated circuits.

At first, a tester described above is provided with a loadboard. The loadboard is then populated with several integrated circuits. The integrated circuits are connected to the input contacts. In this case, a signal generator is provided as well as an electrical short-circuit protection circuit for each integrated circuit to be tested. Subsequently, a test mode is performed in which test signals are applied by the signal generator to the input contacts.

If the provided electrical short-circuit protection circuit is designed as an isolation amplifier, the input contacts are decoupled in the normal test run. So no separate short-circuit test must be performed. For all integrated circuits tested in parallel, the test run can be carried out simultaneously.

If the provided electrical short-circuit protection circuit is designed as a current-controlled disconnector or as a disconnector with isolation amplifier, the short-circuit test is performed before the actual test run.

In this case, it is first determined whether the test signal applied to the relevant input contact has an impermissible value, in particular a short circuit. Subsequently, those input contacts are selectively decoupled, in which an impermissible value, in particular a short circuit has been found.

The testing of the test signal is carried out the embodiment as a current-controlled disconnecting switch by the ammeter and in the embodiment as a circuit breaker with isolating amplifier by the comparator unit.

Only when an impermissible value of the test signal is detected, the relevant signal input is decoupled. This decoupling is done in the embodiment as a current-controlled disconnector by a current meter controlled by the opening of the respective circuit breaker and in the embodiment as a disconnector with buffer amplifier by a controlled by the comparator unit opening the circuit breaker.

Before the test run or before the short-circuit test, a calibration mode can be performed.

The possible uses of the method according to the invention are accordingly extremely diverse.

The invention is also related to a computer program for carrying out the method of parallel testing of integrated circuits. In this case, the computer program contains program instructions which cause a computer system to carry out such test methods in an embodiment described above. In particular, the method steps of the short-circuit protection test mode, the test mode and the calibration mode are controlled by a computer system or performed on a computer system itself. The computer program outputs the results of the integrated circuits tested as digital data sequences or in a representation form generated therefrom on an output unit, in particular on a screen or on a printer, or stores this result data in a memory area. The computer program according to the invention enables integrated circuits to be tested quickly and effectively and reliably and, if necessary, to be sorted out, with a significant acceleration of the test runtime resulting from the parallel treatment of several circuits.

The invention also relates to a computer program stored on a storage medium, in particular in a computer memory or in a random access memory is included or transmitted on an electrical carrier signal. The invention is also related to a carrier medium, in particular a data carrier, such as a floppy disk, a Zip drive, a streamer, a CD or a DVD, on which a computer program described above is stored. Furthermore, the invention relates to a computer system on which such a computer program is stored. Finally, the invention also relates to a download method in which such a computer program is downloaded from an electronic data network, such as, for example, from the Internet to a computer connected to the data network.

The invention is illustrated in more detail in the drawings with reference to an embodiment.

1 shows a schematic representation of a tester structure,

2 shows a parallel test circuit diagram with three AD converters and with three short-circuit protection circuits,

3 shows a fourth short-circuit protection circuit according to a first embodiment of the invention,

4 shows a fifth short-circuit protection circuit according to a second embodiment of the invention,

5 shows a sixth short-circuit protection circuit with two comparators according to a third embodiment of the invention,

6 shows a first switching behavior of the comparators 5 .

7 shows a second switching behavior of the comparators 5 ,

1 shows a schematic representation of a tester construction 1 ,

The tester construction 1 includes a control computer system 101 that's over a network line 103 with the in 1 signal generators and measuring instruments referred to as rack instruments 102 and with a measuring table 106 as well as via a control line 104 with a tester 105 communicates. On the measuring table 106 there is a support surface 107 which is often referred to as Chuck. On this support surface 107 lie in 1 not shown semiconductor wafer with to be tested integrated circuits or already separated integrated circuits. These are from a socket for housed building blocks or from a probe card 108 contacted and via a first intermediate level 109 , over a second intermediate level 110 , over a third intermediate level 111 and over a fourth intermediate level 112 and via measurement data lines 114 with a switching matrix 113 connected. Not shown in 1 is also a loadboard intended to accommodate one or more integrated circuits.

The switching matrix 113 is by means of measured data lines 114 with the tester 105 and with the measuring instruments 102 connected. The switching matrix 113 is designed to receive the signals of the measuring instruments 102 and the input data of the tester 105 over the intermediate levels 109 - 112 to certain connection contacts of the probe card 108 or to certain contacts of the in 1 can guide not shown loadboards. The connection lines of the loadboard with the tester 105 are also referred to as "tester channels".

At the tester 105 It is a low cost, digitally working tester that can be equipped with optional analog meters and analog generators. The highly sensitive and highly accurate measuring instruments 102 are at a certain distance to the measuring table 106 and to the tester 105 arranged in a separate instrument cabinet.

The data lines between the measuring instruments 102 and the terminals of the probe card 108 and the loadboard have a length of up to 2 m. Due to this long cable routing and the ohmic contact resistance of the transitions between the intermediate levels 109 - 112 Voltage drops are caused by the measuring instruments 102 generated measuring signals to the test contacts of the probe card 108 and the loadboard.

2 shows a parallel test plan 2 with a first AD converter 21 , with a second AD converter 22 and with a third AD converter 23 ,

In the parallel test plan 2 is one of the measuring instruments 102 arranged precision signal generator 201 provided that is capable of generating an analog ramp voltage. This ramp voltage is via a test signal line 409 to a first input contact 211 , to a second input contact 221 and to a third input contact 231 created. These at the input contacts 211 . 221 and 231 applied ramp voltage is from the first AD converter 21 , from the second AD converter 22 and from the third AD converter 23 processed. The function of the analog ramp voltage from the AD converters 21 to 23 each generated digital output values are from output contacts 212 . 222 and 232 at one in 2 unspecified memory area of the tester 105 forwarded. The input contacts 211 . 221 and 231 as well as the output contacts 212 . 222 and 232 are arranged on the load board. The measured output values are from the tester 105 compared with the expected setpoints, which then outputs a pass signal or a fail signal, which states whether the relevant AD converter 21 - 23 passed the test or not.

The parallel test plan 2 provides a min / max calibration of the input contacts 211 . 221 . 231 attached test signals ready. For this has the parallel test plan 2 via a first reference signal generator 401 for generating a maximum reference voltage and a second reference signal generator 411 for generating a minimum reference voltage.

From the first reference signal generator 401 are a first reference line 406 and a first calibration line 407 and the second reference signal generator 411 a second reference line 416 and a second calibration line 417 on the comparator units 501 . 511 and 521 guided.

To the reference lines 406 and 416 , the calibration lines 407 and 417 as well as the test signal line 409 each parallel to the three input contacts 211 . 221 . 231 as well as on the comparator units 501 . 511 . 521 lead these lines are each branched on the load board.

The parallel test plan 2 can be implemented on common testers. All you have to do is load the board - as in 2 shown - to accommodate multiple AD converter 21 - 23 be adjusted.

Close to the first input contact 211 is a first comparator unit 501 arranged. In the immediate vicinity of the input contacts 221 and 231 are each a second comparator unit 511 and a third comparator unit 521 ,

The comparator units 501 . 511 . 521 can be operated in a test mode in which individually for each AD converter to be tested 21 - 23 can be determined whether the value of the test signal is too large or too small, or whether the test signal exceeds or falls below a reference signal.

For branching from the test signal line 409 each return lines 507 . 517 . 527 on the comparator units 501 . 511 . 521 from. In 2 branch these return lines 507 . 517 . 527 each before the short-circuit protection circuits 506 . 516 . 526 from. Alternatively, it is possible that these return lines 507 . 517 . 527 each after the short-circuit protection circuits 506 . 516 . 526 , only immediately before the respective input contacts 211 . 221 . 231 branch off and onto the comparator units 501 . 511 . 521 to be led back.

If that is actually at the input contact 211 . 221 . 231 applied test signal that at the first reference line 406 applied reference signal of the first reference signal generator 401 exceeds or at the second reference line 416 applied reference signal of the second reference signal generator 411 falls below, the precision signal generator 201 directly from the relevant comparator unit 501 . 511 . 521 turned off. This is a decision logic unit 531 provided by means of a control signal line 531 with the precision signal generator 201 connected is.

The short-circuit protection circuits 506 . 516 . 526 lie in the signal path and serve to the inputs, so the input contacts 211 . 221 and 231 to decouple from each other, whereby a reduction in the yield can be avoided. Without such short-circuit protection circuits 506 . 516 and 526 would be an internal short circuit of the supply circuit V _SS or V _DD on a single analog input contact 211 . 221 . 231 cause this short circuit also at the other input contacts 211 . 221 . 231 the remaining functional AD converter 21 - 23 would be present. In this case, the tester would 105 all tested AD-converters 21 - 23 classify as faulty, although in fact only one of the three AD converters 21 - 23 is faulty. By providing the short circuit protection circuits 506 . 516 . 526 it is ensured that at an internal short circuit at exactly one of the input contacts 211 . 221 and 231 only the relevant faulty AD converter 21 . 22 . 23 is sorted out. For the other error-free AD converters 21 . 22 . 23 the parallel test can be continued.

From the comparator units 501 . 511 . 521 extend validation signal lines 504 . 514 . 524 on each at the output contacts 212 . 222 . 232 arranged AND gate 505 . 515 . 525 , The inputs of the AND gate 505 . 515 . 525 are each from the validation signal lines 504 . 514 and 524 and formed by the data lines connected to the output contacts 212 . 222 . 223 begin.

The comparator units 501 . 511 and 521 can each have their own, in 2 not shown separately calibration unit with the calibration 406 and with the reference line 407 for the maximum voltage level, with the calibration line 416 and with the reference line 417 for the minimum voltage level as well as the test signal line 409 is supplied for the analog ramp signal.

Before the start of each test cycle, the comparator units 501 . 511 . 521 calibrated in parallel. In this calibration mode, the output signals of the comparator units 501 . 511 . 521 together on the decision logic unit 531 out of these output signals control signals for the precision signal generator 201 derives. The derivation of these control signals is clear to the person skilled in the art from the information obtained in this patent and need not be explained in more detail here.

Subsequently, the AD converters 21 - 23 tested in test mode.

Due to external disturbances or due to the influence of different signal paths, it is possible that the measuring process in the AD converters 21 - 23 starts and ends at slightly offset times. Therefore, the test must 105 or on the tester 105 existing evaluation logic the valid time window are communicated. This is done by a validation signal from the comparator units 501 . 511 . 521 generated and via the validation signal lines 504 . 514 . 524 the AND gates 505 . 515 . 525 is communicated.

3 shows a schematic representation of a fourth short-circuit protection circuit 3 according to a first embodiment of the invention.

3 makes an enlarged section of the in 2 shown parallel test circuit diagram 2 and includes the first comparator unit 501 acting as the active first isolation amplifier 31 trained second short circuit protection circuit 516 , the first AD converter to be tested 21 and the first AND gate 505 ,

When the first short-circuit protection circuit 506 as active first isolation amplifier 31 is formed, no further action must be taken during the calibration and test mode. The short-circuit test can be used simultaneously for several parallel-connected AD converters 21 - 23 respectively.

However, in this embodiment of the invention, high demands are placed on the frequency response and on the linearity of the active first isolation amplifier 31 especially the first isolation amplifier 31 that of the precision signal generator 201 generated signal unadulterated to the immediately thereafter arranged first input contact 211 must pass on. The first isolation amplifier 31 represents a kind of galvanic decoupling, in which the reaction of the first input contact 211 applied input signal to the input contacts 221 and 231 is prevented.

Unlike the parallel test plan 2 in 2 therefore branches the first return line 507 in 3 only after the first isolation amplifier 31 , immediately before the first input contact 211 on the first comparator unit 501 from.

4 shows a schematic representation of a fifth short-circuit protection circuit 4 according to a second embodiment of the invention. 4 makes an enlarged section of the in 2 shown parallel test circuit diagram 2 represents.

At the fifth short-circuit protection circuit 4 is the first short circuit protection 506 as a current-controlled disconnector 41 educated. The precision signal generator 201 is for it with a power knife 202 fitted.

The input impedance of the first input contact 211 is specified. So it is known how much power a working AD converter 21 - 23 consumed. Before the calibration mode is performed, the input contacts become 211 . 221 . 231 of the parallel test plan 2 checked consecutively for a short circuit. The test procedure is sequential, each input contact 211 . 221 and 231 is checked one after the other for a short circuit. At the beginning of the test is the current-controlled disconnector 41 while in the open state. The precision signal generator 201 is set to a fixed voltage. Thereafter, the first current-controlled disconnect switch 41 and the other designed as current-controlled circuit breaker short circuits 516 and 526 closed one after the other. The from the precision signal generator 201 delivered and measured current is compared with the expected current. Dodges after closing one of the current-controlled disconnect switch 41 the measured current value from its expected value, then the respective AD converter 21 . 22 . 23 rated as defective and this AD converter 21 . 22 . 23 associated current-controlled disconnect switches remain open during the following calibration and test mode, whereby the faulty ADC 21 . 22 . 23 is not considered in the following calibration and test mode.

In this embodiment of the invention, the control of the current-controlled disconnect switches from the ammeter 202 accepted. For each current-controlled disconnector, therefore, an additional, in 4 Control line, not shown, extending from the circuit breaker to the precision signal generator 201 arranged power meters 201 extends.

5 shows a schematic representation of a sixth short-circuit protection circuit 5 according to a third embodiment of the invention. 5 makes an enlarged Detail of the in 2 shown parallel test circuit diagram 2 represents.

At the sixth short-circuit protection circuit 5 is the first comparator unit 501 through a first comparator 402 with a first calibration unit 403 , with a first switch 404 and with a second switch 405 and by a second comparator 412 with a second calibration unit 413 , with a third switch 414 and with a fourth switch 415 educated.

The first comparator 402 checks at the first input contact 211 applied signal value to an exceeding of the by the first reference signal generator 401 generated maximum reference value, the second comparator 412 checks signal value for a shortfall of the second reference signal generator 411 generated minimum reference value.

The first calibration unit 403 is with the first comparator 402 connected and controls this. The first reference line 406 leads to the first input of the first comparator 402 ,

The first calibration line 407 leads to the second input of the comparator 402 , Right in front of the second input of the first comparator 402 is a first switch 404 provided, which is the second input of the first comparator 402 either on the first calibration line 407 or on the test signal line 409 can switch. At the output of the first comparator 402 is a second switch 405 arranged the output on the calibration unit 403 can switch.

The structure and operation of the second comparator 412 with the switches 414 and 415 and with the calibration unit 413 corresponds to the described structure and the described operation of the first comparator 402 with the switches 404 and 405 as well as with the calibration unit 403 ,

The test signal line 409 , the reference lines 406 and 416 as well as the calibration lines 407 and 417 are managed as closely together as possible so that all lines experience the same external disturbances. The switch positions of the switches 404 . 405 . 414 and 415 are in 5 with the letters "T" for test mode and "K" for calibration mode.

On the test signal line 409 is a second isolation amplifier 52 arranged. On one each directly before and after the second isolation amplifier 52 attaching parallel signal line of the test signal line 409 is a circuit breaker 52 educated. The circuit breaker 51 and the second isolation amplifier 52 Together they form a comparator controlled isolation circuit 53 , The comparator-controlled disconnector 51 is through the comparators 402 and 412 by means of an in 5 not shown control line switchable.

At the rear of the second isolation amplifier 52 located branch point of this parallel signal line also sets that line, via the switch 404 and 414 with the respective second input of the comparators 402 and 412 can be connected in the switch position "T".

The second isolation amplifier 52 is used to decouple the inputs, there are only low demands on the frequency response, the gain or the linearity of the second isolation amplifier 52 posed. The second isolation amplifier 52 just need the short circuit test voltage, which is the precision signal generator 201 outputs, essentially true to amplitude to the comparators 402 and 412 pass on.

At the beginning of the parallel test is first for all AD-converters 21 - 23 the calibration mode is executed. Here are the switches 404 . 405 . 414 and 415 in position "K". The position of the disconnector 51 plays no role in the calibration mode. The calibration mode is performed to ensure that the comparators 402 and 412 switch exactly at the same voltages. At the entrances of the first comparator 402 are now the first reference line 406 and the first calibration line 407 and at the inputs of the second comparator, the second reference line 416 and the second calibration line 417 connected. The output of the first comparator 402 leads to the first calibration unit 403 and the output of the second comparator 412 leads to the second calibration unit 413 ,

In calibration mode, the first calibration unit adjusts 403 the offset and hysteresis of the first comparator 402 until it switches exactly at equal voltage. Analogously, the second calibration unit adjusts 413 the offset and the hysteresis of the second comparator 412 until it also switches exactly at equal voltage. This ensures that in the test mode the precision signal generator 201 exactly when the maximum reference voltage of the first reference signal generator is reached 401 and the minimum reference voltage of the second reference signal generator 411 is switched off.

Now, the parallel short-circuit test is performed. First, the circuit breaker 51 open. This short-circuit test is therefore only the second isolation amplifier 52 active. After that, the switches 404 . 405 . 414 and 415 placed in the position "T".

Now from the precision signal generator 201 one within the permissible, by the precision signal generators 401 and 411 defined signal interval. Now by one of the comparators 402 and 412 detected a short circuit, remains the comparator-controlled disconnector 51 also open during the following test cycle and thus disconnects the shorted first input contact 211 from the test signal line 409 and thus from the other input contacts 221 and 231 , Used by the comparators 402 and 412 no short circuit is detected, the comparator-controlled disconnect switch 51 from the comparators 402 and 412 closed via the control line. This will create a direct connection between the precision signal generator 201 and the first input contact 211 produced.

The comparator-controlled disconnector 51 is thus only for those AD converters 21 - 23 closed, who have survived the short-circuit test without error. For those AD converters 21 - 23 in which the short-circuit test has detected an error, the comparator-controlled disconnector remains 51 in the open state.

Now the actual test mode is performed. In this case, by the reference signal generator 201 via the test signal line 409 as long as test signals to the input contacts 211 . 221 . 231 until one of the comparators determines that the test signal is being passed through the reference signals of the precision signal generators 401 and 411 spanned interval leaves. In this case the test mode is finished.

In this embodiment, it is advantageous that the short-circuit test for the AD converter to be tested in parallel 21 - 23 can be performed in parallel, resulting in a large time savings. Furthermore, the second isolation amplifier 52 very cost, especially since only low demands on the frequency response, the gain or the linearity of the second isolation amplifier 52 be put. The second isolation amplifier 52 need only for a short time from the precision signal generator 201 delivered short-circuit test voltage in approximately amplitude to the comparators 402 and 412 pass on. Moreover, in this embodiment, no external control lines for actuating the switches 404 . 405 . 414 . 415 needed.

6 shows a first Schaltverhaltensdarstellung 6 the comparators 402 and 412 ,

The horizontal axis represents switching behavior 6 forms the timeline. On the vertical axis is the one at the first input contact 211 applied voltage value U shown.

In the switching behavior diagram 6 is a designated by the name "Uramp" straight line is shown, which is a constantly increasing test waveform of the precision signal generator 201 represents. By lying over this straight triangular area is the switching behavior of the first reference signal generator 401 and by the lying below this straight triangular area, the switching behavior of the second reference signal generator 411 shown.

By the values Uramp _min and Vramp _max is that of the precision signal generator 201 can be generated voltage range. The values V _SS and V _DD are the permissible range of the supply voltage for the first input contact 211 given. The one of the first reference signal generator 401 generated maximum reference value is in 6 denoted by Uref _max . The one of the second reference signal generator 411 generated minimum reference value is in 6 removed with Uref _min.

The area spanned by the lines Uref _min and Uref _max indicates the desired range in which the signal voltage Uramp is smaller than the maximum reference voltage and coarser than the minimum reference voltage. In this area give two comparators 404 and 414 a logical one.

For the short circuit test, the precision signal generator 201 set to any voltage in this range, for example, the average of the minimum and the maximum reference signal value.

In the case of the possible short circuits, a distinction is made between a short circuit to ground, that is to say V _SS and a short circuit to the operating voltage, ie to V _DD . Is the input contact 211 of the first AD converter 21 shorted to V _SS , the signal value is below the minimum reference value Uref _min , so that the second comparator 412 outputs a logical zero. If the first input _{contact is} short-circuited to V _DD , then the test voltage value is above the maximum reference value Uref _max , in this case, the first comparator is 402 a logical zero. On the other hand, if there is no short circuit, both comparator outputs, as already described above, have the same logical output value of one.

7 shows a second switching behavior representation 7 the comparators 402 and 412 ,

In the second switching behavior representation 7 The short-circuit voltage with U _short and the test voltage lying within the permissible range at the first input contact 211 designated U _mid.

The second switching behavior representation 7 is divided into three adjacent areas.

In the left-hand area, a short circuit to ground (stuck at V _SS ) in the middle range shows a permissible test signal value in the short-circuit test and in the right-hand area a short circuit to the supply voltage V _DD (stuck at V _DD ).

The mathematical term shown on the left in each of these three areas describes that in the first comparator 402 conducted investigation, the second term each describes the second comparator 412 conducted investigation.

In the left area of the second switching behavior display 7 gives the second comparator 412 a logic zero, since the difference between U and _short Uref results _min a value less than zero.

In the middle range are from both comparators 402 and 412 logical ones are output.

In the third area gives the first comparator 402 a logical zero, since the difference between Uref _max and U _{short is} less than zero.

LIST OF REFERENCE NUMBERS

1

tester building

101

Control computer system

102

measuring instruments

103

Network management

104

control line

105

tester

106

measuring table

107

bearing surface

108

probe card

109

first intermediate level

110

second intermediate level

111

third intermediate level

112

fourth intermediate level

113

switching matrix

114

Measurement data lines

2

Parallel test diagram

201

Precision signal generator

202

ammeter

21

first AD converter

22

second AD converter

23

third AD converter

211

first input contact

212

first output contact

221

second input contact

222

second output contact

231

third input contact

232

third output contact

401

first reference signal generator

402

first comparator

403

first calibration unit

404

first switch

405

second switch

406

first reference line

407

first calibration line

409

Test signal line

411

second reference signal generator

412

second comparator

413

second calibration unit

414

third switch

415

fourth switch

416

second reference line

417

second calibration line

501

first comparator unit

502

first output signal line

503

second output signal line

504

first validation signal line

505

first and gate

506

first short-circuit protection circuit

507

first return line

511

second comparator unit

512

third output signal line

513

fourth output signal line

514

second validation signal line

515

second and gate

516

second short-circuit protection circuit

517

second return line

521

third comparator unit

522

fifth output signal line

523

sixth output signal line

524

third validation signal line

525

third and gate

526

third short circuit protection circuit

527

third return line

531

Decision logic unit

532

Control signal line

3

fourth short circuit protection circuit

31

first isolation amplifier

4

fifth short-circuit protection circuit

41

current-controlled disconnector

5

sixth short circuit protection circuit

51

comparator-controlled disconnector

52

second isolation amplifier

53

comparator controlled isolation circuit

6

first switching behavior representation

7

second switching behavior representation

Claims (16)

Test device ( 2 ) for testing electrical circuits ( 21 . 22 . 23 ), wherein the test device ( 2 ) has the following features: - at least two input contacts ( 211 . 221 . 231 ) for connection to the electrical circuits ( 21 - 23 ), whereby at the input contacts ( 211 . 221 . 231 ) different electrical circuits can be connected, - for each input contact ( 211 . 221 . 231 ) is ever an electrical short-circuit protection circuit ( 506 . 516 . 526 ) available, The output of each electrical short-circuit protection circuit ( 506 . 516 . 526 ) is connected to the associated input contact ( 211 . 221 . 231 ), - a signal generator ( 201 ), which is intended to generate a test signal and which is connected via a respective connecting line ( 409 ) with each input of the electrical short-circuit protection circuits ( 506 . 516 . 526 ), - by any short-circuit protection circuit ( 506 . 516 . 526 ) is the respective input contact ( 211 . 221 . 231 ) from the front of the input of the electrical short-circuit protection circuit ( 506 . 516 . 526 ) lying connection line ( 409 ), wherein each electrical short-circuit protection circuit ( 506 . 516 . 526 ) via a disconnect switch ( 51 ) and via a parallel to the circuit breaker ( 51 ) switched isolation amplifier ( 52 ), whereby the inputs of the circuit breaker ( 51 ) and the isolation amplifier ( 52 ) to the signal generator ( 201 ) and the outputs of the circuit breaker ( 51 ) and the isolation amplifier ( 52 ) to the respective input contact ( 211 . 221 . 231 ) are connected. Test device according to claim 1, characterized in that for each input contact ( 211 . 221 . 231 ) one comparator unit each ( 501 . 511 . 521 ) connected to the input of the electrical short-circuit protection circuit ( 506 . 516 . 526 ), the test device ( 2 ) at least one reference signal generator ( 401 . 411 ), each of which is intended to generate a reference signal and by means of at least one line ( 406 . 407 . 416 . 417 ) with each comparator unit ( 501 . 511 . 521 ) connected is. Test device according to claim 2, characterized in that the at least one reference signal generator by means of a reference line ( 406 . 416 ) and by means of a calibration line ( 407 . 417 ) with each comparator unit ( 501 . 511 . 521 ) connected is. Test device according to claim 2 or 3, characterized in that a decision logic unit ( 531 ), which are compatible with the comparator units ( 501 . 511 . 521 ) and which is designed so that from output signals of the comparator units ( 501 . 511 . 521 ) Control signals ( 532 ) for the signal generator ( 201 ) are producible. Test device according to one of claims 2 to 4, characterized in that two reference signal generators ( 401 . 411 ), the first reference signal generator ( 401 ) for generating a lower reference signal and the second reference signal generator ( 411 ) are determined to generate an upper reference signal, each comparator unit ( 501 . 511 . 521 ) is able to reduce the test signal to a value lower than that which the first reference signal generator ( 401 ) generated lower reference signal and to an exceeding of the by the second reference signal generator ( 411 ) to verify the generated upper reference signal. Test device according to one of claims 2 to 5, characterized in that each comparator unit ( 501 . 511 . 521 ) each have a comparator ( 402 . 412 ) having. Test device according to one of claims 3 to 6, characterized in that each comparator unit ( 501 . 511 . 521 ) via at least one calibration unit ( 403 . 413 ) and each comparator unit ( 501 . 511 . 521 ) is also operable in a calibration mode, which is designed such that the switching properties of the comparator unit ( 501 . 511 . 521 ) by means of the at the comparator unit ( 501 . 511 . 521 ) applied signal values of the calibration line ( 407 . 417 ) and the reference line ( 406 . 416 ) by the at least one calibration unit ( 403 . 413 ) are adjustable. Test device according to claim 7, characterized in that each comparator ( 402 . 412 ) has two inputs and one output, the first input of each comparator ( 402 . 412 ) with the reference line ( 406 . 416 ) of the reference signal generator ( 401 . 411 ), the second input of each comparator ( 402 . 412 ) on the calibration line ( 407 . 417 ) of the relevant reference signal generator ( 401 . 411 ) or to the output of the electrical short-circuit protection circuit ( 506 . 516 . 526 ), the output of each comparator being connected to its calibration unit ( 403 . 413 ) or to the signal generator ( 201 ), and wherein each calibration unit ( 403 . 413 ) the offset and the hysteresis of the respective comparator ( 402 . 412 ) adjusted. Test device according to one of claims 1 to 8, characterized in that for each input contact ( 211 . 221 . 231 ) one each for connection to an output of an integrated circuit specific output contact ( 212 . 222 . 232 ), which is connected to an output line. Test device according to one of claims 2 to 9, characterized in that of each comparator unit ( 501 . 511 . 521 ) one validation signal line each ( 504 . 514 . 524 ) leads to the relevant output line. Test device according to one of claims 1 to 9, characterized in that the input contact ( 211 . 221 . 231 ) by the electrical short-circuit protection circuit ( 506 . 516 . 526 ) from the front of the input of the electrical short-circuit protection circuit ( 506 . 516 . 526 ) lying connection line ( 409 ) is decoupled, if that at the input contact ( 211 . 221 . 231 ) applied test signal assumes a value deviating from a predetermined range. Test device according to one of claims 2 to 11, characterized in that between each of a circuit breaker ( 51 ) and the associated comparator unit ( 501 . 511 . 521 ) a control line is present, wherein the input contact ( 211 . 221 . 231 ) with the comparator unit ( 501 . 511 . 521 ) is switchably connectable, wherein the test device ( 2 ) is operable in a short circuit test mode having the following features: the short circuit protection circuit ( 506 . 516 . 526 ) is connected so that the connection between the signal generator ( 201 ) and the input contact ( 211 . 221 . 231 ) only via the isolation amplifier ( 52 ), - the input contact ( 211 . 221 . 231 ) is switched so that at the input contact ( 211 . 221 . 231 ) applied test signal with the comparator unit ( 501 . 511 . 521 ), - the disconnector ( 51 ) is from the comparator unit ( 501 . 511 . 521 ) either switchable so that the connection between the signal generator ( 201 ) and the input contact ( 211 . 221 . 231 ) via the disconnect switch ( 51 ), if that at the input contact ( 211 . 221 . 231 ) adjacent test value assumes a value lying in a predetermined range, or switchable so that the connection between the signal generator ( 201 ) and the input contact ( 211 . 221 . 231 ) only via the isolation amplifier ( 52 ), if that at the input contact ( 211 . 221 . 231 ) applied test signal assumes a value deviating from a predetermined range. Test device according to claim 12, characterized in that each comparator unit ( 501 . 511 . 521 ) and each short-circuit protection circuit ( 506 . 516 . 526 ) are switchable between the short circuit test mode, the calibration mode and a test mode. Test device according to one of claims 1 to 13, characterized in that it is applied to a probe card for testing integrated circuits and / or with at least one test socket for testing integrated circuits and / or for connecting a handler to an integrated circuit tester , Test device according to one of Claims 7 to 13, characterized in that it is contained in a tester, the tester comprising the following features: - the tester ( 105 ) has several instruments for generating signals or data streams and several measuring sensors for currents and voltages, - the tester ( 105 ) has a loadboard that is adapted to receive at least one probe card ( 108 ) for testing integrated circuits ( 21 - 23 ) and / or for connecting a handler to an integrated circuit tester ( 21 - 23 ) and / or that with at least one test socket for testing integrated circuits ( 21 - 23 ), - the signal generator ( 201 ) and the reference signal generators ( 401 . 411 ) of the test device are on the tester ( 105 ), wherein the comparator unit (s) ( 501 . 511 . 521 ) with the calibration units ( 403 . 413 ) and the electrical short-circuit protection circuits ( 506 . 516 . 526 ) on the loadboard, adjacent to the input contacts ( 211 . 221 . 231 ) for the integrated circuits ( 21 - 23 ) are arranged. Method for parallel testing of electrical circuits used as integrated circuits ( 21 . 22 . 23 ), comprising the following steps: a) providing a tester ( 105 ) with a loadboard that can hold multiple needle cards ( 108 ) for testing integrated circuits ( 21 - 23 ) and / or for connecting a handler to a tester ( 105 ) of integrated circuits ( 21 - 23 ) and / or with multiple test sockets for testing integrated circuits ( 21 - 23 b) loading the loadboard with several integrated circuits ( 21 - 23 ), the integrated circuits ( 21 - 23 ) to input contacts ( 211 . 221 . 231 ) and wherein a signal generator ( 201 ) and for each integrated circuit under test ( 21 - 23 ) each one electrical short-circuit protection circuit ( 506 . 516 . 526 ), c) testing the integrated. Circuits, whereby test signals are generated by the signal generator ( 201 ) to the input contacts ( 211 . 221 . 231 ), wherein a short-circuit test is carried out prior to method step c), in which it is first determined whether this at the relevant input contact ( 211 . 221 . 231 ) applied test signal has a value deviating from a predetermined range and in which thereafter those input contacts ( 211 . 221 . 231 ) by the electrical short-circuit protection circuits ( 506 . 516 . 526 ) selectively from the signal generator ( 201 ), in which a value deviating from a predetermined range has been determined, wherein each electrical short-circuit protection circuit ( 506 . 516 . 526 ) via a disconnect switch ( 51 ) and via a parallel to the circuit breaker ( 51 ) switched isolation amplifier ( 52 ), whereby the inputs of the circuit breaker ( 51 ) and the isolation amplifier ( 52 ) for connection to a signal generator ( 201 ) and the outputs of the circuit breaker ( 51 ) and the isolation amplifier ( 52 ) for connection to an input contact ( 211 . 221 . 231 ), wherein in the step of determining whether the test signal applied to the respective input contact has a value deviating from a predetermined range, the disconnect switch is opened, and if a short circuit has been detected, the disconnect switch remains open.

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