DE10334841B4 - A manufacturing method for a trench capacitor with an insulation collar, which is electrically connected on one side to a substrate via a buried contact, in particular for a semiconductor memory cell - Google Patents

Abstract

A manufacturing method for a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1) which is electrically connected on one side to the substrate (1) via a buried contact (15a, 15b; 20 '), in particular for a semiconductor memory cell having a planar selection transistor provided in the substrate (1) and connected via the buried contact (15a, 15b), comprising the steps of:
Providing a trench (5) in the substrate (1) using a hard mask (2, 3) with a corresponding mask opening;
Providing a capacitor dielectic (30) in the trench (5) and the isolation collar (10) in the trench (5);
Providing an electrically conductive filling (20) in the trench (5); Etching back the top of the hard mask (2, 3) so that the electrically conductive filling (20) projects over the top of the etched back mask (2, 3);
isotropically back etching the part of the electrically conductive filling (20) projecting beyond the upper side of the hard mask (2, 3) by a predetermined thickness;
Forming a mask ...

Description

production method for one Trench capacitor with an insulation collar that is buried over a Contact is unilaterally electrically connected to a substrate, in particular for one Semiconductor memory cell

The The present invention relates to a manufacturing method for a Trench capacitor with an insulation collar over one buried contact on one side electrically connected to a substrate is, in particular for a semiconductor memory cell.

The US 2001/00 42 880 A1, the DE 102 15 666 A1 , the EP 12 96 369 A1 and the US 6,498,061 B2 disclose such a manufacturing method.

Even though in principle be applicable to any integrated circuits the present invention and its underlying problem in relating to integrated memory circuits in silicon technology explained.

1 shows a schematic sectional view of a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto.

In 1 denotes reference numeral 1 a silicon semiconductor substrate. Provided in the semiconductor substrate 1 are trench capacitors GK1, GK2, which have trenches G1, G2, their electrically conductive fillings 20a . 20b form first capacitor electrodes. The conductive fillings 20a . 20b are in the lower and middle trench area through a dielectric 30a . 30b opposite to the semiconductor substrate 1 isolated, which in turn forms the second capacitor electrodes (possibly in the form of a buried plate, not shown).

In the middle and upper area of the trenches G1, G2 are circumferential insulation collars 10a . 10b provided, above which buried contacts 15a . 15b attached to the conductive fillings 20a . 20b and the adjacent semiconductor substrate 1 to be in electrical contact. The buried contacts 15a . 15b are only one-sided to the semiconductor substrate 1 connected (cf. 2a , b). isolation regions 16a . 16b isolate the other substrate side from the buried contacts 15a . 15b or isolate the buried contacts 15a . 15b towards the top of the trenches G1, G2.

This allows a very high packing density of the trench capacitors GK1, GK2 and the associated selection transistors, which will now be explained. In this case, reference is mainly made to the selection transistor belonging to the trench capacitor GK2, since only the drain region D1 and the source region S3 are shown in adjacent selection transistors. The selection transistor belonging to the trench capacitor GK2 has a source region S2, a channel region K2 and a drain region D2. The source region S2 is connected via a bit line contact BLK to a bit line arranged above an insulation layer I (not shown). The drain region D2 is on one side to the buried contact 15b connected. Above the channel region K2 runs a word line WL2, which has a gate stack GS2 and a gate insulator GI2 surrounding it. The word line WL2 is an active word line for the selection transistor of the trench capacitor GK2.

Parallel adjacent to the word line WL2 run word lines WL1 consisting consisting of gate stack GS1 and gate insulator GI1 and word line WL3 from gate stack GS3 and gate insulator GI3, which for the selection transistor of the trench capacitor GK2 passive word lines are. These word lines WL1, WL3 serve to drive selection transistors, in the third dimension compared to the sectional view shown are shifted.

Obviously out 1 is the fact that this type of single-ended connection of the buried contact enables a direct juxtaposition of the trenches and the adjacent source regions or drain regions of the selection transistors. As a result, the length of a memory cell can only be 4 F and the width only 2 F, where F is the minimum technologically realizable unit of length (cf. 2a , b).

2A shows a plan view of a memory cell array with memory cells according to 1 in a first arrangement possibility.

Reference DT in FIG 2A denotes trenches which are arranged line by line with a period of 4 F to each other and column by column with a period of 2 F. Adjacent lines are shifted by 2 F against each other. UC in 2A denotes the area of a unit cell which is 4 F × 2 F = 8 F ² . STI denotes isolation trenches, which are arranged in the row direction at a distance of 1 F to each other and isolate adjacent active areas against each other. Also at a distance of 1 F each other run bit lines BL in the row direction, whereas the word lines in the column direction at a distance of 1 F to each other. In this arrangement example, all the trenches DT on the left side have a contact area KS of the buried contact for Substrate and an isolation area IS on the right side (areas 15a , b or 16a , b in 1 ).

2 B shows a plan view of a memory cell array with memory cells according to 1 in a second arrangement possibility.

In this second arrangement possibility, the rows of trenches have alternating terminal regions or isolation regions of the buried contacts. So are in the bottom row of 2 B the buried contacts are each provided on the left side with a contact area KS1 and on the right side with an isolation area IS1. On the other hand, in the overlying row all trenches DT on the left side are provided with each isolation area IS2 and on the right side with a contact area KS2. This arrangement is alternating in the column direction.

The Object of the present invention is a simple and safe manufacturing method for such a one-sided specify connected trench capacitor.

According to the invention this Task by the production method specified in claim 1 solved.

The Advantages of the method according to the invention lie in particular in the fact that there is a precise definition of the connection area or the complementary one Isolation area at the respective buried contact of the trench capacitor allows.

In the dependent claims find advantageous developments and improvements of in claim 1 specified production method.

According to a preferred development, the mask is formed by the following steps:
Providing a silicon nitride liner over the hardmask and the filled trench with the overhanging filling;
Providing a silicon liner over the silicon nitride liner;
Performing at least one oblique implantation into the silicon liner, wherein a portion of the silicon liner remains shadowed over the conductive fill and the etch rate of the implanted region of the silicon liner is decreased for a predetermined etch process;
selectively removing the shadowed area by the etching process;
Oxidizing the implanted region of the silicon liner; and
selectively removing the silicon nitride liner under the removed shadowed area to expose the recessed area of the electrically conductive fill which extends to the edge.

According to a further preferred development, the mask is formed by the following steps:
Providing a silicon nitride liner over the hardmask and the filled trench;
Providing a silicon liner over the silicon nitride liner;
Performing at least one oblique implantation into the silicon liner, wherein a portion of the silicon liner remains shadowed over the conductive fill and the etch rate of the implanted region of the silicon liner is decreased for a predetermined etch process;
selectively removing the shadowed area by the etching process;
selectively removing the silicon nitride liner under the removed shadowed area;
selectively removing the implanted region of the silicon liner;
Oxidizing the exposed edge-extending portion of the electrically conductive fill to form an oxide region; and
selectively removing the remaining silicon nitride liner to expose the recessed region of the electrically conductive fill that extends to the edge.

According to a further preferred development, the mask is formed by the following steps:
Performing at least one oblique implantation in the portion of the electrically conductive filling projecting beyond the top of the hardmask, wherein a portion of the portion of the conductive filling projecting beyond the top of the hardmask remains shadowed and the oxidation rate of the implanted portion of the portion of the implant overhanging the top of the hardmask reduced conductive filling for a predetermined oxidation process; and
selectively oxidizing the exposed edge-extending portion of the electrically conductive fill to form an oxide region, leaving the edge-extending portion of the electrically conductive fill free.

According to one Another preferred embodiment is in the implant or the Boron or boron-containing ions implanted.

According to one Another preferred development implanted nitrogen in the implantation nitrogen ions.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

It demonstrate:

1 a schematic sectional view of a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto;

2A , B is a respective plan view of a memory cell array with memory cells according to 1 in a first and second arrangement possibility;

3A -F schematic representations of successive process stages of a manufacturing process as a first embodiment of the present invention;

4A -E schematic representations of successive process stages of a manufacturing process as a second embodiment of the present invention; and

5A , B are schematic representations of successive process stages of a manufacturing process as a third embodiment of the present invention.

In the same reference numerals designate the same or functionally identical Ingredients.

at The embodiments described below are for the sake of clarity to a description of the fabrication of the planar select transistors omitted and only the formation of the unilaterally connected buried contact of the trench capacitor discussed in detail. The steps of manufacture the planar select transistors are the same unless otherwise stated as in the prior art.

3A -F are schematic representations of successive process stages of a manufacturing process as an embodiment of the present invention.

In 3A denotes reference numeral 5 a trench formed in the silicon semiconductor substrate 1 is provided. On the upper side OS of the semiconductor substrate 1 provided is a hard mask consisting of a pad oxide layer 2 and a pad nitride layer 3 , In the ditch 5 is a dielectric 30 For example, provided from silicon nitride, which is an electrically conductive filling 20 opposite the surrounding semiconductor substrate 1 isolated. In the upper and middle area of the ditch 5 is a circumferential, into the substrate 10 taken in isolation collar 10 intended. An exemplary material for the insulation collar 10 is silica and for the electrically conductive filling 20 Polysilicon. But of course, other material combinations are conceivable.

As in 3A is the capacitor dielectric 30 in the entire trench 5 intended. The conductive polysilicon filling 20 is opposite the surrounding pad nitride 3 about 50 to 400 nm above, resulting either in an etching of the pad nitride 3 or removal of a previously provided over the pad nitride further hard mask can be achieved.

Following the in 3A shown process state is initially an isotropic etching back of the conductive polysilicon filling 20 in the area where they are above the padnitride 3 survives.

Regarding 3B At first, a silicon nitride liner is formed over the resulting structure 40 formed and about another liner of amorphous silicon 50 deposited.

Subsequently, a first and a second oblique implantation I1, I2 of boron ions take place in the silicon liner 50 , being an area 50a remains shadowed to define a mask opening over the later buried contact area.

Regarding 3C Then, a selective etching of the shaded area 50a with NH ₄ OH, since the implantations I1 and I2, the etch rate of the remaining silicon liner 50 has been greatly reduced.

In a subsequent process step, the remaining silicon liner 50 to an oxidized silicon liner 50 ' oxiciert, what finally to in 3C shown process state leads.

Regarding 3D becomes the silicon liner 40 in the area where previously the non-implanted silicon liner 50a removed, also removed. Then, an etching of the conductive filling takes place 20 to below the top of the insulation collar 10 , This will cause the capacitor dielectric 30 exposed in the later terminal area of the buried contact.

Regarding 3E then become the oxidized silicon liner 50 ' and the remaining silicon nitride liner 40 and the capacitor dielectric 30 selectively removed in the exposed area by a respective etch to expose the later terminal area of the buried contact. In this case, the SiO ₂ etching mask can also be removed or else removed separately in a subsequent process step.

Finally, with reference to 3F a deposit of another conductive filling 20 ' made of polysilicon, which on the left side of 3F the connection area KS is completed, which is opposite to the isolation area IS.

In further known per se process steps then the filling 20 . 20 ' be polished back mechanically chemically and be sunk below the top of the substrate, whereupon finally the trench can be closed with an insulating lid made of silicon oxide, not shown.

4A -E are schematic representations of successive process stages of a manufacturing process as a second embodiment of the present invention.

The in 4A Process state shown corresponds to the process state according to 3B in which an oblique implantation I1 of boron ions is carried out so that the shaded area 50a does not correspond to the later connection area but the later isolation area.

According to 4B After implantation I1, the selective etching of the shaded area takes place 50a of the liner 50 and then removing the silicon nitride liner 40 in the from the silicon liner 50 uncovered area, eventually leading to in 4B shown process state leads.

In this second embodiment, however, the silicon liner 50 not oxidized. Rather, the silicon liner 50 regarding 4C through an etching process that takes place on the silicon nitride liner 40 stops, and then removes the exposed portion of the conductive polysilicon fill 20 selectively oxidized to an oxide region 70 as a mask on it.

Regarding 4D then becomes the silicon nitride liner 40 selectively removed and then the conductive polysilicon filling 20 to below the top of the insulation collar 10 using the oxide region 70 etched as a mask to the capacitor dielectric 30 to expose later in the connection area.

As in 4E after that, the oxide area becomes thereafter 70 removed by an etch and another conductive filling 20 ' made of polysilicon applied. Thus arises as in 4E shown, the terminal region KS of the buried contact, which is opposite to the isolation region IS.

The other possible Process steps that are not shown correspond to those with reference to the first embodiment already explained are.

5A , B are schematic representations of successive process stages of a manufacturing process as a third embodiment of the present invention.

The in 5A Process state shown corresponds to the process state according to 3B after etching back the conductive filling 25 but before the deposition of the liner 40 respectively. 50 ,

Rather, in this third embodiment, an implantation of nitrogen ions I3 directly into the etched-back upper portion of the conductive polysilicon fill 20 carried out. The nitrogen ions inhibit the oxidizing ability of the implanted region of the conductive filling 20 , However, due to the fact that the implantation is performed obliquely, a region AS of the conductive filling remains shaded. In this area AS, the oxidation capacity is undiminished.

This is done according to 5B thereby exploiting that there selectively a oxide region 70 is grown, whereas the implanted region of the conductive polysilicon filling is not or only marginally oxidized.

The on 5B subsequent process steps of the third embodiment correspond to those according to 4C to E after removing the silicon liner 40 in 4C ,

Even though the present invention above based on a preferred embodiment It is not limited to this, but in many ways and modifiable.

Especially the choice of the layer materials is only exemplary and can be varied in many ways.

Also the invention is not limited to the insulating collar embedded in the substrate limited, but also for conventionally applicable to the trench wall patch insulation collars applicable.

1

Si semiconductor substrate

OS

top

2

pad oxide

3

pad nitride

5

dig

40

senior epitaxial

10 10a, 10b

insulation collar

20 20a, 20b

senior filling (e.g., polysilicon)

15a, 15b

buried Contact

16a, 16b

Quarantine

G1, G2

dig

GK 1, GK2

grave capacitor

30 30a, 30b

capacitor

S1, S2, S3

source region

D1, D2

drain region

K2

channel region

WL WL1, WL2, WL3

wordline

GS1, GS2, GS3

gate stack

GI1, GI2, GI3

gate insulator

I

insulation layer

F

minimum unit of length

BLK

bit line

BL

bit

DT

dig

AA

active area

STI

isolation region (Shallow trench isolation)

UC

Area unit cell

KS, KS1, KS2

contact area

IS, IS1, IS2

Quarantine

40

silicon nitride liner

50

silicon liner

I1, I2, I3

implantation

50a

shadowed area of 50

AS

shaded area at I3

Claims (6)

Manufacturing method for a trench capacitor with an insulation collar ( 10 ; 10a . 10b ) in a substrate ( 1 ), who has a buried contact ( 15a . 15b ; 20 ' ) on one side with the substrate ( 1 ) is electrically connected, in particular for a semiconductor memory cell with a in the substrate ( 1 ) and via the buried contact ( 15a . 15b ) connected planar selection transistor, comprising the steps of: providing a trench ( 5 ) in the substrate ( 1 ) using a hard mask ( 2 . 3 ) with a corresponding mask opening; Providing a capacitor dielectrics ( 30 ) in the ditch ( 5 ) and the insulation collar ( 10 ) in the ditch ( 5 ); Providing an electrically conductive filling ( 20 ) in the ditch ( 5 ); Etching back the top of the hard mask ( 2 . 3 ), so that the electrically conductive filling ( 20 ) over the top of the etched back mask ( 2 . 3 ) survives; isotropic re-etching of the over the top of the hard mask ( 2 . 3 ) projecting part of the electrically conductive filling ( 20 ) by a predetermined thickness; Forming a mask over the etched back over the top of the hardmask ( 2 . 3 ) projecting part of the electrically conductive filling ( 20 ) which extends up to the edge of the electrically conductive filling ( 20 ) leaves; Removing the electrically conductive filling ( 20 ) using the mask to below the top of the insulation collar ( 10 ) exposing the dielectric ( 30 ) in the later connection area (KS); Remove the exposed dielectric ( 30 ) in the later connection area (KS) and the mask; and filling the trench ( 5 ) with another electrically conductive filling ( 20 ' ) to make the buried contact. Method according to claim 1, characterized in that the mask is formed by the following steps: providing a silicon nitride liner ( 40 ) over the hard mask ( 2 . 3 ) and the filled trench ( 5 ) with the overflowing filling; Providing a silicon liner ( 50 ) over the silicon nitride liner ( 40 ); Performing at least one oblique implantation (I1, I2) in the silicon liner ( 50 ), where one area ( 50a ) of the silicon liner ( 50 ) over the conductive filling ( 20 ) and the etch rate of the implanted region of the silicon liner ( 50 ) is lowered for a predetermined etching process; selectively removing the shaded area ( 50a ) by the etching process; Oxidizing the implanted region of the silicon liner ( 50 ); and selective removal of the silicon nitride liner ( 40 ) under the removed shaded area ( 50a ) to expose the recessed area of the electrically conductive filling ( 20 ). Method according to claim 1, characterized in that the mask is formed by the following steps: providing a silicon nitride liner ( 40 ) over the hard mask ( 2 . 3 ) and the filled trench ( 5 ); Providing a silicon liner ( 50 ) over the silicon nitride liner ( 40 ); Performing at least one oblique implantation (I1) in the silicon liner ( 50 ), where one area ( 50a ) of the silicon liner ( 50 ) over the conductive filling ( 20 ) and the etch rate of the implanted region of the silicon liner ( 50 ) is lowered for a predetermined etching process; selectively removing the shaded area ( 50a ) by the etching process; Removing the silicon nitride liner ( 40 ) under the removed shaded area ( 50a ); selective removal of the implanted region of the silicon liner ( 50 ); Oxidizing the exposed to the edge extending portion of the electrically conductive filling ( 20 ) for forming an oxide region ( 70 ); and selectively removing the remaining silicon nitride liner ( 40 ) to expose the recessed area of the electrically conductive filling ( 20 ). Method according to claim 1, characterized in that the mask is formed by the following steps: performing at least one oblique implantation (I3) in the over the top of the hard mask ( 2 . 3 ) projecting part of the electrically conductive filling ( 20 ), wherein an area (AS) of the over the top of the hard mask ( 2 . 3 ) projecting part of the conductive filling ( 20 ) and the oxidation rate of the implanted region of the over the top of the hard mask ( 2 . 3 ) projecting part of the conductive filling ( 20 ) is lowered for a predetermined oxidation process; and selectively oxidizing the exposed to the edge-extending portion of the electrically conductive filling ( 20 ) for forming an oxide region ( 70 ) leaving the edge-extending region of the electrically conductive filling ( 20 ). Method according to claim 2 or 3, characterized that in the implant or the implantations (I1, I2) boron or boron-containing Ions are implanted. Method according to claim 4, characterized in that that in the implantation (I3) nitrogen-nitrogen ions are implanted.