DE10308921B4 - Phase control arrangement for frequency synthesis - Google Patents

Abstract

Phase control arrangement for frequency synthesis, comprising
A digitally controllable oscillator (1) with a control input (2) and with an output (3),
- A phase / frequency comparison means (7) having a first input (10) for supplying a reference signal (φ _ref ), with a second input (6) which is coupled to the output (3) of the oscillator (1), and with an output for outputting an error signal and
A means for increasing the sampling rate (30) of the error signal, which couples the output of the phase / frequency comparison means (7) to the control input (2) of the oscillator (1),
- An accumulator (12) which is connected to the first input of the phase / frequency comparator (7) with its output and the reference signal (φ _ref ) as a phase signal assigns a digital channel word at its input and outputs at its output, and
A synchronization device having an output coupled to a synchronization input of the accumulator, having a first input for supplying an unsynchronized reference signal _, and

Description

The The present invention relates to a phase control arrangement for frequency synthesis.

to Frequency synthesis is usually Phase locked loops, so-called PLL, phase-locked loop, used. For mobile applications, at those carrier frequencies needed in the gigahertz range be, it is common to use analog PLL. For example, in the case of the mobile radio standard Bluetooth must have one carrier frequency in the order of magnitude of 2.4 gigahertz are modulated on the payload on become.

at analog PLL is common an analog, voltage-controlled oscillator provided, a so-called VCO, Voltage Controlled Oscillator, whose output signal, via a Divider frequency divided, a phase / frequency detector is supplied. This compares the divided oscillator signal with a Reference signal and controls in dependence from a phase and / or frequency deviation across a charge pump circuit and a loop filter on the oscillator. In further developments of this analog PLL, the frequency divider as a so-called multi-modulus divider accomplished be with a digital modulation signal, for example via a Sigma-delta converter is driven.

such, Analog PLL include both analog and digital function blocks. One significant disadvantage of such, so-called hybrid PLL in terms on their production possibilities in integrated circuit technology is in the relatively large footprint on the chip, especially regarding the charge pump circuit and the loop filter, and also in the high number of analog function blocks.

It is therefore desirable a high-frequency PLL possible build largely in digital circuit technology, including the Oscillator.

A Problem arises in a purely digital structure of the controlled Oscillator due to the necessarily existing quantization error. There are only discrete in a digitally controlled oscillator Frequencies can be generated with a least significant bit dependent quantization step size. Due to such, digital control of the oscillator arise in its output spectrum unwanted side lines in the distance the switching frequency, with the frequency-determining components in the oscillator be switched. As the switching frequency is usually clear is smaller than the oscillator frequency, this leads to violation of the spectral transmission mask. In the mobile radio system Bluetooth, for example must the sent out Performance, more precisely, the so-called in-band spurious emission a measuring bandwidth of one megahertz at a distance greater than 3 MHz, a value smaller as -40 dBm. This is stated in the Bluetooth specification.

The undesirable Switching frequency could thereby repressed be that on Input of the oscillator is connected to a digital-to-analog (DA) converter, which converts the digital control word to an analog tuning voltage. By such an averaging at the output of the DA converter the clock frequency is suppressed. This approach However, has the serious disadvantage that a high-precision and Above all, very fast DA converter is necessary because of the required bit depth a very big one Effort regarding the integration of the function block would mean.

In Document US 2002/0033737 A1 is a digitally controlled oscillator, DCO, shown in a loop. With a shift register and a multiplexer driven by a sigma-delta modulator disruptions caused by the DCO be reduced.

The document US 6,326,851 B1 concerns a digital PLL. A synchronous control logic synchronizes the PLL with a rising signal of a digital oscillator.

task It is the object of the present invention to provide a cost-effective phase control arrangement specify which for use in mobile devices according to modern digital mobile radio standards is suitable and complies with the specifications provided there.

According to the invention Task solved by a phase locked arrangement having the features of the claim 1.

According to the proposed Principle, a digitally operating phase control arrangement is provided, which is due to the special control of the oscillator increased Sampling rate of the digitally coded tuning signal distinguished.

The Reference sidebands the output spectrum are due to the oversampling of the digital Output words of the phase / frequency comparator outside the useful tape.

By the proposed increase the sampling rate of the control signal or tuning signal of the oscillator Is it possible, Spectral transmission masks of modern, digital mobile radio standards when using cheaper, digital function blocks, in particular a digitally tuned oscillator to comply.

The oversampling the digital Abstimmwortes of the oscillator according to the proposed principle is also called oversampling.

The Clock frequency at which oversampling occurs and the means of increase the sampling rate fed is preferably much larger than that Reference frequency of the phase locked loop.

According to one preferred embodiment of the invention, a converter is provided, the output of the digitally controllable oscillator with the second Input of the phase / frequency comparator couples and designed is for delivering a digitally coded phase signal in dependence from the output frequency of the oscillator.

By Respectively only the phase information of the oscillator and the output signal of the digitally controllable oscillator can be a simply constructed, digital phase / frequency comparator, preferably a so-called Digital Fractional Phase Comparator.

Prefers is between the output of the digitally controllable oscillator and the converter, which is the output frequency of the oscillator's digital assigns coded phase signal, a limiting amplifier switched. This is preferably used to convert the output signal of the oscillator in a rectangular or trapezoidal signal, thus enabling an improved Convertability of the thus obtained clock signal into a phase signal.

The Means to increase the sampling rate preferably has a clock input for synchronization purposes, which is coupled to the output of the oscillator.

By the preferred coupling of the clock input of the means for increasing the Sampling rate with the output of the oscillator can be the digital tuning signal, which is supplied to the oscillator for its control, to a clock frequency be synchronized, which with advantage at low cost of Circuit is significantly larger as the reference frequency of the phase locked loop.

The Clock frequency for synchronization of the means for increasing the Sample rate is preferred by frequency division from the signal the output frequency of the oscillator won.

Of the Frequency divider value of the frequency divider, which is the output of the oscillator preferred with the clock input of the means for increasing the sampling rate couples, can have a fixed value. For example, this divisor value Two or four.

to feed the reference signal to the phase / frequency comparator is an accumulator provided the one input side, digital channel word at his Output assigns a phase reference signal and to the first input the phase / frequency comparator outputs.

As well like the phase / frequency comparator, the accumulator also has preferably an input for feeding a synchronization signal.

For this is one Synchronization device provided at the input an unsynchronized reference frequency signal supplied can be. The synchronization device itself has a clock input, with the output of the oscillator for supplying a synchronization clock is coupled. The output of the synchronization device is with a Synchronization input of the accumulator connected. The exit the synchronization device is preferably with a synchronization input the phase / frequency comparator connected.

The Means to increase the sampling rate includes preferably several D flip-flops. These are particularly low Effort can be integrated in digital circuit technology.

Of the digitally controllable oscillator preferably comprises two switchable Capacitor banks, which each comprise frequency-determining capacities. One of these capacitor banks comprises preferably binary graduated Capacities, while the switchable capacities the further capacity field all are the same size, this means same capacity values exhibit. The capacities both capacity fields are preferably independent from each other, but in dependence from the tuning signal, on and off.

The Control of the same size capacities in the second capacity field preferably takes place via a thermometer code. This is a very fine tuning the oscillator frequency possible, for example with a modulation signal. At the same time can with the binary graduated Capacities very big Frequency range with relatively low Effort to be covered.

Further Details and advantageous embodiments of the proposed Principles are the subject of the dependent claims.

The Invention will be described below in several embodiments with reference to the Drawings closer explained.

It demonstrate:

1a An embodiment of the proposed principle based on a block diagram,

1b an embodiment of a synchronization device for generating a synchronized reference frequency for the circuit according to 1a .

2 an embodiment of a digitally tuned oscillator for use in a phase locked loop according to 1a .

3 a development of the circuit of 1a to an exemplary single-point modulator,

4 a development of the circuit of 3 to an exemplary two-point modulator and

5 a synchronization device according to 1b for generating a synchronized reference frequency for the circuits according to 3 and 4 ,

1a shows a phase locked loop with a digitally controllable oscillator 1 also known as DCO, Digitally Controlled Oscillator. The oscillator 1 has a digital voting input 2 for supplying a digitally coded tuning word and a signal output 3 at which a signal is provided at a frequency which is that at the input 2 dependent voting word is dependent. The output of the oscillator 3 on the one hand forms the output of the phase locked loop according to 1a and, on the other hand, has a limiting amplifier 4 and a downstream converter 5 to an entrance 6 a phase comparator 7 connected. The phase comparator is designed as a so-called digital fractional phase comparator. The limiting amplifier 4 converts the output signal of the oscillator 1 into a trapezoidal, ideally rectangular clock signal at the frequency of the oscillator output signal. The output of the limiting amplifier 4 is applied to the clock input of a D flip-flop 8th given whose input to the output of a summing 9 is connected and whose output is connected to an input of the summing element 9 connected is. At the increment input of the summing element 9 becomes a constant 1 created. The output of the summing element 9 , the output of the converter 5 is adapted for picking up a phase signal φφ _div in response to the output clock signal of the oscillator 3 ,

The digital frequency / phase detector 7 has another entrance 10 in which a phase signal with a reference phase φ _{ref can be} fed. In addition, the digital frequency / phase detector 7 a clock input 11 on, at which a reference frequency f _{ref is} supplied.

The reference phase input 10 is at the output of another converter 12 connected, as well as the converter a D flip-flop 13 and a summing element designed as an accumulator 14 includes. Another input of the summing element 14 is designed to supply a digitally coded channel word, with which the desired output frequency of the phase control arrangement shown can be adjusted. The output of the summing element 14 is on the one hand to the entrance 10 of the digital frequency / phase comparator 7 connected and on the other hand to the data input of the D flip-flop 13 placed. The output of the D flip flop 13 is to an input of the accumulator 14 connected. The D flip flop 13 has a clock input to which a signal with a reference frequency f _{ref can be} fed.

The output of the phase comparator 7 is about a multiplier 29 to the input of a means for sampling rate increase 30 connected. The multiplier 29 has another input for supplying a signal α and fulfills the function of a loop filter in conventional PLL. Accordingly, by suitable dimensioning of the signal α and / or the multiplier 29 the control loop can be dimensioned.

The means for sampling rate increase 30 exemplarily comprises two D-type flip-flops connected in series 32 . 33 indicating the output of the multiplier 29 with the tuning input of the oscillator 1 couple. Every D flip flop 32 . 33 has a clock input, which has a frequency divider 31 connected to the output of the oscillator.

1b shows a synchronization device 15 for providing a signal with a reference frequency f _ref which is already synchronized to the output frequency of the oscillator 1 , Accordingly, the output of the synchronization device 15 suitable for the clock input of the D flip-flop 13 and the phase / frequency comparator 7 head for. The synchronization device 15 exemplarily comprises two D-type flip-flops connected in series 16 . 17 each with a clock input. The clock inputs of the two D flip-flops 16 . 17 are on the output of the oscillator 1 , the reference numeral 3 wears, docked. At the entrance of the input D flip-flop 16 is an unsynchronized reference frequency f _{ref, unsync} fed.

The quantization error of the digitally tunable oscillator DCO can be described by f out = f 0 + x · f LSB , with x = x n-1 2 n-1 + ... + x 1 2 1 + x 0 2 0 ,

In this case, f ₀ denotes the oscillator frequency at the control variable x = 0 and f _LSB the quantization step width with regard to the discretely adjustable frequencies.

The output word of the digital fractional-phase comparator 7 is clocked at the clock frequency fref of present 13 megahertz. This output word is used with the means for sampling rate increase 30 oversampled and synchronized to the divided down output clock frequency f _{clk, div of} the oscillator, which is significantly greater than the reference frequency f _ref . The divider value n of the frequency divider is fixed and is for example 2 or 4. The reference sidebands are thereby outside the Bluetooth frequency band. Compliance with the spectral transmission mask is easily possible. According to the Bluetooth specification, the transmitted power outside the 2.4 gigahertz ISM (Industrial Scientific and Medical) band must be less than -47 dBm. This emitted power is referred to as Out-Of-Band Spurious Emission. With Bluetooth, this is only reduced by 7 dBm compared to the so-called in-band Spurious Emission. Due to the suppression of a connected antenna filter and a matching circuit, which are normally present anyway in mobile devices according to Bluetooth or other modern mobile radio methods, this requirement can be fulfilled much easier.

The phase control arrangement according to 1a with the synchronization device according to 1b is realized as a purely digitally constructed high-frequency PLL. Thus, the system costs can be significantly reduced because on the one hand can be dispensed with an external loop filter and on the other hand, the above-mentioned, complex analog function blocks are also not necessary. However, due to the over-sampling of the tuning signal of the oscillator, spectral transmission masks specified in the respective specifications of mobile radio standards can be easily met.

A further reduction of unwanted emissions is possible in the present principle in that the energy of the switching frequency is not concentrated on discrete frequency components, but the energy is distributed. This is also referred to as noise shaping or dithering. This dithering method is known from analog-to-digital converters and can also be used to drive the digital oscillator 1 be used.

2 shows an embodiment of a digitally tuned oscillator 1 which is designed as a LC oscillator with symmetrical structure. A power source 18 is connected to a supply potential connection 19 connected. To the power source 18 are two inductors 20 . 21 connected, which with their free connections the output 3 form the oscillator. At this exit 3 is a first and a second capacity field 22 . 23 connected as well as a Damping Amplifier 24 , the two cross-coupled MOS transistors 25 . 26 includes. The transistors 25 . 26 of the Damping Amplifier 24 are each with a load terminal to a reference potential terminal 27 placed. The two capacity fields 22 . 23 each comprise a plurality of independently connectable and disconnectable capacities. In the first capacity field 22 the capacities are binary graduated. That is, for example, a first capacitor has the capacitance value C, a second one has twice the capacitance value, a third four times, a fourth eight times, and so on. In the second capacity field 23 however, all switchable capacities are equipped with the same capacity value. The entrance 2 of the oscillator 1 is on the one hand with a control input of the first capacitance field 22 connected to the coarse channel selection, while a fine vote using the second capacity field 23 takes place, the control input via a converter 28 according to a thermometer code to the input 2 of the oscillator is placed.

To avoid monotonic errors, the least significant bits of the matching word with unit capacities become the capacitance field 23 realized and controlled by a thermometer code. Conveniently, the capacity fields 22 . 23 For example, for Bluetooth, Gaussian frequency shift keying (GFSK modulation) is used with a modulation swing of ± 160 kHz. To quantize this range with a resolution of about 5 kHz and taking into account a certain reserve 7 bits are needed. This corresponds to a frequency change of about 2 ppm, which in turn corresponds to a capacitance change in the attofarad range. This very fine frequency resolution is preferably achieved by interpolation, for example by means of a sigma-delta modulator, in which, by switching between the capacitance values, a quantization is achieved which is smaller than the smallest switchable frequency-determining capacitance of the oscillator. The more significant bits control a binary weighted capacitance field 22 on, which is used for channel setting. To cover the 85 MHz wide Bluetooth frequency band, this requires 8 bits.

The shown high-frequency oscillator 1 has a high quality. With the very small, switchable capacities, which are controlled with a thermometer code, a very fine frequency resolution is achieved.

3 shows a development of the circuit of 1a , which largely coincides with this in the components used, their interconnection and the advantageous mode of action. In that regard, the description of the figures should not be repeated at this point. In addition, in the circuit of 3 at the entrance of the accumulator 12 the output of an adder node 34 connected. The adding node 34 has two digital inputs, one of which is designed to supply a channel word and a second is designed as a modulation input for supplying a modulation signal MOD.

Accordingly, the reference phase signal φ _ref is formed not only in response to the channel word but also by the modulation signal.

at the present supply of modulation data in the reference branch The phase control arrangement is also called a direct modulation the reference phase or a one-point modulation.

such Phase-locked arrangements are particularly suitable for use in transmission arrangements the mobile phone suitable.

4 shows a development of the circuit of 3 , which largely coincides with this in the components used, their interconnection and the advantageous mode of action. In that regard, the description of the figures should not be repeated at this point. In addition, in the circuit of 4 another adder node 35 provided, which the output of the means for sampling rate increase 30 with the tuning input 2 of the oscillator 1 combines. The further adder node 35 has an additional input for supplying the modulation signal MOD.

Consequently a two-point modulator arrangement is provided. An advantage is, that the Bandwidth of the modulation signal can be greater than the bandwidth the phase controller itself.

such Phase-locked arrangements are particularly suitable for use in transmission arrangements the mobile with high transfer rates suitable.

5 shows a development of the synchronization device 15 from 1b with which it largely matches in structure and advantageous operation. In this respect, the description should not be repeated here. When switching from 5 is the unsynchronized reference frequency f _{ref, unsync} , the data input of the input side flip-flops 16 is supplied by means of a quartz oscillator 36 . 37 generated. This quartz oscillator comprises a quartz crystal 37 to which an active circuit 36 connected comprising capacitors and a de-attenuation amplifier. At the output of the oscillator, which is connected to the reference signal input of the synchronization device 15 Thus, a very precise and highly stable quartz frequency is provided.

1

oscillator

2

entrance

3

output

4

limiter

5

converter

6

entrance

7

digital fractional phase detector

8th

D flip-flop

9

summing

10

entrance

11

clock input

12

accumulator

13

D flip-flop

14

summing

15

synchronizer

16

D flip-flop

17

D flip-flop

18

power source

19

supply terminal

20

Kitchen sink

21

Kitchen sink

22

capacity field

23

capacity field

24

amplifier

25

transistor

26

transistor

27

Reference potential connection

28

Thermometer code converter

29

multipliers

30

medium for sampling rate increase

31

frequency divider

32

D flip-flop

33

D flip-flop

34

adding node

35

adding node

36

oscillator

37

quartz crystal

Claims (8)

Phase control arrangement for Frequenzsynthe comprising - a digitally controllable oscillator ( 1 ) with a control input ( 2 ) and with an output ( 3 ), - a phase / frequency comparison device ( 7 ) with a first input ( 10 ) for supplying a reference signal (φ _ref ), with a second input ( 6 ) connected to the output ( 3 ) of the oscillator ( 1 ) and having an output for outputting an error signal and - a means for increasing the sampling rate ( 30 ) of the error signal representing the output of the phase / frequency comparator ( 7 ) with the control input ( 2 ) of the oscillator ( 1 ), - an accumulator ( 12 ) located at the first input of the phase / frequency comparator ( 7 ) is connected to its output and assigns to a digital channel word at its input the reference signal (φ _ref ) as a phase signal and outputs at its output, and - a synchronization device ( 15 ) with an output connected to a synchronization input of the accumulator ( 12 ) having a first input for supplying an unsynchronized reference signal (f _{ref, unsync} ) and having a clock input connected to the output ( 3 ) of the oscillator ( 1 ) for supplying the output frequency (f _dco ) of the oscillator ( 1 ), wherein - the synchronization device ( 15 ) two successive D flip-flops ( 16 . 17 ), each having a clock input, wherein the clock inputs of the two D flip-flops ( 16 . 17 ) with the output ( 3 ) of the oscillator ( 1 ) for supplying the output frequency (f _dco ) of the oscillator ( 1 ) are coupled. Phase-locked arrangement according to Claim 1, characterized in that a converter ( 5 ) is provided, the output ( 3 ) of the oscillator with the second input ( 6 ) the phase / frequency comparator ( 7 ) coupled to output a digitally encoded phase signal (φ _div ) in response to the output frequency (f _dco ) of the oscillator. Phase-locked arrangement according to Claim 2, characterized in that a limiting amplifier ( 4 ) provided between the output ( 3 ) of the oscillator ( 1 ) and an input of the converter ( 5 ) is switched. Phase-locked arrangement according to one of Claims 1 to 3, characterized in that the means for increasing the sampling rate ( 30 ) has a clock input connected to the output ( 3 ) of the oscillator ( 1 ) is coupled to synchronize the means for increasing the sampling rate ( 30 ). Phase-locked arrangement according to Claim 4, characterized in that a frequency divider ( 31 ) is provided, the output ( 3 ) of the oscillator with the clock input of the means for increasing the sampling rate ( 30 ) couples. Phase-locked arrangement according to one of Claims 1 to 5, characterized in that the output of the synchronization device ( 15 ) with a synchronization input ( 11 ) of the phase / frequency comparator ( 7 ) connected is. Phase-locked arrangement according to one of Claims 1 to 6, characterized in that the means for increasing the sampling rate ( 30 ) at least one D flip-flop ( 32 ). Phase-locked arrangement according to one of Claims 1 to 7, characterized in that the oscillator ( 1 ) a binary staggered, switchable capacity field ( 22 ) and another capacity field ( 23 ) each having the same size, switchable capacity.