DE10214314A1 - Chip module with a dielectric substrate and at least one chip accommodated in a substrate cavity is provided with several electrodes which are shaped so that they almost completely cover the cavity base surface - Google Patents

Chip module with a dielectric substrate and at least one chip accommodated in a substrate cavity is provided with several electrodes which are shaped so that they almost completely cover the cavity base surface

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Publication number
DE10214314A1
DE10214314A1 DE2002114314 DE10214314A DE10214314A1 DE 10214314 A1 DE10214314 A1 DE 10214314A1 DE 2002114314 DE2002114314 DE 2002114314 DE 10214314 A DE10214314 A DE 10214314A DE 10214314 A1 DE10214314 A1 DE 10214314A1
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Prior art keywords
chip
electrodes
cavity
substrate
epoxy adhesive
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Ceased
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DE2002114314
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German (de)
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NedCard BV
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NedCard BV
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Priority to DE2002114314 priority Critical patent/DE10214314A1/en
Publication of DE10214314A1 publication Critical patent/DE10214314A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The chip module (1) with a dielectric substrate (2) and at least one chip (4) accommodated in a substrate cavity (5) is provided with several electrodes (3) which are shaped in such a way that they almost completely cover the cavity base surface. An Independent claim is also included for a method for producing such a chip module.

Description

Die vorliegende Erfindung betrifft ein Chipmodul mit einem dielektrischen Substrat, wenigstens einem Chip, der in eine Kavität des Substrats eingesetzt ist, und mehreren an dem Substrat angebrachten und gegeneinander elektrisch isolierten flächigen Elektroden, deren elektrische Anschlüsse in den Bereich der Kavität hineinragen und mit den Bondpads des Chips nach Art einer Direktkontaktierung verbunden sind. Des weiteren betrifft die vorliegende Erfindung ein Verfahren zur Herstellung eines solchen Chipmoduls. The present invention relates to a chip module a dielectric substrate, at least one chip, the is inserted into a cavity of the substrate, and several attached to each other and against each other electrically insulated flat electrodes, their electrical Project connections into the area of the cavity and with the bond pads of the chip in the manner of a direct contact are connected. Furthermore, the present concerns Invention a method for producing such Chip module.

Chipmodule der in Rede stehenden Art, bei denen die Bondpads des Chips und die elektrischen Anschlüsse der Elektroden nach Art einer Direktkontaktierung verbunden sind, sind am Markt erhältlich und werden beispielsweise von der STS ATL Corporation unter dem Markennamen "Microsite" vertrieben. Ihrem Grundsatz nach sind solche Module auch in der WO 01/65595 A3 der STS ATL Corporation beschrieben. Im Unterschied zu einer elektrischen Kontaktierung nach dem sogenannten Wire-Bonding-Verfahren, bei dem die Elektroden mit den Bondpads des Chips über Drähte verbunden werden, erfolgt bei den Chipmodulen, von denen die Erfindung ausgeht, eine direkte Verbindung der elektrischen Anschlüsse der Elektroden - auch Leads genannt - mit den Bondpads des Chips. Hierzu ragen die Leads der Elektroden in die Kavität des dielektrischen Substrats herein und sind den Bondpads des Chips genau gegenüberliegend angeordnet, so daß die Leads auf die Bondpads gedrückt werden können. Chip modules of the type in question, in which the Bondpads of the chip and the electrical connections of the Electrodes are connected in the manner of a direct contact, are available on the market and are, for example, from from STS ATL Corporation under the brand name "Microsite" distributed. In principle, such modules are also in WO 01/65595 A3 from STS ATL Corporation described. In contrast to an electrical contact according to the so-called wire-bonding process, in which the Electrodes with the bond pads of the chip over wires are connected to the chip modules, of which the Invention is based, a direct connection of the electrical connections of the electrodes - also called leads - with the bond pads of the chip. The leads of the Electrodes in the cavity of the dielectric substrate and are accurate with the chip's bond pads arranged opposite, so that the leads on the bond pads can be pressed.

Die Direktkontaktierung zwischen den Leads der Elektroden und den Bondpads des Chips wird aus verschiedenen Gründen für vorteilhaft erachtet. Als nachteilig wird jedoch angesehen, daß bei den bekannten Chipmodulen die Kavität oberhalb und unterhalb des Chips mit einem Epoxy-Material ausgegossen werden muß, um den Chip mit den Elektroden und dem dielektrischen Substrat zu verbinden, wobei auch die Leads der Elektroden mit dem Epoxy-Material bedeckt werden, da dies einerseits technisch aufwendig ist und andererseits zu bedeutenden kosmetischen Problemen führen kann. The direct contact between the leads of the electrodes and the bond pads of the chip is used for various reasons considered advantageous. However, being considered a disadvantage viewed that the cavity in the known chip modules above and below the chip with an epoxy material must be poured out to the chip with the electrodes and the dielectric substrate, wherein also the leads of the electrodes are covered with the epoxy material be because this is technically complex on the one hand and on the other hand lead to significant cosmetic problems can.

Aufgabe der vorliegenden Erfindung ist es daher, ein Chipmodul der eingangs genannten Art anzugeben, das auf einfache Weise herzustellen ist. Des weiteren soll ein Verfahren zur Herstellung eines solchen Chipmoduls angegeben werden. The object of the present invention is therefore a Specify chip module of the type mentioned at the beginning is easy to manufacture. Furthermore, one should Method for producing such a chip module can be specified.

Diese Aufgabe ist erfindungsgemäß dadurch gelöst, daß die Elektroden derart ausgebildet sind, daß sie die Grundfläche der Kavität im wesentlichen vollständig abdecken. Erfindungsgemäß ragen somit nicht nur die elektrischen Anschlüsse der Elektroden in den Bereich der Kavität hinein, sondern größere Bereiche der Elektroden, so daß die Kavität mit Ausnahme der zu Isolationszwecken zwischen den Elektroden erforderlichen Abstände im wesentlichen vollständig abgedeckt ist. Zur Herstellung eines in sich geschlossenen Chipmoduls ist es aufgrund dieser Ausbildungsform lediglich erforderlich, die Bereiche der Elektroden, die in den Bereich der Kavität hineinragen, mit dem Chip zu verbinden. Wegen der vergleichsweise großen Flächen, die hier zur Verfügung stehen, ist dies auf einfache Weise möglich und erhält die Anordnung vor allen Dingen eine hohe Stabilität, so daß auf ein Ausgießen der Kavität mit einem Epoxy-Material, das die Leads und den Chip umschließt, verzichtet werden kann. This object is achieved in that the Electrodes are designed such that they Cover the base of the cavity essentially completely. According to the invention, not only the electrical ones protrude Connections of the electrodes in the area of the cavity into larger areas of the electrodes, so that the Cavity except for the isolation between distances essentially required for the electrodes is completely covered. To make one in itself closed chip module it is because of this Form of training only required the areas of Electrodes that protrude into the area of the cavity with to connect the chip. Because of the comparatively large Areas that are available here, this is on simple way possible and maintains the arrangement above all Things a high stability, so that on pouring out the Cavity with an epoxy material covering the leads and the Chip encloses, can be dispensed with.

Die Verbindung zwischen dem Chip und den Elektroden kann beispielsweise durch eine Epoxy-Kleberschicht erfolgen, die in die Kavität eingebracht wird, bevor der Chip eingesetzt wird. In vorteilhafter Weise wird hierbei der Epoxy-Kleber in Form einer Folie in die Kavität eingelegt, wodurch die Handhabung vereinfacht wird. The connection between the chip and the electrodes can for example by an epoxy adhesive layer, which is placed in the cavity before the chip is used. In this case, the Epoxy adhesive in the form of a film in the cavity inserted, which simplifies handling.

Bei der Herstellung des Chipmoduls ist sicherzustellen, daß die Bondpads des Chips den entsprechenden elektrischen Anschlüssen der Elektroden exakt gegenüberliegen, d. h. die Elektroden müssen positionsgenau an dem Substrat angebracht werden, und in gleicher Weise muß der Chip positionsgenau in die Kavität eingesetzt werden, so daß die Bondpads bzw. an diesen angebrachte Bumps aus einem beispielsweise Gold-Nickel-Material und die elektrischen Anschlüsse der Elektroden einander kontaktieren. Des weiteren muß sichergestellt werden, daß durch den Epoxy-Kleber die elektrische Kontaktierung zwischen den Elektroden und dem Chip nicht beeinträchtigt wird. Hierzu können beispielsweise in der Epoxy-Kleber-Folie entsprechende Durchgangsöffnungen für die Bumps vorgesehen sein. In bevorzugter Weise wird jedoch ein anisotropischer Epoxy- Kleber verwendet und die Kontaktierung der elektrischen Anschlüsse der Elektroden mit den an den Bondpads des Chips vorgesehenen Bumps indirekt durch die leitenden Füllstoffe in dem anisotropisch leitenden Epoxy-Material hergestellt. Hierzu wird der Epoxy-Kleber, nachdem der Chip in die Kavität eingebracht worden ist, unter Temperatur und Druck ausgehärtet. Auf Druck kann hierbei verzichtet werden, wenn ein Epoxy-Kleber verwendet wird, der bei seiner Aushärtung stark schrumpft, so daß die Elektroden mit den Bumps während des Aushärtens durch die Schrumpfkraft des Epoxy-Klebers automatisch aneinander gepreßt werden. When manufacturing the chip module, it must be ensured that that the bond pads of the chip match the corresponding electrical connections of the electrodes are exactly opposite, d. H. the electrodes must be precisely positioned on the substrate be attached, and in the same way the chip be positioned exactly in the cavity, so that the Bond pads or bumps attached to them from one for example gold-nickel material and the electrical Contact the electrode connections with each other. Of further it must be ensured that the epoxy the electrical contact between the electrodes and the chip is not affected. You can do this corresponding in the epoxy adhesive film, for example Through openings for the bumps may be provided. In however, an anisotropic epoxy Used glue and contacting the electrical Connections of the electrodes with the on the bond pads of the Bumps provided indirectly by the conductive chips Fillers in the anisotropically conductive epoxy material manufactured. To do this, the epoxy after the Chip has been inserted into the cavity Temperature and pressure hardened. On pressure can be avoided if an epoxy adhesive is used that shrinks strongly when it cures, so that the Electrodes with the bumps while curing through the Shrinking force of the epoxy automatically against each other be pressed.

Gemäß einer bevorzugten Ausführungsform ist vorgesehen, daß die Elektronen durch eine dünne Metallfolie, welche auf das dielektrische Substrat laminiert ist, gebildet werden. Im übrigen kann die von den Elektroden wegweisende Rückseite des Chips durch ein Vergußmaterial geschützt werden. According to a preferred embodiment, that the electrons through a thin metal foil, which is laminated on the dielectric substrate become. Otherwise, the electrodes groundbreaking back of the chip protected by a potting material become.

Hinsichtlich weiterer vorteilhafter Ausgestaltungen und weiterer Bildungen der Erfindung wird auf die Unteransprüche sowie die nachfolgende Beschreibung eines Ausführungsbeispiels anhand der beiliegenden Zeichnung verwiesen. In der Zeichnung zeigt: With regard to further advantageous configurations and further formations of the invention are based on the Subclaims and the following description of a Embodiment with reference to the accompanying drawings directed. The drawing shows:

Fig. 1 ein Chipmodul gemäß der vorliegenden Erfindung von unten her betrachtet, Fig. 1 considered a chip module according to the present invention from below,

Fig. 2 einen vergrößerten Ausschnitt des Chipmoduls aus Fig. 1 im Bereich der Kavität, Fig. 2 shows an enlarged section of the chip module in FIG. 1 in the region of the cavity,

Fig. 3 den Ausschnitt aus Fig. 2 im Schnitt III-III und Fig. 3 shows the detail of Fig. 2 in section III-III and

Fig. 4 die Darstellung aus Fig. 3, bei welcher der Chip von einem Vergußmaterial eingeschlossen ist. Fig. 4 shows the representation of Fig. 3, in which the chip is enclosed by a potting material.

In den Figuren ist ein Chipmodul 1 gemäß der vorliegenden Erfindung dargestellt. Zu dem Chipmodul 1 gehört ein flächiges Substrat 2 aus einem dielektrischen Material, an dessen Unterseite insgesamt fünf flächige Elektroden 3 vorgesehen sind. In der Darstellung von Fig. 2 ist gut erkennbar, daß die Elektroden 3 mit Abstand zueinander an dem Substrat 2 angeordnet sind, so daß sie gegeneinander elektrisch isoliert sind. Zu dem Chipmodul 1 gehört weiterhin ein Chip 4, der in eine Kavität 5, welche etwa mittig in dem Substrat 2 ausgebildet ist, von der den Elektroden 3 gegenüberliegenden Oberseite des Substrats 2 her eingesetzt ist. A chip module 1 according to the present invention is shown in the figures. The chip module 1 includes a flat substrate 2 made of a dielectric material, on the underside of which a total of five flat electrodes 3 are provided. In the illustration of Fig. 2 can be seen clearly that the electrodes 3 are arranged at a distance from one another on the substrate 2 so that they are insulated from each other. The chip module 1 also includes a chip 4 , which is inserted into a cavity 5 , which is formed approximately centrally in the substrate 2 , from the upper side of the substrate 2 opposite the electrodes 3 .

Wie in den Fig. 1 und 2 gut erkennbar ist, ragen die Elektroden 3 an der Unterseite des Substrats 2 in den Bereich der Kavität 5 hinein, und zwar in der Weise, daß die Kavität 5 mit Ausnahme der zu Isolationszwecken zwischen den Elektroden 3 erforderlichen Abstände im wesentlichen vollständig abgedeckt ist. Die Anordnung ist dabei so getroffen, daß die fünf Bondpads 6 des Chips 4 den elektrischen Anschlüssen der fünf Elektroden 3 genau gegenüberliegen, so daß eine Direktkontaktierung zwischen den elektrischen Anschlüssen der Elektroden und den Bondpads 6 des Chips 4 möglich ist. Wie die Fig. 3 und 4 gut erkennen lassen, erfolgt diese Direktkontaktierung über sogenannte Bumps 7 aus einem Gold-Nickel-Material, die an den Bondpads 6 des Chips 4 angebracht sind. As can be clearly seen in FIGS. 1 and 2, the electrodes 3 protrude on the underside of the substrate 2 into the region of the cavity 5 , specifically in such a way that the cavity 5, with the exception of those required for insulation purposes between the electrodes 3 Distances is essentially completely covered. The arrangement is such that the five bond pads 6 of the chip 4 lie exactly opposite the electrical connections of the five electrodes 3 , so that direct contact between the electrical connections of the electrodes and the bond pads 6 of the chip 4 is possible. As can be clearly seen in FIGS. 3 and 4, this direct contacting takes place via so-called bumps 7 made of a gold-nickel material, which are attached to the bond pads 6 of the chip 4 .

Die Fig. 3 und 4 zeigen weiterhin, daß zwischen dem Chip 4 und den Elektroden 3 eine Epoxy-Kleberschicht 8 vorgesehen ist, über welche die Elektroden 3 und der Chip 4 mechanisch miteinander verbunden sind. In der dargestellten Ausführungsform wird für den Epoxy-Kleber 8 ein anisotropisch leitendes Epoxy-Material verwendet, über dessen elektrisch leitende Füllstoffe auch die Kontaktierung der elektrischen Anschlüsse der Elektroden 3 mit den an den Bondpads 6 des Chips 4 vorgesehenen Bumps 7 auf indirektem Weg erfolgt. Das Chipmodul 1 kann an seiner von den Elektroden 3 wegweisenden Seite durch ein Vergußmaterial 9 geschützt sein, wie es in Fig. 4 gezeigt ist. FIGS. 3 and 4 further show that an epoxy adhesive layer 8 is provided between the chip 4 and the electrode 3, over which the electrode 3 and the chip 4 are mechanically connected to each other. In the embodiment shown, an anisotropically conductive epoxy material is used for the epoxy adhesive 8 , via the electrically conductive fillers of which the electrical connections of the electrodes 3 are also contacted indirectly with the bumps 7 provided on the bond pads 6 of the chip 4 . The chip module 1 can be protected on its side facing away from the electrodes 3 by a potting material 9 , as shown in FIG. 4.

Das erfindungsgemäße Chipmodul läßt sich auf einfache Weise nach dem folgenden Verfahren herstellen:
Zunächst wird das dielektrische Substrat 2 mit der mittigen Kavität 5 hergestellt. Auf die Unterseite des Substrats 2 werden dann die fünf Elektroden 3 beispielsweise in Form einer Metallfolie angebracht, beispielsweise laminiert. Parallel dazu wird der Chip 4 mit den Bumps 7 versehen. The chip module according to the invention can be produced in a simple manner using the following method:
First, the dielectric substrate 2 with the central cavity 5 is produced. The five electrodes 3 are then attached to the underside of the substrate 2 , for example in the form of a metal foil, for example laminated. In parallel, the chip 4 is provided with the bumps 7 .

Anschließend wird in die Kavität 5 des Substrats 2 von dessen Oberseite her der Epoxy-Kleber 8 beispielsweise in Form einer Folie eingebracht, und dann wird der Chip 4 in die Kavität 5 eingesetzt, wobei die Bumps 7 unmittelbar oberhalb der elektrischen Anschlüsse der Elektroden 3 positioniert werden. Die so vorbereitete Anordnung wird fixiert, indem der Epoxy-Kleber 8 unter Druck und Temperatur ausgehärtet wird. Durch die flächige mechanische Verbindung zwischen dem Chip 4 und den Elektroden 3 wird eine sehr stabile Anordnung erzielt, so daß es nicht mehr erforderlich ist, das Chipmodul 1 beispielsweise in ein Epoxy-Material einzugießen. Subsequently, the epoxy adhesive 8, for example in the form of a film, is introduced into the cavity 5 of the substrate 2 from its upper side, and then the chip 4 is inserted into the cavity 5 , the bumps 7 being positioned directly above the electrical connections of the electrodes 3 become. The arrangement prepared in this way is fixed in that the epoxy adhesive 8 is cured under pressure and temperature. The flat mechanical connection between the chip 4 and the electrodes 3 results in a very stable arrangement, so that it is no longer necessary to cast the chip module 1, for example, in an epoxy material.

Claims (11)

1. Chipmodul mit einem dielektrischen Substrat (2), wenigstens einem Chip (4), der in eine Kavität (5) des Substrats (2) eingesetzt ist, und mehreren an dem Substrat (2) angebrachten und gegeneinander elektrisch isolierten flächigen Elektroden (3), deren elektrische Anschlüsse in den Bereich der Kavität (5) hineinragen und mit den Bondpads (6) des Chips (4) nach Art einer Direktkontaktierung verbunden sind, dadurch gekennzeichnet, daß die Elektroden (3) derart ausgebildet sind, daß sie die Grundfläche der Kavität (5) im wesentlichen vollständig abdecken. 1. Chip module with a dielectric substrate ( 2 ), at least one chip ( 4 ) which is inserted into a cavity ( 5 ) of the substrate ( 2 ), and a plurality of flat electrodes ( 3 ) attached to the substrate ( 2 ) and electrically insulated from one another ), whose electrical connections protrude into the region of the cavity ( 5 ) and are connected to the bond pads ( 6 ) of the chip ( 4 ) in the manner of a direct contact, characterized in that the electrodes ( 3 ) are designed such that they cover the base area cover the cavity ( 5 ) essentially completely. 2. Chipmodul nach Anspruch 1, dadurch gekennzeichnet, daß im Bereich der Kavität (5) zwischen dem Chip (4) und den Elektroden (3) eine Epoxy-Kleberschicht (8) vorgesehen ist. 2. Chip module according to claim 1, characterized in that an epoxy adhesive layer ( 8 ) is provided in the region of the cavity ( 5 ) between the chip ( 4 ) and the electrodes ( 3 ). 3. Chipmodul nach Anspruch 2, dadurch gekennzeichnet, daß die Epoxy-Kleberschicht durch eine Epoxy- Kleberfolie (8) gebildet ist. 3. Chip module according to claim 2, characterized in that the epoxy adhesive layer is formed by an epoxy adhesive film ( 8 ). 4. Chipmodul nach Anspruch 2 oder 3, dadurch gekennzeichnet, daß die Epoxy-Kleberfolie (8) aus einem anisotropisch leitenden Epoxy-Material besteht und die elektrische Kontaktierung zwischen an den Bondpads (6) des Chips (4) angebrachten Bumps (7) und den Elektroden (3) indirekt durch die leitenden Füllstoffe in dem anisotropisch leitenden Epoxy-Material erfolgt. 4. Chip module according to claim 2 or 3, characterized in that the epoxy adhesive film ( 8 ) consists of an anisotropically conductive epoxy material and the electrical contact between the bond pads ( 6 ) of the chip ( 4 ) attached bumps ( 7 ) and the electrodes ( 3 ) take place indirectly through the conductive fillers in the anisotropically conductive epoxy material. 5. Chipmodul nach einem der vorherigen Ansprüche, dadurch gekennzeichnet, daß die Elektroden (3) durch eine dünne Metallfolie, welche auf das dielektrische Substrat (2) laminiert ist, gebildet werden. 5. Chip module according to one of the preceding claims, characterized in that the electrodes ( 3 ) are formed by a thin metal foil which is laminated on the dielectric substrate ( 2 ). 6. Chipmodul nach einem der vorherigen Ansprüche, dadurch gekennzeichnet, daß die von den Elektroden (3) wegweisende Rückseite des Chips (4) durch ein Vergußmaterial (9) geschützt ist. 6. Chip module according to one of the preceding claims, characterized in that the rear of the chip ( 4 ), which points away from the electrodes ( 3 ), is protected by a potting material ( 9 ). 7. Verfahren zur Herstellung eines Chipmoduls, insbesondere nach einem der Ansprüche 1 bis 6, bei welchem
ein dielektrisches Substrat (2) mit einer Kavität (5) für einen Chip (4) zur Verfügung gestellt wird,
flächige Elektroden (3) auf einer Hauptfläche des Substrats (2) in der Weise angebracht werden, daß ihre elektrischen Anschlüsse in den Bereich der Kavität (5) des Substrats (2) hineinragen,
ein Chip (4) in die Kavität (5) von der den Elektroden (3) gegenüberliegenden Seite her eingesetzt wird und
die Bondpads (6) des Chips (4) mit den elektrischen Anschlüssen der Elektroden nach Art einer Direktkontaktierung verbunden werden,
dadurch gekennzeichnet, daß
die Elektroden (3) so ausgebildet und an dem Substrat (2) angebracht werden, daß sie die Kavität (5) zumindest im wesentlichen abdecken. 7. A method for producing a chip module, in particular according to one of claims 1 to 6, in which
a dielectric substrate ( 2 ) with a cavity ( 5 ) for a chip ( 4 ) is made available,
flat electrodes ( 3 ) are attached to a main surface of the substrate ( 2 ) in such a way that their electrical connections protrude into the region of the cavity ( 5 ) of the substrate ( 2 ),
a chip ( 4 ) is inserted into the cavity ( 5 ) from the side opposite the electrodes ( 3 ) and
the bond pads ( 6 ) of the chip ( 4 ) are connected to the electrical connections of the electrodes in the manner of a direct contact,
characterized in that
the electrodes ( 3 ) are designed and attached to the substrate ( 2 ) in such a way that they at least substantially cover the cavity ( 5 ). 8. Verfahren nach Anspruch 7, dadurch gekennzeichnet, daß der Chip (4) und die Elektroden (3) durch einen Epoxy-Kleber (8) miteinander verbunden werden. 8. The method according to claim 7, characterized in that the chip ( 4 ) and the electrodes ( 3 ) are connected to one another by an epoxy adhesive ( 8 ). 9. Verfahren nach Anspruch 8, dadurch gekennzeichnet, daß vor der Anbringung des Chips (4) an dem Substrat (2) der Epoxy-Kleber (8) in Form einer Folie in die Kavität (5) von der den Elektroden (3) gegenüberliegenden Seite eingebracht wird. 9. The method according to claim 8, characterized in that before the application of the chip ( 4 ) to the substrate ( 2 ) of the epoxy adhesive ( 8 ) in the form of a film in the cavity ( 5 ) of the electrodes ( 3 ) opposite Side is introduced. 10. Verfahren nach Anspruch 8 oder 9, dadurch gekennzeichnet, daß ein anisotropischer Epoxy-Kleber (8) verwendet wird und die Kontaktierung der elektrischen Anschlüsse der Elektroden (3) mit an den Bondpads (6) des Chips (4) vorgesehenen Bumps (7) indirekt über den Epoxy-Kleber (8) hergestellt wird, indem der Epoxy-Kleber (8) unter Druck und Temperatur ausgehärtet wird. 10. The method according to claim 8 or 9, characterized in that an anisotropic epoxy adhesive ( 8 ) is used and the contacting of the electrical connections of the electrodes ( 3 ) with on the bond pads ( 6 ) of the chip ( 4 ) provided bumps ( 7 ) is produced indirectly via the epoxy adhesive ( 8 ) by curing the epoxy adhesive ( 8 ) under pressure and temperature. 11. Verfahren nach einem der Anspüche 7 bis 10, dadurch gekennzeichnet, daß die von den Elektroden (3) wegweisende Rückseite des Chips (4) mit einem Vergußmaterial eingegossen wird. 11. The method according to any one of claims 7 to 10 , characterized in that the rear of the chip ( 4 ) pointing away from the electrodes ( 3 ) is cast in with a potting material.
DE2002114314 2002-03-28 2002-03-28 Chip module with a dielectric substrate and at least one chip accommodated in a substrate cavity is provided with several electrodes which are shaped so that they almost completely cover the cavity base surface Ceased DE10214314A1 (en)

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
WO2005051059A1 (en) * 2003-11-17 2005-06-02 Siemens Aktiengesellschaft Rough contacts
WO2013034759A1 (en) * 2011-09-08 2013-03-14 Sansystems Electronic chip device and method of manufacturing by coils

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US5255430A (en) * 1992-10-08 1993-10-26 Atmel Corporation Method of assembling a module for a smart card
DE4326816A1 (en) * 1993-08-10 1995-02-16 Giesecke & Devrient Gmbh Electronic module for cards and manufacture of such a module
DE4424396C2 (en) * 1994-07-11 1996-12-12 Ibm Carrier element for installation in chip cards or other data carrier cards
US5975420A (en) * 1995-04-13 1999-11-02 Dai Nippon Printing Co., Ltd. Apparatus and method of manufacturing an integrated circuit (IC) card with a protective IC module

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Publication number Priority date Publication date Assignee Title
US5255430A (en) * 1992-10-08 1993-10-26 Atmel Corporation Method of assembling a module for a smart card
DE4326816A1 (en) * 1993-08-10 1995-02-16 Giesecke & Devrient Gmbh Electronic module for cards and manufacture of such a module
DE4424396C2 (en) * 1994-07-11 1996-12-12 Ibm Carrier element for installation in chip cards or other data carrier cards
US5975420A (en) * 1995-04-13 1999-11-02 Dai Nippon Printing Co., Ltd. Apparatus and method of manufacturing an integrated circuit (IC) card with a protective IC module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005051059A1 (en) * 2003-11-17 2005-06-02 Siemens Aktiengesellschaft Rough contacts
WO2013034759A1 (en) * 2011-09-08 2013-03-14 Sansystems Electronic chip device and method of manufacturing by coils
FR2980015A1 (en) * 2011-09-08 2013-03-15 Sansystems ELECTRONIC DEVICE WITH CHIP AND METHOD FOR MANUFACTURING COILS

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