DE102022116363B3 - Device for generating a high-frequency clock - Google Patents

Abstract

The invention relates to a device 300 for generating a high-frequency clock 303. The device 300 comprises a controller 311, a first FLL or PLL control loop 323, a second FLL or PLL control loop 324 and an input signal 308 which sporadically contains a reference signal as a synchronization signal having. The second FLL or PLL control loop 324 converts the sporadically occurring reference signal into a continuous reference clock 306 with typically the same frequency, period length and phase position. This reference clock 306 is the input signal for the second FLL or PLL control loop 324, which increases the low-frequency but continuous reference clock 306 to a higher-frequency high-frequency clock 303. If the second FLL or PLL control loop 324 is readjusted using the reference signal, the first FLL or PLL control loop 323 is preferably frozen. The second FLL or PLL control loop 324 is only active when the reference clock is readjusted using the reference signal. Otherwise, the second FLL or PLL control loop 324 is preferably frozen and then supplies a constant reference clock 306.

Description

Field of invention

The invention is directed to a device and a method for generating a high-frequency clock as a function of an input signal, which is preferably a LIN data signal on a LIN data bus.

General introduction and state of the art

The frequency, period duration or phase-accurate synchronization of a high-frequency clock of a high-frequency oscillator and a continuous low-frequency reference clock to a reference signal that is permanently present at sporadic time intervals has been known for a very long time, especially from the analog transmission of signals (radio, television).

During FM transmission, a so-called pilot tone is permanently transmitted, which is used by the receiver as a reference for mixing down the difference signal for the stereo transmission.

With the invention of analog color television, a technology was developed in which a so-called burst signal is used to transmit a reference signal that is not permanent but exists regularly and to which the receiver can synchronize. 1 shows the burst signal and part of the other signal progression before and after. The document presented here gives an example WO 1999 055 088 A1 , the WO 1993 010 605 A1 , the US 4,115,811 A and the DE 19 619 509 C1 .

For this purpose, a phase locked loop (PLL) is preferably used, which has a hold mode and an adjustment mode.

Wikipedia defines a PLL as follows: “A phase-locked loop (PLL) is a control loop with a controlled oscillator, the phase of which is tracked to that of an external signal. In phase locked loops, the dependence of the manipulated variable on the control deviation - the phase shift - is periodic. The control can therefore “lock” to different relative phase positions that differ by multiples of 2π (360°). When locked, the frequency of the oscillator is that of the reference signal." (Source: https://de.wikipedia.org/wiki/Phasenregelschleife#: ^~ :text=Ein%20Phasenregelschleife%20%28PLL% 2C%20nach%20english%20phase -locked%20loop%29%20ist, from%20der%20control deviation %20%E2%80%93%20der%20phase shift%20%E2%80%93%20periodically, download: June 6th, 2022).

Typically, a PLL control circuit has an oscillator that generates a clock signal at a clock frequency. This clock frequency depends on the value of a control input signal from the oscillator. If necessary, a clock divider converts the clock signal by dividing it into a comparison clock with a lower comparison clock frequency. A phase detector compares the temporal position of the clock edges of the comparison clock with the temporal position of the edges of an input clock signal of the PLL. The phase position detector therefore compares the phase position of the clock edges of the comparison clock and the clock edges of an input clock signal of the PLL to one another and generates a phase position signal which can preferably assume negative and positive values. A PI controller or another suitable controller then preferably forms the control input signal of the oscillator from the phase position signal. Preferably, the sign of the transfer function of the controller is selected in combination with the sign of the phase position detector so that the device establishes PLL phase synchronism.

As with the CVBS signal, for example, the input signal cannot permanently show the synchronization signal for the clock. For example, it is known that the CVBS signal for teletext data can show a different clock run-in from CVBS line to CVBS line. The document presented here refers to the standard “Enhanced Teletext Specification” EUROPEAN TELECOMMUNICATION STANDARD ETS 300 706, May 1997, EBU/CENELEC/ETSI JTC, DE/JTC-TTEXT-EACEM, in particular “Figure 4: Clock run-in, framing code and timing reference” and to the writing DE 19 619 509 C1 and Infineon Technologies “Preliminary User's Manual TVTEXT PRO SDA 55xx”, Version 1.21 July 99, Chapter 5, with special emphasis on Chapter 5.2.2 “Data Separation”. The number of cycles of the clock run-in of a teletext signal can also vary from CVBS line to CVBS line, deviating from the ideal standard. It therefore makes sense if the PLL a) detects the start of the clock run-in and b) then adjusts the clock very quickly within a few cycles during the clock run-in and c) determines the end of the clock run-in . The following teletext data is RTZ (Return to Zero) data. This means that each data bit has at least one edge. It is preferred that d) the control characteristic of the PI controller of the PLL for the data field is different than for the clock run-in, since the distance between the edges can be twice as large. In addition, the edge direction can change depending on the data. The PLL preferably determines or detects the end of the data field. Preferably, e) ignores the PI controller of the PLL from then on until the beginning of the next clock run-in the values of the phase position signal and then freezes the frequency of the oscillator. This increases the speed of phase and frequency adjustment to the next line clock run-in.

• • Wegen des festgeschriebenen vorgegebenen Zeitregimes lässt sich Beginn und Ende der Synchronisationsphase für den Farbwinkel sehr einfach und sofort von einem einfachen äußeren Detektor feststellen. Dieser schaltet eine PLL für die Erzeugung des Farbsignals zwischen einem Haltemodus und einem Nachstellmodus um.
• • Die initiale Synchronisation der PLL für die Erzeugung des Farbsignals erfolgt beim Einschalten und bei jedem Umschalten auf einen anderen Sender. Dabei spielt es typischerweise für das analoge Farbwinkelsignal keine Rolle, ob während des Synchronisationsvorgangs Informationen verloren gehen oder nicht. Selbst wenn die Synchronisation eine Anzahl von 300 Burst-Impulsen benötigen würde, wäre damit nur ein Halbbild verloren, was der Mensch nicht wahrnehmen würde.
• • Die Störung eines Burst-Signals des Farb-Bursts zur Einstellung des Farbwinkels führt nur zu minimaler Störung der Übertragung, da die Einschwingzeit der PLL für die Erzeugung des Farbsignals hier bevorzugt erheblich größer als die Dauer eines Burst-Signals ist. Damit integriert die PLL für die Erzeugung des Farbsignals über solche temporären Fehler hinweg.

The burst signal of the color burst for adjusting the color angle is transmitted repeatedly exactly after the line synchronization pulse. This form of transmission, together with the color television application field, has the following properties:

• • Because of the fixed time regime, the beginning and end of the synchronization phase for the color angle can be determined very easily and immediately by a simple external detector. This switches a PLL for generating the color signal between a hold mode and an adjustment mode.
• • The initial synchronization of the PLL for generating the color signal occurs when switching on and every time you switch to another transmitter. For the analog color angle signal, it typically doesn't matter whether information is lost or not during the synchronization process. Even if synchronization required a number of 300 burst pulses, only one field would be lost, which humans would not notice.
• • Disturbing a burst signal of the color burst to adjust the color angle only leads to minimal disruption of the transmission, since the settling time of the PLL for generating the color signal is preferably considerably longer than the duration of a burst signal. The PLL thus integrates over such temporary errors to generate the color signal.

The clock run-in of a teletext signal is also transmitted repeatedly in a CVBS signal at a well-defined time interval following the end of the line synchronization pulse of a line signal of a CVBS signal.

• • Wegen des festgeschriebenen vorgegebenen Zeitregimes lassen sich Beginn und Ende der Synchronisationsphase zumindest bei einem idealen FBAS-Signal wieder von einem äußeren Detektor feststellen. Dieser schaltet eine Teletext-PLL (PLL=Phase-Locked-Loop) zur Teletext-Taktextraktion (Englisch: Clock-Recovery) zwischen einem Haltemodus, in dem die Teletext-PLL-Regelschleife der Teletext-PLL eingefroren ist, und einem Nachstellmodus, in dem die Teletext-PLL-Regelschleife der Teletext-PLL die Phasenlage mittels einer Frequenznachstellung des Teletext-PLL-Oszillators nachregelt, um.
• • Die initiale Synchronisation der Teletext-PLL erfolgt beim Einschalten und bei jedem Umschalten auf einen anderen Sender sowie bevorzugt hier mit jeder neuen Bildzeile.
• • Die Störung eines Clock-Run-Ins führt hier zum einem kompletten Datenverlust der in einer Bildzeile übertragenen Daten da die Einschwingzeit der PLL hier bevorzugt erheblich kürzer ist als die Dauer des Teletext-Clock-Run-Ins. Damit integriert die Teletext-PLL nicht über solche temporären Fehler hinweg.

This form of data transmission in a CVBS line, together with the teletext transmission application field, has the following properties:

• • Because of the established time regime, the beginning and end of the synchronization phase can again be determined by an external detector, at least with an ideal CVBS signal. This switches a teletext PLL (PLL=phase-locked loop) for teletext clock extraction (English: clock recovery) between a hold mode, in which the teletext PLL control loop of the teletext PLL is frozen, and an adjustment mode in which the teletext PLL control loop of the teletext PLL adjusts the phase position by means of a frequency adjustment of the teletext PLL oscillator.
• • The initial synchronization of the teletext PLL takes place when switching on and every time you switch to another station and preferably with every new picture line.
• • The disruption of a clock run-in leads to a complete loss of data transmitted in a picture line since the settling time of the PLL is preferably considerably shorter than the duration of the teletext clock run-in. This means that the Teletext PLL does not integrate over such temporary errors.

The situation is similar with digital message transmission in cases where such data losses are also unacceptable and, in particular, where only sporadic data transmission and thus synchronization takes place. 2 shows the synchronization signal for data transmission via LIN bus. There is a requirement that a complete settling has already occurred after the first synchronization field, so that the subsequent data is received error-free. Since the quality of the synchronization signal must be evaluated before the transmission can start, the evaluation of the synchronization signal and thus a possible frequency correction for the reference frequency of the transmission can only be carried out at the end of the synchronization signal but before the start of the data transmission at a time when there is no longer a synchronization signal. This means that the methods described above and the associated devices for the synchronized generation of a high-frequency clock to a reference signal that only occurs sporadically for a short time and serves as a synchronization signal cannot be used, since they actually produce the synchronization signal in parallel with the entire time period for carrying out the readjustment Require high frequency clock as a reference signal.

There are already solutions to meet this requirement, such as: US 6,097,754 , US 2002 / 0 101 884 A1 and US 2005 / 0 024 111 A1 , which work with a fixed high-frequency reference clock and use an adapted, low-frequency clock to decode the input signal or to clock a processor. However, the fixed, high-frequency reference clock is not corrected.

In some slave systems there is a requirement for an accurate (<1%) high-frequency reference clock while at the same time requiring low system costs. The system costs prohibit the use of an appropriate oscillator with the required inherent accuracy. However, such frequency accuracy is usually available in the master and can therefore also be transmitted via the synchronization signal. The solution is therefore sought in a system that can provide a highly accurate, high-frequency reference clock using the synchronization signal and is able to achieve the target accuracy after receiving a maximum of two synchronization signals.

With the solutions mentioned above, this would be possible if the high-frequency clock is a high multiple (>100) of the processor frequency. This property is sometimes very difficult to achieve in a typical semiconductor process if you want to maximize the processor's maximum speed, especially with small processors. There is therefore a lack of a solution in which the high-frequency reference clock can also be the processor clock at the same time and the accuracy requirement can be met with the high-frequency reference clock itself.

EP 1 971 069 A1 To do this, determines a correction signal from the counted duration of the synchronization signal to adjust the high-frequency reference clock. This is then sent to the high-frequency oscillator. The problem with this solution is that the transfer function from the correction signal to the frequency of the high-frequency oscillator is generally both non-linear and is subject to strong scatter from component to component. This means that target accuracy can only be achieved after many synchronization signals. This means the requirement is not met.

From the US 2015 / 0 326 232 A1 An arrangement of two PLLs connected in series is known, with the output of the second PLL being fed back to the input of the first PLL in order to enable cost-effective, low-noise and at the same time highly accurate clock generation. The US 2015 / 0 326 232 A1 However, it does not solve the problem of a reference signal that only occurs sporadically in the input signal of the PLL design.

Task

The task of the proposal presented here is to provide a structure and a method with which a high-precision high-frequency clock of a high-frequency oscillator is available within a very short time using an accurate external, possibly only sporadically occurring reference signal within an input signal, the high-frequency clock preferably being used as System clock of the device can be used.

The reference signal within the input signal should not have to be present permanently, but should only be present temporarily, possibly only rarely. In a special case, for example, this reference signal within the input signal can be the sync field of the LIN communication of a LIN master. Infrequent communication should be sufficient to synchronize the high-precision high-frequency clock of the high-frequency oscillator with the reference signal within the input signal.

This task is solved by the technical teaching of the independent claims. Further refinements may be the subject of subclaims.

Solution to the task

The proposal relates to a device 300 and an associated method for generating a high-frequency clock 303. The device 300 includes a controller 311, a first FLL or PLL control loop 323, a second FLL or PLL control loop 324 and an input signal 308 that sporadically has a reference signal as a synchronization signal.

The special thing about the proposal presented here is that the proposed method provides for the presence of the reference signal in the input signal 308 to be detected, then parameters of this detected reference signal, such as frequency and/or period duration and/or phase position, as valid measured values of these parameters of the reference signal of the input signal 308 and preferably temporarily stored in one or more first memories of the measuring device 509 or the like. The proposed method envisages checking the plausibility of these parameters stored in the first memory or the first memory of the measuring device 509 before further use in order to minimize interference. In the sense of the document presented here, the measured values of the parameters of the reference signal temporarily stored in the first memory or memories should be plausible if they lie within typically predetermined expected value intervals for the corresponding assigned parameters. The proposed method provides, preferably only such plausibility-checked measured values of the detected reference signal from the respective first memory of the measuring device 509 assigned to a respective measured value of the respective parameter in one the second memory of the measuring device 509 assigned to the corresponding valid measured value of this parameter and stored there. The proposed method then envisages generating a reference clock 306 depending on these stored, plausibility-checked and thus validated valid measured values. The values of the parameters of the reference clock 306 generated in this way then correspond in accordance with a relationship that is preferably predefined or set by the controller 300 of the proposed device 300 with the valid measured values 517 of the parameters of one or more of the valid and typically no longer present reference signals in the input signal 308. Since the Valid values of the recorded parameters are preferably buffered in a second memory of the measuring device 509, the generation of the reference clock 306 is also possible if the reference signal or the reference signals are no longer present in the input signal 308. This enables the processing of very rarely present reference signals. The synthesis of the high-frequency clock 303 as a function of the reference clock 306 then completes the method.

The detection of a reference signal can be carried out by a time control based on a start signal, for example a synchronization pulse, a start bit or the like, which postulates the detection of the reference signal when a predetermined or set period of time has elapsed after the reception of a start signal. The detection of a reference signal can also be carried out using a matched filter (optimal filter) or, for example, a continuous wavelet analysis of the input signal with the wavelet of a predetermined, prototype reference signal, for example a clock run-in. These determine that a predetermined signal curve can be observed on the input signal 308 and interpret this signal curve as a reference signal.

If a start signal is used that precedes the reference signal, for example at a predefined time interval, the proposed device can also use the start signal, for example, by means of a suitable matched filter (optimal filter) or, for example, a continuous wavelet analysis of the input signal with the wavelet of a predetermined, prototype Start signal, for example a synchronization pulse or a start code in the form of a predetermined bit or pulse sequence. These determine that a predetermined signal curve can be observed on the input signal 308 and, if necessary, interpret this signal curve as a start signal.

A proposed device 300 corresponds to this method: The second FLL or PLL control loop 324 of the proposed device 300 converts the sporadically occurring reference signal into a continuous reference clock 306 with at least the same frequency, period length and phase position. In many preferred applications, the frequency of the continuous reference clock 306 may also be a multiple of the frequency of the reference signal in the input signal 308. In such preferred applications, the period of the continuous reference clock 306 can also be only a fraction of the period of the reference signal in the input signal 308. This reference clock 306 is the input signal for the second FLL or PLL control circuit 324, which raises the low-frequency but continuous reference clock 306 to a high-frequency clock 303 with a much higher frequency. If the second FLL or PLL control loop 324 is readjusted using the deviation signal from the target value calculation 518, the first FLL or PLL control loop 323 is preferably frozen. The second FLL or PLL control circuit 324 is only active if it readjusts the reference clock 306 with the help of the reference signal that only occurs sporadically in the input signal 308. Otherwise, the second FLL or PLL control loop 324 is preferably frozen and then supplies a constant reference clock 306.

The proposed device 300 can operate the first FLL or PLL control loop 323 as a PLL (phase-locked loop) or as an FLL (frequency-locked loop).

The proposed device 300 can operate the second FLL or PLL control loop 324 as a PLL (phase-locked loop) or as an FLL (frequency-locked loop).

A PLL is generally referred to as a phase locked loop (PLL), which is a control loop with a controlled oscillator whose phase is tracked to that of an external signal.

A FLL is generally referred to as a frequency-locked loop (FLL), which is a control loop with a controlled oscillator whose frequency is tracked to that of an external signal. Since the frequency is the time derivative of the phase, the two control loops can usually be converted into one another.

An input signal has, at least temporarily or sporadically, a low-frequency reference signal that, as a synchronization signal, is the high-frequency signal of a high-frequency oscilla tor should synchronize with regard to phase position and/or frequency and/or period duration.

The basic idea is to carry out this synchronization in two stages.

In a first synchronization stage, the high-frequency clock of a high-frequency oscillator of a first FLL or PLL control loop is synchronized to a permanently available low-frequency reference clock of a reference oscillator. In a second synchronization stage, the low-frequency reference clock of the reference oscillator of a second FLL or PLL control loop synchronizes itself to the reference signal, which is only available sporadically and is temporarily part of the input signal as a synchronization signal.

1. 1. Der zweite FLL- oder PLL-Regelkreis 324 kann das Referenzsignal mittels des eingefrorenen Hochfrequenztakts 303 des ersten FLL- oder PLL-Regelkreises 323 und unter Nutzung der vermessenen Parameter des bereits wieder verschwundenen Referenzsignals des Eingangssignals 308 als Referenztakt 306 rekonstruieren.
2. 2. Der zweite FLL- oder PLL-Regelkreis 324 kann die Abweichung der Parameter des rekonstruierten Referenztakts 306 von den korrespondieren und erfassten Parametern des Referenzsignals ermitteln und die entsprechenden Parameter des Referenztakts 306, beispielsweise die Frequenz des Referenztakts 306 gegenüber der erfassten Frequenz des Referenzsignals, nachregeln.

The special thing about the second FLL or PLL control loop 324 is that the second FLL or PLL control loop 324 measures the sporadically applied reference signal of the input signal 308 in a first phase using the high-frequency clock 303. As long as the high-frequency clock 303 remains constant, the proposed device 303 is then able to do the following things after the second FLL or PLL control circuit 324 or a device part thereof has measured and evaluated the reference signal in the input signal 308, in particular also then when the reference signal is no longer present in the input signal 308:

1. 1. The second FLL or PLL control loop 324 can reconstruct the reference signal using the frozen high-frequency clock 303 of the first FLL or PLL control loop 323 and using the measured parameters of the already disappeared reference signal of the input signal 308 as a reference clock 306.
2. 2. The second FLL or PLL control loop 324 can determine the deviation of the parameters of the reconstructed reference clock 306 from the corresponding and detected parameters of the reference signal and the corresponding parameters of the reference clock 306, for example the frequency of the reference clock 306 compared to the detected frequency of the reference signal, readjust.

1. 1. Der zweite FLL- oder PLL-Regelkreis 324 kann das sporadische Referenzsignal des Eingangssignals 308 in den Zeiten, in denen kein Referenzsignal im Eingangssignal 308 vorhanden ist, rekonstruieren, nachdem der zweite FLL- oder PLL-Regelkreis 324 ein empfangenes Referenzsignal des Eingangssignals 308 bewertet hat, und den niederfrequenten Referenztakt 306 entsprechend den ermittelten Parametern eines oder mehrerer empfangener und gültiger Referenzsignale des Eingangssignals 308 nachregeln, wobei bevorzugt der zweite FLL- oder PLL-Regelkreis 324 den für diese Zeit der Nachregelung des zweiten FLL- oder PLL-Regelkreises 324 eingefrorenen Hochfrequenztakt 303 des ersten FLL- oder PLL-Regelkreis 323 zur Rekonstruktion nutzt. Der zweite FLL- oder PLL-Regelkreis 324 regelt sich dann mit dem Referenztakt 306 auf die erfassten Parameter eines oder mehrerer gültiger Referenzsignale des Eingangssignals 308 ein.
2. 2. Nach Ermittlung der Abweichungen hinsichtlich Frequenz, Periodendauer oder Phasenlage zwischen dem Referenztakt 306 und einem oder mehreren gültigen Referenzsignalen im Eingangssignal 308 kann der zweite FLL- oder PLL-Regelkreis 324 beispielsweise durch Teilung des Hochfrequenztakts 303 in einem Rekonstruktionsoszillator 810 mit einem Teilerverhältnis einen rekonstruiertes Referenzsignal 806 erzeugen. Auf dieses rekonstruierte Referenzsignal 806 kann sich der zweite FLL- oder PLL-Regelkreis 324 dann auch dann einregeln, wenn das Referenzsignal im Eingangssignal 308 nur sporadisch auftritt. Bevorzugt friert die Steuerung 311 den ersten FLL- oder PLL-Regelkreises 324 für die Dauer der Einregelung des zweiten FLL- oder PLL-Regelkreises 324 ein, sodass die Parameter des Hochfrequenztakts 303 wie Frequenz, Periodendauer und Phasenlage für die Dauer des Einfrierens unverändert bleiben. Nach der Einregelung des zweiten FLL- oder PLL-Regelkreises 324 friert bevorzugt die Steuerung 311 den zweiten FLL- oder PLL-Arbeitskreis 324 ein, sodass die Parameter des Referenztakts 306 wie Frequenz, Periodendauer und Phasenlage für die Dauer des Einfrierens von da an unverändert bleiben. Gleichzeitig hebt die Steuerung 311 bevorzugt das Einfrieren des ersten FLL-oder PLL-Regelkreises 323 auf, sodass der erste FLL- oder PLL-Regelkreis 323 den Hochfrequenztakt 303 nun so nachregeln kann, dass die Frequenz oder Periodendauer oder Phasenlage des Hochfrequenztakts 303 dann sich auf Werte einpegelt, die in den gewünschten Verhältnissen relativ zur Frequenz oder Periodendauer oder Phasenlage des Referenztakts 306 und damit zur Frequenz oder Periodendauer oder Phasenlage eines oder mehrerer gültiger Referenzsignale im Eingangssignal 308 liegen .
3. 3. Der erste FLL- oder PLL-Regelkreis 323, der den Hochfrequenztakt 303 erzeugt kann einen Taktteiler 520 aufweisen, der den Hochfrequenztakt 303 zu einem heruntergeteilten Hochfrequenztakt 521 entsprechend einem Teilerverhältnis des Taktteilers 520 herunterteilt. Die Steuervorrichtung 311 oder eine andere geeignete Vorrichtung der vorschlagsgemäßen Vorrichtung 300 kann beispielsweise mittels einer Teilerverhältnisberechnung 1110 die Abweichung zwischen der Frequenz oder der Periodendauer oder der Phasenlage eines oder mehrerer gültiger Referenzsignale im Eingangssignal 308 einerseits und den korrespondierenden Parametern der Frequenz oder Periodendauer oder Phasenlage eines Hilfstakts 1112 andererseits ermitteln. Der Hilfstakt 1112 kann identisch mit dem heruntergeteilten Hochfrequenztakt 521 sein. Der Hilfstakt 1112 steht typischerweise in einem vorgegebenen Teilerverhältnis zum Hochfrequenztakt 303. Bevorzugt erzeugt der erste Teiler 520 ebenfalls diesen Hilfstakt 1112 aus dem Hochfrequenztakt 303. Bevorzugt erzeugt die Teilerverhältnisberechnung 1110 in Abhängigkeit von der ermittelten Abweichung einen neuen Wert für das zukünftige Teilerverhältnis 1111 mit dem der erste Teiler 520 in Zukunft den Hochfrequenztakt 303 zum heruntergeteilten Hochfrequenztakt 521 herunterteilt. Typischerweise regelt der erste FLL- oder PLL-Regelkreis 323 auf diese Weise dann in diesem Fall dann die Frequenz oder Periodendauer oder Phasenlage des Hochfrequenztakts 303. Da der Taktteiler 520 im Gegensatz zu den anderen Stellmöglichkeiten der Oszillatoren eine rein mathematische Beziehung ohne Herstellungstoleranzen darstellt, ist hier eine sofortige Korrektur ohne Einfrieren des ersten FLL- oder PLL-Regelkreises 323 möglich.

This ultimately results in 3 possible solutions:

1. 1. The second FLL or PLL control loop 324 can reconstruct the sporadic reference signal of the input signal 308 at the times when there is no reference signal in the input signal 308 after the second FLL or PLL control loop 324 receives a received reference signal of the input signal 308 has evaluated, and readjust the low-frequency reference clock 306 according to the determined parameters of one or more received and valid reference signals of the input signal 308, the second FLL or PLL control loop 324 preferably being the readjustment of the second FLL or PLL control loop 324 for this time frozen high-frequency clock 303 of the first FLL or PLL control loop 323 is used for reconstruction. The second FLL or PLL control circuit 324 then regulates itself using the reference clock 306 to the recorded parameters of one or more valid reference signals of the input signal 308.
2. 2. After determining the deviations in terms of frequency, period duration or phase position between the reference clock 306 and one or more valid reference signals in the input signal 308, the second FLL or PLL control loop 324 can, for example, by dividing the high-frequency clock 303 in a reconstruction oscillator 810 with a division ratio Generate reference signal 806. The second FLL or PLL control circuit 324 can then adjust to this reconstructed reference signal 806 even if the reference signal in the input signal 308 only occurs sporadically. The controller 311 preferably freezes the first FLL or PLL control loop 324 for the duration of the adjustment of the second FLL or PLL control loop 324, so that the parameters of the high-frequency clock 303 such as frequency, period duration and phase position remain unchanged for the duration of the freezing. After adjusting the second FLL or PLL control loop 324, the controller 311 preferably freezes the second FLL or PLL working circuit 324, so that the parameters of the reference clock 306 such as frequency, period length and phase position remain unchanged for the duration of the freezing from then on . At the same time, the controller 311 preferably cancels the freezing of the first FLL or PLL control loop 323, so that the first FLL or PLL control loop 323 can now readjust the high-frequency clock 303 so that the frequency or period duration or phase position of the high-frequency clock 303 then increases Values are leveled that are in the desired ratios relative to the frequency or period or phase position of the reference clock 306 and thus to the frequency or period or phase position of one or more valid reference signals in the input signal 308.
3. 3. The first FLL or PLL control loop 323, which generates the high-frequency clock 303, may have a clock divider 520, which generates the high-frequency clock frequency clock 303 is divided down to a divided high-frequency clock 521 according to a division ratio of the clock divider 520. The control device 311 or another suitable device of the proposed device 300 can, for example, by means of a divider ratio calculation 1110, determine the deviation between the frequency or the period duration or the phase position of one or more valid reference signals in the input signal 308 on the one hand and the corresponding parameters of the frequency or period duration or phase position of an auxiliary clock 1112 on the other hand determine. The auxiliary clock 1112 may be identical to the divided-down high-frequency clock 521. The auxiliary clock 1112 is typically in a predetermined division ratio to the high-frequency clock 303. Preferably, the first divider 520 also generates this auxiliary clock 1112 from the high-frequency clock 303. The division ratio calculation 1110 preferably generates a new value for the future division ratio 1111 with that of the In the future, the first divider 520 divides the high-frequency clock 303 down to the divided high-frequency clock 521. In this case, the first FLL or PLL control loop 323 typically regulates the frequency or period or phase position of the high-frequency clock 303. Since the clock divider 520, in contrast to the other adjustment options of the oscillators, represents a purely mathematical relationship without manufacturing tolerances An immediate correction is possible here without freezing the first FLL or PLL control loop 323.

So that the reference clock remains as undisturbed as possible during the absence of the synchronization signal, the control of the proposed device, which carries out the proposed method, preferably freezes during times in which the input signal does not have a synchronization signal as a reference signal for the reference oscillator, the second FLL or PLL control loop a. The reference oscillator of the second FLL or PLL control loop thereby works as an unregulated reference oscillator with a constant frequency or period or phase position at times in which the input signal does not have a synchronization signal as a reference signal for the reference oscillator. The first FLL or PLL control loop tracks the frequency and/or period and/or phase of the high-frequency clock of the high-frequency oscillator to the reference clock of the reference oscillator as a reference signal of the first FLL or PLL control.

If a reference signal in the form of a synchronization signal appears in the input signal, variant A of the proposal provides that the control of the proposed device freezes the first FLL or PLL control loop when carrying out the proposed method and then the high-frequency oscillator as operates an unregulated oscillator. The high-frequency oscillator then supplies the high-frequency clock with a constant frequency and period and phase position, which does not differ from the frequency and period and phase position that the high-frequency clock of the high-frequency oscillator had before freezing.

This control of the proposed device can determine this appearance of the reference signal in the form of a synchronization signal in the input signal in various ways or make assumptions.

Firstly, the application that uses the proposed device can have a predeterminable time scheme in which the reference signal always appears in the input signal at predetermined times. The control of the proposed device can then use a timer to determine that a reference signal should now be present in the input signal at a corresponding time and start the synchronization process under the hypothesis of detection of a reference signal.

Secondly, the controller can use suitable means to observe the input signal and detect the announcement of a reference signal by means of a suitable start signal in the input signal. The application that uses the proposed device can also have a predeterminable time scheme in relation to this reference signal, in which the reference signal always appears in the input signal at predetermined times at a known time interval from the start signal after the appearance of the start signal in the input signal.

Thirdly, the controller can use suitable means to observe the input signal and determine the start of a reference signal by means of a suitable reference signal start in the input signal. The application that uses the proposed device can also have a predeterminable time scheme in relation to this reference signal, in which the rest of the reference signal in the input signal is always at predetermined times at a known time interval after the start of the reference signal after the occurrence of the start of the reference signal in the input signal exists long enough for synchronization.

The proposed device, which carries out the proposed method, now uses the constant-frequency high-frequency clock to measure the reference signal that occurs in the input signal, in particular with regard to the frequency and/or period duration and/or the phase position of the reference signal. The proposed device preferably generates, if necessary, a suitable low-frequency auxiliary clock from the high-frequency clock for this measurement of the reference signal.

Preferably, the control of the proposed device or another auxiliary device of the proposed device evaluates the measured values of the reference signal that are the result of this measurement. For example, if the detected frequency and/or the period duration and/or the phase position lies outside a respective expected value interval, then it does not make sense to use this reference signal for synchronization. The control of the proposed device then aborts the synchronization process and unfreezes the first FLL or PLL control loop for the high-frequency oscillator.

However, if the reference signal in the input signal is valid, the control of the proposed device, which carries out the proposed method, then cancels the freezing of the second FLL or PLL control loop that exists in the normal operating state. As a result, the high-frequency oscillator of the first FLL or PLL control loop then supplies a constant high-frequency clock and the low-frequency reference oscillator supplies a regulated low-frequency reference clock.

The proposed device uses the high-frequency clock to determine values of the reference clock of the reference oscillator that correspond to the detected values of the reference signal and compares them. For this purpose, the proposed device preferably generates, if necessary, a suitable low-frequency auxiliary clock from the high-frequency clock for this comparison. The proposed device preferably stores the measured values of the reference signal, so that the second FLL or PLL control loop can have a control constant that is longer than the time duration of the occurrence of the reference signal, which serves as a synchronization signal, in the input signal. The subsequent comparison can concern the frequency and/or period duration and/or the phase of the reference clock compared to the reference signal of the input signal. Depending on the comparison result, the second FLL or PLL control loop regulates the frequency and/or period duration and/or phase of the reference oscillator until the reference oscillator delivers a reference clock that corresponds to the frequency and/or period duration and/or phase position corresponding previously measured values of the frequency or period duration or phase position determined in the reference signal by the proposed device.

As soon as the control of the proposed device determines that the deviations of the reference clock in terms of frequency and/or period duration and/or phase position from the corresponding previously measured values of the frequency and/or period duration and/or phase position determined in the reference signal by the proposed device are smaller in magnitude than predetermined maximum deviation values, the control determines that the regulation has settled. Alternatively, after it has determined that the reference signal was a valid reference signal that is probably suitable for synchronizing the reference oscillator, the controller can also readjust for a certain time using the second FLL or PLL control loop, during which the control thereof It can be assumed that the second FLL or PLL control loop has most likely settled after this time has elapsed. In the sense of the document presented here, this time-controlled termination procedure is functionally equivalent to the measurement-controlled termination procedure for the control by the second FLL or PLL control loop.

As soon as the termination condition is reached in a time-measured value-controlled manner, the control of the proposed device ends the regulation of the reference oscillator and freezes the second FLL or PLL control loop, so that the reference oscillator now operates again as a synchronization signal within the input signal at least until the next occurrence of the reference signal provides a constant and unregulated reference clock. The control then reactivates the regulation of the high-frequency oscillator by means of the first FLL or PLL control loop, so that this high-frequency oscillator then again supplies a high-frequency clock, the frequency and / or period length and / or phase position of which is again the first FLL or PLL control loop depending on the reference clock.

In one variant, the control freezes the first FLL or PLL control loop in the input signal during the measurement of the reference signal, so that the high-frequency clock, which serves as a means for this measurement, is constant during this time of measuring the reference signal and does not change Regulations changed.

The document presented here describes a device for generating a high-frequency clock 303, with a controller 311, a first FLL or PLL control loop 323, a second FLL or PLL control loop 324 and an input signal 308. As part of the input signal 308, a reference signal occurs intermittently and/or sporadically, which is to be used as a synchronization signal for the high-frequency clock 303. The second FLL or PLL control loop 324 generates a reference clock 306 depending on the reference signal when the second FLL or PLL control loop 324 is active. The reference signal serves as the target signal of the second FLL or PLL control loop 324. If the second FLL or PLL control loop 324 is inactive, the second FLL or PLL control loop 324 generates the reference clock 306 independently of the reference signal of the Input signal 308, in which case the second FLL or PLL control loop 324 continues to generate the reference clock 306 with the frequency and the period duration and the phase position with which the second FLL or PLL control loop 324 last generated the reference clock 306 in the last period of time , in which the second FLL or PLL control loop 324 was active. If the second FLL or PLL control loop 324 and the reference clock 306 are inactive, the parameters of the reference clock 306 are essentially frozen. The second FLL or PLL control loop 324 is thus preferably set up to use the reference clock 306 as a target signal of the second FLL or PLL control loop depending on the state of the reference signal to the last active state of the second FLL or PLL control loop 324 324 to generate when the second FLL or PLL control loop 324 is inactive. The first FLL or PLL control loop 323 generates a high-frequency clock 303 depending on the reference clock 306, which serves as a target signal of the first FLL or PLL control loop 323 when the first FLL or PLL control loop 323 is active. The first FLL or PLL control loop 323 generates the high-frequency clock 303 depending on the state of the reference clock 306 to the last active state of the first FLL or PLL control loop 323 as a target signal of the first FLL or PLL control loop 323, if the first FLL or PLL control loop 323 is inactive. The document presented here also describes this state as frozen. The frequency of the high-frequency clock 303 is preferably larger in magnitude than the frequency of the reference clock 306. The period duration of the high-frequency clock 303 is preferably smaller in magnitude than the period duration of the reference clock 306. The controller 311 can use a second activation/inactivation signal 325 of the controller 311 to set the second FLL - or deactivate and activate PLL control loop 324. The proposed device 300 can be in a normal state 400. In particular, in the normal state 400 of the proposed device 300, the controller 311 preferably deactivates the second FLL or PLL control loop 324 by means of a second activation/inactivation signal 325 of the controller 311. The controller 311 can by means of a first activation/inactivation signal 313 of the controller 311 activate or deactivate the first FLL or PLL control loop 323. In the normal state 400 of the proposed device 300, the controller 311 preferably activates the first FLL or PLL control loop 323 by means of the first activation/inactivation signal 313 of the controller 311. In the normal state 400, the controller 311 detects the arrival of the reference signal of the input signal 308. In the normal state 400, the controller 311 can instead expect the arrival of the reference signal of the input signal at a predetermined time based on a starting time, for example characterized by a start signal of the input signal 308, or have it signaled by a device part of the second control circuit 324. The controller 311 and/or device parts of the second FLL or PLL control loop 324 measure the reference signal serving as a synchronizing signal in the input signal 308 in a state 403 of measuring the synchronization signal of the input signal 308 and determine values for parameters of the reference signal serving as a synchronizing signal in the input signal 308. The controller 311 activates the second FLL or PLL control loop 324 and, for example, after such a detection, puts the second FLL or PLL control loop 324 into the state 406 of correcting the frequency or the period duration or the phase position of the reference clock 306, so that this second FLL or PLL control loop 324 tracks the corresponding parameters of the reference clock 306 until these parameters of the reference clock 306 essentially correspond to the determined values for these parameters of the reference signal serving as a synchronous signal in the input signal 308 or values derived therefrom. Essentially this means that the remaining deviations from the rules are smaller in amount than the maximum permissible for the intended application. The controller 311 then deactivates the second FLL or PLL control loop 324 and thus causes the second FLL or PLL control loop 324 to return to the normal state 400 of the proposed device 300 as soon as the values of the corresponding parameters of the reference clock 306 correspond to the determined values for These parameters essentially correspond to the reference signal serving as a synchronizing signal in the input signal 308 or values derived therefrom. Essentially this means that the remaining deviations from the rules are smaller in amount than the maximum permissible for the intended application.

In a first possible refinement of the proposal, the controller 311 or a device part of the second control circuit 324 evaluates the values of the measurement of the reference signal in the input signal 308 and determines an evaluation result. This makes it possible to prevent interference with the reference clock 306 and thus with the radio frequency clock 303. Whether a reference signal is actually a reference signal depends, for example, on the time at which the presence of the reference signal is detected in the input signal 308 and on the measured values of the reference signal, such as frequency, period length and phase position, which must lie in predetermined value intervals. The proposed device 300 only processes the values of those measured values of the parameters of the reference signal that lie in these value intervals and in the correct time periods, for example based on the time after the time at which a start signal was recognized.

In a second possible refinement of the proposal, the controller 311 allows the proposed device 300 to remain in the normal state 400 with an inactivated second FLL or PLL control loop 324 if the evaluation result includes one or more values that are not within a predetermined value interval or not correspond to a default value. This prevents interference with the reference clock 306 and thus the high-frequency clock 303.

In a third possible refinement of the proposal, the reference signal serving as a synchronization signal in the input signal 308 is measured using the high-frequency clock 303 and/or a signal derived from the high-frequency clock 303 and/or a signal associated with the high-frequency clock 303. This has the advantage that no external time reference is necessary.

In a fourth possible refinement of the proposal, the reference clock 306 is measured within the activated second FLL or PLL control loop 324 with the aid of the high-frequency clock 303 and/or a signal derived from the high-frequency clock 303 and/or a signal associated with the high-frequency clock 303. This also has the advantage that no external time reference is necessary.

• • Anzahl der Takte des Referenzsignals im Eingangssignal 308 in einem vorbestimmten Zeitraum und/oder
• • Eingangssignalfrequenz des Referenzsignals im Eingangssignal 308 und/oder
• • zeitliche Dauer eines vollständigen Takts (Periodendauer) des Referenzsignals im Eingangssignal 308 und/oder
• • die Phasenlage des Referenzsignals im Eingangssignal 308 gegenüber einem heruntergeteilten Hochfrequenztakts 521 und/oder,
• • die Phasenlage des Referenzsignals im Eingangssignal 308 gegenüber dem Referenztakt 306 und/oder
• • zeitliche Dauer einer Low- und/oder High-Phase des Takts des Referenzsignals im Eingangssignal 308 und/oder
• • zeitliche Dauer einer bestimmten Anzahl von Takten des E des Referenzsignals im Eingangssignal 308 und/oder
• • zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenzsignals im Eingangssignal 308.

In a fifth possible refinement of the proposal, the values for parameters of the reference signal serving as a synchronization signal in the input signal 308, which device parts of the device determine in the state 403 of measuring the synchronization signal of the input signal 308, include at least one or more values of one or more of the following parameters:

• • Number of clocks of the reference signal in the input signal 308 in a predetermined period of time and/or
• • Input signal frequency of the reference signal in input signal 308 and/or
• • Duration of a complete clock (period duration) of the reference signal in the input signal 308 and/or
• • the phase position of the reference signal in the input signal 308 compared to a divided high-frequency clock 521 and/or,
• • the phase position of the reference signal in the input signal 308 relative to the reference clock 306 and/or
• • Duration of a low and/or high phase of the clock of the reference signal in the input signal 308 and/or
• • Duration of a certain number of clocks of the E of the reference signal in the input signal 308 and/or
• • Duration of a certain number of low and/or high phases of the reference signal in the input signal 308.

In a sixth possible refinement of the proposal, the controller 311 inactivates the first FLL or PLL control loop 323 before activating the second FLL or PLL control loop 324 and inactivates the second FLL or PLL control loop 324 before activating the first FLL - or PLL control rice 323 activated. This avoids interference with the reference clock 306 and the high-frequency clock 303.

In a seventh possible refinement of the proposal, the controller 311 deactivates the first FLL or PLL control loop 323 when the proposed device 300 is in a state 402 to 405 that is not the normal state 400 of the proposed device 300. As a result, the proposed device 300 can only use reference signals that occur sporadically in the input signal 308 as synchronization signals for the reference clock 306.

In an eighth possible refinement of the proposal, the second FLL or PLL control loop 324 includes a low-frequency reference oscillator 505, which generates the reference clock 306 with a reference clock frequency and a reference clock period and a reference clock phase position. In the eighth possible refinement of the proposal, the controller 311 and/or a device part of the second FLL or PLL control loop 324 determine a value of the deviation of the frequency and/or period duration and/or phase position of the reference signal of the input signal 308 from the reference clock frequency and/or from the reference clock period duration and/or from the reference clock phase position of the reference clock 306 of the low-frequency reference oscillator 505. As a result, the proposed device 300 has an actual value that makes it possible to readjust the reference clock 306.

In a ninth possible refinement of the proposal, the second FLL or PLL control loop 324 has a measuring device 509 for measuring the input signal 308. This makes it possible to detect the reference signal in the input signal 308 and determine the parameters of this input signal. For example, the measuring device 509 can store samples of a time section of the input signal 308 in a memory and extract the parameters of interest of the reference signal from the sampled time profile.

In a tenth possible refinement of the proposal, the measuring device 509, as a device part of the second FLL or PLL control circuit 324, detects the arrival of the reference signal of the input signal 308 in the normal state 400 of the proposed device 300 and then signals this arrival of the reference signal of the input signal 308 to the control device 311 in the normal state 400 of the proposed device 300. This enables the start of the proposed method.

In an eleventh possible refinement of the proposal, the measuring device 509, as a device part of the second FLL or PLL control circuit 324, measures the reference signal serving as a synchronizing signal in the input signal 308, in particular in a state 403 of measuring the synchronization signal of the input signal 308. This provides the proposed device 300 Access to the parameters of the reference signal, which are required for the readjustment of the reference clock 306.

In a twelfth possible refinement of the proposal, the measuring device 509, as a device part of the second FLL or PLL control circuit 324, determines valid values 517 for parameters of one or more of the sporadically occurring reference signals in the input signal 308 that serve as synchronous signals. By providing these values, the device according to the proposal has 300 still has setpoints for controlling the reference clock 306 even if the reference signal is no longer present in the input signal 308 when it has already passed. This means that more time is available for regulating the reference clock 306 than the length of the reference signal.

• • Anzahl der Takte des als Synchronsignal dienenden Referenzsignals im Eingangssignal 308, und/oder
• • Eingangssignalfrequenz des Referenzsignals im Eingangssignal 308 und/oder
• • zeitliche Dauer eines vollständigen Takts (Periodendauer) des Referenzsignals im Eingangssignal 308 und/oder
• • die Phasenlage des Referenzsignals im Eingangssignal 308 gegenüber einem heruntergeteilten Hochfrequenztakts 521 und/oder,
• • die Phasenlage des Referenzsignals im Eingangssignal 308 gegenüber dem Referenztakt 306 und/oder
• • zeitliche Dauer einer Low- und/oder High-Phase des Takts des Referenzsignals im Eingangssignal 308 und/oder
• • zeitliche Dauer einer bestimmten Anzahl von Takten des Referenzsignals im Eingangssignal 308 und/oder
• • zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenzsignals im Eingangssignal 308.

In a thirteenth possible refinement of the proposal, the valid values for parameters of the reference signal serving as a synchronizing signal in the input signal 308, which the measuring device 509 determines as part of the device of the second FLL or PLL control loop 324, include at least one or more valid values 517 of one or more of the following Parameter:

• • Number of clocks of the reference signal serving as a synchronizing signal in the input signal 308, and/or
• • Input signal frequency of the reference signal in input signal 308 and/or
• • Duration of a complete clock (period duration) of the reference signal in the input signal 308 and/or
• • the phase position of the reference signal in the input signal 308 compared to a divided high-frequency clock 521 and/or,
• • the phase position of the reference signal in the input signal 308 relative to the reference clock 306 and/or
• • Duration of a low and/or high phase of the clock of the reference signal in the input signal 308 and/or
• • Duration of a certain number of clocks of the reference signal in the input signal 308 and/or
• • Duration of a certain number of low and/or high phases of the reference signal in the input signal 308.

In a fourteenth possible refinement of the proposal, the reference signal serving as a synchronous signal in the input signal 30) has at least two reference signal features, in particular rising and/or falling edges, and the measuring device 509 counts the number of clocks of the high-frequency clock 303 and/or one of the high-frequency clock 303 derived signal and/or a signal associated with the high-frequency clock 303 between the first time of occurrence of a first reference signal feature in the input signal 308 and the second time of occurrence of a second reference signal feature in the input signal 308. In the fourteenth possible refinement of the proposal, the measuring device 509 determines a second count value. The measuring device preferably evaluates this second counted value and outputs this or a value derived therefrom as a valid measured value 517 of a parameter of one or more reference signals in the input signal 308. This then provides the proposed device with a target value for regulating the reference clock 306.

In a fifteenth possible refinement of the proposal, the control device 311 and/or the second FLL or PLL control loop 324 uses this second count value as a valid measurement 517 of the frequency and/or period duration and/or Phase position of the reference signal of the input signal 308. This then provides the second FLL or PLL control loop 324 of the proposed device 300 with a target value for controlling the reference clock 306.

In a sixteenth possible refinement of the proposal, the second FLL or PLL control loop 324 has a reference measuring device 507 for measuring the low-frequency reference clock 306. This enables the proposed device 300 to record an actual value of the reference clock 306 for regulating the same.

In a seventeenth possible refinement of the proposal, the reference measuring device 507, as a device part of the second FLL or PLL control loop 324, determines values for parameters of the low-frequency reference clock 306, in particular the frequency and/or the period duration and/or the phase position of the low-frequency reference clock 306. This is detected the proposed device 300 provides an actual value for regulating the reference clock 306.

In an eighteenth possible refinement of the proposal, the low-frequency reference clock 306 has at least two reference clock features, in particular rising and/or falling edges, and the reference measuring device 507 counts the number of clocks of the high-frequency clock 303 and/or a signal derived from the high-frequency clock 303 and/or a signal associated with the high-frequency clock 303 between the first time of occurrence of a first reference clock feature in the low-frequency reference clock 306 and the second time of occurrence of a second reference clock feature in the low-frequency reference clock 306. In the eighteenth possible refinement of the proposal, the reference measuring device 507 thus determines a third count value. As a result, the proposed device 300 has an actual value of the reference clock 306 for its regulation.

In a nineteenth possible refinement of the proposal, the control device 311 and/or the second FLL or PLL control circuit 324 use this third count value or a value derived therefrom as a reference clock frequency measurement value signal 516 of the reference measurement device 507 for the measurement value 516 of the low-frequency reference clock 306, in particular as a measurement value 516 the frequency and/or period duration of the reference clock 306. As a result, the proposed device 300 uses the actual value of the reference clock 306 to regulate it.

In a twentieth possible refinement of the proposal, the low-frequency reference clock 306 has at least one reference clock feature, in particular rising and/or falling edges, and the reference signal in the input signal 308 has at least one reference signal feature, in particular rising and/or falling edges. In this twentieth possible refinement of the proposal, the reference measuring device 507 counts the number of clocks of the high-frequency clock 303 and/or a signal derived from the high-frequency clock 303 and/or a signal associated with the high-frequency clock 303 between the time of occurrence of a reference clock feature in the low-frequency reference clock 306 and the time at which a reference signal feature occurs in the reference signal of the input signal 308. In this twentieth possible refinement of the proposal, the reference measuring device 507 determines a third count value.

In a twenty-first possible refinement of the proposal, the control device 311 and/or the second FLL or PLL control loop 324 are set up to use this third count value or a value derived therefrom as a reference clock phase position measurement value signal 516 of the reference measuring device 507 for the measured value 516 of the low-frequency reference clock 306, in particular as a measured value 516 of the phase position of the reference clock 306.

In a twenty-second possible refinement of the proposal, the low-frequency reference clock 306 has at least one reference clock feature, in particular rising and/or falling edges, and the divided high-frequency clock 521 has at least one reference high-frequency clock feature, in particular rising and/or falling edges.

In a twenty-third possible refinement of the proposal, the reference measuring device 507 counts the number of clocks of the high-frequency clock 303 and/or a signal derived from the high-frequency clock 303 and/or a signal associated with the high-frequency clock 303 between the time of occurrence of a reference clock feature in the low-frequency reference clock 306 and the time of occurrence of a reference high-frequency clock feature in the divided-down high-frequency clock 521. In this twenty-third possible refinement of the proposal, the reference measuring device 507 determines a third count value in this way.

In a twenty-fourth possible refinement of the proposal, the tax proposal uses direction 311 and/or the second FLL or PLL control loop 324 use this third count value or a value derived therefrom as a reference clock phase position measurement signal 516 of the reference measuring device 507 for the measured value 516 of the low-frequency reference clock 306, in particular as a measured value 516 of the phase position of the reference clock 306.

In a twenty-fifth possible refinement of the proposal, reference signal in input signal 308 has at least one reference signal feature, in particular rising and/or falling edges, and the divided high-frequency clock 521 has at least one reference high-frequency clock feature, in particular rising and/or falling edges.

In a twenty-sixth possible refinement of the proposal, the phase position detector 519 counts the number of clocks of the high-frequency clock 303 and/or a signal derived from the high-frequency clock 303 and/or a signal associated with the high-frequency clock 303 between the time of occurrence of a reference signal feature in the reference signal of the input signal 308 and the time of occurrence of a reference high-frequency clock feature in the divided-down high-frequency clock 521. In this twenty-sixth possible refinement of the proposal, the phase position detector 519 determines a fourth count value in this way.

In a twenty-seventh possible refinement of the proposal, the control device 311 and/or the first FLL or PLL control loop 323 uses this fourth count value or a value derived therefrom as a high-frequency clock phase position measurement signal 516 of the phase position detector 519, in particular as a measured value 519 of the phase position of the high-frequency clock 303.

In a twenty-eighth possible refinement of the proposal, the reference clock 306 has at least one reference clock feature, in particular rising and/or falling edges, and the divided high-frequency clock 521 has at least one reference high-frequency clock feature, in particular rising and/or falling edges.

In a twenty-ninth possible refinement of the proposal, the phase position detector 519 counts the number of clocks of the high-frequency clock 303 and/or a signal derived from the high-frequency clock 303 and/or a signal associated with the high-frequency clock 303 between the time of occurrence of a reference clock feature in the reference clock 306 and the Time of occurrence of a reference high-frequency clock feature in the divided-down high-frequency clock 521. In this twenty-ninth possible refinement of the proposal, the phase position detector 519 determines a fifth count value in this way.

In a thirtieth possible refinement of the proposal, the control device 311 and/or the first FLL or PLL control loop 323 uses this fifth count value or a value derived therefrom as a high-frequency clock phase position measurement signal 516 of the phase position detector 519, in particular as a measured value 519 of the phase position of the high-frequency clock 303.

In a thirty-first possible refinement of the proposal, the second FLL or PLL control loop 324 includes a target value calculation 510. This enables the proposed device 300 to determine the control deviation when regulating the reference clock 306.

In a thirty-second possible refinement of the proposal, the target value calculation 510 determines a deviation 518 between the measured value 516 of the low-frequency reference clock 306 or a value derived therefrom or associated therewith, on the one hand, and from determined valid values 517 for parameters of one or more reference signals of the input signal 308 serving as a synchronous signal, especially in the form of a difference, on the other hand. As a result, the proposed device 300 has a measured value of the control deviation for regulating the reference clock 306.

In a thirty-second possible refinement of the proposal, the frequency and/or the period duration and/or the phase position of the reference clock 306 depends on the deviation 518 and/or a value derived therefrom or related thereto. This closes the control loop of the proposed device 300 for regulating the reference clock 306.

In a thirty-fourth possible refinement of the proposal, the second FLL or PLL control loop 324 includes a second control II 504. The second control II 504 of the proposed device 300 is preferably a PI controller or the like. It ensures that the control error in the control of the reference clock 306 essentially disappears except for a small remainder.

In a thirty-fifth possible refinement of the proposal, the second FLL or PLL control loop 324 has the reference oscillator 505 and the second control II 504 forms depending on the deviation 518 and/or in proportion to this deviation and/or depending on one value derived from it or value associated therewith, a second control signal II 514 of the second control II 504. As a result, the proposed device 300 has a manipulated variable for controlling the reference oscillator 306. In the thirty-fifth possible refinement of the proposal, the reference oscillator 505 forms the reference clock 306 depending on the second control signal II 514.

In a thirty-sixth possible refinement of the proposal, the second regulation forms II 504 depending on a correction value that is a) from the deviation 518 or b) from a value derived therefrom or c) from a value related thereto in cases a) to c) taking into account the trimming curve and/or trimming step size, the second control signal II 514 of the second control II 504. This has the advantage that non-ideal behavior can be taken into account and that the proposed device 300 can be improved by means of calibration steps.

In a thirty-seventh possible refinement of the proposal, the second FLL or PLL control loop 324 has a reconstruction oscillator 810 which emulates the control signal of the input signal 308 at least during the times when it is not available, so that a parameter-like time reference of the proposed device 300 is also available in such times. The parameters can be, for example, the values of the frequency, the period length and the phase position.

In a thirty-eighth possible refinement of the proposal, the reconstruction oscillator 810 generates a reconstructed reference signal 806 depending on the valid values of parameters 517 of one or more reference signals of the input signal 308 detected by the measuring device 509.

In a thirty-ninth possible refinement of the proposal, the reconstruction oscillator 810 preferably generates a reconstructed reference signal 806 from the high-frequency clock 303 as a function of the valid values of parameters 517 of one or more reference signals of the input signal 308 detected by the measuring device 509. The parameters can be for example, the values of the frequency, the period length and the phase position.

In a fortieth possible refinement of the proposal, the reconstruction oscillator 810 includes a further clock divider. This further clock divider preferably generates a reconstructed reference signal 806 from the high-frequency clock 303 by means of a divider ratio associated with this clock divider by clock division of the high-frequency clock 303 in accordance with this divider ratio. This division ratio preferably depends on the valid values of parameters 517 of one or more reference signals of the input signal 308 detected by the measuring device 509 and/or values derived therefrom. In particular, the division ratio can be proportional or inversely proportional to the values of such parameters or, for example, a time integral of such values or their reciprocals or other values derived from these parameters. The parameters can, for example, be the values of the frequency, the period length and the phase position.

In a forty-first possible refinement of the proposal, said reconstruction oscillator 810 generates a frequency-corrected reference signal 906. Said reconstruction oscillator 810 generates the frequency-corrected reference signal 906 preferably as a function of the valid values of parameters 517 of one or more reference signals of the input signal 308 and in, detected by means of the measuring device 509 Dependency on the parameters 516 of the reference clock 306 determined by means of the reference measuring device 507. The parameters can be, for example, the values of the frequency, the period duration and the phase position.

In a forty-second possible refinement of the proposal, the reconstruction oscillator 810 generates a frequency-corrected reference signal depending on the valid values of parameters 517 of one or more reference signals of the input signal 308 detected by means of the measuring device 509 and depending on the parameters 516 of the reference clock 306 determined by means of the reference measuring device 507 906 from the high-frequency clock 303. The parameters can, for example, be the values of the frequency, the period length and the phase position.

In a forty-third possible refinement of the proposal, the reconstruction oscillator 810 includes another clock divider. In this forty-third possible refinement of the proposal, this further clock divider is generated by means of a divider ratio that depends on the valid values of parameters 517 of one or more reference signals of the input signal 308 detected by means of the measuring device 509 and that depends on the parameters 516 of the reference clock 306 determined by means of the reference measuring device 507 depends, by means of a clock division of the high-frequency clock 303 according to the division ratio of the clock divider, the frequency-corrected reference signal 906 from the high-frequency clock 303. The parameters can, for example, be the values of the frequency, the period length and the phase position.

It is then possible to use the reconstruction oscillator 810 to actually produce a frequency-corrected reference signal 906 from the detected valid values of parameters 517 of one or more reference signals of the input signal 308, which the measuring device 509 has detected, and the determined parameters 516 of the reference clock 306, which the reference measuring device 507 has been recorded, to which the second FLL or PLL control loop 324 can then adjust. In the simplest case, the generation takes place by dividing the clock 303 into a further clock divider of the reconstruction oscillator 810 with a division ratio that, for example, the controller 311 derives from detected valid values of parameters 517 of one or more reference signals of the input signal 308 and/or the determined parameters 516 of the reference clock 306 is calculated and set in the clock divider or that the clock divider determines and sets itself from the detected valid values of parameters 517 of one or more reference signals of the input signal 308 and / or the determined parameters 516 of the reference clock 306.

In a forty-fourth possible refinement of the proposal, the second FLL or PLL control loop 324 has a second phase position detector 819 and/or a second frequency difference detector 819 and/or a second period duration difference detector 819. As a result, the proposed device 300 can detect a deviation between the frequency or the period duration or the phase position of the reference clock 306 and the frequency or the period duration or the phase position of the reconstructed reference signal 806 or the frequency-corrected reference signal 906.

In a forty-fifth possible refinement of the proposal, the second phase position detector 819 therefore compares the reconstructed reference signal 806 or the frequency-corrected reference signal 906 with the reference clock 306 and/or the second frequency difference detector 819 compares the reconstructed reference signal 806 or the frequency-corrected reference signal 906 with the reference clock 306 and/or the second period duration difference detector 819, the reconstructed reference signal 806 or the frequency-corrected reference signal 906 with the reference clock 306. In this forty-fifth possible refinement of the proposal, the second phase position detector 819, depending on the result of this comparison, generates a deviation signal of the phase position detector 819 for the deviation of the phase position between the reconstructed reference signal 806 or the frequency-corrected reference signal 906 on the one hand and the reference clock 306 on the other hand. Alternatively, in this forty-fifth possible refinement of the proposal, the second frequency difference detector 819, depending on the result of this comparison, generates a deviation signal of the frequency difference detector 819 for the deviation of the frequency between the reconstructed reference signal 806 or the frequency-corrected reference signal 906 on the one hand and the reference clock 306 on the other hand. Alternatively, in this forty-fifth possible refinement of the proposal, the second period duration difference detector 819, depending on the result of this comparison, generates a deviation signal of the period duration difference detector 819 for the deviation of the period duration between the reconstructed reference signal 806 or the frequency-corrected reference signal 906 on the one hand and the reference clock 306 on the other hand.

In a forty-sixth possible refinement of the proposal, the frequency and/or the period duration and/or the phase position of the reference clock 306 then depends on the value of the deviation signal 818 and/or a value derived therefrom or related thereto.

In a forty-seventh possible refinement of the proposal, the second control II 504 generates the second control signal II 514 depending on the value of the deviation signal 818 and/or in proportional dependence on the value of the deviation signal 818 and/or on a value derived therefrom or a value associated therewith and forms the reference clock 306 depending on the second control signal II 514.

In a forty-eighth possible refinement of the proposal, the second control II 504 forms the second control signal II 514 depending on a) a correction value that is dependent on the value of the deviation signal 818 or b) on a value derived therefrom or c) on a value associated therewith cases a) to c) taking into account the trimming curve and/or trimming step size.

In a forty-ninth possible refinement of the proposal, the second control II 504 leaves the second control signal II 514 at an unchanged value as long as the control device 311 signals the second second control II 504 by means of a second activation/inactivation signal 325 that the second FLL or PLL -Control circuit 324 is in the inactive state should. This thus enables the second FLL or PLL control loop 324 to be deactivated.

In a fiftieth possible refinement of the proposal, the first FLL or PLL control loop 323 includes one of the high-frequency oscillators 502 that generates the high-frequency clock 303.

In a fifty-first possible refinement of the proposal, the first FLL or PLL control loop 323 includes a first clock divider 520. In the fifty-first possible refinement of the proposal, the first clock divider 520 divides the high-frequency clock 303 of the high-frequency oscillator 502 into a divided-down high-frequency clock 521 according to a first divider ratio of the first clock divider 520. As a result, the first FLL or PLL control circuit 323 has an actual signal that it can use for comparison with the reference clock 306 for controlling the high-frequency clock 303.

In a fifty-second possible refinement of the proposal, the first FLL or PLL control loop 323 includes a phase position detector 519 and/or a frequency difference detector 519 and/or a period difference detector 519 of the first FLL or PLL control loop 323, so that the proposed device 300 determines the phase position and / or can detect the frequency deviation of the high-frequency clock 303 and use it to control the high-frequency clock 303. The document presented here typically refers to the phase position detector 519 and the frequency difference detector 519 and the period duration difference detector 519 collectively with the common term phase position detector 519 to simplify the description.

In a fifty-third possible refinement of the proposal, the phase position detector 519 of the first FLL or PLL control loop 323 detects a phase difference and / or a frequency difference and / or a period length difference between the reference clock 306 and the one divided down high-frequency clock 521 as a measured value and forms a measured value depending on this Measured value is a high-frequency clock frequency measured value signal 522 that represents this measured value or a value derived therefrom. As a result, the proposed device 300 is able to determine the current deviation of the current frequency and/or period length and/or phase position of the high-frequency clock 303 from the target value of the reference clock 306 and to use it for the control of the high-frequency clock 303.

In a fifty-fourth possible refinement of the proposal, the first FLL or PLL control loop 323 includes a first control I 502 of the first FLL or PLL control loop 323.

In a fifty-fifth possible refinement of the proposal, the first control I 501 forms a first control signal I 515 of the first control I 501 depending on the high-frequency clock frequency measured value signal 522. In this fifty-fifth possible refinement of the proposal, the high-frequency oscillator 502 forms the high-frequency clock 303 at least temporarily as a function of this first control signal I 515 of the first control I 501.

In a fifty-sixth possible refinement of the proposal, the first control II 501 is set up to leave the first control signal I 515 at an unchanged value as long as the control device 311 signals the first control II 501 by means of a first activation/inactivation signal 313 that the first FLL or PLL control loop 323 should be in the inactive state.

In a fifty-seventh possible refinement of the proposal, the first control I 501 no longer leaves the first control signal I 515 at an unchanged value and regulates the high-frequency clock 303 by means of this first control signal I 515 when the control 311 of the first control I 501 by means of a first activation / Inactivation signal 313 signals that the first FLL or PLL control loop 323 should be in the active state. As a result, the proposed device 300 can minimize interference with the measurements of the second FLL or PLL control loop 324, which uses the high-frequency clock 303 for measurements, since each of the measurements, even if they take place at different times within a correction phase, essentially contains a high-frequency clock 303 with the same parameters such as frequency and/or period length and/or phase position.

In a fifty-eighth possible refinement of the proposal, the first control I 501 leaves the first control signal I 515 at an unchanged value until the appearance of a reference clock feature, in particular a rising or falling edge, in the reference clock 306. In the fifty-eighth possible refinement of the proposal, with the appearance of a reference clock feature, in particular the rising or falling edge, in the reference clock 306, the first control I 501 sets the first divider 520 and / or the first control signal I 515 to a predetermined value and forces from there to the first control signal I 515 is no longer at an unchanged value. As a result, the proposed device 300 can regulate the high-frequency clock 303 by the first FLL or Reactivate PLL control loop 323 if it was previously deactivated.

In a fifty-ninth possible refinement of the proposal, the controller 311 detects the duration of a certain number of clocks of the reference clock 306 of the reference oscillator 505 by means of the high-frequency clock 303 and by means of means 507 for measuring the reference clock 306. In this fifty-ninth possible refinement of the proposal, the controller 311 corrects the Frequency and/or period duration and/or phase position of the reference clock 306 of the reference oscillator 505 depending on the determined deviation, in particular proportional to the determined deviation, and records the duration of a certain number of clocks of the reference clock 306 of the reference oscillator 505 again until the frequency and/or or period duration and/or phase position of the reference clock 306 of the reference oscillator 505 reaches the target value of the frequency or the period duration or the phase position of the reference clock 306 of the reference oscillator 505.

In a sixtieth possible refinement of the proposal, the controller 311 freezes the first FLL or PLL control loop 323 with the arrival of the reference signal of the input signal 308 and thus deactivates the first FLL or PLL control loop 323, so that the high-frequency clock 303 of the high-frequency, adjustable Oscillator 502 or the first FLL or PLL control loop 323 does not change its frequency and / or period and / or phase position, in particular for the duration that the reference signal of the input signal 308 is present.

In a sixty-first possible refinement of the proposal, the proposed device 300 does not carry out the reactivation of the first FLL or PLL control loop 323 after an inactivation of the first FLL or PLL control loop 323 immediately after the temporal end of the occurrence of a reference signal as a synchronization signal in the Input signal 308 to carry out. In the sixty-first possible refinement of the proposal, the proposed device 300 instead reactivates the first FLL or PLL control loop 323 only at the time end of a remaining data frame following the reference signal in the input signal 308 or only at the time end of a reference signal in the associated data message following the input signal 308, a data communication that is transmitted by means of the input signal 308. In the sixty-first possible refinement of the proposal, the proposed device 300 thus delays the reactivation of the first FLL or PLL control loop 323 until the end of communication. As a result, the compensation processes are less likely to disrupt data communication.

In a sixty-second possible refinement of the proposal, if the proposed device 300 is not in the normal state 400 and then the controller 311 detects the arrival of a further additional reference signal in the input signal 308, the proposed device 300 jumps back to the normal state 400, since then possibly the last reference signal was not a reference signal, but the proposed device 300 had just incorrectly interpreted this signal as such a reference signal. This avoids interference with the regulation of the high-frequency clock 303.

In a sixty-third possible refinement of the proposal, the proposed device 300 has means 510 for detecting the successful completion of the correction 406 of the frequency and/or phase position and/or the period duration of the reference clock 306. In the sixty-third possible refinement of the proposal, the proposed device 300 signals, in particular their control 311 to a higher-level system that the frequency and/or the phase position and/or period duration of the reference clock 306 has been reached. This enables the higher-level system to recognize that data communication is now possible, at least with regard to the timely sampling of the data signal on the input signal 308.

In a sixty-fourth possible refinement of the proposal, the proposed device 300 changes after the successful completion of the correction 406 of the frequency and/or period duration and/or phase position of the reference clock 306 and after reaching the frequency and/or period duration and/or the phase position of the Reference clock 306 into a “fine correction mode”. The fine correction mode of the proposed device 300 differs from a normal mode that the device assumes during initial synchronization, for example after a system start of the proposed device 300, in that the device carries out the corrections of the second FLL or PLL control loop 324 or of the reference oscillator 505 only by a certain number of trimming step widths or by a certain frequency change or period change or phase change of the reference clock 306 of the second FLL or PLL control loop 324 and / or the reference oscillator 504 or is limited to this, in particular to a trimming step or the smallest possible change in the frequency change or period change or phase change of the reference clock 306 of the second FLL or PLL control loop 324 and/or the reference oscillator 504. In addition, when leaving the normal state 400, the device then allows the first FLL or PLL control loop 324 to be deactivated due to the previous completion of the transient process of the first FLL or PLL control loop 324 and the limitation of the frequency change and/or period duration change and/or or phase change is omitted.

In a sixty-fifth possible refinement of the proposal, the proposed device 300 includes non-volatile memory. The controller 311 of the proposed device 300 particularly preferably has this non-volatile memory. The proposed device 300 and/or the controller 311 of the proposed device 300 and/or another suitable partial device of the proposed device 300 preferably store the determined values for the frequency correction and/or period duration correction and/or phase correction of the reference clock 306 in the non-volatile memory after completion the correction 406 of the frequency or period duration or the phase position of the reference clock 306 or immediately before decommissioning the proposed device 300.

In a sixty-sixth possible refinement of the proposal, the proposed device 300 and/or the controller 311 of the proposed device 300 and/or another suitable partial device of the proposed device 300 read the values for the frequency correction and/or the period duration correction and/or determined during commissioning Phase correction of the reference clock 306 from the non-volatile memory and use these values for the frequency correction and/or the period duration correction and/or phase correction and/or phase correction of the reference clock 306.

In a sixty-seventh possible refinement of the proposal, the second FLL or PLL control loop 324 has a phase position detector 819 and/or a frequency difference detector 819 and/or period duration difference detector 819. In the immediately following paragraphs, the document presented here sometimes refers to the phase position detector 819 and the frequency difference detector 819 and the period duration difference detector 819 as just the phase position detector 819 in order to increase the comprehensibility of the text. The second FLL or PLL control loop 324, in the sixty-seventh possible refinement of the proposal, has a clock divider 1024, a reference clock 306, a reconstruction oscillator 810 and a measuring device 509. In the sixty-seventh possible refinement of the proposal, the measuring device 509 records measured values 517 of the parameters of one or more sporadically occurring reference signals in an input signal 308, these parameters typically being the frequency and/or the period length and/or the phase position of one or more several sporadically occurring reference signals in an input signal 308. In the sixty-seventh possible refinement of the proposal, the reconstruction oscillator 810 generates a reconstructed reference signal 806 depending on the recorded measured values 517 of the frequency and/or the period duration and/or the phase position of one or more reference signals of the input signal 308. This dependence of the reconstructed reference signal 806 is preferred in such a way that the values of essential parameters of the reference clock 306 match the corresponding values of the corresponding essential parameters of one or more reference signals in the input signal 308 or have a fixed numerical ratio to them. These parameters are preferably the respective frequency and/or phase position and/or period duration. In the sixty-seventh possible refinement of the proposal, the clock divider 1024 of the second FLL or PLL control loop 324 divides the reference clock 306 into a divided reference clock 1025 according to a divider ratio of the clock divider 1024 of the second FLL or PLL control loop 324. The phase position detector 819 compares the value of the parameter of the frequency or the phase position or the period duration of the reconstructed reference signal 806 on the one hand with the value of the corresponding parameter of the frequency or the phase position or the period duration of the divided reference clock 1025 and forms according to the value of the Comparison result a value of the deviation signal 1018 of the phase position detector 819. In the sixty-seventh possible refinement of the proposal, the second control II 504) forms the value of a second control signal II 514 depending on the value of the deviation signal 1018. The reference oscillator 505 then preferably forms depending on that Value of the second control signal II 514 the reference clock 306.

In the sixty-seventh possible refinement of the proposal, the measuring device 509 detects measured values of the parameters of one or more sporadically occurring reference signals in the input signal 308, evaluates these for plausibility and passes them on as valid measured values 517 of parameters of one or more sporadically occurring valid reference signals in the input signal 308 . The reconstruction oscillator 810 then generates a reconstructed reference signal 806 depending on these recorded valid measured values 517 of the frequency and/or the period duration and/or the phase position of one or more valid reference signals of the input signal 308.

In the sixty-eighth possible refinement of the proposal regarding a device for generating a high-frequency clock 303, the device has a controller 311, a first FLL or PLL control loop 323, a fixed-frequency reference clock oscillator 1101, an input signal 308, a divider ratio calculation 1110 and a measuring device 509. The first FLL or PLL control loop 323 has a first divider 520. A reference signal occurs intermittently and/or sporadically as part of the input signal 308 in the sixty-eighth possible refinement of the proposal. The fixed-frequency reference clock oscillator 1101 typically generates a reference clock 306 in the sixty-eighth possible refinement of the proposal. The frequency of the high-frequency clock 303 is typically larger in magnitude than the frequency of the reference clock 306 in the sixty-eighth possible refinement of the proposal. The period duration of the high-frequency clock 303 is in the sixty-eighth possible Refinement of the suggestion is typically smaller in magnitude than the period duration of the reference clock 306. In the sixty-eighth possible refinement of the suggestion, the measuring device 509 measures one or more of the reference signals occurring sporadically in the input signal 308 in a state 403 of measuring parameters of the reference signals of the input signal 308 and preferably determines corresponding measured values of the frequency and/or the period duration and/or the phase position of one or more reference signals in the input signal 308. If necessary, the measuring device 509 evaluates these determined measured values in the sixty-eighth possible refinement of the proposal. Here, the proposed device preferably checks whether the measured values lie in previously known and/or predetermined and/or stored measured value intervals. If these determined measured values lie in previously known and/or predefined and/or stored measured value intervals, then these measured values are valid measured values and the one reference signal or the several reference signals from which these measured values originate are valid reference signals. The first divider 520 divides a high-frequency clock 303 with a divider ratio to the frequency of a divided-down high-frequency clock 521 in the sixty-eighth possible refinement of the proposal. The first divider 520 preferably divides in parallel a high-frequency clock 303 according to a second divider ratio to an auxiliary clock 1112 of the first divider 520. The auxiliary clock 1112 can optionally be identical to the divided down high-frequency clock 521. In the sixty-eighth possible refinement of the proposal, the divider ratio calculation 1110 preferably uses the auxiliary clock 1112 to determine a measured value of the frequency and/or the period duration and/or the phase position of this auxiliary clock 1112. In the sixty-eighth possible refinement of the proposal, the divider ratio calculation 1110 preferably receives the measured value 517 of the Frequency and/or the period duration and/or the phase position of one or more reference signals in the input signal 308 from the measuring device 509. In the sixty-eighth possible refinement of the proposal, the divider ratio calculation 1110 compares the measured values 517 of the frequency or period duration of one or more reference signals of the input signal 308 with the Measured values of the frequency and/or the period duration of this auxiliary clock 1112 and determines a ratio value from this. The ratio value preferably reflects the ratio and/or the difference between the measured values 517 of the frequency or period duration or phase position of one or more valid reference signals of the input signal 308 and the measured values of the frequency and/or the period duration and/or phase position of this auxiliary clock 1112 or one derived therefrom Value reflected. Preferably, in the sixty-eighth possible refinement of the proposal, the divider ratio calculation 1110 changes the target divider ratio 1111 of the first divider 520 depending on the value of the deviation between a predetermined ratio value 1113 and the ratio value.

In the sixty-ninth possible refinement of the proposal regarding a device for generating a high-frequency clock 303, the measuring device 509 measures one or more of the reference signals appearing sporadically in the input signal 308 and evaluates these as “valid” or “invalid” reference signals in a state 403 of measuring parameters the reference signals of the input signal 308. In the sixty-ninth possible refinement of the proposal regarding a device for generating a high-frequency clock 303, the measuring device 509 determines valid measured values 517 from the measured values of the valid reference signals while excluding the invalid reference signals. These valid measured values 517 are typically measured values for parameters of one or more reference signals in the input signal 308. These parameters are typically the frequency and/or the period length and/or the phase position of one or more reference signals of the input signal and values that are determined using these valid measured values. In the sixty-ninth possible refinement of the proposal, the divider ratio calculation 1110 receives the currently valid measured value 517 of the frequency and/or the period length and/or the phase position of one or more references reference signals in the input signal 308 typically from the measuring device 509. In the sixty-ninth possible refinement of the proposal, the divider ratio calculation 1110 compares the valid measured values 517 of the frequency and / or period duration and / or phase position of one or more reference signals of the input signal 308 with the corresponding measured values of the frequency and /or the period duration and/or phase position of this auxiliary clock 1112. In the sixty-ninth possible refinement of the proposal, the divider ratio calculation 1110 determines from the valid measured values a ratio value which is the ratio and/or the difference between the measured values 517 of the frequency or period duration or phase position of an or several valid reference signals of the input signal 308 and the measured values of the frequency and / or the period duration and / or phase position of this auxiliary clock 1112 or a value derived therefrom.

In the seventieth possible refinement of the proposal, the corresponding method includes generating a reconstructed reference signal 806 depending on the captured valid measured values 517 of the frequency and/or the period duration and/or the phase position of one or more reference signals of the input signal 308, in particular by a reconstruction oscillator 810 The reconstruction oscillator 810 preferably generates the reconstructed reference signal 806 from the high-frequency clock 303 by dividing the high-frequency clock 303 down to the reconstructed reference signal 806 depending on the acquired valid measured values 517. In parallel, the proposed method includes dividing the reference clock 306 into a divided reference clock 1025 according to a division ratio by a clock divider 1024 of the second FLL or PLL control loop 324. Furthermore, the proposed method includes comparing the value of the parameter of the frequency or the Phase position or the period duration of the reconstructed reference signal 806 on the one hand with the value of the corresponding parameter of the frequency or the phase position or the period duration of the divided reference clock 1025 on the other hand, by a phase position detector 819 or a frequency difference detector 819 or a period duration difference detector 819 and the formation of a Value of a deviation signal 1018 corresponding to the value of the comparison result. In addition, the proposed method includes forming the value of a second control signal II 514 as a function of the value of the deviation signal 1018, for example by a second control II 504, and forming the reference clock 306 as a function of the value of the second control signal II 514, in particular by a Reference oscillator 505.

In the seventieth possible refinement of the proposal, the method comprises, in deviation from the description immediately above, generating the reconstructed reference signal 806 depending exclusively on detected valid measured values 517 of the frequency and/or the period duration and/or the phase position of one or more reference signals of the input signal 308, in particular by a reconstruction oscillator 810.

In the seventy-first possible refinement of the proposal, the method for generating a high-frequency clock 303 includes generating a substantially fixed-frequency reference clock 306, in particular by a fixed-frequency reference clock oscillator 1101. In this case, the frequency of the high-frequency clock 303 is typically greater in magnitude than the frequency of the reference clock 306 or the The period duration of the high-frequency clock 303 is typically smaller in magnitude than the period duration of the reference clock 306.

In the seventy-second possible refinement of the proposal, the method includes detecting the values of parameters of one or more of the reference signals occurring sporadically in the input signal 308 in a state 403 of measuring parameters of the reference signals of the input signal 308, in particular by a measuring device 509, the parameters being the Frequency and / or the period and / or the phase position can include.

In the seventy-second possible refinement of the proposal, the method includes evaluating the detected values of the parameters of one or more of the reference signals occurring sporadically in the input signal 308 in the state 403 of measuring parameters of the reference signals of the input signal 308, in particular by the measuring device 509.

In the seventy-third possible refinement of the proposal, the method includes the determination of measured values 517 for parameters of one or more reference signals in the input signal 308 on the basis of determined and evaluated values of the parameters of one or more of the reference signals occurring sporadically in the input signal 308, in particular by the measuring device 509, where the parameters can include the frequency and/or the period and/or the phase position. In the seventy-second possible refinement of the proposal, the method includes dividing the high-frequency clock 303 with a divider ratio to the frequency and/or the period of a divided-down high-frequency clock 521, in particular by a first divider 520. In the seventy-second possible version refinement of the proposal, the method includes dividing the high-frequency clock 303 according to a second division ratio to an auxiliary clock 1112, in particular by the first divider 520. In the seventy-second possible refinement of the proposal, the method includes determining a measured value of the frequency and / or the period length and / or the phase position of this auxiliary clock 1112, in particular by a divider ratio calculation 1110. In the seventy-second possible refinement of the proposal, the method includes comparing the determined measured values 517 of the frequency and/or period duration and/or phase position of one or more reference signals of the input signal 308 with the corresponding measured values the frequency and/or the period duration and/or phase position of this auxiliary clock 1112, in particular by the divider ratio calculation 1110. In the seventy-second possible refinement of the proposal, the method includes the determination of a ratio value which is the ratio and/or the difference between the measured values 517 of the frequency and/or period duration and/or phase position of one or more reference signals of the input signal 308 on the one hand and the corresponding measured values of the frequency and/or the period duration and/or phase position of this auxiliary clock 1112 or a value derived therefrom on the other hand, by the divider ratio calculation 1110. In the seventy-second possible refinement of the proposal, changing the target division ratio 1111 of the first divider (520), in particular through the division ratio calculation 1110, depending on the value of the deviation between a predetermined ratio value 1113 and the ratio value, completes the method by way of example.

In the seventy-third possible refinement of the proposal for a device for generating a high-frequency clock 303, the measuring device 509 measures and possibly evaluates one or more of the valid reference signals occurring sporadically in the input signal 308 in a state 403 of measuring parameters of the reference signals of the input signal 308. The measuring device 509 preferably determines valid measured values 517 for parameters of one or more reference signals in the input signal 308. In parallel, the divider ratio calculation 1110 preferably receives the valid measured value 517 of the frequency and/or the period duration and/or the phase position of one or more reference signals in the input signal 308 from the measuring device 509 .Typically, the divider ratio calculation 1110 In the seventy-third possible refinement of the proposal compares the valid measured values 517 of the frequency and/or period duration and/or phase shift of one or more reference signals of the input signal 308 with the respective corresponding measured values of the frequency and/or period duration and/or phase shift of this auxiliary clock 1112 and uses it to determine a ratio value which is the ratio and/or the difference between the valid measured values 517 of the frequency or period duration or phase position of one or more valid reference signals of the input signal 308 and the measured values of the frequency and/or the period duration and/or phase position this auxiliary clock 1112 or a value derived from it.

List of characters

• 1 shows a PAL burst signal from the prior art according to: https://www.ni.com/de-de/innovations/white-papers/06/analog-video-101.html
• 2 shows a LIN Sync Field, source: https://www.ni.com/de-de/innovations/whitepapers/06/analog-video-101.html Regarding the description of the 1 and 2 The document presented here refers to the contents of the 1 and 2 cited prior art.
• 3 shows schematically and simplified a proposed device 300 in its basic structure
• 4 shows simplified and schematically the sequence of the proposed method in a first variant.
• 5 shows schematically and simplified a proposed device 300, the execution of the first FLL or PLL control loop 323 and the second FLL or PLL control loop 324 being more detailed than in 3 is.
• 6 equals to 4 except for the different activity of the first FLL or PLL control loop 323.
• 7 largely corresponds to that 5 , where m is different from 5 the reference oscillator 505 the 5 here in the 7 is split into an adjustable second clock divider 702 and a non-adjustable reference oscillator 701.
• 8th largely corresponds to that 5 , where in contrast to 5 a reconstruction oscillator 810 and second phase position detector 819 or a second frequency difference detector 819 or a second period difference detector 819 the reference measuring device 507 of 5 and the target value calculation 510 of 5 substitute.
• 9 largely corresponds to that 5 , whereby the proposed device 300 of 9 now a comparator instead 910, which preferably includes the value of the deviation between the measured values of the frequency and/or the period duration and/or the phase position of the reference clock frequency measured value signal 516 or reference clock period duration measured value signal 516 or of the reference clock phase position measured value signal 516 on the one hand and the valid measured values 517 of the frequency or the period duration or on the other hand, the phase position of one or more of the last valid reference signals in the input signal 308 is determined and a comparison result is generated in the form of a comparison result signal 918.
• 10 represents a simplification of the technical teaching of the 9 wherein a reconstruction oscillator 810 generates the reference signal as a continuous reconstructed reference signal 806 as a continuous reconstructed reference signal 806 as a function of the detected valid measured values of the frequency and/or the period duration and/or the phase position of one or more valid reference signals of the input signal 308 8th generated.
• 11 shows a particularly simple version of a proposed device 300, wherein a fixed-frequency reference clock oscillator 1101 generates the reference clock 306.

Description of the characters

Figure 1

1 shows a PAL burst signal from the prior art according to: https://www.ni.com/de-de/innovations/white-papers/06/analog-video-101.html

Regarding the description of the 1 The document presented here refers to the content of the 1 cited prior art.

Figure 2

2 shows a LIN Sync Field, source: https://www.ni.com/de-de/innovations/whitepapers/06/analog-video-101.html

Regarding the description of the 2 The document presented here refers to the content of the 2 cited prior art.

Figure 3

3 shows schematically and simplified a proposed device 300 in its basic structure.

The input signal 308 includes, at least at times, a reference signal that is intended to serve as a synchronization signal for the high-frequency clock 303. The reference signal is therefore typically only available sporadically in the input signal 308. The input signal 308 typically only includes said one reference signal sporadically in time. Therefore, synchronizing the high-frequency clock 303 to the reference signal is not so easy. The basic idea of the method and the device presented here is therefore to first use a second FLL and PLL control loop 324 to obtain a continuous reference clock 306 from the sporadic reference signal, the frequency and period duration and phase position of which correspond as closely as possible to the frequency and period duration and phase position of the reference signal of the input signal 308 matches. Only in a second step does a first FLL and PLL control circuit 323 synchronize with the reference clock 306 and generate a high-frequency clock 303. The first FLL or PLL control circuit 323 is designed so that the frequency of the high-frequency clock 303 corresponds to a first Divider ratio is above the frequency of the reference clock 306 in amount or that the period duration of the high-frequency clock 303 is below the period duration of the reference clock 306 in accordance with a first divider ratio. The second FLL or PLL control circuit 324 therefore generates a low-frequency continuous reference clock 306 from the low-frequency and only sporadically occurring reference signal of the input signal 308. The first FLL or PLL control circuit 323 therefore generates a continuous high-frequency clock 306 from the low-frequency continuous reference clock 306. Since the reference signal in the input signal 308 typically only occurs sporadically, the second FLL or PLL control loop 324 is typically frozen when no reference signal is present at the input signal 308. If there is no reference signal at the input signal 308, a device part of the second FLL or PLL control loop 324 preferably signals to the controller 311 via reference signal signaling 326 whether a reference signal is detected in the input signal 308 or not. The controller 311 inactivates or activates the second FLL or PLL control loop 324 by means of a respective second activation/inactivation signal 325 or independently, depending on the reference signal signaling 326 and the other states that the device parts of the proposed device 300 are currently in of this, the first FLL or PLL control loop 323 by means of a respective first activation/inactivation signal 313. An inactivated or frozen second control loop 324 is to be understood here as meaning that the inactivated second FLL or PLL control loop 324 has the last adjusted frequency and period length and phase position of the reference clock 306 does not change, i.e. preferably keeps it constant. If the second FLL or PLL control loop 324 detects the presence of a reference signal in the input signal 308 or if the second FLL or PLL control loop 324 or the controller 311 assumes this due to the timing of a previously detected start signal in the input signal 308, they activate Controller 311 or the second FLL or PLL control circuit 324 regulates the reference clock 306 by the second FLL or PLL control circuit 324. The second FLL or PLL control circuit now preferably uses the high-frequency clock 303 as a time reference for measuring the reference signal in the input signal 308 .It has been shown that it is optimal if the regulation of the high-frequency clock 303 is stopped by the first FLL and PLL control circuit 323 for the duration of the activation of the control of the reference clock 306 by the second FLL or PLL control circuit 324 and the frequency and period duration and the phase position of the high-frequency clock 303 remain constant and unchanged for the duration of the inactivation of the control of the high-frequency clock 303 by the first FLL or PLL control loop 323. As soon as the second FLL or PLL control loop 324 determines that the frequency and/or period duration and/or phase of the reference clock 306 corresponds again to the frequency and/or period duration and/or phase position of the last detected reference signal of the input signal 308, the controller 311 freezes preferably turns on the second control loop 324 again and thus deactivates its control of the reference clock 306. As a result, the frequency and period duration and phase position of the reference clock 306 are constant again. The controller 311 then activates the first FLL or PLL control loop 323 again, whereby it adjusts the frequency and period duration and phase position of the high-frequency clock 303 to the new frequency and phase position of the reference clock 306. The proposed device 300 remains in this state until the next reference signal appears in the input signal 308.

If a reference signal appears too early or in an unexpected place, the controller 311 assumes an error. Typically, the proposed device 300 ignores this reference signal. If necessary, the proposed device 300 also, if possible, aborts an already running readjustment of the reference clock 306 in order to prevent something worse from happening.

Depending on how far the readjustment of the reference clock has progressed, the proposed device 300 may wait with a reactivation of the first FLL or PLL control loop 323 until the reference clock 306 is readjusted by the second FLL or PLL control loop on the basis of a subsequent new valid reference signal in input signal 308 was successful. Until that point, the controller 311 of the proposed device 300 typically keeps the frequency and period length and phase position of the high-frequency clock 303 constant. Thus, by evaluating the validity of the reference signals in the input signal 308 detected by the second FLL or PLL control loop 324, the proposed device is able to minimize the influence of disturbed reference signals in the input signal 308 and to maintain emergency operation.

This stability in turn makes it possible to use the high-frequency clock 303 for the control and the measuring devices of the first FLL or PLL control loop 323 and the second FLL or PLL control loop 324 and to assign the digital circuits of these device parts to the proposed device 300 with the high-frequency clock clock.

Figure 4

4 shows simplified and schematically the sequence of the proposed method in a first variant.

In the normal state and normal operation 400 of the proposed device 300, the first FLL or PLL control loop 323 is preferably active. This means that the first control I 501 is preferably active and that the first FLL or PLL control loop 323 readjusts the high-frequency clock 303 depending on the reference clock 306. In the normal state and normal operation 400 of the proposed device 300, the second FLL or PLL control loop 324 is preferably inactive. This means that the second control II 504 is preferably active and that the second FLL or PLL control circuit 324 does not readjust the reference clock 306, but rather at the last set frequency of the reference clock 306 and/or the last set period duration of the reference clock 306 and/or or the last set phase position of the reference clock 306 remains constant.

The proposed device 300 repeatedly checks in a checking state 401 whether the detection of a reference signal in the form of a synchronization signal of the input signal 308 takes place, for example, by device parts of the proposed device, in particular by device parts of the second FLL or PLL control circuit 324.

If the proposed device does not detect any detection of a reference signal in the input signal 308, the proposed device 300 typically returns to the normal state 400 of the proposed device 300.

If the proposed device 300 detects something that could be a reference signal in the input signal 308 or something that could announce a reference signal, the proposed device 300 typically switches to a state 402 of measuring the reference signal serving as a synchronization signal in the input signal 308. For example The proposed device 300 can detect a start signal in the input signal, which announces a reference signal. The proposed device 300 then typically only enters the state 402 of measuring the reference signal serving as a synchronization signal in the input signal 308 with a predetermined time delay if the time interval between the start signal and the synchronization signal, which is to serve as a reference signal for the reference clock 306, is sufficient accuracy is known.

• • Die Anzahl der Takte des Referenzsignals im Eingangssignal 308 in einem vorbestimmten Zeitraum, wobei die vorschlagsgemäße Vorrichtung 300 den vorbestimmten Zeitraum bevorzugt durch Zählung einer vorbestimmten Anzahl an Takten des Hochfrequenztakts 303 ermittelt.
• • Die Frequenz und/oder Periodendauer des Referenzsignals im Eingangssignal 308, wobei die vorschlagsgemäße Vorrichtung 300 die Periodendauer des Referenzsignals bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer eines Halbtakts oder eines Takts oder einer vorgegebenen Anzahl von Takten des Referenzsignals im Eingangssignal 308 ermittelt und ggf. zur Frequenzermittlung den Kehrwert bildet oder dergleichen Berechnung durchführt.
• • Die Phasenlage des Referenzsignals im Eingangssignal 308 gegenüber dem Referenztakt 303, wobei die vorschlagsgemäße Vorrichtung 300 beispielsweise mittels ihrer Steuerung 311 oder eines Zählers die Phasenlage des Referenzsignals bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 beginnend mit einer Flanke des Referenzsignals im Eingangssignal 308 und endend mit einer korrespondierenden Flanke des Referenztakts 306 ermittelt.
• • Die Phasenlage des Referenzsignals im Eingangssignal 308 gegenüber dem heruntergeteilten Hochfrequenztakt 521, wobei die vorschlagsgemäße Vorrichtung 300 beispielsweise mittels ihrer Steuerung 311 oder eines Zählers die Phasenlage des Referenzsignals bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 beginnend mit einer Flanke des Referenzsignals im Eingangssignal 308 und endend mit einer korrespondierenden Flanke des heruntergeteilten Hochfrequenztakts 521 ermittelt.
• • Die zeitliche Dauer eines vollständigen Takts (Periodendauer) des Referenzsignals im Eingangssignal 308, wobei die vorschlagsgemäße Vorrichtung 300 die Dauer eines vollständigen Takts (Periodendauer) des Referenzsignals im Eingangssignal 308 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer eines vollständigen Takts des Referenzsignals im Eingangssignal 308 ermittelt.
• • Die zeitliche Dauer einer Low- und/oder High-Phase des Takts des Referenzsignals im Eingangssignal 308, wobei di e vorschlagsgemäße Vorrichtung 300 die Dauer einer Low- und/oder High-Phase des Takts des Referenzsignals im Eingangssignal 308 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer einer Low- und/oder High-Phase des Takts des Referenzsignals im Eingangssignal 308 ermittelt.
• • Die zeitliche Dauer einer bestimmten Anzahl von Takten des Referenzsignals im Eingangssignal 308, wobei die vorschlagsgemäße Vorrichtung 300 die Dauer einer bestimmten Anzahl von Takten des Referenzsignals im Eingangssignal 308 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer einer bestimmten Anzahl von Takten des Referenzsignals im Eingangssignal 308 ermittelt.
• • Die zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenzsignals im Eingangssignal 308, wobei die vorschlagsgemäße Vorrichtung 300 die zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenzsignals im Eingangssignal 308 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenzsignals im Eingangssignal 308 ermittelt.

Otherwise, the proposed device 300 can also track the signal curve of the input signal 308 and, based on a characteristic signal curve, conclude that a synchronization signal is present in the input signal 308. In the state 402 of measuring the reference signal serving as a synchronization signal in the input signal 308, the proposed device 300 and/or its device parts, for example device parts of the second control circuit 324, typically detects one or more important parameters of the reference signal in the input signal 308, preferably using the high-frequency clock 303. The values for parameters of the reference signal serving as a synchronization signal in the input signal 308, which determine device parts of the proposed device 300 in the state 402 of measuring the synchronization signal of the input signal 308, preferably include at least one or more values of one or more of the following parameters:

• • The number of cycles of the reference signal in the input signal 308 in a predetermined period of time, the proposed device 300 preferably determining the predetermined period of time by counting a predetermined number of cycles of the high-frequency clock 303.
• • The frequency and/or period duration of the reference signal in the input signal 308, the proposed device 300 preferably determining the period duration of the reference signal by counting the number of cycles of the high-frequency clock 303 over the time duration of a half cycle or a cycle or a predetermined number of cycles of the reference signal Input signal 308 is determined and, if necessary, forms the reciprocal to determine the frequency or carries out a similar calculation.
• • The phase position of the reference signal in the input signal 308 relative to the reference clock 303, the proposed device 300, for example by means of its controller 311 or a counter, determining the phase position of the reference signal preferably by counting the number of clocks of the high-frequency clock 303 starting with an edge of the reference signal in the input signal 308 and ending with a corresponding edge of the reference clock 306 is determined.
• • The phase position of the reference signal in the input signal 308 compared to the divided high-frequency clock 521, the proposed device 300, for example by means of its controller 311 or a counter, determining the phase position of the reference signal preferably by counting the number of clocks of the high-frequency clock 303 starting with an edge of the reference signal in the input signal 308 and ending with a corresponding edge of the divided down high-frequency clock 521 is determined.
• • The time duration of a complete clock (period duration) of the reference signal in the input signal 308, the proposed device 300 determining the duration of a complete clock (period duration) of the reference signal in the input signal 308 preferably by counting the number of clocks of the high-frequency clock 303 over the time duration of a complete one Clock of the reference signal in the input signal 308 is determined.
• • The time duration of a low and/or high phase of the clock of the reference signal in the input signal 308, the proposed device 300 preferably determining the duration of a low and/or high phase of the clock of the reference signal in the input signal 308 by counting the number on clocks of the high-frequency clock 303 over the time duration of a low and / or high phase of the clock of the reference signal in the input signal 308.
• • The time duration of a certain number of clocks of the reference signal in the input signal 308, the proposed device 300 determining the duration of a certain number of clocks of the reference signal in the input signal 308 preferably by counting the number of clocks of the high-frequency clock 303 over the time duration of a certain number of Clocking of the reference signal in the input signal 308 is determined.
• • The time duration of a certain number of low and/or high phases of the reference signal in the input signal 308, the proposed device 300 determining the time duration of a certain number of low and/or high phases the high phases of the reference signal in the input signal 308 are preferably determined by counting the number of clocks of the high-frequency clock 303 over the time duration of a certain number of low and / or high phases of the reference signal in the input signal 308.

The proposed device 300 preferably keeps the first FLL and PLL control loop 324 inactive in this state 402 of measuring the synchronization signal of the input signal 308, so that the frequency and/or the period duration and/or the phase position of the high-frequency clock 303 is constantly frozen. The remaining device parts of the proposed device 300 can therefore use the high-frequency clock 303 in this state 402 as a time reference, which is an essential idea according to the proposal.

After the proposed device 300 has processed the state 402 of measuring the synchronization signal of the input signal 308 and has made all essential measurements, it preferably switches to the state 403 of evaluating the synchronization signal of the input signal 308. The processing of this state 403 is intended to prevent supposed reference signals , which are either not reference signals or are disturbed reference signals, can influence and thus disrupt the reference clock 306 and thus the high-frequency clock 303. Very particularly preferably, the proposed device 300 or device parts of the proposed device 300, for example the controller 311, examine the measured values of the reference signal of the input signal 308 determined in the previous state 402 for plausibility. For example, the reference signal in the input signal 308 should have a frequency and/or a clock period with a period length that is each within a respective expected value interval for these parameters.

Depending on this evaluation in the previous state 403, the proposed device 300 or a corresponding sub-device of the proposed device 300, for example the controller 311, decides as part of a decision 404 whether the synchronization signal of the input signal 308 is valid and whether the synchronization signal of the input signal 308 and the parameters extracted from it are likely to be suitable or not for the readjustment of the reference clock 306. If this is not the case, the proposed device 300 preferably returns to the normal state, i.e. does not readjust the reference clock 306 and activates the first FLL or PLL control loop 323 again when it returns to the normal state. In this case, the proposed device 300 or one of its sub-devices, for example its controller 311, preferably does not activate the second FLL or PLL control circuit 324, since the probably incorrect parameters could otherwise lead to a disruption in the reference clock 306 and thus in the high-frequency clock 303 .

• • Die Anzahl der Takte des Referenztakts 306 in einem vorbestimmten Zeitraum, wobei die vorschlagsgemäße Vorrichtung 300 den vorbestimmten Zeitraum bevorzugt durch Zählung einer vorbestimmten Anzahl an Takten des Hochfrequenztakts 303 ermittelt.
• • Die Frequenz und/oder Periodendauer des Referenztakts 306, wobei die vorschlagsgemäße Vorrichtung 300 die Periodendauer des Referenztakts 306 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer eines Halbtakts oder eines Takts oder einer vorgegebenen Anzahl von Takten Referenztakts 306 ermittelt und ggf. zur Frequenzermittlung den Kehrwert bildet oder dergleichen Berechnung durchführt.
• • Die Phasenlage des Referenztakts 306 gegenüber dem heruntergeteilten Hochfrequenztakts 521, wobei die vorschlagsgemäße Vorrichtung 300 die Phasenlage des Referenztakts 306 bevorzugt beginnend mit einer Flanke des heruntergeteilten Hochfrequenztakts 521 und endend mit der korrespondierenden Flanke des Referenztakts 506 oder beginnend mit einer Flanke des Referenztakts 506 und endend mit der korrespondierenden Flanke des heruntergeteilten Hochfrequenztakts 521 durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 ermittelt.
• • Die Phasenlage des Referenztakts 306 gegenüber dem Referenzsignal im Eingangssignal 308, wobei die vorschlagsgemäße Vorrichtung 300 die Phasenlage des Referenztakts 306 bevorzugt beginnend mit einer Flanke des Referenzsignals im Eingangssignal 308 und endend mit der korrespondierenden Flanke des Referenztakts 506 oder beginnend mit einer Flanke des Referenztakts 506 und endend mit der korrespondierenden Flanke dem Referenzsignals im Eingangssignal 308 durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 ermittelt.
• • Die zeitliche Dauer eines vollständigen Takts des Referenztakts 306, wobei die vorschlagsgemäße Vorrichtung 300 die Dauer eines vollständigen Takts des Referenztakts 306 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer eines vollständigen Takts des Referenztakts 306 ermittelt.
• • Die zeitliche Dauer einer Low- und/oder High-Phase des Takts des Referenztakts 306, wobei die vorschlagsgemäße Vorrichtung 300 die Dauer einer Low- und/oder High-Phase des Takts des Referenztakts 306bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer einer Low- und/oder High-Phase des Takts des Referenztakts 306 ermittelt.
• • Die zeitliche Dauer einer bestimmten Anzahl von Takten Referenztakts 306, wobei die vorschlagsgemäße Vorrichtung 300 die Dauer einer bestimmten Anzahl von Takten des Referenztakts 306 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer einer bestimmten Anzahl von Takten des Referenztakts 306 ermittelt.
• • Die zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenztakts 306, wobei die vorschlagsgemäße Vorrichtung 300 die zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenztakts 306 bevorzugt durch Zählung der Anzahl an Takten des Hochfrequenztakts 303 über die zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenztakts 306 ermittelt.

However, if the synchronization signal of the input signal 308 is valid and the synchronization signal of the input signal 308 and the parameters extracted from it are likely to be suitable for the readjustment of the reference clock 306, the proposed device 300 typically changes to the state 405 of calculating the target value of the frequency and the Measuring the frequency of the reference clock 306 or the calculation of the target value of the period duration and the measurement of the period duration of the reference clock 306 or the calculation of the target value of the phase position and the measurement of the phase position of the reference clock 306. In the state 405 of the calculation of the target value of the frequency, Period duration and/or phase position and the measurement of the frequency, period duration and/or phase position of the reference clock 306, the proposed device 300 preferably detects one of the following parameters of the reference clock 306:

• • The number of cycles of the reference clock 306 in a predetermined period of time, the proposed device 300 preferably determining the predetermined period of time by counting a predetermined number of cycles of the high-frequency clock 303.
• • The frequency and/or period duration of the reference clock 306, wherein the proposed device 300 preferably determines the period duration of the reference clock 306 by counting the number of clocks of the high-frequency clock 303 over the time duration of a half-cycle or a clock or a predetermined number of clocks of the reference clock 306 and If necessary, the reciprocal value is formed to determine the frequency or a similar calculation is carried out.
• • The phase position of the reference clock 306 relative to the divided-down high-frequency clock 521, the proposed device 300 preferably changing the phase position of the reference clock 306 starting with an edge of the divided-down high-frequency clock 521 and ending with the corresponding edge of the reference clock 506 or starting with an edge of the reference clock 506 and ending with the corresponding edge of the divided down high-frequency clock 521 by counting the number of clocks of the high-frequency clock 303.
• • The phase position of the reference clock 306 relative to the reference signal in the input signal 308, the proposed device 300 preferably setting the phase position of the reference clock 306 starting with an edge of the reference signal in the input signal 308 and ending with the corresponding edge of the reference clock 506 or starting with an edge of the reference clock 506 and ending with the corresponding edge of the reference signal in the input signal 308 is determined by counting the number of clocks of the high-frequency clock 303.
• • The time duration of a complete clock of the reference clock 306, wherein the proposed device 300 preferably determines the duration of a complete clock of the reference clock 306 by counting the number of clocks of the high-frequency clock 303 over the time duration of a complete clock of the reference clock 306.
• • The temporal duration of a low and/or high phase of the clock of the reference clock 306, wherein the proposed device 300 determines the duration of a low and/or high phase of the clock of the reference clock 306 preferably by counting the number of clocks of the high-frequency clock 303 the duration of a low and/or high phase of the clock of the reference clock 306 is determined.
• • The time duration of a specific number of cycles of the reference clock 306, wherein the proposed device 300 determines the duration of a specific number of cycles of the reference clock 306 preferably by counting the number of cycles of the high-frequency clock 303 over the time duration of a specific number of cycles of the reference clock 306 .
• • The time duration of a certain number of low and/or high phases of the reference clock 306, wherein the proposed device 300 determines the time duration of a certain number of low and/or high phases of the reference clock 306 preferably by counting the number of clocks of the high-frequency clock 303 is determined over the time duration of a certain number of low and / or high phases of the reference clock 306.

Here, the proposed device 300 then has a measured value 317 of the reference signal in the input signal 308 and a measured value of the reference clock 306. The proposed device 300 then changes to the state 406 of correcting the frequency and/or the period duration and/or the phase position of the reference clock 306 . Preferably, the proposed device 300 in this state 406 determines the deviation between the measured value 317 of the reference signal in the input signal 308 and the measured value of the reference clock 306. For this purpose, for example, the proposed device 300 in this state 406 preferably forms the difference between the measured value 317 of the reference signal in Input signal 308 minus the measured value of the reference clock 306. The reverse difference formation is possible. Preferably, in this state 406 of the proposed device 300, the proposed device 300 then corrects the reference clock 306 depending on the determined deviation.

For example, the proposed device 300 can determine the deviation of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal 308 from the frequency and/or period duration and/or phase position of the reference clock 306 and then the frequency depending on the determined deviation or period duration or phase position of the reference clock 306 by a correction. Preferably the correction depends proportionally on the deviation. For example, if the course of the trimming curve of the frequency or the period duration or the phase position of the reference oscillator 305, which generates the reference clock 306, is known, the proposed device 300 can correct the frequency or the period duration or the phase position of the reference clock 306 directly Carry out calculations taking into account the trimming curve or trimming step size. The proposed device 300 preferably carries out the correction of the frequency or the period duration or the phase position of the reference clock 306 not in one step, but step by step. After each correction, the proposed device 300 checks in a test step 407 whether the value of the frequency or the period duration or the phase position of the reference clock 306 is in a permissible frequency value interval around the frequency target value for the frequency of the reference clock 306 or in a permissible phase position value interval around the Phase position target value for the phase position of the reference clock 306 is lying around. The frequency target value typically corresponds to the frequency of the reference signal of the input signal 308 or a value derived therefrom. The period duration target value typically corresponds to the period duration of the reference signal of the input signal 308 or a value derived therefrom. The phase position target value typically corresponds to the phase position of the reference signal of the input signal 308 or a value derived therefrom. If the frequency of the reference clock 306 is not within a permissible frequency value interval around the frequency target value for the frequency of the reference clock 306 or if the period duration of the reference is If the clock 306 is not in a permissible period duration value interval around the period duration target value for the period duration of the reference clock 306 or if the phase position of the reference clock 306 is not in a permissible phase position value interval around the phase position target value for the phase position of the reference clock 306, the proposed device repeats the state 406 of the Correction of the frequency or the period duration or the phase position of the reference clock 306 and the subsequent control measurement of the frequency or the period duration or the phase position of the reference clock 306. However, if the frequency of the reference clock 306 is in a permissible frequency value interval around the frequency target value for the frequency of the reference clock 306 or the period duration of the reference clock 306 is in a permissible period duration value interval around the period duration target value for the period duration of the reference clock 306 or the phase position of the reference clock 306 is however in a permissible phase position value interval around the phase position target value for the phase position of the reference clock 306 , the proposed device 300 deactivates the second FLL or PLL control loop 324 and then preferably subsequently activates the first FLL or PLL control loop 323, so that the reference clock 306 is then frozen to a specific frequency and a specific period length and a specific phase position and the high-frequency clock 303 is controlled by the first FLL or PLL control loop depending on the reference clock 306. The proposed device 300 then preferably switches back to the normal state 400.

Figure 5

5 shows schematically and simplified a proposed device.

The document presented here further explains the device using the 3 .

An input signal 308 has, at least temporarily or sporadically, a reference signal that, as a synchronization signal, is intended to synchronize the high-frequency signal 303 of a high-frequency oscillator 502 with regard to phase position and/or period duration and/or frequency.

The proposed device 300 includes a first FLL or PLL control loop 323 (502, 303, 520, 521, 519, 522, 501, 515, 502), which generates the high-frequency clock 303 as a function of a low-frequency reference clock 306. The proposed device 300 can operate the first FLL or PLL control loop 323 as a PLL (phase-locked loop) or as an FLL (frequency-locked loop).

The proposed device 300 includes a second FLL or PLL control loop 324 (505, 306, 507, 516, 518, 504, 514, 505), which generates the reference clock 306 as a function of the reference signal within an input signal 308. The proposed device 300 can operate the second FLL or PLL control loop as a PLL (phase-locked loop) or as an FLL (frequency-locked loop).

The proposed device 300 provides a high-frequency oscillator 502 in the first FLL or PLL control loop 323 and a low-frequency reference oscillator 505 in the second FLL or PLL control loop 324.

The high-frequency oscillator 502 generates the high-frequency clock 303 in the first FLL or PLL control loop 323 with a frequency that depends on the value of a first control signal I 515 of a first control I 501. The first control I 501 therefore controls the high-frequency oscillator 502 by means of the first control signal I 515. The first control I 501 is preferably a PI controller or a PID controller or the like. The first control I 501 therefore preferably controls the frequency and/or the period duration and/or the phase position of the high-frequency clock 303 of the high-frequency oscillator 502 by means of the first control signal I 515. A first clock divider 520 divides the high-frequency clock 303 of the high-frequency oscillator 502 into a divided high-frequency clock 521 down according to a first division ratio, which can also be 1. The frequency of the divided-down high-frequency clock 521 is therefore typically smaller than the frequency of the high-frequency clock 303 of the high-frequency oscillator 502. The period duration of the divided-down high-frequency clock 521 is therefore typically greater than the period duration of the high-frequency clock 303 of the high-frequency oscillator 502. The division ratio can also be a non-integer. However, this is less preferred. In the steady state, the frequency of the divided down high-frequency clock 521 preferably corresponds essentially to the frequency of the reference clock 306. In the steady state, the period duration of the divided down high-frequency clock 521 preferably corresponds essentially to the period duration of the reference clock 306. A phase position detector 519 of the first control loop compares the frequency and/or Period duration and/or the phase position of the reference clock 306 with the frequency or period duration or phase position of the divided high-frequency clock 521 and forms a high-frequency clock frequency measured value signal 522 of the phase position detector 519 of the first control loop depending on the result of this comparison. The first control I 501 uses the value of the high-frequency clock frequency measured value signal 522 of the phase position detector 519 of the first control loop as Measured value of the high-frequency clock 303 to form the first control signal I 515 of the first control I 501 depending on this measured value. The first control I 501 controls the high-frequency oscillator 502 with this first control signal I 515 of the first control I 501 and in this way controls, for example, the frequency and/or the period duration and/or the phase position of the high-frequency clock 303 of the high-frequency oscillator 502. The value of the High-frequency clock frequency measurement value signal 522 of the phase position detector 519 can be the difference in the frequency of the reference clock 306 and the frequency of the divided-down high-frequency clock 521. The value of the high-frequency clock frequency measurement value signal 522 of the phase position detector 519 can be the difference between the period duration of the reference clock 306 and the period duration of the divided-down high-frequency clock 521. The value of the high-frequency clock frequency measurement value signal 522 of the phase position detector 519 can be the difference of the phase shift of the reference clock 306 and the corresponding phase shift of the divided-down high-frequency clock 521. It can also be the difference in the number of clocks of the reference clock 306, which the phase position detector 519 of the first control loop measures in the period in which the divided high-frequency clock 521 has a predetermined first number of clocks, minus this first number of clocks. It can also be the difference in the number of clocks of the divided high-frequency clock 521, which the phase position detector 519 of the first control loop measures in the period in which the reference clock 306 has a predetermined first number of clocks, minus this first number of clocks. Depending on the value of the high-frequency clock frequency measured value signal 522 of the phase position detector 519 and/or depending on a signal associated therewith or derived therefrom, the first control I 501 generates the first control signal I 515 of the first control I 501, with which the first control I 501 controls high-frequency oscillator 502 and, for example, controls the frequency and/or period and/or the phase of the high-frequency clock 303 of the high-frequency oscillator 502. In the normal state 400, this first FLL or PLL control loop 323 is active and keeps the high-frequency clock 303 of the high-frequency oscillator 502 at a constant frequency and / or period and / or, if necessary, phase position, so that the frequency and period of the high-frequency clock 303 is constant and only depends on the frequency or period duration or phase position of the reference clock 306.

A reference measuring device 507 of the second FLL or PLL control loop 324 measures the frequency and/or period duration of the low-frequency reference clock 306 of the reference oscillator 505 and determines a reference clock frequency measured value signal 516 of the reference measuring device 507. The reference measuring device 507 of the second FLL or PLL control loop 324 preferably measures the Frequency and/or period duration of the low-frequency reference clock 306 of the reference oscillator 505 and determines a reference clock frequency measurement value signal 516 of the reference measuring device 507 using the high-frequency clock 303. Preferably, the reference measuring device 507 of the second FLL or PLL control loop 324 is a counter which measures the clocks of the high-frequency clock 303 depending on the reference clock 306 counts as a start/stop signal of the counting. A target value calculation 510 for the measured value of the low-frequency reference clock 306 in the form of the reference clock frequency measured value signal 516 compares the measured value of the frequency and / or period duration of the low-frequency reference clock 306 in the form of the reference clock frequency measured value signal 516 with a valid value of parameters 517 of the frequency or period duration or the phase position of a or several sporadically occurring reference signals of the input signal 308 of a measuring device 509, which is used to measure the input signal 308, and determines a deviation. Very particularly preferably, the measuring device 509 records the respective period duration of one or more of the reference signals in the input signal 308 and the reference measuring device 507 records the period duration of the reference clock 306, since these measurements only involve a measuring device 509 designed as a counter of the high-frequency clock 303 and a reference measuring device designed as a counter of the high-frequency clock 303 507 require. In this case, the measuring device 509 preferably has a counter that counts cycles of the high-frequency clock 303 as a start/stop signal depending on a reference signal of the input signal 308.

Preferably, the measuring device 509 has one or more first measured value memories in which the measuring device 509 stores the measured values of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal 308 that it has acquired after they have been detected by the measuring device 509 before passing them on which the measuring device 509 caches to the target value calculation 510. The purpose of this is that these recorded measured values continue to be available even if the reference signal is no longer available on the input signal 308. The target value calculation 510 serves to compare the measured value of the low-frequency reference clock 306 with the corresponding, valid measured value of the reference signal in the input signal 508. The measuring device 509 preferably evaluates these recorded measured values of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal nals 308, which are located in the one or more first measured value memories.

The measuring device 509 and/or the controller 311 can evaluate whether the reference signal that the measuring device 509 detected was really a reference signal when the reference signal has already passed, i.e. the input signal 308 no longer shows a reference signal. That is the problem solved in the proposal presented here.

For example, the value of a detected frequency of the reference signal in a second memory of the measuring device 509 should preferably lie within a permitted frequency value interval. The measuring device 509 preferably checks this requirement. For example, the value of a detected period duration of the reference signal in a second memory of the measuring device 509 should preferably lie within a permitted period duration value interval. The measuring device 509 preferably checks this requirement. For example, the value of a detected phase position of the reference signal in a second memory of the measuring device 509 should preferably lie within a permitted phase position value interval. The measuring device 509 preferably checks this requirement. If necessary, the controller 311 can take over this task instead of the measuring device 509. In this respect, the controller 311 itself can also be used and viewed as part of the measuring device 509 and, if necessary, at the same time as part of other device parts of the proposed device 300. If this is the case, the measuring device 509 is more likely to have detected an intact reference signal. Therefore, the measuring device 509 then uses these values, which most likely come from an intact reference signal since their measured values satisfy one or more of these conditions, for the control of the second FLL or PLL control loop 324. Conversely, if one or more are not met Under these conditions, measuring device 509 assumes that the measured values recorded do not come from an intact reference signal. The measuring device 509 preferably no longer uses the recorded measured values of a reference signal that is recognized as a possibly not intact reference signal. Preferably, the measuring device 509 only transmits the measured values of a reference signal rated as most likely intact or values that the measuring device 509 has derived from one or more reference signals of the input signal 308 rated as most likely intact, as valid measured values 517 to the target value calculation 510. The target value calculation 510 generates this Deviation signal 518 of the target value calculation 510 for the measured value of the low-frequency reference clock 306 from the valid measured value 517 of the frequency or another suitable parameter (e.g. the period duration and / or the phase position) of one or more valid reference signals of the input signal 308. The deviation signal 518 of the target value calculation 510 from the Measuring device 509 signals to the second control system II 504 the valid value of the deviation between the measured value of the frequency and/or the period duration and/or the phase position of the reference clock frequency measured value signal 516 or reference clock period duration measured value signal 516 or the reference clock phase position measured value signal 516 on the one hand and the valid measured value 517 of the frequency or the period duration or the phase position of one or more valid reference signals of the input signal 308 on the other hand. Depending on these valid measured values, the second control II 504 generates the second control signal II 514 of the second control II 504, with which the freezeable control II 504 controls the reference oscillator with adjustable frequency 505 and, for example, the frequency and / or the phase of the reference clock 306 of the Reference oscillator with adjustable frequency 505 controls. The measuring device 509 preferably stores these valid measured values in one or more memories until the measuring device 509 has again detected new valid measured values of a subsequent reference signal of the input signal 308. Until the measuring device 509 has again acquired new valid measured values of a subsequent reference signal of the input signal 308, the measuring device 509 preferably returns the measured values stored in the one or more second memories as valid measured values 517, for example of the frequency or the period duration or the phase position of one or more valid reference signals of the input signal 308 to the target value calculation 510, which the deviation signal 518 of the target value calculation 510 for the measured value of the low-frequency reference clock 306 from the valid measured value 517 of the frequency or another suitable parameter (e.g. the period duration and / or the phase position) of one or more valid ones Reference signals of the input signal 308 are generated.

In the exemplary case of 5 represents the second FLL or PLL control loop 324 5 i.e. an FLL with a frequency control loop, with the target value calculation 510 determining the frequency deviation in the form of the value of a deviation signal 518. The target value calculation 510 for the measured value of the low-frequency reference clock 306 in the form of the reference clock frequency measured value signal 516 can also include a measured value of the phase position of the low-frequency reference clock 306 in the form of the reference clock phase measured value signal 516 with a valid measured value 516 of the phase position of one or more of the sporadically occurring valid reference signals of the input signal 308 from a Compare measuring device 509 for measuring the input signal 308 and determine a deviation. The target value calculation 510 preferably transmits this deviation by means of a deviation signal 518 of the target value calculation 510 to a second control II 504 of the second FLL or PLL control loop 324. The deviation signal 518 preferably signals the value of the deviation between the reference clock frequency measurement value of the reference clock frequency measurement value signal 516 and the valid measurement value 517 for example the frequency or the period duration or the phase position of one or more valid reference signals of the input signal 308 or the value of the deviation between the reference clock phase measurement value of the reference clock frequency measurement value signal 516 and the valid measurement value 517, for example the frequency or the period duration or the phase position of one or more valid ones Reference signals of the input signal 308 or a value derived therefrom or values directly related thereto to the second control II 504 of the second FLL or PLL control loop 324. The second control II 504 of the second FLL or PLL control loop 324 generates a second control signal II 514 of the second control II 504 of the second FLL or PLL control loop 324, with which the second control II 504 of the second FLL or PLL control loop 324 controls the reference oscillator 505 with an adjustable frequency or adjustable period or adjustable phase. The second control II 504 of the second FLL or PLL control loop 324 thus controls, for example, the frequency and/or period duration and/or the phase of the reference clock 306 of the reference oscillator 505 depending on the value that it receives by means of the reference clock frequency measurement value signal 516. The frequency and/or period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 thus preferably depend on the value that it receives by means of the reference clock frequency measurement value signal 516. The frequency and/or period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 thus preferably depend on the deviation that the target value calculation 510 uses by means of the deviation signal 518 of the second control system II 504 of the second FLL or PLL control loop 324 transmitted.

The basic idea of the proposal provides that a controller 311 of a proposed device 300 freezes the second controller II 504 of the reference oscillator 505 of the PLL or FLL of the second FLL or PLL control loop 324 for generating the reference clock 306 during normal operation 400. The second control II 504 of the reference oscillator 505 is therefore inactive in normal operation 400. In this normal operating state 400, the frequency and the period duration and the phase position of the high-frequency clock 303 depend exclusively on the frozen frequency and period duration and phase position of the reference clock 306.

The controller 311 preferably monitors the input signal 308 by means of the measuring device 509 of the second FLL or PLL control loop 324 by measuring the input signal 308. As long as the measuring device 509 for measuring the input signal 308 does not report a detection 401 of a synchronization signal as a reference signal in the input signal 308 of the controller 311 , the proposed device 300 preferably remains in the normal state 400. In this normal state 400, the second control II 504 of the second FLL or PLL control loop 324 is frozen and therefore inactive, while the first control I 501 of the first FLL or PLL control loop 323 is active and thus adjusts the frequency and the period duration and, if applicable, the phase position of the high-frequency clock 303 of the high-frequency oscillator 502 to the frequency and period duration and, if necessary, the phase position of the reference clock 306 of the reference oscillator 505. The frequency and period duration and the phase position of the reference clock 306 of the reference oscillator 505 and thus the frequency and period duration and phase position of the high-frequency clock 303 of the high-frequency oscillator 502 are fixed in this normal state.

However, as soon as the measuring device 509 for measuring the input signal 308 reports a detection 401 of a synchronization signal as a sporadic reference signal in the input signal 308 of the controller 311, the proposed device 300 typically leaves the normal state 400 at the instigation of the controller 311 and changes to a state 402 of the measurement of the detected synchronization signal of the input signal 308. In this state 402, the proposed device 300 carries out a measurement of the reference signal, which appears as the content of said input signal 308 as a synchronization signal of said input signal 308, by means of the measuring device 509 for measuring the input signal 308. The controller 311 of the proposed device 300 typically continues to keep the control of the frequency and the period duration and, if applicable, phase position of the generated reference clock 306 by the second FLL or PLL control loop 323 inactive and preferably freezes for the duration of this measurement of the reference signal in the input signal 308 also the frequency and period duration and phase position of the reference clock 306. The controller 311 of the proposed device 300 maintains this frequency and period length and phase position of the Reference clock 306 preferably remains constant in this state 402. During the inactivation of the second control II 504, the controller 311 can then carry out a correction on the reference oscillator 505 and thus on the reference clock 306 as follows, which depends on a deviation between a detected parameter of the detected reference signal of the input signal 308 and the corresponding parameter of the reference clock signal 306 , for example the respective frequencies or period lengths or phase positions.

As stated above, the reference measuring device 507 detects the reference clock frequency of the reference clock 306 for measuring the frequency and/or period duration of the low-frequency reference clock 306. The reference measuring device 507 is preferably a counting circuit which, for example, detects how many clocks of the high-frequency clock 303 are a predetermined one second number of clocks of the reference clock 306 or how many clocks of the reference clock 306 lie in a period that correspond to a predetermined second number of the high-frequency clock 303. If necessary, the reference measuring device 507 forms the reciprocal of the result of the count. Here, the high-frequency clock 303 preferably forms the time base for the measurements of the reference signal in the input signal 308 and the reference clock 306. If the high-frequency clock 303 is somewhat constant, the reference measuring device 507 can thus determine a value of the reference clock 306 that depends on the average frequency or average Period length of the high-frequency clock 303 depends. In this state 402 of measuring the synchronization signal of the input signal 308, the controller 311 of the proposed device 300 then uses the high-frequency oscillator 502 and the high-frequency clock 303 generated by it as a reference.

In state 402 of measuring the synchronization signal of the input signal 308; the second FLL or PLL control loop 324 with the second control II 504 is frozen and the frequency and period duration and phase position of the reference clock 306 of the reference oscillator 505 are frozen. In state 402 of measuring the synchronization signal of the input signal 308, the first FLL or PLL control circuit 323 with the first control I 501 is therefore in the variant of 5 active and the first FLL or PLL control loop 323 regulates the frequency and period duration and phase position of the high-frequency oscillator 502 and thus of the high-frequency clock 303 depending on the reference clock 306.

After the state 402 of measuring the synchronization signal of the input signal 308 and thus with a deviation 518 known after the measurement 402 through the target value calculation 510 to achieve the desired target accuracy, the proposed device 300 can go into the state 403 of evaluating the synchronization signal of the input signal 308 and one Decision 404 makes whether the synchronization signal of the input signal 308 is valid. The controller 311 preferably makes this decision 404 as to whether the synchronization signal of the input signal 308 is valid, depending on data that the controller 311 receives from other device parts of the proposed device 300, but preferably from the target value calculation 510.

In the state 402 of evaluating the synchronization signal of the input signal 308 and during the decision 404 as to whether the synchronization signal of the input signal 308 is valid, the second FLL or PLL control loop 324 with the second control II 504 is therefore preferably still frozen and the frequency and the period duration and phase position of the reference clock 306 of the reference oscillator 505 are still preferably frozen. In the state 402 of evaluating the synchronization signal of the input signal 308 and during the decision 404 as to whether the synchronization signal of the input signal 308 is valid, the first FLL or PLL control loop 323 with the first control I 501 is therefore preferably still active and the first FLL - or PLL control loop 323 preferably continues to regulate the frequency and period length and phase position of the high-frequency oscillator 502 and thus of the high-frequency clock 303 depending on the reference clock 306.

If the synchronization signal of the input signal 308 is not valid, the proposed device 300 preferably changes back to the normal state 400. If the synchronization signal of the input signal 308 is not valid, the controller 311 preferably causes the proposed device 300 to preferably change back to the normal state 400 .

However, if the synchronization signal of the input signal 308 is valid, the proposed device 300 preferably switches to state 405 of calculating the target value of the frequency and/or period duration and/or phase position of the reference clock 506. In state 405 of calculating the target value of the frequency and/or or period duration and/or phase position of the reference clock 506, the measuring device 509 for measuring the input signal 308 preferably detects relevant parameters of the valid synchronization signal of the input signal 308. If necessary, the proposed device 300 can also use parameters that the measuring device 509 uses for measuring the input signal 308 already in one of the previous states or during previous measurement and/or synchronization runs (400-407). The values of these parameters are preferably in a memory of the proposed device 300, for example in a memory of the controller 311, after the proposed device 300 and/or the controller 311 had temporarily stored the values of these parameters there after they were determined. The measuring device 509 preferably determines the values Measuring the input signal 308, the valid measured value 517 of the frequency and/or period duration and/or the phase position of one or more synchronous signals of the input signal 308 that occur sporadically as a valid reference signal.

In the state 405 of measuring the frequency and/or period duration and/or the phase position of the reference clock 306 and the calculation of the target value of the frequency and/or period duration and/or phase position of the reference clock 306, the reference measuring device 507 detects the value of the frequency and/or the Period duration and/or the phase position of the low-frequency reference clock 306 and, in accordance with this value, generates a reference clock frequency measured value signal 516 of the reference measuring device 507 for the measured value of the low-frequency reference clock 306. The target value calculation 510 uses this value of the reference clock frequency measured value signal 516 to determine a deviation. For this purpose, the target value calculation 510 now compares the measured value of the low-frequency reference clock 306 in the form of the value of the reference clock frequency measured value signal 516 with the valid measured value 517 of the frequency or period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308 from the measuring device 509. The measuring device 509 For this purpose, the valid measured value 517 of the frequency or the period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308 is transmitted to the target value calculation 510 by means of an associated measured value signal 517. The target value calculation 510 preferably determines the deviation between the valid measured value of the measured value signal 517 and the value of the reference clock frequency measured value signal 516. The technical teaching of the document presented here particularly emphasizes that the measuring device 509 preferably keeps the valid measured value of the measured value signal 517 of the frequency or the period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308 constant and maintained, even if the reference signal of the input signal 308, on whose measurement this measured value is based, is no longer present at the input signal 308. The measuring device 509 preferably replaces the valid measured value 517 of the frequency or period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308 only then again with a new measured value of the frequency or period duration or phase position of one or more sporadically occurring valid reference signals of the Input signal 308, which is based on a new, previously unconsidered measured value of a new, previously unconsidered reference signal of the input signal 308, if the proposed device has assumed state 402 again and if the evaluation of this new measured value of the frequency or period duration or phase position of the previously unconsidered reference signal of input signal 308 was successful as a valid new measured value in states 403 and 404. In this case, the proposed device 300 evaluates the resulting new measured value of the frequency or period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308, which it forms taking into account the recorded measured values of the previously unconsidered reference signal of the input signal 308, as new valid measured value 517 of the frequency or period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308. This enables the damped correction and tracking of the reference clock 306 regardless of the duration of the reference signal in the input signal 308. The target value calculation 510 can thus use the measured value compare the last valid reference clock phase of the low-frequency reference clock 306 in the form of the reference clock phase measured value signal 516 with the valid measured value 517 of the frequency or period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308 and determine the deviation between them.

In the state 405 of calculating the target value of the frequency or the period duration or the phase position, the second FLL or PLL control loop 324 with the second control system II 504 is still preferably frozen and the frequency and period duration and phase position of the reference clock 306 of the reference oscillator 505 still preferably frozen. In the state 405 of calculating the target value of the frequency or period duration or phase position, the first FLL or PLL control loop 323 with the first control I 501 is therefore preferably still active and the first FLL or PLL control loop 323 preferably continues to regulate the Frequency or period duration or phase position of the high-frequency oscillator 502 and thus of the high-frequency clock 303 as a function of the reference clock 306.

From the state 405 of the calculation of the target value of the frequency or period duration or Phase position of the reference clock 306, the proposed device 300 changes, preferably at the instigation of the controller 311, into the state 406 of correcting the frequency or the period duration or the phase position of the reference clock 306 of the reference oscillator 505.

In the state 406 of the correction of the frequency or period duration or the phase position of the reference clock 306 of the reference oscillator 505, the second FLL or PLL control loop 324 with the second control II 504 is now preferably active in order to carry out the correction according to the value or depending on from the value of a deviation signal 518 of the target value calculation 510. The deviation signal 518 of the target value calculation 510 typically signals the value of the deviation between the reference clock frequency measured value of the reference clock frequency measured value signal 516 of the reference measuring device 507 and the measured value of the measured value signal 517 of the frequency or period duration or the phase position of one or more valid reference signals of the input signal 308 or one that is proportional to this deviation Value or a value dependent on this deviation or a value derived from this deviation or a value associated with this deviation. In the case of a phase position-related control of the reference clock 306, the deviation signal 518 of the target value calculation 510 typically signals the value of the deviation between the reference clock phase position measured value of the reference clock phase position measured value signal 516 of the reference measuring device 507 and the valid measured value of the measured value signal 517 of the phase position of one or more valid reference signals of the input signal 308 or one a value proportional to this deviation or a value dependent on this deviation or a value derived from this deviation or a value related to this deviation. The regulation using other parameters such as period length, time length of the high phases, time length of the low phases, time duration of a predetermined number of cycles, etc. is also possible in an analogous manner and is deemed to be disclosed and claimed here.

The frequency and period length and phase position of the reference clock 306 of the reference oscillator 505 are now no longer frozen. In the case of frequency control, the second control II 504 now corrects the frequency of the reference oscillator 505 until the reference clock frequency measurement value signal 519 of the reference measuring device 507 for the measured value of the low-frequency reference clock 306 matches the valid measured value 517 of the frequency of one or more reference signals of the input signal 308 from the measuring device 509 matches within specified limits. In the case of regulation of the period duration, the second control II 504 now corrects the period duration of the reference oscillator 505 until the reference clock period duration measured value signal 519 of the reference measuring device 507 for the measured value of the low-frequency reference clock 306 matches the valid measured value 517 of the period duration of one or more reference signals of the input signal 308 the measuring device 509 matches within predetermined limits. In the case of a phase position control, the second controller II 504 now corrects the phase position of the reference oscillator 505 until the measured value of the phase position of the reference clock phase position measured value signal 519 of the reference measuring device 507 for the measured value of the low-frequency reference clock 306 matches the valid measured value of the measurement signal 517 of the phase position of one or more reference signals of the input signal 308 from the measuring device 509 matches within predetermined limits. Since both signals are usually quantized digital signals, complete agreement may also be required here. Here the high-frequency oscillator 502 now works in this state 406 of correcting the frequency or the period duration or the phase position of the reference clock 306 of the reference oscillator 505 as a “replacement reference oscillator” for the synchronization of the reference oscillator 505. The digital device parts of the second FLL are therefore preferred - or PLL control loop 324 and the controller 311 are clocked with the high-frequency clock 303 as the system clock, as long as they require clocking.

Since the reference oscillator 505 and thus the reference clock 306 no longer represent a reliable time base until the correction, the controller 311 freezes the first FLL or PLL control loop 323 and thus deactivates it before activating the second FLL or PLL control loop 324. In the state 406 of the correction of the frequency or the period duration or the phase position of the reference clock 306 of the reference oscillator 505, the second FLL or PLL control loop 324 with the second control II 504 is now preferably active and the second FLL or PLL Control circuit 324 continues to regulate the frequency and period duration and phase position of the reference oscillator 505 and thus of the reference clock 306 depending on the synchronization signal within the input signal 308. In the state 406 of the correction of the frequency or period duration or phase position of the reference clock 306 of the reference oscillator 505 is the First FLL or PLL control loop 323 with the first control I 501 is now preferably frozen and the frequency and period duration and phase position of the high-frequency clock 303 of the high-frequency oscillator 502 are preferably frozen.

A core idea of the technical teaching of the document presented here is that reference oscillator 505 and high-frequency oscillator 502 briefly swap roles for the duration of the synchronization of reference oscillator 505 to the synchronization signal of input signal 308.

The advantageous effect that results from this is that the correction of the frequency or the period duration or the phase position of the high-frequency clock 303 of the high-frequency oscillator 201 takes place in a single correction step.

The proposed device 300, which carries out the proposed method, is particularly suitable for devices that have communication with the outside world, for example via a data bus, and which must have a high-precision high-frequency clock 303, for example as the system clock of the proposed device 300, for example always in Center of an eye of the data transmitted via the data bus, for example a LIN data bus, to be able to scan this data on the data bus. The proposal of the document presented here provides that in the application of the proposed device 300, a reference signal external to the proposed device 300 is available as a synchronization signal as part of the input signal 308 sporadically, for example as a special synchronous data field of the LIN data bus transmission, which the proposed device 300 can be used as a reference signal of the input signal 308 during the execution of the proposed method in order to synchronize the reference oscillator 505 and, based on this, also the high-frequency oscillator 502. In the case of a single-wire data bus, such as the LIN data bus, the input signal 308 is preferably the data bus line or a signal that is obtained directly from the data bus signal. The data bus can also be, for example, a uni- or bi-directional differential data bus with two data lines. Exemplary representatives of such a data bus are CAN data buses, CAN FD data buses, LVDS data buses or ISLED data buses or the like. The input signal 308 can also be a differential data signal between two or more data lines.

• • Erzeugen eines Referenztakts 306 mittels eines niederfrequenten, einstellbaren Referenzoszillators 505 wobei der Referenzoszillator 505 Teil eines zweiten FLL- oder PLL-Regelkreises 324 ist und einen Referenztakt 306 erzeugt;
• • Erzeugen eines Hochfrequenztakts 303 mittels eines hochfrequenten, einstellbaren Oszillators 502, wobei der einstellbare hochfrequente Oszillator 502 Teil eines ersten FLL-oder PLL-Regelkreises 323 ist und wobei die Frequenz des Hochfrequenztakts 303 betragsmäßig größer als die Frequenz des Referenztakts 306 des Referenzoszillators 505 ist und wobei die Periodendauer des Hochfrequenztakts 303 betragsmäßig kleiner als die Periodendauer des Referenztakts 306 des Referenzoszillators 505 ist und wobei der erste FLL- oder PLL-Regelkreis 323 im Zustand 400 des Normalbetriebs den Referenztakt 306 des zweiten FLL- oder PLL-Regelkreises 324 als Sollgröße des ersten FLL- oder PLL-Regelkreises 323 nutzt;
• • Detektieren des Eintreffens eines Referenzsignals in Form eines Synchronisationssignals eines externen Eingangssignals 308 bevorzugt mittels einer Messvorrichtung 509 zur Vermessung des Eingangssignals 308 in einem ersten Schritt;
• • Ggf. Einfrieren und somit Inaktivieren des ersten FLL- oder PLL-Regelkreises 324, die den hochfrequenten Oszillator 502 umfasst, bevorzugt durch die Steuerung 311 der vorschlagsgemäßen Vorrichtung 300 vorzugsweise zeitlich mit dem Eintreffen des externen Eingangssignals oder zeitlich kurz danach zumindest aber in den Zuständen 406 und 407 , sodass der Hochfrequenztakt 303 seine Frequenz und Periodendauer und/oder Phasenlage für die Dauer, in der der zweite FLL- oder PLL-Regelkreis 324 den Referenztakt 306 nachgeregelt, nicht ändert. Je nach Variante der Ausführung der vorschlagsgemäßen Vorrichtung bzw. der Durchführung des vorschlagsgemäßen Verfahrens kann auch auf das Einfrieren des ersten FLL- oder PLL-Regelkreis 324 an dieser Stelle im Prozess verzichtet werden
• • Erfassen des Referenzsignals in dem Eingangssignal 308 bevorzugt mittels der Messvorrichtung 509 zur Vermessung des Eingangssignals 308 und Ermitteln verschiedener Parameter in einem zweiten Schritt bevorzugt mittels der Messvorrichtung 509 zur Vermessung des Eingangssignals 308.

In a method for generating a high-frequency clock 303 of a high-frequency oscillator 502 of the type described at the beginning, the task is solved according to the proposal by the following steps:

• • Generating a reference clock 306 by means of a low-frequency, adjustable reference oscillator 505, the reference oscillator 505 being part of a second FLL or PLL control loop 324 and generating a reference clock 306;
• • Generating a high-frequency clock 303 by means of a high-frequency, adjustable oscillator 502, the adjustable high-frequency oscillator 502 being part of a first FLL or PLL control loop 323 and the frequency of the high-frequency clock 303 being greater in magnitude than the frequency of the reference clock 306 of the reference oscillator 505 and wherein the period duration of the high-frequency clock 303 is smaller in magnitude than the period duration of the reference clock 306 of the reference oscillator 505 and wherein the first FLL or PLL control loop 323 in the state 400 of normal operation uses the reference clock 306 of the second FLL or PLL control loop 324 as the setpoint of the first FLL or PLL control loop 323 uses;
• • Detecting the arrival of a reference signal in the form of a synchronization signal of an external input signal 308, preferably by means of a measuring device 509 for measuring the input signal 308 in a first step;
• • If necessary, freezing and thus inactivating the first FLL or PLL control loop 324, which includes the high-frequency oscillator 502, preferably by the controller 311 of the proposed device 300, preferably in time with the arrival of the external input signal or shortly afterwards, but at least in the states 406 and 407, so that the high-frequency clock 303 does not change its frequency and period duration and / or phase position for the duration in which the second FLL or PLL control loop 324 readjusts the reference clock 306. Depending on the variant of the design of the proposed device or the implementation of the proposed method, freezing of the first FLL or PLL control circuit 324 at this point in the process can also be dispensed with
• • Detecting the reference signal in the input signal 308, preferably by means of the measuring device 509 for measuring the input signal 308 and determining various parameters in a second step, preferably by means of the measuring device 509 for measuring the input signal 308.

1. a. Erste Anzahl der Takte des Referenzsignals des Eingangssignals 308 in einem Zeitabschnitt, der von einer zweiten Anzahl an Takten im Hochfrequenztakt 303 des hochfrequenten Oszillators 502 abhängig ist, und/oder
2. b. Frequenz des Referenzsignals des Eingangssignals 308 und/oder
3. c. zeitliche Dauer eines vollständigen Takts des Referenzsignals des Eingangssignals 308, (Periodendauer) insbesondere in Form einer Anzahl an Takten des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 gemessen, und/oder
4. d. die Phasenlage des Referenzsignals des Eingangssignals 308 gegenüber dem Referenztakt 306, insbesondere in Form einer Anzahl an Takten des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 beginnend mit einer Flake des Referenzsignals des Eingangssignals 308 und endend mit einer korrespondierenden Flanke des Referenztakts 306 gemessen oder beginnend mit einer Flake des Referenztakts 306 und endend mit einer korrespondierenden Flanke des Referenzsignals des Eingangssignals 308 gemessen, und/oder
5. e. die Phasenlage des Referenzsignals des Eingangssignals 308 gegenüber einem heruntergeteilten Hochfrequenztakt 321, insbesondere in Form einer Anzahl an Takten des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 beginnend mit einer Flake des Referenzsignals des Eingangssignals 308 und endend mit einer korrespondierenden Flanke des heruntergeteilten Hochfrequenztakts 521 gemessen oder beginnend mit einer Flake des heruntergeteilten Hochfrequenztakts 521 und endend mit einer korrespondierenden Flanke des Referenzsignals des Eingangssignals 308 gemessen, und/oder
6. f. die zeitliche Dauer einer Low- und/oder High-Phase des Takts des Referenzsignals des Eingangssignals 308, insbesondere in Form einer Anzahl an Takten des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 gemessen, und/oder
7. g. zeitliche Dauer einer bestimmten Anzahl von Takten des Referenzsignals des Eingangssignals 308, insbesondere in Form einer Anzahl an Takten des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 gemessen, und/oder zeitliche Dauer einer bestimmten Anzahl von Low- und/oder High-Phasen des Referenzsignals des Eingangssignals 308, insbesondere in Form einer Anzahl an Takten des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 gemessen;

• • Bewerten des so als Synchronisationssignal erfassten Referenzsignals des Eingangssignals 308 und/oder der so erfassten Parameter des als Synchronisationssignal erfassten Referenzsignals des Eingangssignals 308 durch die Steuerung 311 oder eine andere Teilvorrichtung der vorschlagsgemäßen Vorrichtung 300 und Entscheiden durch die Steuerung 311 oder eine andere Teilvorrichtung der vorschlagsgemäßen Vorrichtung 300, ob das Referenzsignals des Eingangssignal 308 ein gültiges Referenzsignal war. Dieser Schritt des von der vorschlagsgemäßen Vorrichtung 300 ausgeführten Verfahrens erfolgt typischerweise nach Abschluss der Messungen der vorschlagsgemäßen Vorrichtung 300 am Referenzsignal des Eingangssignals 308. Hier kann die vorschlagsgemäße Vorrichtung 300 z.B. bewerten, ob das Referenzsignal des Eingangssignals 308 eine bestimmte Anzahl von Takten beispielsweise innerhalb eines vorbestimmten Zeitraums aufwies und damit ein valides, d.h. gültiges Referenzsignal ist. Weiterhin kann die vorschlaggemäße Vorrichtung 300 anhand der gemessenen zeitlichen Dauern unter Berücksichtigung der typischerweise vorhandenen Kenntnis der Grundgenauigkeit des Hochfrequenztakts 303 des hochfrequenten Oszillators 302 bewerten, ob die Frequenz oder die Periodendauer oder die Phasenlage des Referenzsignals des Eingangssignals 308 innerhalb eines erwarteten und zulässigen Wertebereichs liegt. Zusätzlich kann die vorschlagsgemäße Vorrichtung 300 die von ihr gemessenen Dauern der Low- und High-Phasen zur Bewertung der Eingangssignalqualität heranziehen, um z.B. festzustellen, ob das Referenzsignal des Eingangssignals 308 stark gestört ist oder die Signalqualität ausreichend ist;
• • Verwerfen des erfassten Referenzsignals des Eingangssignals 308 und/oder der erfassten Parameter und Beenden des ggf. vorgenommen Einfrierens des ersten FLL- oder PLL-Regelkreises 324 , der den hochfrequenten Oszillator 502 umfasst, durch die Steuerung 311 der vorschlagsgemäßen Vorrichtung 300 oder eine andere Teilvorrichtung der vorschlagsgemäßen Vorrichtung 300 und Rückkehr in den Normalzustand 400 der vorschlagsgemäßen Vorrichtung 300 in einem vierten Schritt, sofern die erfassten Parameter und erfassten Messwerte des Referenzsignals des Eingangssignals 308 nicht innerhalb eines oder mehrerer dieser vorbestimmten Erwartungswertintervalle liegen und somit das Referenzsignal des Eingangssignals 308 nicht valide, also ungültig, ist;
• • Bevorzugtes Halten des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 auf einer festen Frequenz und Periodendauer und Phasenlage und inaktiv Halten des ersten FLL- oder PLL-Regelkreises 324 durch die Steuerung 311 oder eine andere Teilvorrichtung der vorschlagsgemäßen Vorrichtung 300 in dem vierten Schritt, sofern die erfassten Parameter und erfassten Messwerte des Referenzsignals des Eingangssignals 308 innerhalb der vorbestimmten Erwartungswertintervalle liegen und somit das Eingangssignal valide, also gültig, ist, wobei dieser Schritt auch erst unmittelbar vor der der Korrektur des Referenztakts 306 erfolgen kann.;
• • Erfassung der Frequenz und/oder Periodendauer und/oder der Phasenlage des Referenztakts 306 des niederfrequenten Referenzoszillators 505 und Bestimmung der Abweichung der ermittelten Frequenz und/oder Periodendauer und/oder Phasenlage des Referenzsignals des Eingangssignals 308 von der erfassten Frequenz und/oder Periodendauer und/oder Phasenlage des Referenztakts 306 des niederfrequenten Referenzoszillators 505 und/oder der Abweichung der ermittelten Parameter des Referenzsignals des Eingangssignals 308 von der den entsprechenden Werten der diesen korrespondierenden Parametern des Referenztakts 306 des niederfrequenten Referenzoszillators 505 in dem vierten Schritt. Für diesen vierten Schritt ist es nötig, dass die vorschlagsgemäße Vorrichtung die Frequenz oder Periodendauer des Referenzsignals des Eingangssignals 308 kennt. Dies schränkt das Verfahren jedoch nicht zwangsläufig auf ein einzelnes gültiges Frequenzintervall der Frequenz des Referenzsignals des Eingangssignals 308 ein bzw. auf ein einzelnes gültiges Periodendauerintervall der Periodendauer des Referenzsignals des Eingangssignals 308 ein. Es sind durchaus mehrere verschiedene, vorher bekannte zulässige Frequenzintervalle bzw. Periodendauerintervalle zulässig (die z.B. durch Baudraten definiert sind) denkbar. Diese verschiedenen, vorher bekannten zulässigen Frequenzintervalle bzw. Periodendauerintervalle müssen lediglich im Rahmen der Grundgenauigkeit der Frequenz bzw. der Periodendauer des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 der vorschlagsgemäßen Vorrichtung 300 unterscheidbar sein, also voneinander im Frequenzbereich bzw. Periodendauerbereich beabstandet sein, sein und dürfen sich nicht überlappen. Hat die Frequenz bzw. Periodendauer des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 der vorschlagsgemäßen Vorrichtung z.B. ohne externes Referenzsignal des Eingangssignals 308 eine Grundgenauigkeit von ±5%, so ergibt sich eine sehr feine Granularität an unterscheidbaren möglichen Referenzsignalen des Eingangssignals 308, die die vorschlagsgemäße Vorrichtung 300 als Referenzsignal verwenden kann. In diesem Schritt bestimmt die vorschlagsgemäße Vorrichtung 300 die Abweichung der Frequenz und/oder Periodendauer und/oder Phasenlage des Referenzsignals Eingangssignals 308 von der Frequenz und/oder Periodendauer und/oder Phasenlage des Referenztakts 306 des niederfrequenten Referenzoszillators 505. Bevorzugt kann die vorschlagsgemäße Vorrichtung 300 den Hochfrequenztakt 303 des hochfrequenten Oszillators 502 nutzen, um die Dauer einer bestimmten Anzahl von Takten des Referenztakts 306 des Referenzoszillators 505 z.B. durch Zählung der Takte des Hochfrequenztakts 303 in diesem Zeitraum zu messen.
• • Korrigieren der Frequenz und/oder Periodendauer und/oder Phasenlage des Referenztakts 306 des niederfrequenten Referenzoszillators 505 um diese bestimmte Abweichung und/oder einen mit dieser Abweichung zusammenhängenden Wert oder um einen Wert, der von dieser Abweichung abhängt in dem vierten Schritt mittels des aktivierten zweiten FLL- bzw. PLL-Regelkreises 324, der den Referenzoszillators 505 umfasst. Die die vorschlagsgemäße Vorrichtung 300 korrigiert somit nun die Frequenz und/oder Periodendauer und/oder Phasenlage des Referenztakts 306 des niederfrequenten Referenzoszillators 505 um die zuvor ermittelte Abweichung oder einen daraus abgeleiteten Wert. Ist z.B. der Verlauf der Trimmkurve der Frequenz bzw. Periodendauer bzw. Phasenlage des Referenzoszillators 505 bekannt, so kann die Korrektur der Frequenz und/oder Periodendauer und/oder der Phasenlage des Referenztakts 306 direkt unter Berücksichtigung der Trimmkurven oder Trimmschrittweiten mittels Berechnung beispielsweise durch die Steuerung 311 erfolgen;
• • Feststellen der ausreichenden Korrektur der Frequenz und/oder Periodendauer und/oder Phasenlage des Referenztakts 306 des niederfrequenten Referenzoszillators 505 mittels der Referenzmessvorrichtung 507 zum Vermessung der Frequenz bzw. Periodendauer bzw. der Phasenlage des niederfrequenten Referenztakts 306 und der Zielwertberechnung 510 für den Messwert des niederfrequenten Referenztakts 306, Inaktivierung des zweiten FLL-bzw. PLL-Regelkreises 324 durch die durch die Steuerung 311 der vorschlagsgemäßen Vorrichtung 300 oder eine andere Teilvorrichtung der vorschlagsgemäßen Vorrichtung 300 und abschließende Re-Aktivierung der ersten FLL-bzw. PLL-Regelkreises 324 zum Abschluss der Korrektur in einem fünften Schritt, und
• • Korrektur und Regelung der der Frequenz und/oder Periodendauer und/oder Phasenlage des Hochfrequenztakts 303 des hochfrequenten Oszillators 502 in diesem fünften Schritt mittels des ersten FLL- bzw. PLL-Regelkreises 324 im Normalzustand 400.

The proposed device 300 preferably uses the high-frequency clock 303 to measure the reference signal in the input signal 308. The proposed device 300 can, if necessary, also measure several parameters at the same time, so that it can, for example, better evaluate the signal quality and the validity of the reference signal later. These determined parameters of the reference signal of the input signal 308 include at least one or more of the following parameters:

1. a. First number of clocks of the reference signal of the input signal 308 in a time period that is dependent on a second number of clocks in the high-frequency clock 303 of the high-frequency oscillator 502, and / or
2. b. Frequency of the reference signal of the input signal 308 and/or
3. c. time duration of a complete clock of the reference signal of the input signal 308, (period duration) measured in particular in the form of a number of clocks of the high-frequency clock 303 of the high-frequency oscillator 502, and / or
4. d. the phase position of the reference signal of the input signal 308 relative to the reference clock 306, in particular in the form of a number of clocks of the high-frequency clock 303 of the high-frequency oscillator 502 starting with a flake of the reference signal of the input signal 308 and ending with a corresponding edge of the reference clock 306 measured or starting with a flake of the reference clock 306 and ending with a corresponding edge of the reference signal of the input signal 308 measured, and / or
5. e. the phase position of the reference signal of the input signal 308 relative to a divided-down high-frequency clock 321, in particular in the form of a number of clocks of the high-frequency clock 303 of the high-frequency oscillator 502, starting with a flake of the reference signal of the input signal 308 and ending with a corresponding edge of the divided-down high-frequency clock 521 measured or starting with a flake of the divided down high-frequency clock 521 and ending with a corresponding edge of the reference signal of the input signal 308 measured, and / or
6. f. the time duration of a low and/or high phase of the clock of the reference signal of the input signal 308, in particular measured in the form of a number of clocks of the high-frequency clock 303 of the high-frequency oscillator 502, and/or
7. G. time duration of a certain number of clocks of the reference signal of the input signal 308, in particular measured in the form of a number of clocks of the high-frequency clock 303 of the high-frequency oscillator 502, and / or time duration of a certain number of low and / or high phases of the reference signal of the input signal 308, measured in particular in the form of a number of clocks of the high-frequency clock 303 of the high-frequency oscillator 502;

• • Evaluating the reference signal of the input signal 308 thus detected as a synchronization signal and/or the parameters of the reference signal of the input signal 308 detected as a synchronization signal by the controller 311 or another sub-device of the proposed device 300 and making a decision by the controller 311 or another sub-device of the proposed device Device 300 whether the reference signal of the input signal 308 was a valid reference signal. This step of the method carried out by the proposed device 300 typically takes place after completion of the measurements by the proposed device 300 on the reference signal of the input signal 308. Here, the proposed device 300 can, for example, evaluate whether the reference signal of the input signal 308 has a certain number of clocks, for example within a predetermined one period and is therefore a valid, ie valid reference signal. Furthermore, the proposed device 300 can use the measured time durations, taking into account the typically existing knowledge of the basic accuracy of the high-frequency clock 303 of the high-frequency oscillator 302, to evaluate whether the frequency or the period duration or the phase position of the reference signal of the input signal 308 lies within an expected and permissible value range. In addition, the proposed device 300 can use the durations of the low and high phases measured by it to evaluate the input signal quality, for example to determine whether the reference signal of the input signal 308 is severely disturbed or the signal quality is sufficient;
• • Discarding the detected reference signal of the input signal 308 and/or the detected parameters and terminating any freezing of the first FLL or PLL control loop 324, which includes the high-frequency oscillator 502, by the controller 311 of the proposed device 300 or another sub-device the proposed device 300 and return to the normal state 400 of the proposed device 300 in a fourth step, provided that the recorded parameters and recorded measured values of the reference signal of the input signal 308 are not within one or more of these predetermined expected value intervals and therefore the reference signal of the input signal 308 is not valid, therefore invalid, is;
• • Preferential holding of the high-frequency clock 303 of the high-frequency oscillator 502 a fixed frequency and period length and phase position and keeping the first FLL or PLL control loop 324 inactive by the controller 311 or another sub-device of the proposed device 300 in the fourth step, provided that the recorded parameters and recorded measured values of the reference signal of the input signal 308 are within the predetermined expected value intervals and therefore the input signal is valid, i.e. valid, whereby this step can only take place immediately before the reference clock 306 is corrected.;
• • Detecting the frequency and/or period duration and/or the phase position of the reference clock 306 of the low-frequency reference oscillator 505 and determining the deviation of the determined frequency and/or period duration and/or phase position of the reference signal of the input signal 308 from the detected frequency and/or period duration and/ or phase position of the reference clock 306 of the low-frequency reference oscillator 505 and/or the deviation of the determined parameters of the reference signal of the input signal 308 from the corresponding values of the parameters of the reference clock 306 of the low-frequency reference oscillator 505 corresponding to these in the fourth step. For this fourth step it is necessary that the proposed device knows the frequency or period of the reference signal of the input signal 308. However, this does not necessarily limit the method to a single valid frequency interval of the frequency of the reference signal of the input signal 308 or to a single valid period duration interval of the period duration of the reference signal of the input signal 308. Several different, previously known permissible frequency intervals or period duration intervals (which are defined, for example, by baud rates) are conceivable. These different, previously known permissible frequency intervals or period duration intervals only have to be distinguishable within the framework of the basic accuracy of the frequency or the period duration of the high-frequency clock 303 of the high-frequency oscillator 502 of the proposed device 300, i.e. they have to be and may be spaced apart from one another in the frequency range or period duration range do not overlap. If the frequency or period duration of the high-frequency clock 303 of the high-frequency oscillator 502 of the proposed device has a basic accuracy of ±5%, for example without an external reference signal of the input signal 308, this results in a very fine granularity of distinguishable possible reference signals of the input signal 308, which the proposed device 300 can be used as a reference signal. In this step, the proposed device 300 determines the deviation of the frequency and/or period duration and/or phase position of the reference signal input signal 308 from the frequency and/or period duration and/or phase position of the reference clock 306 of the low-frequency reference oscillator 505. Preferably, the proposed device 300 can Use high-frequency clock 303 of high-frequency oscillator 502 to measure the duration of a certain number of clocks of reference clock 306 of reference oscillator 505, for example by counting the clocks of high-frequency clock 303 in this period.
• • Correcting the frequency and/or period length and/or phase position of the reference clock 306 of the low-frequency reference oscillator 505 by this specific deviation and/or a value associated with this deviation or by a value that depends on this deviation in the fourth step by means of the activated second FLL or PLL control loop 324, which includes the reference oscillator 505. The proposed device 300 now corrects the frequency and/or period duration and/or phase position of the reference clock 306 of the low-frequency reference oscillator 505 by the previously determined deviation or a value derived therefrom. If, for example, the course of the trimming curve of the frequency or period duration or phase position of the reference oscillator 505 is known, the correction of the frequency and/or period duration and/or the phase position of the reference clock 306 can be carried out directly, taking into account the trimming curves or trimming step sizes, by means of calculation, for example by the controller 311 done;
• • Determining the sufficient correction of the frequency and/or period duration and/or phase position of the reference clock 306 of the low-frequency reference oscillator 505 by means of the reference measuring device 507 for measuring the frequency or period duration or the phase position of the low-frequency reference clock 306 and the target value calculation 510 for the measured value of the low-frequency Reference clock 306, inactivation of the second FLL or PLL control loop 324 through the control 311 of the proposed device 300 or another sub-device of the proposed device 300 and final reactivation of the first FLL or. PLL control loop 324 to complete the correction in a fifth step, and
• • Correction and regulation of the frequency and/or period length and/or phase position the high-frequency clock 303 of the high-frequency oscillator 502 in this fifth step by means of the first FLL or PLL control loop 324 in the normal state 400.

The advantage of the method presented here is that it is possible to use the frequency, period and phase position of the high-frequency clock 303, for example in the case of data communication via a LIN data bus, after a single LIN Sync Field of data communication via a LIN data bus as a synchronization signal To bring the input signal 308 to a frequency or period and phase position that corresponds to the target frequency or target period or target phase position with very good accuracy. The use of the high-frequency clock 303 as a system clock, for example of the controller 311, the other digital parts of the proposed device 300 or a computer system that evaluates the data from the input signal 308, which is preferably a data bus signal, is particularly useful. For this purpose, the proposed device 300 does not require a frequently recurring, high-precision reference signal in the input signal 308. A very rare reference signal is sufficient for the proposed device 300. Instead of a complete sync field, a previously known individual signal of a proposed device 300 with a known duration or a previously known data content can also be used.

The method can also be combined, for example, with the already known auto baud rate determination for serial communication such as LIN. It should be noted that step 4 requires a certain amount of time to complete. Depending on the specific design, this can be longer than the time between, for example, the end of the LIN sync field as a reference signal and the start of the actual data transmission in a LIN data frame. If this is to be expected, at least step 5, and possibly also step 4, will not be carried out immediately after the end of the sync field, i.e. the reference signal, but the start of the execution of these steps will be delayed until the end of the communication, here the Lin data communication . The communication itself is secured by the auto baud rate generation, even with a different high-frequency clock 303. After the communication has ended, there is still enough time to carry out steps 4 and 5 (states 405, 406 and 407).

If, unexpectedly, a new sync field, i.e. a new reference signal in the input signal 308, arrives as the start of a new data transmission during the execution of steps 4 or 5 (states 405, 406 and 407), the method can at any time go from one of these steps to step 1 (normal state 400). The communication itself is then secured again via the well-known auto baud rate detection. In this special case, the high-frequency clock 303 gradually approaches the desired target accuracy of the high-frequency clock 303.

The system of the proposed device 300 may include means (e.g. 310, 311) for identifying the completion of step 5 (states 406 and 407). The identification of the completion of step 5 (states 406 and 407) by the means (e.g. 310, 311) for identifying the completion of step 5 (states 406 and 407) preferably signals to the higher-level system that the target accuracy of the high-frequency clock 303 of the high-frequency oscillator 502 was reached.

The implementation requires a low-frequency reference oscillator 505 to generate the low-frequency reference clock 306 and a high-frequency, adjustable oscillator 502 to generate the high-frequency clock 303. The low-frequency reference oscillator 505 serves as a reference for generating the high-frequency clock 303, for example in the form of the said first FLL or PLL. Control loop 323. (FLL=frequency locked loop; PLL=phase locked loop) This already has a certain basic accuracy g ₁ even without an additional, highly precise external reference signal of the input signal 308, which, according to the proposal, needs to be improved here with the external reference signal of the input signal 308 . The sequence of the method that the proposed device 300 preferably carries out to increase accuracy is typically as described above.

Alternatively, if the reference oscillator 701 is not adjustable, the proposed device can correct the division ratio of the control loop in accordance with the determined deviation. However, this requires a correspondingly fine-grained division ratio. This can be generated, for example, by using non-integer dividers in the proposed device.

• • Im Schritt 4 (Zustände 406 und 407) die Korrektur nur noch um eine bestimmte Anzahl von Trimmschrittweiten erfolgt oder auf diese begrenzt wird, insbesondere auf einen Trimmschritt.
• • Das Anhalten des ersten FLL- oder PLL-Regelkreises 322 in Schritt 1 (Zustände 402 bis 407) aufgrund des bereits vorher erfolgten Abschlusses des Einschwingvorgangs des zweiten FLL- oder PLL-Regelkreises 324 und der Begrenzung der Frequenzänderung bzw. Periodendaueränderung bzw. Phasenlageänderung im Schritt 4 entfallen kann. Dann wird Schritt 5 zum Bestandteil von Schritt 4.

The procedure can also switch to a “fine correction mode” after completing step 5 and achieving target accuracy. The fine correction mode differs from the above sequence in that

• • In step 4 (states 406 and 407) the correction is only made by a certain number of trimming increments or is limited to this, in particular to one trimming increment.
• • Stopping the first FLL or PLL control loop 322 in step 1 (states 402 to 407) due to the previous completion ses of the transient response of the second FLL or PLL control loop 324 and the limitation of the frequency change or period change or phase position change in step 4 can be omitted. Then step 5 becomes part of step 4.

The fine correction mode has the task of correcting only frequency changes and/or period length changes and/or phase position changes that arise, for example, from temperature dependencies or aging during operation.

The method can also be expanded in that after completion of step 5 or when the proposed device 300 is decommissioned, the determined values for the frequency correction or period duration correction or phase position correction of the second FLL or PLL control loop 324 are stored in a non-volatile memory of the proposed device 300 and/or their control 311 are stored. This has the advantage that the next time it is put into operation, the proposed device 300 can then immediately start with a higher basic accuracy of the reference clock 306.

However, the core of the proposal presented here is the process listed above in steps 1 to 5, which allows the target accuracy of the high-frequency clock 303 to be achieved after the presence of an exact reference signal in the input signal 308 once.

Figure 6

The 6 equals to 4 except for the different activity of the first FLL or PLL control loop 323. While in 4 the first FLL or PLL control loop 323 is active in states 402, 403, 404, 405, the first FLL or PLL control loop 323 is inactive in states 402, 403, 404, 405. So while 4 in the states 402, 403, 404, 405 of the detection, evaluation and processing of the values of the reference signal in the input signal 308, the high-frequency clock 303 is regulated and therefore not constant, is in 6 the high-frequency clock 303 is not regulated in the states 402, 403, 404, 405 of the detection, evaluation and processing of the values of the reference signal in the input signal 308 and is therefore constant. This makes measured values that are recorded at different times using the cooking frequency clock 303 comparable.

Figure 7

7 largely corresponds to that 5 . In this respect, the document presented here refers to the corresponding descriptions of the 5 . In contrast to 5 is the reference oscillator 505 5 here in the 7 split into an adjustable second clock divider 702 and a non-adjustable reference oscillator 701. The non-adjustable reference oscillator 701 supplies a structurally fixed or otherwise fixed reference preclock 703. The adjustable second clock divider 702 divides the reference preclock 703 down to the reference clock 306 according to a second division ratio. The second control II 304 preferably supplies a clock divider signal 714 of the second control II 504 instead of the second control signal II 514 of the second control II 504. The second divider ratio of the second clock divider 702 preferably depends on the value of the clock divider signal 714 of the second control II 504. As a result, the second control II 504 can use the clock divider signal 714 to regulate the frequency and/or the period duration and/or the phase position of the reference clock 306, which the second clock divider 702 generates.

Figure 8

8th largely corresponds to that 5 . In this respect, the document presented here refers to the corresponding descriptions of the 5 . In contrast to 5 A reconstruction oscillator 810 and second phase position detector 819 or a second frequency difference detector 819 and a second period difference detector 819 replace the reference measuring device 507 5 and the target value calculation 510 of 5 . In particular, the phase position detector 819 replaces the target value calculation 510 5 , if the reference variable of the second FLL or PLL control loop 324 is the phase position of the reference clock 306. In particular, the frequency difference detector 819 replaces the target value calculation 510 5 , if the command variable of the second FLL or PLL control loop 324 is the frequency of the reference clock 306. In particular, the period difference detector 819 replaces the target value calculation 510 5 , if the reference variable of the second FLL or PLL control loop 324 is the period of the reference clock 306.

The reconstruction oscillator 810 reconstructs the reference signal that only occurs sporadically in the input signal 308, so that a reconstructed reference signal 806 is provided to the proposed device 300 and in particular to the second FLL or PLL control loop 324 continuously and not just sporadically as a target value signal for the control of the reference clock 306 Available. Depending on the valid measured values 517 of the frequency and/or the period duration and/or the phase position of one or more sporadically occurring reference signals of the input signal 308, which are detected by the measuring device 509, the Reconstruction oscillator 810 this reconstructed reference signal 806 from the reference signal of the input signal 308. The frequency and/or the period duration and/or the phase position of this reconstructed reference signal 806 preferably each correspond to a corresponding measured value of the recorded valid measured values 517 of the frequency and/or the period duration and/or or the phase position of one or more sporadically occurring reference signals of the input signal 308, provided that the measuring device 509 detects them. The reconstruction oscillator 810 can, for example, be designed as a clock divider that divides the high-frequency clock 303 down to a reconstructed clock 806. In this case, the division ratio with which the reconstruction oscillator 810 divides the high-frequency clock 303 down to a reconstructed clock 806 preferably depends on one or more of these recorded valid measured values 517 of the frequency and / or the period and / or the phase position of one or more reference signals of the Input signal 308.

Preferably, the measuring device 509 has one or more first measured value memories in which the measuring device 509 stores the measured values of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal 308 that it has acquired after they have been detected by the measuring device 509 before passing them on which the measuring device 509 buffers to the reconstruction oscillator 810. The purpose of this is that these recorded measured values continue to be available even if the reference signal, which only occurs sporadically and typically for a short time, is no longer available on the input signal 308. The measuring device 509 preferably evaluates these recorded measured values, which are preferably measured values of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal 308 and which are then typically located in the one or more first measured value memories. For example, the value of a detected frequency of the reference signal, which is then located in a first memory of the measuring device 509, should preferably lie within a permitted frequency value interval. The measuring device 509 preferably checks this requirement. For example, the value of a detected period duration of the reference signal, which is then located in a first memory of the measuring device 509, should preferably lie within a permitted period duration value interval. The measuring device 509 preferably checks this requirement. For example, the value of a detected phase position of the reference signal, which is then located in a first memory of the measuring device 509, should preferably lie within a permitted phase position value interval. The measuring device 509 preferably checks this requirement. If necessary, the controller 311 can carry out this task instead of the measuring device 509. In this respect, the controller 311 itself can also be part of the measuring device 509 in this sense and, if necessary, also act and be viewed at the same time as a device part of other device parts of the proposed device 300. If the check of these requirements shows that the recorded measured values meet them, the measuring device 509 is more likely to have detected an intact reference signal in the input signal 308. Therefore, the measuring device 509 then uses these measured values, which most likely come from an intact reference signal, to control the second FLL or PLL control loop 324, since their measured values satisfy one or more of the above conditions. These measured values are then valid measured values 517. The measuring device can then also use these measured values to form such valid measured values 517 when using several measured values of different reference signals to form a valid measured value 517. Conversely, if one or more of the above conditions are not met, the measuring device 509 can assume that the recorded measured values do not come from an intact reference signal. The measuring device 509 preferably no longer uses the recorded measured values of a reference signal that is recognized as a possibly not intact reference signal, but rather discards them. The proposed device 300 then preferably increases an error counter by a first error counter increment, which is preferably an integer positive number greater than 0. In the case of a reference signal recognized as probably intact, the proposed device 300 decreases the error counter by a second error counter increment, which is preferably an integer positive number greater than 0. The first error counter increment can be the same as the second error counter increment. If the counter reading of the error counter exceeds a predetermined error counter reading threshold value, the proposed device 300 can signal this information to a higher-level system, for example via a data bus, or keep it ready for the higher-level system to read out this information via the data bus. In the case of a reference signal recognized as probably not intact, the controller 311 preferably increases an error counter in a memory or a register of the controller 311 and/or the proposed device 300 by the first error counter increment, which is preferably an integer positive number greater than 0. In the case of a reference signal recognized as probably intact, the controller 311 decrements the error counter in the memory or the register of the controller 311 and/or the proposed one Device 300 by the second error counter increment, which is preferably an integer positive number greater than 0. The first error counter increment can be the same as the second error counter increment. If the counter reading of the error counter exceeds a predetermined error counter reading threshold value, then, for example, the proposed device 300 and/or the controller 311 can signal this information to a higher-level system, for example via a data bus, or keep it ready for the higher-level system to read out this information via the data bus. If the measured values in the first memories of the measuring device 509 meet the above conditions, the measuring device 509 considers these measured values to be valid measured values and stores these measured values in a second memory of the measuring device 509 as valid measured values, for example of the frequency and/or period length and/or phase position of the reference signal in the input signal 308 in the second memory of the measuring device and overwrites any existing measured values there. After the system starts the proposed device 300, there are preferably valid starting values in the second memories of the measuring device 509, which ensure that the system of the proposed device 300 starts up with presumably sensible starting values. Preferably, the measuring device 509 transmits only the valid measured values of the reference signal assessed as most likely intact, which are located in its second memories, as valid measured values 517 of the frequency or period or phase position of one or more sporadically occurring valid reference signals of the input signal 308 to the reconstruction oscillator 810 , which generates the reconstructed reference signal 806 from the high-frequency clock 303 depending on these transmitted valid measured values. The measuring device 509 preferably stores these valid measured values in said one or more second memories until the measuring device 509 has again detected new valid measured values of a temporally subsequent and newly occurring reference signal of the input signal 308 and evaluated them as valid. Until the measuring device 509 has again acquired new valid measured values of a subsequent reference signal of the input signal 308, the measuring device 509 preferably continuously outputs the measured values stored in the one or more second memories to the reconstruction oscillator 810 as valid measured values. The valid measured values stored in the one or more second memories thus preferably influence the generation of the reconstructed reference signal 806 by the reconstruction oscillator 810 as described above.

The second phase position detector 819 or the second frequency difference detector 819 or the second period duration difference detector 819 generate the depending on the difference between the values of the frequency or between the values of the period duration or between the values of the phase position of the reconstructed reference signal 806 on the one hand and the corresponding one Values of the frequency or the period duration or phase position of the reference clock 306, on the other hand, the deviation signal 818. The value of the deviation signal 818 preferably represents a) the value of the phase position difference between the phase position of the reconstructed reference signal 806 and the phase position of the reference clock 306 and / or b). Value of the frequency difference between the frequency of the reconstructed reference signal 806 and the frequency of the reference clock 306 and / or c) the value of the period duration difference between the period duration of the reconstructed reference signal 806 and the period duration of the reference clock 306 and / or values derived from these, which have a similar or can fulfill an analog function within the second FLL-PLL control loop 324. For example, the value of the deviation signal 818 may represent a value that is proportional to a) the value of the phase position difference between the phase position of the reconstructed reference signal 806 and the phase position of the reference clock 306 and/or to b) the value of the frequency difference between the frequency of the reconstructed reference signal 806 and the frequency of the reference clock 306 and/or c) the value of the period duration difference between the period duration of the reconstructed reference signal 806 and the period duration of the reference clock 306. The second control II 504 of the second FLL or PLL control loop 324 also generates in the example 8th a second control signal II 514 of the second control II 504 of the second FLL or PLL control loop 324. The second control II 504 of the second FLL or PLL control loop 324 controls the reference oscillator 505 with an adjustable frequency or an adjustable period or an adjustable phase by means of this a second control signal II 514. The second control II 504 of the second FLL or PLL control loop 324 thus controls, for example, the frequency and / or period duration and / or the phase of the reference clock 306 of the reference oscillator 505 depending on the reconstructed reference signal 806. The Values of the frequency and/or the period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 thus preferably depend on the corresponding values of the frequency and/or the period duration and/or the phase position of the reconstructed reference signal 806 from. The FLL or PLL control loop 324 particularly preferably regulates the phase position. Accordingly, the phase position detector 819 particularly preferably detects the phase difference (phase difference) between these signals 806 and 306. Thus the frequency and/or the period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 thus preferably depend on values of the deviation of the reconstructed reference signal 806 from the corresponding values of the reference clock 306, which the second Phase position detector 819 or the second frequency difference detector 819 or the second period duration difference detector 819 determine and signal it to the second control system II 504 by means of the deviation signal 818. The deviation signal 818 of the phase position detector 819 or the frequency difference detector 819 or the period duration difference detector 819 for the deviation of the frequency or the period duration or the phase position between the reconstructed reference signal 806 and the reference clock 306 thus controls the reference oscillator 505 and thus the frequency and/or Period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324. In the example, the second FLL or PLL control loop 324 includes the 8th thus a reconstruction oscillator 810, which further processes the reference signal that occurs sporadically in the input signal 308 at least in the times when the reference signal in the input signal 308 is not available or is no longer available, while maintaining the most important parameters of the last valid reference signal or several of the last valid reference signals generated, so that a parameter-like time reference of the proposed device 300 is also available at such times. These most important parameters can be, for example, the values of the frequency, the period length and the phase position. For this purpose, the reconstruction oscillator 810 preferably generates, depending on the valid measured values 517 of the frequency or period duration or phase position of one or more sporadically occurring valid reference signals of the input signal 308, a preferably continuous reconstructed reference signal 806, which is a temporally continuous extension of the occurred Reference signal essentially corresponds. The values of the parameters of the reconstructed reference signal 806 therefore essentially preferably correspond to the valid measured values 517 of the parameters of one or more of the sporadically occurring valid reference signals of the input signal 308. The reconstruction oscillator 810 preferably generates valid measured values of the parameters 517 as a function of the measuring device 509 detected one or more valid reference signals of the input signal 308, thus a reconstructed reference signal 806 from the high-frequency clock 303. For example, the reconstruction oscillator 810 can be a further divider which converts the high-frequency clock according to a division ratio to the reconstructed reference signal 806 depending on the values determined by the measuring device 509 recorded valid measured values of the parameters 517 of one or more valid reference signals occurring sporadically in the input signal 308 so that the reconstructed reference signal 806 has the most important valid parameters of the valid reference signal occurring sporadically in the input signal 308. These most important parameters can again be, for example, the values of the frequency, the period length and the phase position. The reconstruction oscillator 810 therefore preferably has this further clock divider. This further clock divider preferably generates the reconstructed reference signal 806 from the high-frequency clock 303 by means of a clock divider with said associated division ratio by clock division of the high-frequency clock 303 in accordance with this division ratio. This division ratio, as described, preferably depends on the valid measured values of parameters 517 recorded by the measuring device 509 one or more valid reference signals of the input signal 308 and/or the most important parameters derived therefrom. In particular, the division ratio can be proportional or inversely proportional to the values of such valid parameters or, for example, a time integral of such values or their reciprocals or other values derived from these valid parameters. The valid parameters can, for example, be the values of the frequency, the period length and the phase position.

The second FLL or PLL control loop 324 preferably has the second phase position detector 819 and/or the second frequency difference detector 819 and/or the second period duration difference detector 819. As a result, the proposed device 300 can detect a deviation between the frequency or the period duration or the phase position of the reference clock 306 and the frequency or the period duration or the phase position of the reconstructed reference signal 806. The second FLL or PLL control loop 324 8th In this sense, a real PLL (phase locked loop) with a phase position detector 819 is particularly preferred. The second phase position detector 819 compares the reconstructed reference signal 806 with the reference clock 306 and/or the second frequency difference detector 819 compares the reconstructed reference signal 806 with the reference clock 306 and/or the second Period duration difference detector 819 the reconstructed reference signal 806 with the reference clock 306. Depending on the result of this comparison, the second phase position detector 819 generates a deviation signal of the phase position detector 819 for the deviation of the phase position between the reconstructed reference signal 806 on the one hand and the reference clock 306 on the other on the side. Alternatively, depending on the result of this comparison, the second frequency difference detector 819 generates a deviation signal for the deviation of the frequency between the reconstructed reference signal 806 on the one hand and the reference clock 306 on the other hand. Alternatively, depending on the result of this comparison, the second period duration difference detector 819 generates a deviation signal of the period duration difference detector 819 for the deviation of the period duration between the reconstructed reference signal 806 on the one hand and the reference clock 306 on the other hand.

For the duration of the measurement, evaluation and reconstruction of the reference signal of the input signal 308 by the reference oscillator 810, the controller 311 preferably deactivates the first FLL or PLL control loop 323. This means that the high-frequency clock 303 is for the duration of the measurement, evaluation and reconstruction of the reference signal of the Input signal 308 through the measuring device 509 is typically essentially constant in terms of frequency and/or period length and/or phase position. The second FLL or PLL control loop 324 readjusts the phase position of the reference clock 306 until the values of the parameters (frequency, period duration, phase position) of the reference clock 306 except for the control error with the corresponding valid measured values of the parameters 517 of one or more reference signals of the input signal 308 match.

Figure 9

9 largely corresponds to that 5 . In this respect, the document presented here refers to the corresponding descriptions of the 5 . In 5 the second FLL and PLL control loop 324 used a target value calculation 510. In 5 the target value calculation 510 calculated the value of a deviation signal 518 and, using this deviation signal 518, transmitted this value of the deviation to the second controller II 504 of the second FLL or PLL control loop 324. The value of the deviation signal 518 of the target value calculation 510 represented in 5 typically the value of the deviation between the measured values of the frequency and / or the period duration and / or the phase position of the reference clock frequency measured value signal 516 or reference clock period duration measured value signal 516 or the reference clock phase position measured value signal 516 on the one hand and the valid measured values 517 of the frequency or the period duration or the phase position of one or several of the last valid reference signals in the input signal 308 on the other hand.

The proposed device 300 of 9 now instead comprises a comparator 910. The comparator 910 preferably determines the value of the deviation between the measured values of the frequency and/or the period duration and/or the phase position of the reference clock frequency measured value signal 516 or reference clock period duration measured value signal 516 or of the reference clock phase position measured value signal 516 on the one hand and the valid measured values 517 of the Frequency or the period duration or the phase position of one or more of the last valid reference signals in the input signal 308 on the other hand and forms a comparison result in the form of a comparison result signal 918. For this purpose, the comparator 910 preferably determines the difference between the value of the deviation between the measured values of the frequency and/or or the period duration and/or the phase position of the reference clock frequency measured value signal 516 or the reference clock period duration measured value signal 516 or the reference clock phase position measured value signal 516 on the one hand and the corresponding valid measured values 517 of the frequency or the period duration or the phase position of one or more of the last valid reference signals in the input signal 308 on the other hand . The comparator 910 preferably forms the comparison result signal 918 depending on this difference. Typically, the value of the comparison result signal 918 is proportionally dependent on this difference. The value of the comparison result signal 918 may optionally be equal to the value of this difference. With the help of the high-frequency clock 303, the frequency-corrected oscillator 920 generates the frequency-corrected reference signal 960. The frequency-corrected reference signal 960 is preferably continuous and does not only occur sporadically like the reference signals in the input signal 308. The values of the parameters of the frequency-corrected reference signal 960 preferably correspond to the corresponding valid measured values of the parameters 517 of one or more of the last valid reference signals in the input signal 308. The frequency-corrected reference signal 918 is therefore significantly more suitable for the control than the reference signals of the input signal 308. Like in the 8th includes the second FLL or PLL control loop 324 in the example of 9 a second phase position detector 819 or a second frequency difference detector 819 or a second period duration difference detector 819. This is particularly preferred in the case of 9 the use of a second phase position difference detector 819 if the reference variable of the second FLL or PLL control loop 324 is the phase position of the reference clock 306 relative to the frequency-corrected reference signal 906. This is particularly preferred here in the case of 9 the use of a second frequency difference detector 819 if the command variable of the second FLL or PLL control loop 324 is the frequency of the reference Renztakts is 306. This is particularly preferred here in the case of 9 the use of a second period duration difference detector 819 if the reference variable of the second FLL or PLL control loop 324 is the period duration of the reference clock 306.

The frequency-corrected oscillator 920 reconstructs, depending on the comparison result 918, the reference signal that only occurs sporadically in the input signal 308 and thus generates the frequency-corrected reference signal 906, so that the frequency-corrected reference signal 906 of the proposed device 300 and in particular the second FLL or PLL control loop 324 continuously and is not only available sporadically as a target value signal for regulating the reference clock 306. Depending on the valid measured values 517 of the frequency and/or the period duration and/or the phase position of one or more sporadically occurring valid reference signals of the input signal 308 detected by the measuring device 509, the frequency-corrected oscillator 920 therefore generates this frequency-corrected reference signal 906 from one or more valid reference signals of the input signal 308. The frequency and/or the period duration and/or the phase position of this frequency-corrected reference signal 906 preferably each correspond to a corresponding valid measured value of the recorded valid measured values 517 of the frequency and/or the period duration and/or the phase position of one or more of the sporadic occurring valid reference signals of the input signal 308, provided that the measuring device 509 has detected them. The frequency-corrected oscillator 920 can, for example, be designed as a clock divider that divides the high-frequency clock 303 down to a frequency-corrected reference signal 906. In this case, the division ratio with which the frequency-corrected oscillator 920 divides the high-frequency clock 303 down to a frequency-corrected reference signal 906 preferably depends on one or more of these recorded valid measured values 517 of the frequency and / or the period and / or the phase position of one or more of the valid reference signals of the input signal 308.

Preferably, the measuring device 509 has one or more first measured value memories in which the measuring device 509 stores the measured values of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal 308 that it has acquired after they have been detected by the measuring device 509 before passing them on which the measuring device 509 buffers to the comparator 910. The purpose of this is that these recorded measured values continue to be available even if the reference signal, which only occurs sporadically and typically for a short time, is no longer available on the input signal 308. The measuring device 509 preferably evaluates these recorded measured values, which are preferably measured values of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal 308 and which are then typically in the one or more first measured value memories of the measuring device 509 condition. For example, the value of a detected frequency of the reference signal, which is then located in a first memory of the measuring device 509, should preferably lie within a permitted frequency value interval. The measuring device 509 preferably checks this requirement. For example, the value of a detected period duration of the reference signal, which is then located in a first memory of the measuring device 509, should preferably lie within a permitted period duration value interval. The measuring device 509 preferably checks this requirement. For example, the value of a detected phase position of the reference signal, which is then located in a first memory of the measuring device 509, should preferably lie within a permitted phase position value interval. The measuring device 509 preferably checks this requirement. If necessary, the controller 311 can carry out this task instead of the measuring device 509. In this respect, the controller 311 itself can also be part of the measuring device 509 in this sense and, if necessary, also act and be viewed at the same time as a device part of other device parts of the proposed device 300. If the check of these requirements shows that the recorded valid values 517 of the parameters of one or more reference signals of the input signal 308 meet them, then the measuring device 509 is more likely to have detected an intact reference signal in the input signal 308. Therefore, the measuring device 509 then uses these measured values, which most likely come from an intact reference signal, or values derived from them, as valid measured values 517 for the control of the second FLL or PLL control loop 324, since their measured values meet one or more of the above conditions suffice. Conversely, if one or more of the above conditions are not met, the measuring device 509 can assume that the recorded measured values do not come from an intact reference signal. The measuring device 509 preferably no longer uses the recorded measured values of a reference signal that is recognized as a possibly not intact reference signal, but rather discards them. The proposed device 300 then preferably increases an error counter by a first error counter increment, which is preferably an integer positive number greater than 0. In the case of a reference signal that is recognized as probably intact, the proposed device 300 decreases the value beforehand increases the error counter by a second error counter increment, which is preferably an integer positive number greater than 0. The first error counter increment can be the same as the second error counter increment. If the counter reading of the error counter exceeds a predetermined error counter reading threshold value, the proposed device 300 can signal this information to a higher-level system, for example via a data bus, or keep it ready for the higher-level system to read out this information via the data bus. If the counter reading of the error counter falls below a possibly identical or alternatively different predetermined additional error counter reading threshold value, the proposed device 300 can also signal this further information to a higher-level system, for example via a data bus, or have it ready for the higher-level system to read out this information via the data bus. In the case of a reference signal recognized as probably not intact, the controller 311 preferably increases an error counter in a memory or a register of the controller 311 and/or the proposed device 300 by the first error counter increment, which is preferably an integer positive number greater than 0. In the case of a reference signal recognized as probably intact, the controller 311 preferably decreases the error counter in the memory or the register of the controller 311 and/or the proposed device 300 by the second error counter increment, which is preferably an integer positive number greater than 0. The first error counter increment can be the same as the second error counter increment. If the counter reading of the error counter exceeds a predetermined error counter reading threshold value, then, for example, the proposed device 300 and/or the controller 311 can signal this information to a higher-level system, for example via a data bus, or keep it ready for the higher-level system to read out this information via the data bus. If the counter reading of the error counter falls below a possibly identical or alternatively different predetermined additional error counter reading threshold value, the proposed device 300 can also signal this further information to a higher-level system, for example via a data bus, or have it ready for the higher-level system to read out this information via the data bus. If the measured values in the first memories of the measuring device 509 meet the above conditions, the measuring device 509 considers these measured values to be valid measured values and stores these measured values in a second memory of the measuring device 509 as valid measured values, for example of the frequency and/or period length and/or phase position of a or several valid reference signals in the input signal 308 in second memories of the measuring device and overwrites any valid measured values that already exist there. After the system starts the proposed device 300, there are preferably valid starting values in the second memories of the measuring device 509 as valid measured values, which ensure that the system of the proposed device 300 starts up with presumably sensible starting values. The measuring device 509 preferably transmits only the measured values of one or more reference signals that are assessed as most likely intact, these measured values being in the second memories of the measuring device 509, as valid measured values 517 to the reconstruction oscillator 810. The comparator 910 determines the difference between the valid measured values one or more reference signals of the input signal 308 on the one hand and the corresponding measured values of the reference clock frequency measured value signal 516 or the reference clock period duration measured value signal 516 or the reference clock phase position measured value signal 516 of the reference clock 306 on the other hand, if necessary using the high-frequency clock 303. The measuring device 509 preferably stores these valid measured values in the said one or several second memories until the measuring device 509 has again recorded new valid measured values of a temporally subsequent and newly occurring reference signal of the input signal 308 and evaluated them as valid. Until the measuring device 509 has again detected new valid measured values of a subsequent reference signal of the input signal 308 and evaluated them as valid, the measuring device 509 preferably passes on the measured values stored in the one or more second memories to the reconstruction oscillator 810 as valid measured values, preferably continuously to the comparator 910 out. The valid measured values stored in the one or more second memories thus preferably influence the generation of the error-corrected reference signal 906 by the frequency-corrected oscillator 920 as described above.

The second phase position detector 819 or the second frequency difference detector 819 or the second period duration difference detector 819 generate the signal depending on the difference between the frequency values or between the period duration values or between the phase position values of the error-corrected reference signal 906 on the one hand and the corresponding one Values of the frequency or the period duration or phase position of the reference clock 306, on the other hand, the deviation signal 818. The value of the deviation signal 818 preferably represents a) the value of the phase position difference between the phase position of the error-corrected reference signal 906 and the phase position of the reference clock 306 and / or b). Value the frequency difference between the frequency of the error-corrected reference signal 906 and the frequency of the reference clock 306 and / or c) the value of the period duration difference between the period duration of the error-corrected reference signal 906 and the period duration of the reference clock 306 and / or values derived from these, which are a similar or analog Function within the second FLL-PLL control loop 324 can fulfill. For example, the value of the deviation signal 818 may represent a value that is proportional to a) the value of the phase position difference between the phase position of the error-corrected reference signal 906 and the phase position of the reference clock 306 and/or to b) the value of the frequency difference between the frequency of the error-corrected reference signal 906 and the frequency of the reference clock 306 and/or c) the value of the period duration difference between the period duration of the error-corrected reference signal 906 and the period duration of the reference clock 306. The second control II 504 of the second FLL or PLL control loop 324 also generates in the example 9 a second control signal II 514 of the second control II 504 of the second FLL or PLL control loop 324. The second control II 504 of the second FLL or PLL control loop 324 controls the reference oscillator 505 with an adjustable frequency or an adjustable period or an adjustable phase by means of this a second control signal II 514. The second control II 504 of the second FLL or PLL control loop 324 thus controls, for example, the frequency and / or period duration and / or the phase of the reference clock 306 of the reference oscillator 505 depending on the error-corrected reference signal 906. The Values of the frequency and/or the period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324 thus preferably depend on the corresponding values of the frequency and/or the period duration and/or the phase position of the r error-corrected Reference signal 906. The FLL or PLL control loop 324 particularly preferably regulates the phase position. Accordingly, the phase position detector 819 particularly preferably detects the phase difference (phase difference) between these signals, the error-corrected reference signal 906 and the reference clock 306. The frequency and/or the period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL depend on this. or PLL control loop 324 thus preferably depends on values of the deviation of the error-corrected reference signal 906 from the corresponding values of the reference clock 306, which the second phase position detector 819 or the second frequency difference detector 819 or the second period duration difference detector 819 determine and send to the second by means of the deviation signal 818 Signal regulation II 504. The deviation signal 818 of the phase position detector 819 or the frequency difference detector 819 or the period duration difference detector 819 for the deviation of the frequency or the period duration or the phase position between the reconstructed reference signal 806 and the reference clock 306 thus controls the reference oscillator 505 and thus the frequency and/or Period duration and/or the phase position of the reference clock 306 of the reference oscillator 505 of the second FLL or PLL control loop 324. In the example, the second FLL or PLL control loop 324 includes the 9 thus a frequency-corrected oscillator 920, which continues the valid reference signals that occur sporadically in the input signal 308 at least in the times when the valid reference signals in the input signal 308 are not or no longer available, i.e. in the pauses between the occurrence of valid reference signals in the input signal 308 while maintaining the most important parameters of the last valid reference signal or several of the last valid reference signals, so that a time reference of the proposed device 300 that is similar to these valid reference signals is also available at such times. These most important parameters can be, for example, the values of the frequency, the period length and the phase position. For this purpose, the frequency-corrected oscillator 920 preferably generates, depending on the valid measured values of parameters 517 of one or more reference signals that occur sporadically in the input signal 308, a preferably continuous frequency-corrected reference signal 906, which essentially corresponds to a temporally continuous addition to the reference signal that has occurred. The frequency-corrected oscillator 920 preferably generates a reconstructed reference signal 806 from the high-frequency clock 303 depending on the valid parameters 517 of one or more reference signals of the input signal 308 detected by the measuring device 509. For example, the error-corrected oscillator 920 can be a further divider, which divides the high-frequency clock 303 according to a division ratio to the error-corrected reference signal 906 depending on the valid measured values of the parameters 517 of one or more valid reference signals that occur sporadically in the input signal 308, recorded by the measuring device 509, in such a way that the error-corrected reference signal 906 contains the most important valid parameters of one or more which has several valid reference signals occurring sporadically in the input signal 308. These most important parameters can again be, for example, the values of the frequency, the period length and the phase position. The frequency-corrected oscillator 920 therefore preferably has this further clock divider. This further clock divider generates preferentially by means of a clock divider with said associated divider ratio by clock division of the high-frequency clock 303 in accordance with this divider ratio, the frequency-corrected reference signal 906 from the high-frequency clock 303. As described, this divider ratio preferably depends on the valid values of the parameters 517 of the one or more detected by the measuring device 509 Reference signals of the input signal 308 and/or values of the most important parameters derived therefrom. In particular, the division ratio can be proportional or inversely proportional to the valid values of such valid parameters or, for example, a time integral of such valid values or their reciprocals or other values derived from these valid values of the parameters of one or more reference signals of the input signal 308. The valid parameters can, for example, be the values of the frequency, the period length and the phase position.

The second FLL or PLL control loop 324 preferably has the second phase position detector 819 and/or the second frequency difference detector 819 and/or the second period duration difference detector 819. As a result, the proposed device 300 can detect a deviation between the frequency or the period duration or the phase position of the reference clock 306 and the frequency or the period duration or the phase position of the frequency-corrected reference signal 906. The second FLL or PLL control loop 324 9 In this sense, a real PLL (phase locked loop) with a phase position detector 819 is particularly preferred. The second phase position detector 819 compares, if necessary, the error-corrected reference signal 906 with the reference clock 306. The second frequency difference detector 819 possibly compares the error-corrected reference signal 906 with the reference clock 306. The second period duration difference detector 819 compares, if necessary, the error-corrected reference signal 906 with the reference clock 306. Depending on the result of this comparison, the second phase position detector 819 generates a deviation signal of the phase position detector 819 for the deviation of the phase position between the error-corrected reference signal 906 on the one hand and the reference clock 306 on the other hand. Alternatively, depending on the result of this comparison, the second frequency difference detector 819 generates a deviation signal for the deviation of the frequency between the error-corrected reference signal 906 on the one hand and the reference clock 306 on the other hand. Alternatively, depending on the result of this comparison, the second period duration difference detector 819 generates a deviation signal of the period duration difference detector 819 for the deviation of the period duration between the error-corrected reference signal 906 on the one hand and the reference clock 306 on the other hand.

For the duration of the measurement, evaluation and reconstruction of the reference signal of the input signal 308 by the error-corrected oscillator 920, the controller 311 preferably deactivates the first FLL or PLL control loop 323. As a result, the high-frequency clock 303 is for the duration of the measurement, evaluation and reconstruction of the reference signal of the input signal 308 through the measuring device 509 is typically essentially constant in terms of frequency and/or period length and/or phase position. The second FLL or PLL control loop 324 readjusts the phase position of the reference clock 306 until the values of the parameters (frequency, period duration, phase position) of the reference clock 306, except for the control error, match the corresponding valid values of the valid parameters 517 of the reference signal .

Figure 10

10 represents a simplification of the technical teaching of the 9 A reconstruction oscillator 810 generates the reference signal as a continuous reconstructed reference signal 806 as a continuous reconstructed reference signal 806 as a function of the detected valid measured values of the frequency and/or the period duration and/or the phase position of one or more valid reference signals of the input signal 308 8th . However, the phase position detector 819 does not now use the reference clock 306 for comparison with the reconstructed reference signal 806. Instead, a clock divider 1024 divides the reference clock 306 into a divided reference clock 1025. This allows the frequency range of the frequency of the reference clock 306 to be chosen more freely in the design depending on the application . The phase layer 819 or the frequency difference detector 819 or the period duration duration detector 819 compare the reference act 306 with the reconstructed reference signal 806 and form the deviation signal 1018 of the phase -laying detector 819 or the period duration duration difference in 81 9 for the deviation of the frequency or the period period or .The phase position between the reconstructed reference signal 806 and the divided reference clock 1025, which the phase position detector 819 or the frequency difference detector 819 or the period duration difference detector 819 then signals to the second controller II 504.

For example, the frequency difference detector 819 can compare the value of the frequency of the reconstructed reference signal 806 with the value of the frequency of the divided reference clock 1025 and, as a comparison result, a value of the deviation between the value of the frequency of the reconstructed reference signal 806 and the value of the frequency of the divided reference clock 1025. The frequency difference detector 819 preferably transfers this determined value of the deviation or a value derived therefrom as the value of the deviation signal 1018 to the second controller II 504.

For example, the phase position detector 819 can compare the value of the phase position of the reconstructed reference signal 806 with the value of the phase position of the divided reference clock 1025 and, as a comparison result, determine a value of the deviation between the value of the phase position of the reconstructed reference signal 806 and the value of the phase position of the divided reference clock 1025. The phase position detector 819 preferably transfers this determined value as the value of the deviation or a value derived therefrom as the value of the deviation signal 1018 to the second controller II 504.

For example, the period duration difference detector 819 can compare the value of the period duration of the reconstructed reference signal 806 with the value of the period duration of the divided reference clock 1025 and, as a comparison result, determine a value of the deviation between the value of the period duration of the reconstructed reference signal 806 and the value of the period duration of the divided reference clock 1025. The period duration difference detector 819 preferably transfers this determined value of the deviation or a value derived therefrom as the value of the deviation signal 1018 to the second controller II 504.

As before, the second control II 504 preferably forms the control signal II 514 of the second control II 504 depending on the deviation signal 1018. The second control II 504 is preferred, as is also the case elsewhere in this document, a PI controller or the like. The adjustable reference oscillator 505 generates the reference clock 306 depending on the control signal II 514 of the second control II 504, which closes the control loop of the second FLL or PLL control loop 324. Otherwise it corresponds 10 the 8th .

Figure 11

11 shows a particularly simple version of a proposed device 300. A fixed-frequency reference clock oscillator 1101 generates the reference clock 306. The frequency and/or the period duration and/or the phase position of the fixed-frequency reference clock oscillator 1101 and thus of the reference clock 306 typically drift. The technical teaching of the 11 now assumes that this drift is so slow that the first FLL or PLL control loop 323 can compensate for this when generating the high-frequency clock 303. The first divider 520 divides the high-frequency clock 303 down to the frequency of the divided high-frequency clock 521 with a divider ratio. Preferably the first divisor in the example divides the 9 the high-frequency clock 303 corresponding to a second divider ratio to the auxiliary clock 1112 of the divider 520. The divider ratio calculation 1110 uses this auxiliary clock 1112 to record a measured value of the frequency and / or the period of this auxiliary clock 1112. The divider ratio calculation 1110 compares the valid measured values 517 of the frequency or period of one or several valid reference signals of the input signal 308 with the measured values of the frequency and / or the period of this auxiliary clock 1112. This results in a relationship between the valid measured values 517 of the frequency or period of one or more valid reference signals of the input signal 308 with the measured values of the frequency and / or the period duration of this auxiliary clock 1112. According to the ratio that deviates from the predetermined ratio 1113, the divider ratio calculation 1110 changes the target divider ratio 1111 of the divider 520. The divider ratio calculation 1110 preferably behaves like a PI controller, so that the target divider ratio 1111 only changes gradually and slowly. However, this change is still faster than the drift of the fixed-frequency reference clock oscillator 1101 and thus the reference clock 306. As a result, the divider ratio calculation 1110 compensates for the drift of the fixed-frequency reference clock oscillator 1101. If necessary, the controller 311 can specify a factor 1113 by which the frequency and / or the period duration of this auxiliary clock 1112 differs from the valid measured values 517 of the frequency or period duration of one or more valid reference signals of the input signal 308 in relation to the steady state.

Advantage

The proposed method and the proposed device have the advantage that it is possible to bring the CPU frequency to a CPU frequency with very good target accuracy of the target frequency after just a single LIN Sync Field of data communication via a LIN data bus corresponds. The proposed device does not require a frequently recurring, high-precision reference signal for this purpose. A very rare reference signal is sufficient for the proposed device. But the advantages are not limited to this.

By using the proposed method, the proposed device can have a reduced inherent accuracy compared to the necessary target accuracy. When implementing the proposed device As a micro-integrated circuit, the testing and calibration effort can be reduced. This saves costs. In addition, the necessary target accuracy can then also be beyond what could be achieved due to temperature changes and aging in a semiconductor process for producing the proposed device without using the proposed method in the proposed device. By using the proposed method, the proposed device can achieve the desired frequency targeting accuracy already after the first sporadically occurring reference signal, e.g. B. after receiving a LIN sync field (LIN synchronization field). The proposed device therefore typically does not require any longer transient response processes across multiple reference signals, for example multiple LIN synchronization fields. A further advantage is that the method proposed in this document is compatible with methods for auto-baud rate detection known from the prior art. It is therefore a proposed idea of the document presented here to combine the method presented here with a known method of auto-baud rate detection.

Reference symbol list

300

proposed device

303

High frequency clock (fast system clock). Preferably, the high-frequency clock also drives the controller 311 and other digital circuits of the device 300 as a system clock;

306

low-frequency reference clock having a reference clock frequency;

308

Input signal, e.g. with synchronization signal, e.g. with synchronization field;

311

Steering;

313

first activation/deactivation signal of the controller 311 for the freezeable control I 501;

323

first FLL or PLL control loop;

324

second FLL or PLL control loop;

325

second activation/deactivation signal of the controller 311 for the second controller II 504;

326

reference signal signaling;

400

Normal state and normal operation of the proposed device 300;

401

detecting a synchronization signal in the form of the reference signal in the input signal 308;

402

State of measurement of the reference signal in input signal 308;

403

State of the evaluation of the reference signal of the input signal 308;

404

deciding whether the reference signal of the input signal 308 is valid;

405

State of measuring the frequency and/or the period duration and/or the phase position of the reference clock 306 and the calculation of the target value of the frequency and/or the period duration and/or the phase position of the reference clock 306;

406

State of the correction of the frequency and/or the period duration and/or the phase position of the reference clock 306 and the control measurement of the frequency and/or the period duration and/or the phase position of the reference clock 306;

407

Test step as to whether the target value of the frequency and/or the period length and/or the phase position has been reached;

501

Regulation I, freezeable;

502

high-frequency oscillator for generating the high-frequency clock (system clock) 303;

504

second regulation II, which can be freezeable;

505

adjustable reference oscillator for generating the reference clock 306;

507

Reference measuring device for measuring the frequency and/or period duration and/or phase shift of the low-frequency reference clock 306;

509

Measuring device for measuring the input signal 308. The measuring device is used in particular to measure the reference signals in the input signal 308;

510

Target value calculation for the measured value of the low-frequency reference clock 306;

514

Control signal II of the second control II 504, with which the freezeable control II 504 controls the reference oscillator 505 with an adjustable frequency and, for example, controls the frequency and / or the phase of the reference clock 306 of the reference oscillator 505 with an adjustable frequency;

515

first control signal I of the first control I 501, with which the first control I 501 controls the high-frequency oscillator 502 and, for example, controls the frequency and/or period duration and/or the phase of the high-frequency clock 303 of the high-frequency oscillator 502;

516

Reference clock frequency measured value signal or reference clock period duration measured value signal or reference clock phase position measured value signal of the reference measuring device 507 for use by the target value calculation 510 for the measured value of the frequency or the period duration or the phase position of the low-frequency reference clock 306;

517

valid measured value of the frequency or another suitable parameter (e.g. the period and/or the phase position) of one or more valid reference signals of the input signal 308 from the measuring device 509 for measuring the input signal 308;

518

Deviation signal of the target value calculation 510 for the measured value of the low-frequency reference clock 306, which is the value of the deviation between the measured value of the frequency and / or the period duration and / or the phase position of the reference clock frequency measured value signal 516 or reference clock period duration measured value signal 516 or the reference clock phase position measured value signal 516 and the valid measured value 517 of the Frequency or the period duration or the phase position of one or more valid reference signals of the input signal 308 is signaled to the second controller II 504;

519

Phase position detector 519 and/or a frequency difference detector 519 and/or a period difference detector 519 of the first FLL or PLL control loop 323;

520

first clock divider;

521

divided down high-frequency clock that the first clock divider 520 divides down from the high-frequency clock 303 with a first division ratio;

522

High-frequency clock frequency measured value signal of the phase position detector 519 of the first control loop for use by the first control I 501 for the measured value of the high-frequency clock 303;

701

non-adjustable reference oscillator;

702

second clock divider;

703

reference preclock;

714

clock divider signal;

806

reconstructed reference signal;

810

Reconstruction oscillator, which generates the reference signal as a reconstructed reference signal 806 depending on the measured values of the frequency and/or the period duration and/or the phase position of the reference signal of the input signal 308;

818

Deviation signal of the phase position detector 819 or the frequency difference detector 819 or the period duration difference detector 819 for the deviation of the frequency or the period duration or the phase position between the reconstructed reference signal 806 and the reference clock 306, that the phase position detector 819 or the frequency difference detector 819 or the period duration difference detector 819 signaled to the second regulation II 504;

819

second phase position detector 819 and / or second frequency difference detector 819 and / or second period duration difference detector 819, which, depending on the difference in frequency and / or period duration and / or phase position between the reconstructed reference signal 806 and the reference clock 306, the deviation signal 818;

906

frequency-corrected reference signal;

910

comparator;

918

comparison result signal;

920

frequency-corrected oscillator;

1018

Deviation signal of the phase position detector 819 or the frequency difference detector 819 or the period duration difference detector 819 for the deviation of the frequency or the period duration or the phase position between the reconstructed reference signal 806 and the divided reference clock 1025, that the phase position detector 819 or the frequency difference detector 819 or the Period duration difference detector 819 signals to the second control II 504;

1024

Clock divider for the reference clock 306;

1025

shared reference clock 1025;

1101

fixed frequency reference clock oscillator;

1110

divider ratio calculation;

1111

520 divider ratio;

1112

auxiliary cycle;

1113

factor (factor signaling);

Closing remarks

The above description is not intended to be complete and does not limit this disclosure to the examples shown. Other variations to the disclosed examples may be understood and accomplished by those of ordinary skill in the art from the drawings, disclosure and claims. The indefinite articles “a” or “an” and their inflections do not exclude a plurality, while the mention of a certain number of elements does not exclude the possibility that there are more or fewer elements. A single unit may perform the functions of multiple elements mentioned in the disclosure, and conversely, multiple elements may perform the functions of one unit. Numerous alternatives, equivalents, variations and combinations are possible without departing from the scope of the present disclosure.

Unless otherwise stated, all features of the present invention can be freely combined with one another. This applies to the entire document presented here. Unless otherwise stated, the features described in the description of the figures can also be freely combined with the other features as features of the invention. A limitation of individual features of the exemplary embodiments to the combination with other features of the exemplary embodiments is expressly not intended. In addition, objective features of the device can also be used reformulated as process features and process features can be reformulated as objective features of the device. Such a reformulation is therefore automatically disclosed.

In the foregoing detailed description, reference is made to the accompanying drawings. The examples in the specification and drawings should be considered as illustrative and are not to be viewed as limiting the specific example or element described. Several examples can be derived from the preceding description and/or the drawings and/or the claims by modifying, combining or varying certain elements. In addition, examples or elements not described literally may be derived from the description and/or drawings by a person skilled in the art.

List of Scriptures Cited

• DE 19 619 509 C1 ,
• EP 1 971 069 A1 ,
• US 4,115,811 A ,
• US 6,097,754 ,
• US 2002 / 0 101 884 A1 ,
• US 2005/ 0 024 111 A1
• WO 1993 010 605 A1 ,
• WO 1999 055 088 A1
• https://www.ni.com/de-de/innovations/white-papers/06/analog-video-101.html,
• https://www.ni.com/de-de/innovations/white-papers/06/analog-video-101.html
• Infineon Technologies “Preliminary User's Manual TVTEXT PRO SDA 55xx”, Version 1.21 July 99, Chapter 5, with special emphasis on Chapter 5.2.2 “Data Separation”.
• Standard “Enhanced Teletext specification” EUROPEAN TELECOMMUNICATION STANDARD ETS 300 706, May 1997, EBU/CENELEC/ETSI JTC, DE/JTC-TTEXT-EACEM, in particular “Figure 4: Clock run-in, framing code and timing reference”.

Claims (64)

Device for generating a high-frequency clock (303), wherein the device has a controller (311) and wherein the device has a first FLL or PLL control circuit (323) and wherein the device has a second FLL or PLL Control loop (324) and wherein the device has an input signal (308) and wherein a reference signal occurs temporarily and / or sporadically as part of the input signal (308) and wherein the second FLL or PLL control loop (324) is set up to have a Generate reference clock (306) as a target signal of the second FLL or PLL control loop (324) as a function of one or more reference signals of the input signal (308) when the second FLL or PLL control loop (324) is active, and wherein the second FLL or PLL control loop (324) is set up to use the reference clock (306) as a target signal of the second FLL or PLL control loop (324) to generate when the second FLL or PLL control loop (324) is inactive, and wherein the first FLL or PLL control loop (323) is set up to generate a high-frequency clock (303) depending on the Generate reference clock (306) as a target signal of the first FLL or PLL control loop (323) when the first FLL or PLL control loop (323) is active, and wherein the first FLL or PLL control loop (323) is set up to continue the high-frequency clock (303) as a target signal of the first FLL or PLL control loop (323) depending on the state of the reference clock (306) to the last active state of the first FLL or PLL control loop (323). to be generated when the first FLL or PLL control loop (323) is inactive, and wherein the frequency of the high-frequency clock (303) is greater in magnitude than the frequency of the reference clock (306) or the period duration of the high-frequency clock (303) is smaller in magnitude is the period duration of the reference clock (306) and wherein the controller (311) is set up to set the second FLL by means of a second activation/inactivation signal (325) of the controller (311) in a normal state (400) of the proposed device (300). - or PLL control loop (324) and wherein the controller (311) is set up to use a first activation/inactivation signal (313) of the controller (311) in the normal state (400) of the proposed device (300). FLL or PLL control loop (323) to activate and wherein the controller (311) is set up to detect the arrival of one or more reference signals of the input signal (308) in the normal state (400) or to expect it at a predetermined time or from a device part of the second control loop (324), and wherein the controller (311) and / or device parts of the second FLL or PLL control loop (324) are set up to receive the reference signal serving as a synchronous signal in the input signal (308) in one To measure and, if necessary, evaluate the state (403) of the measurement of the synchronization signal of the input signal (308) and to determine values for parameters of the reference signal serving as a synchronizing signal in the input signal (308), and the controller (311) is set up to do the second The FLL or PLL control loop (324) is then activated and the second FLL or PLL control loop (324) is switched to the state (406) of correcting the frequency or the period duration or the phase position of the reference clock (306). offset so that it tracks the corresponding parameters of the reference clock (306) until they essentially correspond to the determined values for these parameters of one or more of the reference signals serving as synchronous signals in the input signal (308) or values derived therefrom, and the controller (311) does this is set up to then deactivate the second FLL or PLL control loop (324) and thus cause the second FLL or PLL control loop (324) to return to the normal state (400) as soon as the values of the corresponding parameters of the reference clock (306 ) essentially correspond to the determined values for these parameters of the reference signal serving as a synchronizing signal in the input signal (308) or values derived therefrom. Device according to Claim 1 wherein the controller (311) or a device part of the second control circuit (324) is set up to evaluate the values of the measurement of the reference signal in the input signal (308) and to determine an evaluation result. Device according to Claim 2 wherein the controller (311) is set up to allow the device to remain in the normal state (400) with an inactivated second FLL or PLL control loop (324) if the evaluation result includes one or more values that are not within a predetermined value interval or do not correspond to a default value. Device according to one of the Claims 1 until 3 wherein the device is set up to measure the reference signal serving as a synchronization signal in the input signal (308) with the aid of the high-frequency clock (303) and/or a signal derived from the high-frequency clock (303) and/or a signal related to the high-frequency clock (303). signal occurs. Device according to one of the Claims 1 until 4 wherein the device is set up to: Measuring the reference clock (306) within the activated second FLL or PLL control loop (324) using the high-frequency clock (303) and/or a signal derived from the high-frequency clock (303) and/or a signal related to the high-frequency clock (303). he follows. Device according to one of the Claims 1 until 5 , wherein the values for parameters of the reference signal serving as a synchronization signal in the input signal (308), which determine the device parts of the device in the state (403) of measuring the synchronization signal of the input signal (308), at least one or more values of one or more of the following parameters - Number of clocks of the reference signal in the input signal (308) in a predetermined period of time and/or - frequency and/or period duration of the reference signal in the input signal (308) and/or - time duration of a complete clock of the reference signal in the input signal (308) and/or its Reciprocal value and/or - the phase position of the reference signal in the input signal (308) compared to the divided high-frequency clock (521) and/or, - the phase position of the reference signal in the input signal (308) compared to the reference clock (306) and/or - time duration of a low and/or high phase of the clock of the reference signal in the input signal (308) and/or - time duration of a certain number of clocks of the E of the reference signal in the input signal (308) and/or - time duration of a certain number of low and/or Include high phases of the reference signal in the input signal (308). Device according to one of the Claims 1 until 6 , wherein the controller (311) is set up to deactivate the first FLL or PLL control loop (323) before it activates the second FLL or PLL control loop (324) and wherein the controller (311) is set up to to deactivate the second FLL or PLL control loop (324) before activating the first FLL or PLL control loop (323) and Device according to Claim 7 , wherein the controller (311) is designed to deactivate the first FLL or PLL control loop (323) when the device is in a state (402 to 405) that is not the normal state (400). Device according to one of the Claims 1 until 8th , wherein the second FLL or PLL control loop (324) comprises a low-frequency reference oscillator (505) which generates the reference clock (306) with a reference clock frequency and a reference clock phase position, and wherein the controller (311) and / or a device part of the second FLL - or PLL control loop (324) are set up to assign a value of the deviation of the frequency and / or phase position of one or more reference signals of the input signal (308) from the reference clock frequency and / or reference clock phase position of the reference clock (306) of the low-frequency reference oscillator (505). determine. Device according to one of the Claims 1 until 9 , wherein the second FLL or PLL control circuit (324) has a measuring device (509) for measuring the input signal (308), in particular for measuring one or more reference signals that occur sporadically in the input signal (308). Device according to Claim 10 , wherein the measuring device (509) as a device part of the second FLL or PLL control loop (324) is set up to detect the arrival of one or more reference signals of the input signal (308) in the normal state (400) or to the control device (311). signal. Device according to Claim 10 or 11 , wherein the measuring device (509) as a device part of the second FLL or PLL control circuit (324) is set up to measure the reference signal serving as a synchronizing signal in the input signal (308), in particular in a state (403) of measuring the synchronization signal of the input signal (308 ), to measure. Device according to Claim 12 , wherein the measuring device (509) as a device part of the second FLL or PLL control circuit (324) is set up to determine values (517) for parameters of the reference signal serving as a synchronous signal in the input signal (308). Device according to Claim 13 , wherein the values for parameters of the reference signal serving as a synchronous signal in the input signal (308), the measuring device (509) as a device part of the second FLL or PLL control loop (324) determines at least one or more values (517) of one or more of the following Parameters - number of cycles of the reference signal serving as a synchronous signal in the input signal (308), and/or - frequency and/or period duration of one or more reference signals of the input signal (308) and/or - time duration of a complete cycle (Perio duration) of one or more reference signals of the input signal (308) and/or its reciprocal and/or - the phase position of the reference signal in the input signal (308) compared to a divided high-frequency clock (521) and/or, - the phase position of the reference signal in the input signal (308) compared to the reference clock (306) and/or - time duration of a low and/or high phase of the clock of the reference signal in the input signal (308) and/or - time duration of a certain number of clocks of one or more reference signals of the input signal (308) and/or - the duration of a certain number of low and/or high phases of one or more reference signals of the input signal (308). Device one of the Claims 10 until 14 , wherein the reference signal serving as a synchronous signal in the input signal (308) has at least two reference signal features, in particular rising and/or falling edges, and wherein the measuring device (509) is set up to determine the number of clocks of the high-frequency clock (303) and/or one the signal derived from the high-frequency clock (303) and/or a signal associated with the high-frequency clock (303) between the first time of occurrence of a first reference signal feature in the input signal (308) and the second time of occurrence of a second reference signal feature in the input signal (308) and to determine a second count value (517). Device according to Claim 15 , wherein the control device (311) and / or the second FLL or PLL control loop (324) are set up to use this second count value (517) as a measured value (517) of the frequency and / or period and / or phase position of one or more reference signals of the input signal (308). Device according to one of the Claims 1 until 16 , wherein the second FLL or PLL control loop (324) has a reference measuring device (507) for measuring the low-frequency reference clock (306). Device according to Claim 17 , wherein the reference measuring device (507) as a device part of the second FLL or PLL control loop (324) is set up to measure values for parameters of the low-frequency reference clock (306), in particular the frequency and / or the period duration and / or the phase position of the low-frequency Reference clock (306) to be determined. Device according to one of the Claims 1 until 18 , wherein the reference measuring device (507) for measuring the low-frequency reference clock (306) as a device part of the second FLL or PLL control loop (324) is set up to determine values (516) for parameters of the reference clock (306). Device according to Claim 19 , wherein the values for parameters of the reference clock (306), which the reference measuring device (507) as part of the device of the second FLL or PLL control loop (324) determines, at least one or more values (516) of one or more of the following parameters - number of Clocks of the reference clock (306), and/or - frequency and/or period duration of the reference clock (306) and/or - time duration of a complete clock (period duration) of the reference clock (306) and/or its reciprocal and/or - the phase position of the Reference clock (306) compared to a divided high-frequency clock (521) and / or, - the phase position of the reference clock (306) compared to the reference signal in the input signal (308) and / or - time duration of a low and / or high phase of the clock of the reference clock (306) and/or - time duration of a certain number of clocks of the reference clock (306) and/or - time duration of a certain number of low and/or high phases of the reference clock (306). Device one of the Claims 17 until 18 , wherein the low-frequency reference clock (306) has at least two reference clock features, in particular rising and/or falling edges, and wherein the reference measuring device (507) is set up to determine the number of clocks of the high-frequency clock (303) and/or one of the high-frequency clock (303). derived signal and / or a signal associated with the high-frequency clock (303) between the first time of occurrence of a first reference clock feature in the low-frequency reference clock (306) and the second time of occurrence of a second reference clock feature in the low-frequency reference clock (306) and so a third to determine the count value. Device according to Claim 21 , wherein the control device (311) and / or the second FLL or PLL control circuit (324) are set up to use this third count value or a value derived therefrom as a reference clock frequency measurement signal (516) of the reference measuring device (507) for the measured value (516) of the low-frequency reference clock (306), in particular as a measured value (516) of the frequency and/or period duration of the reference clock (306). Device one of the Claims 19 until 20 , wherein the low-frequency reference clock (306) has at least one reference clock feature, in particular rising and/or falling edges, and wherein the reference signal in the input signal (308) has at least one reference signal feature, in particular rising and/or falling edges, and wherein the reference measuring device (507) does so is set up, the number of clocks of the high-frequency clock (303) and / or a signal derived from the high-frequency clock (303) and / or a signal associated with the high-frequency clock (303) between the time of occurrence of a first reference clock feature in the low-frequency reference clock (306) and counting the time of occurrence of a second reference signal feature in the reference signal of the input signal (308) and thus determining a third count value. Device according to Claim 23 , wherein the control device (311) and / or the second FLL or PLL control loop (324) are set up to use this third count value or a value derived therefrom as a reference clock phase position measurement signal (516) of the reference measuring device (507) for the measured value (516) of the low-frequency reference clock (306), in particular as a measured value (516) of the phase position of the reference clock (306). Device one of the Claims 19 until 20 , wherein the low-frequency reference clock (306) has at least one reference clock feature, in particular rising and / or falling edges, and wherein the divided high-frequency clock (521) has at least one reference high-frequency clock feature, in particular rising and / or falling edges, and wherein the reference measuring device (507) is set up for this purpose is, the number of clocks of the high-frequency clock (303) and / or a signal derived from the high-frequency clock (303) and / or a signal associated with the high-frequency clock (303) between the time of occurrence of a first reference clock feature in the low-frequency reference clock (306) and to count the time of occurrence of a second reference high-frequency clock feature in the divided down high-frequency clock (521) and thus determine a third count value. Device according to Claim 25 , wherein the control device (311) and / or the second FLL or PLL control loop (324) are set up to use this third count value or a value derived therefrom as a reference clock phase position measurement signal (516) of the reference measuring device (507) for the measured value (516) of the low-frequency reference clock (306), in particular as a measured value (516) of the phase position of the reference clock (306). Device according to one of the Claims 1 until 26 , wherein the second FLL or PLL control loop (324) has a target value calculation (510). Device according to Claim 27 and after one of the Claims 19 until 26 and after one of the Claims 13 until 16 , wherein the target value calculation (510) is set up to calculate a deviation (518) between the measured value (516) of the low-frequency reference clock (306) or a value derived therefrom or associated therewith, on the one hand, and from determined values (517) for parameters of the synchronizing signal Reference signal in the input signal (308), in particular in the form of a difference, on the other hand. Device according to Claim 28 , wherein the frequency and/or the period duration and/or the phase position of the reference clock (306) depends on the deviation (518) and/or a value derived therefrom or associated therewith. Device according to one of the Claims 1 until 29 , wherein the second FLL or PLL control circuit (324) has a second control II (504). Device according to Claim 30 and one of the Claims 28 or 29 , wherein the second FLL or PLL control loop (324) has the reference oscillator (505) and wherein the second control system II (504) is set up to operate as a function of the deviation (518) and/or as a proportional dependence on this deviation and / or depending on a value derived therefrom or a value associated therewith, to form a second control signal II (514) of the second control II (504) and wherein the reference oscillator (505) is set up to set the reference clock (306) depending on the second To form control signal II (514). Device according to Claim 31 , whereby the second control II (504) is set up as a function of a correction value which is a) from the deviation (518) or b) from a value derived therefrom or c) from a value associated therewith in cases a) to c) taking into account the trimming curve and / or trimming step size, the second control signal II (514) of the second control II (504) depends. Device according to one of the Claims 1 until 26 , wherein the second FLL or PLL control loop (324) has a reconstruction oscillator (810). Device according to Claim 33 and after one of the Claims 19 until 26 and after one of the Claims 13 until 16 , wherein the reconstruction oscillator (810) is set up to generate a reconstructed reference signal (806) depending on the parameters (517) of one or more reference signals of the input signal (308) detected by the measuring device (509). Device according to Claim 34 wherein the reconstruction oscillator (810) is set up to generate a reconstructed reference signal (806) from the high-frequency clock (303) depending on the parameters (517) of one or more reference signals of the input signal (308) detected by the measuring device (509). Device according to Claim 35 wherein the reconstruction oscillator (810) has a clock divider which is designed to, by means of a divider ratio, which is derived from the parameters (517) of one or more reference signals of the input signal (308) detected by the measuring device (509) or from these parameters (517). Parameters depend on generating a reconstructed reference signal (806) from the high-frequency clock (303) by clock division according to this division ratio. Device according to Claim 33 and after one of the Claims 19 until 26 and after one of the Claims 13 until 16 and one of the Claims 17 until 19 , wherein the reconstruction oscillator (810) is set up to generate one or more reference signals of the input signal (308) as a function of the parameters (517) detected by means of the measuring device (509) and as a function of the parameters (516) determined by means of the reference measuring device (507). ) of the reference clock (306) to generate a frequency-corrected reference signal (906). Device according to Claim 37 wherein the reconstruction oscillator (810) is set up to generate one or more reference signals of the input signal (308) depending on the parameters (517) detected by means of the measuring device (509) and depending on the parameters (516) determined by means of the reference measuring device (507). of the reference clock (306) to generate a frequency-corrected reference signal (906) from the high-frequency clock (303). Device according to Claim 38 wherein the reconstruction oscillator (810) has a clock divider which is set up to correspond to a division ratio which - from the parameters (517) of one or more reference signals of the input signal (308) detected by means of the measuring device (509) and - from those using the reference measuring device (507) determined parameters (516) of the reference clock (306) to generate a frequency-corrected reference signal (906) from the high-frequency clock (303) by means of a clock division corresponding to this division ratio of the clock divider. Device according to one of the Claims 1 until 39 wherein the second FLL or PLL control loop (324) has a second phase position detector (819) and/or a second frequency difference detector (819) and/or a second period duration difference detector (819). Device according to Claim 40 wherein the second phase position detector (819) and/or the second frequency difference detector (819) and/or the second period duration difference detector (819) are set up to communicate the reconstructed reference signal (806) or the frequency-corrected reference signal (906) on the one hand with the reference clock (306) on the other hand to compare and wherein the second phase position detector (819) and / or the second frequency difference detector (819) and / or the second period duration difference detector (819) are set up to, depending on the result of this comparison - a deviation signal from the phase position detector (819) for the deviation of the Phase position between the reconstructed reference signal (806) or the frequency-corrected reference signal (906) on the one hand and the reference clock (306) on the other hand or - a deviation signal from the frequency difference detector (819) for the deviation of the frequency between the reconstructed reference signal (806) or the frequency-corrected one Reference signal (906) on the one hand and the reference clock (306) on the other hand or - a deviation signal of the period duration difference detector (819) for the deviation of the period duration between the reconstructed reference signal (806) or the frequency-corrected reference signal (906) on the one hand and the reference clock (306) on the other hand. Device according to Claim 41 , wherein the frequency and/or the period duration and/or the phase position of the reference clock (306) depends on the value of the deviation signal (818) and/or a value derived therefrom or related thereto. Device according to Claim 42 wherein the second control II (504) is set up to generate a second control signal II (514) as a function of the value of the deviation signal (818) and/or as a proportional dependence on the value of the deviation signal (818) and/or on a value derived therefrom Value or value associated therewith and to form the reference clock (306) depending on the second control signal II (514). Device according to Claim 43 wherein the second control II (504) is set up to control the second control signal II (514) depending on a) a correction value that depends on the value of the deviation signal (818) or b) on a value derived therefrom or c) on a value derived therefrom to form a coherent value in cases a) to c) taking into account the trimming curve and/or trimming step size. Device according to one of the Claims 31 until 44 , wherein the second control II (504) is set up to leave the second control signal II (514) at an unchanged value as long as the control device (311) of the second second control II (504) uses a second activation/inactivation signal (325 ) signals that the second FLL or PLL control loop (324) should be in the inactive state. Device according to one of the Claims 1 until 45 wherein the first FLL or PLL control loop (323) has a high-frequency oscillator (502) and wherein the high-frequency oscillator (502) generates the high-frequency clock (303). Device according to Claim 46 , wherein the first FLL or PLL control loop (323) comprises a first clock divider (520) and wherein the first clock divider (520) is designed to convert the high-frequency clock (303) of the high-frequency oscillator (502) into a divided-down high-frequency clock (521). to divide down according to a first division ratio of the first clock divider (520). Device according to Claim 46 or 44 , wherein the first FLL or PLL control loop (323) has a phase position detector (519) and/or a frequency difference detector (519) and/or a period difference detector (519) of the first FLL or PLL control loop (323), here summarized as a phase position detector (519), includes. Device according to Claim 47 and Claim 48 , wherein the phase position detector (519) of the first FLL or PLL control loop (319) is set up to receive a phase difference and / or a frequency difference and / or a period difference between the reference clock (306) and the one divided down high-frequency clock (521) as a measured value to detect and, depending on this measured value, to form a high-frequency clock frequency measured value signal (522). Device according to one of the Claims 1 until 49 , wherein the first FLL or PLL control loop (323) comprises a first control I (502) of the first FLL or PLL control loop (323). Device according to Claim 49 and 50 , wherein the first control I (501) is set up to form a first control signal I (515) of the first control I (501) as a function of the high-frequency clock frequency measured value signal (522) and the high-frequency oscillator (502) controls the high-frequency clock (303). at least temporarily depending on this first control signal I (515) of the first control I (501). Device according to Claim 51 , wherein the first control II (501) is set up to leave the first control signal I (515) at an unchanged value as long as the control device (311) of the first control II (501) is activated by means of a first activation/inactivation signal (313). signals that the first FLL or PLL control loop (323) should be in the inactive state. Device according to Claim 51 or 52 , wherein the first control II (501) is set up to no longer leave the first control signal I (515) at an unchanged value when the control device (311) of the first control II (501) is activated by means of a first activation/inactivation signal ( 313) signals that the first FLL or PLL control loop (323) should be in the active state. Device according to Claim 53 , wherein the first control II (501) is set up to leave the first control signal I (515) at an unchanged value until the appearance of a reference clock feature, in particular a rising or falling edge, in the reference clock (306) and with the appearance of a reference clock feature , in particular the rising or falling edge, in the reference clock (306), set the first divider (520) and / or the first control signal I (515) to a predetermined value and from then on the first control signal I (515) is no longer at one force unchanged value. Device according to one of the Claims 1 until 54 , wherein the control (311) and / or means (507) of the proposed device (300) is switched off measuring the reference clock (306) are set up to record the time duration of a certain number of clocks of the reference clock (306) of the reference oscillator (505) by means of the high-frequency clock (303) and by means of the means (507) for measuring the reference clock (306). and wherein the control (311) and/or means (510) of the proposed device (300) for determining a deviation are set up to detect the deviation between the recorded duration (516) and/or a value derived therefrom, on the one hand, and a measured value (517 ) the frequency and/or the period duration of one or more reference signals of the input signal (308), on the other hand, and wherein the controller (311) and/or the second FLL or PLL control loop (324) are set up to determine the frequency and/or Period duration and / or phase of the reference clock (306) of the reference oscillator (505) depending on the determined deviation, in particular proportional to the determined deviation, to correct and the duration of a certain number of clocks of the reference clock (306) of the reference oscillator (505) to be corrected again detect until the target value of the frequency and / or the period duration and / or the phase position of the reference clock (306) of the reference oscillator (505) has been reached. Device according to one of the Claims 1 until 55 wherein the controller (311) is set up to freeze and thus deactivate the first FLL or PLL control loop (323) when one or more reference signals of the input signal (308) arrive, so that the high-frequency clock (303) of the high-frequency, adjustable oscillator (502) or the first FLL or PLL control loop (323) does not change its frequency and / or period duration and / or phase position for the duration that the reference signal of the input signal (308) is present. Device according to one of the Claims 1 until 56 wherein the device is designed to reactivate the first FLL or PLL control loop (323) after inactivation of the first FLL or PLL control loop (323) not immediately after the end of the occurrence of a reference signal as a synchronization signal in the input signal (308), and wherein the device is set up to reactivate the first FLL or PLL control loop (323) instead only at the time end of a remaining data frame following the reference signal in the input signal (308) or only at the time end At the end of an associated data message following the reference signal in the input signal (308), a data communication that is transmitted by means of the input signal (308) is to be carried out, and thus delayed until the end of the communication. Device according to one of the Claims 1 until 57 wherein the device is designed to jump back to the normal state (400) when the device is not in the normal state (400) and when the controller then detects the arrival of a further additional reference signal in the input signal (308). Device according to one of the Claims 1 until 58 with means (510) for detecting the successful completion of the correction (406) of the frequency and/or period duration and/or phase position of the reference clock (306) and wherein the device, in particular the controller (311), is set up to signal a higher-level system that the frequency and/or the period duration and/or the phase position of the reference clock (306) has been reached. Device according to one of the Claims 1 until 59 , wherein the device is set up to do so after successful completion of the correction (406) of the frequency and/or period duration and/or phase position of the reference clock (306) and after reaching the target frequency and/or target period duration and/or the target - Phase position of the reference clock (306) to switch to a “fine correction mode”, whereby the fine correction mode of the device differs in that • the device is set up to accept the corrections of the second FLL or PLL control loop (324) or . of the reference oscillator (505) only by a certain number of trimming increments or in order to make a certain frequency change or period duration change or phase position change of the reference clock (306) of the second FLL or PLL control loop (324) and / or the reference oscillator (504). to limit this, in particular to a trimming step or the smallest possible frequency change or period change or phase position change of the reference clock (306) of the second FLL or PLL control loop (324) and / or the reference oscillator (504), and • that the device for this purpose is set up, upon leaving the normal state (400), the first FLL or PLL control loop (324) is deactivated due to the previous completion of the transient process of the first FLL or PLL control loop (324) and the limitation of the frequency change or period change or phase position change to be omitted. Device according to one of the Claims 1 until 60 , wherein the device (300), in particular the control (311) and / or another suitable sub-device of the proposed device (300), comprises a non-volatile memory and wherein the device (300) is set up to, after completion of the correction (406 ) the frequency and/or period length and/or phase position of the reference clock (306) or when the device is decommissioned, the determined values for the frequency correction and/or period length correction and/or phase position correction of the reference clock (306) are stored in the non-volatile memory. Device according to Claim 61 wherein the device, in particular the controller (311) and/or another suitable sub-device of the proposed device (300), is set up to output values determined for the frequency correction and/or period duration correction and/or phase position correction of the reference clock (306) upon commissioning to read the non-volatile memory and to use it for the frequency correction and/or period duration correction and/or phase position correction of the reference clock (306). became. Device according to one of the Claims 1 until 62 , wherein the second FLL or PLL control loop (324) has a phase position detector (819) and / or a frequency difference detector (819) and / or period duration difference detector (819), which are referred to below as a phase position detector (819) for simplification , and wherein the second FLL or PLL control loop (324) has a clock divider (1024) and wherein the second FLL or PLL control loop (324) has a reference clock (306) and wherein the second FLL or PLL control loop ( 324) has a reconstruction oscillator (810) and wherein the second FLL or PLL control loop (324) comprises a measuring device (509) and wherein the measuring device (509) contains measured values (517) of the parameters of one or more sporadically occurring reference signals in an input signal ( 308). ) as a function of the recorded measured values (517) of the frequency and/or the period duration and/or the phase position of one or more reference signals of the input signal (308) and wherein the clock divider (1024) of the second FLL or PLL control loop (324) divides the reference clock (306) into a divided reference clock (1025) according to a division ratio of the clock divider (1024) of the second FLL or PLL control loop (324) and wherein the phase position detector (819) determines the value of the parameter of the frequency or the phase position or . on the one hand compares the period duration of the reconstructed reference signal (806) with the value of the corresponding parameter of the frequency or the phase position or the period duration of the divided reference clock (1025) and, corresponding to the value of the comparison result, a value of the deviation signal (1018) of the phase position detector (819 ) and wherein the second control II (504) forms the value of a second control signal II (514) depending on the value of the deviation signal (1018) and wherein the reference oscillator (505) depends on the value of the second control signal II (514) forms the reference clock (306). Device according to Claim 63 , wherein the measuring device (509) detects valid measured values (517) of the parameters of one or more sporadically occurring valid reference signals in the input signal (308) and wherein the reconstruction oscillator (810) generates a reconstructed reference signal (806) depending on the detected valid measured values (517 ) the frequency and / or the period and / or the phase position of one or more valid reference signals of the input signal (308).

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