DE102021100006A1 - SEMICONDUCTOR DEVICE AND METHOD - Google Patents

Abstract

One embodiment relates to a package structure with a first integrated circuit die and a redistribution structure that is bonded to the first integrated circuit die, the redistribution structure comprising: a first metallization structure in a first dielectric layer, the first metallization structure having a plurality of first conductive structure elements, wherein the first conductive structure elements each comprise a first conductive via and a first conductive line, which is arranged over the first dielectric layer and is electrically connected to the respective first conductive via, the first conductive lines in a plan view each have a curve shape; a second dielectric layer over the first dielectric layer and the first metallization structure; and a second metallization structure in the second dielectric layer, the second metallization structure having a plurality of second conductive vias in the second dielectric layer, the second conductive vias each being arranged over a respective first conductive line and being electrically connected to this.

Description

Priority claim and cross-reference

This application claims priority from U.S. provisional patent application filed on April 27, 2020 with file number 63/015 775 which is incorporated by reference into the present application.

background

The semiconductor industry has experienced rapid growth due to constant improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density is due to repeated reductions in the smallest feature width, which means that more components can be integrated on a given area. As the demand for miniaturization of electronic devices has increased, a need for faster and more creative packaging methods for semiconductor devices has arisen. Package-on-package technology (PoP technology) is an example of such encapsulation systems. In a PoP device, an upper semiconductor package is stacked on a lower semiconductor package in order to achieve a high degree of integration and a high component density. PoP technology generally enables semiconductor devices with improved functionality and small pads to be fabricated on a printed circuit board (PCB).

Figure list

• 1 zeigt eine Schnittansicht eines integrierten Schaltungs-Dies gemäß einigen Ausführungsformen.
• Die 2 bis 7 und 10 bis 18 zeigen Schnittansichten von Zwischenstufen während eines Prozesses zur Herstellung einer Package-Komponente gemäß einigen Ausführungsformen.
• 8 ist eine Draufsicht von leitfähigen Strukturelementen gemäß einigen Ausführungsformen.
• Die 9A und 9B sind detaillierte Draufsichten der in 8 gezeigten leitfähigen Strukturelemente gemäß einigen Ausführungsformen.
• 19 zeigt eine Schnittansicht der Herstellung und Implementierung von Vorrichtungsstapeln gemäß einigen Ausführungsformen.

Aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. Rather, the dimensions of the various elements can be arbitrarily increased or decreased for the sake of clarity of explanation.

• 1 FIG. 10 shows a cross-sectional view of an integrated circuit die in accordance with some embodiments.
• the 2 until 7th and 10 until 18th Figure 10 shows cross-sectional views of intermediate stages during a process of manufacturing a package component in accordance with some embodiments.
• 8th FIG. 3 is a top view of conductive features in accordance with some embodiments.
• the 9A and 9B are detailed top views of the in 8th shown conductive structure elements according to some embodiments.
• 19th Figure 12 shows a cross-sectional view of manufacturing and implementing device stacks in accordance with some embodiments.

Detailed description

The description below provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below in order to simplify the present invention. These are of course only examples and are not intended to be limiting. For example, the manufacture of a first element over or on a second element in the description below may include embodiments in which the first and second elements are made in direct contact, and it can also include embodiments in which additional elements are placed between the first and the second element can be made so that the first and second elements are not in direct contact. In addition, in the present invention, reference numbers and / or letters may be repeated in the various examples. This repetition is for the sake of simplicity and clarity and does not per se prescribe a relationship between the various embodiments and / or configurations discussed.

In addition, spatially relative terms such as "below", "below", "lower" / "lower", "above", "upper" / "upper" and the like can be used for simplicity Description of the relationship of an element or structure to one or more other elements or structures shown in the figures. The spatially relative terms are intended to include other orientations of the device in use or in operation in addition to the orientation shown in the figures. The device can be oriented differently (rotated 90 degrees or in a different orientation) and the spatially relative descriptors used herein can also be interpreted accordingly.

Redistribution structures with metallization structures and methods for their production according to some embodiments are provided. In particular, the redistribution structures have metallization structures with shapes that allow greater flexibility so that the metallization structure can withstand bending and other deformations without break. For example, the metallization structures may have a curve shape, a C shape, or a U shape in a plan view. Metallization structures in redistribution structures can bend or deform due to a CTE discrepancy (CTE: coefficient of thermal expansion) between materials in a semiconductor package. This CTE discrepancy can result in the metallization structures being exposed to high mechanical stress due to the deflection and deformation. However, the disclosed forms of the metallization structures with the increased flexibility increase the reliability of the redistribution structure. These flexibly shaped metallization structures are enclosed by conformal dielectric layers, such as for example polymer layers. The combination of the flexibly shaped metallization structures and the enclosing conformal dielectric layers provides a buffer for relaxation in the redistribution structure and the package structure.

1 Figure 12 shows a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 is capped to an integrated circuit package during later processing. The integrated circuit die 50 can be: a logic die, e.g. B. a CPU die (CPU: main processor), a GPU die (GPU: graphics processor), a SoC die (SoC: system-on-a-chip), an application processor die (AP die), a microcontroller -The; a memory die, e.g. B. a DRAM die (DRAM: dynamic random access memory), an SRAM die (SRAM: static random access memory), a power management die, e.g. B. an integrated power management circuit (PMIC), a radio frequency die (HF die), a sensor die; a MEMS die (MEMS: microelectromechanical system); a signal processing die, e.g. B. a DSP die (DSP: digital signal processing); a front-end die, e.g. B. an analog front-end die (AFE die), or the like; or a combination of these.

The integrated circuit die 50 can be fabricated in a wafer that may have different device areas that are diced in later steps to fabricate a plurality of integrated circuit dies. The integrated circuit die 50 can be machined with suitable manufacturing processes to produce integrated circuits. The integrated circuit die 50 comprises, for example, a semiconductor substrate 52 such as doped or undoped silicon or an active layer of a semiconductor-on-insulator substrate (SOI substrate). The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. The semiconductor substrate 52 has an active page (e.g. the page that is in 1 facing up), sometimes referred to as a front side, and an inactive side (e.g., the side that appears in 1 facing down), sometimes referred to as a back side.

On the front of the semiconductor substrate 52 can fixtures 54 (which are represented by a transistor). The devices 54 can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, or the like. Over the front of the semiconductor substrate 52 becomes an interlayer dielectric (ILD) 56 manufactured. The ILD 56 encloses the devices 54 and can cover them. The ILD 56 may include one or more dielectric layers made from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

Through the ILD 56 extend conductive pins 58 to get the fixtures 54 physically and electrically connect. When the devices 54 for example transistors can be the conductive pins 58 Connect the gates and source / drain regions of the transistors. The conductive pins 58 can be made from tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or combinations thereof. Above the ILD 56 and the conductive pins 58 is an interconnect structure 60 arranged. The interconnect structure 60 connects the devices 54 together to form an integrated circuit. The interconnect structure 60 can, for example, of metallization structures in dielectric layers on the ILD 56 are formed. The metallization structures include metal lines and vias fabricated in one or more low-k dielectric layers. The metallization structures of the interconnect structure 60 are through the conductive pins 58 with the devices 54 electrically connected.

The integrated circuit die 50 also has pads 62 such as aluminum pads that are used to make external connections. The pads 62 are on the active side of the integrated circuit die 50 arranged, such as in and / or on the interconnect structure 60 . One or more passivation layers 64 are on the integrated circuit die 50 arranged, such as on parts of the interconnect structure 60 and the pads 62 . Through the passivation layers 64 openings extend to the pads 62 . Die fasteners 66 , such as conductive pillars (those for example made of a metal such as copper) extend through the openings in the passivation layers 64 and are physically and electrically connected to respective ones of the pads 62 tied together. The die fasteners 66 can be made, for example, by plating or the like. The die fasteners 66 connect the respective integrated circuits of the integrated circuit die 50 electric.

Optionally, solder areas (e.g. solder balls or solder bumps) can be placed on the pads 62 to be ordered. The solder balls can be used to perform chip probe (CP) testing on the integrated circuit die 50 be used. The CP exam can be taken at the integrated circuit die 50 be performed to determine if the integrated circuit die 50 is a proven good die (KGD). Thus, only integrated circuit dies 50 that are KGDs are processed further and masked, and those that fail the CP exam are not masked. After the CP check, the solder areas can be removed in later processing steps.

On the active side of the integrated circuit die 50 such as on the passivation layers 64 and the die fasteners 66 , can be a dielectric layer 68 be produced (or not). The dielectric layer 68 encapsulates the die fasteners 66 laterally and laterally adjacent to the integrated circuit die 50 at. First of all, the dielectric layer 68 the die fasteners 66 cover up so that the top side of the dielectric layer is 68 over top sides of the die fasteners 66 is located. In some embodiments that have solder areas on the die connectors 66 are arranged, the dielectric layer 68 also cover the solder areas. Alternatively, the solder areas can be removed before the production of the dielectric layer.

The dielectric layer 68 can be a polymer such as polybenzoxazole (PBO), a polyimide, benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silica, PSG, BSG, BPSG, or the like; or the like or a combination thereof. The dielectric layer 68 can be made, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors 66 during the manufacture of the integrated circuit die 50 through the dielectric layer 68 exposed. In some embodiments, the die connectors remain 66 hidden and will be used during a later process of packaging the integrated circuit die 50 exposed. By exposing the die fasteners 66 Solder areas can be removed that are on the die fasteners 66 may be present.

In some embodiments, the integrated circuit die is 50 a stacking device that includes multiple semiconductor substrates 52 having. The integrated circuit die 50 For example, a memory device such as a hybrid memory cube (HMC) module, high bandwidth memory (HBM) module, or the like that has multiple memory dies. In these embodiments, the integrated circuit die 50 multiple semiconductor substrates 52 which are interconnected by substrate vias (TSVs). The semiconductor substrates 52 can each have an interconnect structure 60 have (or not).

the 2 until 18th Figure 11 shows sectional views of intermediate stages during a process for manufacturing a package component 100 according to some embodiments. A first package area is shown 100A and a second package area 100B , where one or more of the integrated circuit dies 50 in each of the package areas 100A and 100B be capped to form an integrated circuit package. The integrated circuit packages can also be referred to as integrated fan-out packages (InFO packages).

In 2 becomes a carrier substrate 102 provided, and on the carrier substrate 102 becomes a release layer 104 manufactured. The carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate or the like. The carrier substrate 102 can be a wafer so that several packages are placed on the carrier substrate at the same time 102 can be produced.

The release layer 104 can be made from a polymer-based material that coexists with the support substrate 102 can be removed from overlying structures that will be fabricated in later steps. In some embodiments, the release liner is 104 a heat-releasable epoxy-based material that loses its adhesion when heated, such as an LTHC release liner (LTHC: light-to-heat conversion). In other embodiments, the release layer 104 an ultraviolet (UV) adhesive that loses its adhesion when exposed to UV light. The release layer 104 can be distributed as a liquid and cured, or it can be a laminate layer with which the carrier substrate 102 is coated, or the like. A top of the release liner 104 can be leveled and can have a high degree of planarity.

In the 3 until 7th becomes a redistribution structure 120 (please refer 7th ) over the release layer 104 manufactured. The redistribution structure 120 has dielectric layers 124 , 128 , 132 , 136 and 140 and metallization structures 126 , 130 , 134 and 138 on. The metallization structures can also be referred to as redistribution layers or redistribution lines. The redistribution structure 120 is shown as an example with four layers of metallization structures. In the redistribution structure 120 more or less dielectric layers and metallization structures can be produced. If fewer dielectric layers and metallization structures are to be produced, the steps and processes described below can be omitted. If more dielectric layers and metallization structures are to be fabricated, the steps and processes described below can be repeated.

In 3 becomes the dielectric layer 124 on the release liner 104 deposited. In some embodiments, the dielectric layer is 124 made of a photosensitive material such as PBO, a polyimide, BCB or the like, which can be patterned using a lithographic mask. The dielectric layer 124 can be made by spin coating, CVD, lamination, or the like, or a combination thereof. The dielectric layer 124 is then patterned to create openings which are portions of the release liner 104 uncover. The patterning can be carried out by a suitable method, such as by exposing and developing the dielectric layer 124 when it is a photosensitive material, or by etching such as anisotropic etching.

Then the metallization structure 126 manufactured. The metallization structure 126 includes conductive elements that extend along the major surface of the dielectric layer 124 and through the dielectric layer 124 extend. For example, the metallization structure 126 be made by having a seed layer over the dielectric layer 124 and is made in the openings extending through the dielectric layer 124 extend. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with a plurality of sub-layers made from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be produced, for example, by physical vapor deposition (PVD) or the like. A photoresist is then produced on the seed layer, which is then structured. The photoresist can be prepared by spin coating or the like and can be exposed for patterning. The structure of the photoresist corresponds to the metallization structure 126 . The patterning creates openings through the photoresist in order to expose the seed layer. A conductive material is then deposited in the openings of the photoresist and on the exposed parts of the seed layer. The conductive material can be deposited by plating such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the parts of the seed layer underneath it forms the metallization structure 126 . Then the photoresist and the parts of the seed layer on which the conductive material has not been deposited are removed. The photoresist can be removed by a suitable stripping or stripping process, for example using an oxygen plasma or the like. After the photoresist has been removed, exposed parts of the seed layer are removed, for example using a suitable etching process, such as wet or dry etching.

In 4th becomes the dielectric layer 128 on the metallization structure 126 and the dielectric layer 124 deposited. The dielectric layer 128 may be made in a similar manner and material as the dielectric layer 124 getting produced.

Then the metallization structure 130 manufactured. The metallization structure 130 includes lead portions on and along the major surface of the dielectric layer 128 . The metallization structure 130 further includes via portions extending through the dielectric layer 128 extend to the metallization structure 126 physically and electrically connect. The metallization structure 130 can be made in a similar manner and material as the metallization structure 126 getting produced. In some embodiments, the metallization structure has 130 a different size than the metallization structure 126 . For example, the conductive lines and / or vias of the metallization structure 130 wider or thicker than the conductive lines and / or vias of the metallization structure 126 be. In addition, the metallization structure 130 with a greater distance than the metallization structure 126 getting produced.

In 5 becomes the dielectric layer 132 on the metallization structure 130 and the dielectric layer 128 deposited. The dielectric layer 132 may be made in a similar manner and material as the dielectric layer 124 getting produced.

Then the metallization structure 134 manufactured. The metallization structure 134 includes portions on and along the major surface of the dielectric layer 132 . The metallization structure 134 also has parts that extend through the dielectric layer 132 extend to the metallization structure 130 physically and electrically connect. The metallization structure 134 can be made in a similar manner and material as the metallization structure 126 getting produced. In some embodiments, the metallization structure has 134 a different size than the metallization structures 126 and 130 . For example, the conductive lines and / or vias of the metallization structure 134 wider or thicker than the conductive lines and / or vias of the metallization structures 126 and 130 be. In addition, the metallization structure 134 with a greater distance than the metallization structure 130 getting produced.

In 6th becomes the dielectric layer 136 on the metallization structure 134 and the dielectric layer 132 deposited. The dielectric layer 136 may be made in a similar manner and material as the dielectric layer 124 getting produced.

Then the metallization structure 138 manufactured. The metallization structure 138 includes parts 138a (with parts i38ai, 138a2, and 138a3 discussed later with reference to the 9A and 9B on and along the major surface of the dielectric layer 132 . The metallization structure 138 also has parts 138b on that extends through the dielectric layer 136 extend to the metallization structure 134 physically and electrically connect. The metallization structure 138 can be made in a similar manner and material as the metallization structure 126 getting produced. The metallization structure 138 is the top metallization structure of the redistribution structure 120 . In some embodiments, the metallization structure has 138 a different shape than the metallization structures 126 , 130 and 134 . For example, the parts can 138a the metallization structure 138 have a curve shape, a C shape or a U shape in a plan view, and they can bend and deform without breaking (see 8th , 9A and 9B) as will be set out later. In addition, the metallization structures 134 , 130 and 126 with a greater distance than the metallization structure 138 getting produced.

In 7th becomes the dielectric layer 140 on the metallization structure 138 and the dielectric layer 136 deposited. The dielectric layer 140 may be made in a similar manner and material as the dielectric layer 124 getting produced. The dielectric layer 140 is then patterned to create openings which are parts of the metallization structure 138 uncover. The patterning can be carried out by a suitable method, such as by exposing and developing the dielectric layer 140 when it is a photosensitive material, or by etching such as anisotropic etching.

The dielectric layer 140 has a thickness T ₁ , and the conductive structural elements of the metallization structure 138 have a thickness T2 . In some embodiments, the thickness is T _{1 of} the dielectric layer 140 greater than the thickness T _{2 of} the metallization structure 138 . In some embodiments, the thickness T _{1 is} 5 µm to 20 µm. In some embodiments, the thickness T _{1 is} 5 µm to 8 µm. In some embodiments, the thickness T _{2 is} 2 µm to 15 µm. In some embodiments, the thickness T _{2 is} 2 µm to 5 µm.

In some embodiments, the metallization structure has 138 a different size than the metallization structures 126 , 130 and 134 . For example, in some embodiments, the conductive lines and / or vias of the metallization structure 138 wider or thicker than the conductive lines and / or vias of the metallization structures 126 , 130 and 134 be. In some embodiments, the conductive lines and / or vias may have the same widths and / or thicknesses as the metallization structures 126 , 130 and 134 to have.

In some embodiments, the dielectric layer has 140 a different thickness than the dielectric layers 124 , 128 , 132 and 136 . For example, in some embodiments, the dielectric layer 140 thicker than the dielectric layers 124 , 128 , 132 and 136 be. In some embodiments, the dielectric layer can 140 the same thickness as the dielectric layers 124 , 128 , 132 and 136 to have.

Then conductive vias are made 142 in the openings in the dielectric layer 140 made to the metallization structure 138 physically and electrically connect. As an example of making the vias 142 a seed layer is made in the openings that extend through the dielectric layer 140 extend. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with a plurality of sub-layers made from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can for example by PVD or the like can be produced. A conductive material is then deposited on the seed layer in the openings. The conductive material can be deposited by plating such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying parts of the seed layer forms the conductive vias 142 . A planarization process can be performed around a substantially planar top surface of the dielectric layer 140 and the conductive vias 142 to create. The planarization process can be, for example, a CMP process (CMP: chemical mechanical polishing).

8th Figure 13 is a top plan view of the conductive features of the redistribution structure 120 who have favourited the metallization structure 138 (ie, the parts 138a and 138b) and the conductive vias 142 having. As in 8th shown have the parts 138a a curve shape, a C shape or a U shape in plan view, in which the parts 138b are arranged at a first end of the curve shape and the conductive vias 142 are arranged at a second end of the curve shape. The curve shape, the C shape or the U shape can act like a coil of a spring and can bend and deform without breaking. Metallization structures in redistribution structures can bend or deform due to a CTE discrepancy (CTE: coefficient of thermal expansion) between materials in a semiconductor package. This CTE discrepancy can lead to the metallization structures being exposed to high mechanical stress due to the deflection and deformation. However, the disclosed forms of the metallization structures with the increased flexibility increase the reliability of the redistribution structure. The flexibly shaped metallization structures 138 and the flexible dielectric layer 140 can be referred to as stress buffer layers as they provide a buffer for safe relaxation in the redistribution structure and the package structure.

9A shows a detailed illustration of a C-shaped conductive structure element of the metallization structure 138 from 8th . The part 138a includes a first portion i38ai directly over a via portion 138b ; a second part 138a2 extending from the first part i38ai; and a third portion 138a3 that is directly below the conductive via 142 is located. The first and third parts 138a1 and 138a3 are pad parts with the vias above and below 138 and 142 are connected, and the second part 138a2 has a curve or loop structure and connects the first and third parts 138a1 and 138a3. Due to the loop structure of the second part 138a2, the conductive structure elements of the metallization structure 138 Reliably relax the redistribution structure and / or the package structure.

In some embodiments, the pad parts i38ai and 138a3 are wider than the curve part 138a2 in plan view. As a result, the pad parts 138a1 and 1438a3 can produce better connections with the vias located above and below and improve the reliability of the redistribution structure.

As in 9A As shown, line A passes through the center of the conductive via 142 and the center of the part 138b of the only conductive structure element of the metallization structure 138 that by the part 138a this conductive structural element of the metallization structure 138 with the conductive through-hole 142 is electrically connected. A line B runs from the center of the same via 142 along a center line of a first line segment of the part 138a2 of the same conductive structure element of the metallization structure that extends from the conductive via 142 extends. A line C extends from the center of the same part 138a of the same conductive structure element of the metallization structure 138 along a center line of the first line segment of the part 138a2 of the same conductive structure element of the metallization structure 138 that extends from the via part 138b extends.

In some embodiments, lines A, B, and C are parallel to the major surface of the dielectric layer 140 . Lines A and B form an angle θ1. In some embodiments, the angle θ1 is 30 ° to 150 °. In some embodiments, the angle θ1 is 30 ° to 90 °. In some embodiments, the angle θ1 is 40 ° to 50 °. Lines A and C form an angle θ2. In some embodiments, the angle θ2 is 30 ° to 150 °. In some embodiments, the angle θ2 is 30 ° to 90 °. In some embodiments, the angle θ2 is 40 ° to 50 °. In some embodiments, the angles θ1 and θ2 are equal. In some other embodiments, angles θ1 and θ2 are different. In some embodiments, the conductive line portions 138a2 are the metallization structure 138 curved, and they have no sharp corners or sudden changes in direction. For example, the conductive line parts 138a2 gradually change their directions by arcs in plan view, but they do not have corners such as 90 ° corners with abrupt changes in direction. In some embodiments, the relaxing metallization structure disclosed may be used 138 and the dielectric layer 140 the metallization structures underneath (e.g. the metallization structure 134 ) applied tensions by 15% to 35%, e.g. B. by 30%.

9B shows a detailed illustration of a U-shaped conductive structure element of the metallization structure 138 from 8th . The major components of the U-shaped conductive structure member (e.g., parts 138a1, 138a2, 138a3 and angles θ1 and 82) are above with reference to FIG 9A and the description is not repeated here.

In some embodiments, the conductive structure elements have the metallization structure 138 in the first package component 100 each have the same shape, and they are each oriented in the same direction such that their lines A are each parallel, their lines B are each parallel, and their lines C are each parallel (see e.g. the metallization structures of FIG 8th ). In some embodiments, the conductive structure elements have the metallization structure 138 different shapes and are oriented differently such that their lines A are not parallel, their lines B are not parallel, and / or their lines C are not parallel. In some embodiments, the conductive features are the metallization structure 138 all C-shaped, all U-shaped or a mixture of C- and U-shaped.

While angles θ1 and θ2 have been described using lines A, B and C, lines A, B and C can also be replaced by planes A, B and C, with planes A, B and C perpendicular to the Main surface of the dielectric layer 140 are.

In 10 are metallizations under the contact bump (UBMs) 144 for external connections to the conductive vias 142 manufactured. The UBMs 144 can be used as pads 144 are designated. The UBMs 144 have bump portions on and along the major surface of the dielectric layer 140 and connect the conductive vias 142 physically and electrically. The UBMs 144 can be made of the same material as the conductive vias 142 getting produced. In some embodiments, the UBMs have 144 a different size than the metallization structures 126 , 130 , 134 and 138 .

As an example, the UBMs 144 be made by first placing a seed layer over the dielectric layer 140 and the conductive vias 142 will be produced. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with a plurality of sub-layers made from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. For example, the seed layer can be made by PVD or the like. A photoresist is then produced on the seed layer, which is then structured. The photoresist can be prepared by spin coating or the like and can be exposed for patterning. The structure of the photoresist corresponds to the UBMs 144 . The patterning creates openings through the photoresist in order to expose the seed layer. A conductive material is then deposited in the openings of the photoresist and on the exposed parts of the seed layer. The conductive material can be deposited by plating such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, the UBMs 144 Alloys have such as electroless nickel, electroless palladium, gold deposited with the ENEPIG process (ENEPIG: Electroless Nickel Electroless Palladium Immersion Gold), gold deposited with the ENIG (ENIG: Electroless Nickel Immersion Gold) process, or the like. The combination of the conductive material and the underlying parts of the seed layer form the UBMs 144 . Then the photoresist and the parts of the seed layer on which the conductive material has not been deposited are removed. The photoresist can be removed by a suitable stripping or stripping process, for example using an oxygen plasma or the like. After the photoresist has been removed, exposed parts of the seed layer are removed, for example using a suitable etching process, such as wet or dry etching.

In 11 become conductive connecting elements 146 on the UBMs 144 manufactured. The conductive connecting elements 146 BGA connection elements (BGA: Ball Grid Array), solder balls, metal pillars, C4 contact bumps (C4: chip connection with controlled collapse), microbumps, contact bumps produced with the ENEPIG process or the like. The conductive connecting elements 146 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connectors 146 made by first making a layer of solder by vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. After the layer of solder has been made on the structure, a Melting process can be carried out in order to bring the material into the desired contact bump shapes. In another embodiment, the conductive connectors are 146 Metal pillars (such as copper pillars) made by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be free of perpendiculars and have substantially vertical side walls. In some embodiments, a metallic capping layer is formed on the metal pillars. The metallic capping layer can comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold or the like or a combination thereof and can be produced with a plating process.

In 12th become integrated circuit dies 50 (e.g. first integrated circuit dies 50A and second integrated circuit dies 50B) on the structure of 11 attached. The integrated circuit dies 50 are in a desired type and quantity in each of the package areas 100A and 100B attached. The integrated circuit dies 50 can also be used as package modules 50 are designated. In the illustrated embodiment, multiple integrated circuit dies 50 who have favourited the First Integrated Circuit Die 50A and the second integrated circuit die 50B include, each in the first package area 100A and the second package area 100B glued adjacent to each other. The first integrated circuit die 50A can be a logic device such as a CPU, GPU, SoC, microcontroller, or the like. The second integrated circuit die 50B may be a memory device such as a DRAM, an SRAM, an HMC module (HMC: hybrid memory cube), an HBM module (HBM: high bandwidth memory), or the like. In some embodiments, the integrated circuit dies 50A and 50B the same kind of dies as SoC dies. The first integrated circuit die 50A and the second integrated circuit die 50B can be produced in processes of the same technology node or in processes of different technology nodes. For example, the first integrated circuit die 50A a die of a more modern process node than the second integrated circuit die 50B be. The integrated circuit dies 50A and 50B can have different sizes (e.g. different heights and / or areas), or they can be the same size (e.g. same heights and / or same areas).

The integrated circuit dies 50 are attached to the conductive connecting elements 146 attached. That is, the die fasteners 66 the integrated circuit dies 50A and 50B are with the conductive connecting elements 146 towards the UBMs 144 tied together.

In some embodiments, the conductive connectors 146 melted to the integrated circuit dies 50 at the UBMs 144 to fix. The conductive connecting elements 146 connect the redistribution structure 120 such as the metallization structures in the redistribution structure 120 , physically and / or electrically to the integrated circuit dies 50 . In some embodiments, a solder resist (not shown) is placed on the redistribution structure 120 manufactured. The conductive connecting elements 146 can be placed in openings in the solder resist to connect electrically and mechanically to the UBMs 144 to be connected. The solder resist can be used to protect areas of the redistribution structure 120 can be used against external damage.

On the conductive connecting elements 146 For example, an epoxy flux (not shown) may be applied before they are melted, with at least a portion of the epoxy portion of the epoxy flux remaining after the integrated circuit dies 50 on the redistribution structure 120 have been attached. This remaining epoxy component can act as an underfill to reduce mechanical stresses and can protect the connection points caused by the melting of the conductive connection elements 146 develop.

In 13th becomes an underfill 150 between the integrated circuit dies 50A and 50B in each of the areas 100A and 100B and the dielectric layer 140 established, among other things, between and around the UBMs 144 , conductive connector (s) 146 and die connector (s) 66. The underfill 150 can be made with a capillary flow process after the integrated circuit dies 50 attached, or it can be fabricated by a suitable deposition process prior to the integrated circuit dies 50 be attached. Although it is in 13th and not shown in later figures, in some embodiments the underfill 150 also between the integrated circuit dies 50 in neighboring areas 100A and 100B manufactured.

In 14th becomes an encapsulation material 152 to the integrated circuit dies 50 who have favourited Conductive Fasteners 146 and the underfill 150 manufactured. After its manufacture, the encapsulation material encapsulates 152 the conductive connecting elements 146 and the integrated circuit dies 50 . The encapsulation material 152 can be a molding compound, an epoxy or the like. The encapsulation material 152 can through Compression molding, compression molding or the like can be applied. The encapsulation material 152 can be applied in a liquid or semi-liquid form and then cured. In some embodiments, a planarization step may be performed to remove material from a top surface of the encapsulation material 152 remove and planarize the top. In some embodiments, surfaces are the underfill 150 , the encapsulation material 152 and the integrated circuit dies 50 (within process fluctuations) coplanar.

In 15th a carrier substrate detachment is carried out to the carrier substrate 102 from the redistribution structure 120 , e.g. B. from the dielectric layer 124 to replace. In some embodiments, the stripping includes projecting light, such as laser light or UV light, onto the release liner 104 so that this decomposes due to the heat of the light and the carrier substrate 102 can be removed. Then the structure is turned over and placed on a belt (not shown).

In 16 become UBMs 160 for external connections to the redistribution structure 120 , e.g. B. the metallization structure 126 , manufactured. The UBMs 160 have bump portions on and along the major surface of the dielectric layer 124 . The UBMs 160 can be made of the same material as the metallization structure 126 getting produced.

In 17th become conductive connecting elements 162 on the UBMs 160 manufactured. The conductive connecting elements 162 can be BGA connection elements, solder balls, metal columns, C4 contact bumps, microbumps, contact bumps produced with the ENEPIG process or the like. The conductive connecting elements 162 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connectors 162 made by first making a layer of solder by vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. After the layer of solder has been produced on the structure, a reflow process can be performed to bring the material into the desired bump shapes. In another embodiment, the conductive connectors are 162 Metal pillars (such as copper pillars) made by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be free of perpendiculars and have substantially vertical side walls. In some embodiments, a metallic capping layer is formed on the metal pillars. The metallic capping layer can comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold or the like or a combination thereof and can be produced with a plating process.

As in 18th is shown, a dicing process is carried out by sawing along scribed trench areas, e.g. B. between the first package area 100A and the second package area 100B , carried out. The first package area 100A is made by sawing the second package area 100B separated. The resulting separated device stack comes from the first package area 100A or the second package area 100B . The individual structures are then turned over and attached to a package substrate 200 (please refer 19th ) assembled.

In 19th can be the first package component 100 using the conductive connectors 162 to the package substrate 200 to be assembled. The package substrate 200 comprises a substrate core 202 and bond pads 204 above the substrate core 202 . The substrate core 202 can be made of a semiconductor material such as silicon, germanium or diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide, combinations thereof, and the like can also be used. In addition, the substrate core 202 be a silicon on insulator (SOI) substrate. In general, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, or SGOI, or a combination thereof. In an alternative embodiment, the substrate core is based 202 on an insulating core such as a core made of glass fiber reinforced resin. An exemplary core material is fiberglass resin such as FR4. Alternatives for the core material are bismaleimide triazine (BT) resin or alternatively other printed circuit board (PCB) materials or layers. Build-up layers, such as an Ajinomoto build-up layer (ABF), or other laminates can also be used for the substrate core 202 be used.

The substrate core 202 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors or resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements for the device stack. The devices can be made by any suitable method.

The substrate core 202 may also have metallization layers and vias (not shown), wherein the bond pads 204 physically and / or electrically connected to the metallization layers and vias. The metallization layers can be fabricated over the active and passive devices, and they are configured to interconnect the various devices into functional circuits. The metallization layers can be made from alternating layers of dielectric materials (e.g., a low-k dielectric material) and conductive materials (e.g., copper) with vias connecting the layers of conductive materials together, and they can with any suitable method (such as deposition, single damascene process, dual damascene process, or the like). In some embodiments, the substrate core has 202 essentially no active and passive devices.

In some embodiments, the conductive connectors 162 melted to the first package component 100 on the bond pads 204 to fix. The conductive connecting elements 162 connect the package substrate 200 such as the metallization layers in the substrate core 202 , electrically and / or physically with the first package component 100 . In some embodiments, a solder resist is used 206 on the substrate core 202 manufactured. The conductive connecting elements 162 can in openings in the solder resist 206 be arranged to be electrically and mechanically connected to the bond pads 204 to be connected. The solder resist 206 can be used to protect areas of the substrate core 202 can be used against external damage.

On the conductive connecting elements 162 For example, an epoxy flux (not shown) can be applied before they are melted, with at least a portion of the epoxy portion of the epoxy flux remaining after the first package component 100 on the package substrate 200 have been attached. This remaining epoxy component can act as an underfill to reduce mechanical stresses and can protect the connection points caused by the melting of the conductive connection elements 162 develop. In some embodiments, an underfill 208 between the first package component 100 and the package substrate 200 and around the conductive connectors 162 getting produced. The underfill 208 can be made with a capillary flow process after the second package component 200 has been attached, or it can be fabricated with a suitable deposition process prior to the second package component 200 is attached.

Other structural elements and processes can also be used. For example, test structures can be used to aid in verification testing of a 3D package or 3DIC devices. The test structures can include, for example, test pads fabricated in a redistribution layer or on a substrate that enable testing of 3D packaging or 3DIC devices, the use of probes and / or probe cards, and the like. The verification test can be carried out on intermediate structures as well as on final structures. In addition, the structures and methods described herein can be used in conjunction with testing methodologies that include interim verification of proven good dies to increase yield and reduce costs.

Embodiments can achieve benefits. According to some embodiments, redistribution structures with metallization structures and methods for their production are provided. In particular, the redistribution structures have metallization structures with shapes that allow greater flexibility so that the metallization structure can withstand bending and other deformations without breaking. For example, the metallization structures can have a curve shape, a C shape or a U shape. Metallization structures in redistribution structures can bend or deform due to a CTE discrepancy between materials in a semiconductor package. This CTE discrepancy can result in the metallization structures being exposed to high mechanical stress due to the deflection and deformation. However, the disclosed forms of the metallization structures with the increased flexibility increase the reliability of the redistribution structure. These flexibly shaped metallization structures are enclosed by conformal dielectric layers, such as for example polymer layers. The combination of the flexibly shaped metallization structures and the enclosing conformal dielectric layers provides a buffer for relaxation in the redistribution structure and the package structure.

In one embodiment, a package structure includes a first integrated circuit die. The package structure also has a redistribution structure bonded to the first integrated circuit die, the redistribution structure having a first dielectric layer. The redistribution structure also has a first metallization structure in the first dielectric layer, the first Metallization structure has a plurality of first conductive structure elements, wherein the first conductive structure elements each comprise a first conductive via and a first conductive line, wherein the first conductive via is located in the first dielectric layer and the first conductive line is arranged above the first dielectric layer and is electrically connected to the respective first conductive via, wherein the first conductive lines each have a curve shape in a plan view. The redistribution structure furthermore has a second dielectric layer over the first dielectric layer and the first metallization structure. The redistribution structure furthermore has a second metallization structure in the second dielectric layer, the second metallization structure having a plurality of second conductive structure elements, the second conductive structure elements each comprising a second conductive via in the second dielectric layer, the second conductive via in each case over a respective first conductive line are arranged and are electrically connected to this.

Embodiments may have one or more of the following features. In the package structure, the second metallization structure is arranged closer to the first integrated circuit die than the first metallization structure. The package structure may also include a package substrate bonded to a first side of the redistribution structure, the first integrated circuit die bonded to a second side of the redistribution structure, the first metallization structure being closer to the first side of the redistribution structure than the second metallization structure is arranged. The package substrate is bonded to the first side of the redistribution structure with a first group of conductive interconnect elements, and the first integrated circuit die is bonded to the second side of the redistribution structure with a second group of conductive interconnect elements. The package structure further comprises: an underfill between the first integrated circuit die and the second side of the redistribution structure, the underfill enclosing the second group of conductive connection elements; and an encapsulation material on the second side of the redistribution structure and on sidewalls of the first integrated circuit die and the underfill. A first angle is formed by a first plane and a second plane, the first and the second plane intersecting a first of the plurality of first conductive structure elements and the first and the second plane being perpendicular to a main surface of the second dielectric layer, the first level extends from a center line of a first conductive via of the first of the plurality of first conductive structure elements to a center line of the second conductive via which is arranged over and connected to the first of the plurality of first conductive structure elements, and the second level extends extends from the centerline of the second conductive via disposed over and connected to the first of the plurality of first conductive features along a first portion of the first conductive line of the first of the plurality of first conductive features, wherein ei the first angle is 30 ° to 150 °. The first conductive lines of the plurality of first conductive structure elements each have no corners in the plan view. The first conductive lines each comprise copper and the second dielectric layer comprises a polymer. The second dielectric layer comprises polybenzoxazole (PBO), a polyimide or benzocyclobutene (BCB).

In one embodiment, a package structure has a first package component with a first module and a second module, the first module having a logic chip and the second module having a memory chip. The first package component also has a first redistribution structure with metallization structures in dielectric layers, wherein a first side of the first redistribution structure is physically and electrically connected to the first and the second module and a first metallization structure of the metallization structures in a first dielectric layer of the dielectric layers is arranged, the first metallization structure first having conductive structure elements each comprising a first conductive via and a first conductive line, wherein the first conductive via is located in the first dielectric layer and the first conductive line is arranged over the first dielectric layer and electrically connected to the respective first conductive via wherein the first conductive lines each have a curve shape and have no corners in a plan view. The package structure furthermore has a second package component with a package substrate which is bonded to a second side of the first redistribution structure, wherein the second side is opposite the first side.

Embodiments may have one or more of the following features. In the package structure, the first redistribution structure further comprises: a second dielectric layer over the first dielectric layer and the first metallization structure; and a second metallization structure in the second dielectric layer, the second metallization structure having second conductive structure elements each comprising a second conductive via in the second dielectric layer, the second conductive via being each arranged over a respective first conductive line and electrically with it are connected. The first conductive line connects the first conductive via directly to the second conductive via. The second metallization structure is arranged closer to the first and the second module than the first metallization structure. The first conductive lines each comprise copper and the second dielectric layer comprises a polymer. The first package component further includes: an underfill between the first module, the second module, and the first side of the first redistribution structure, the underfill extending along first sidewalls of the first and second modules, the first sidewalls of the first and second modules of the second module facing each other; and an encapsulation material on the first side of the first redistribution structure and on second sidewalls of the first and second modules, the second sidewalls of the first and second modules facing away from each other. Top surfaces of the first module, the second module, the underfill and the encapsulation material are coplanar.

In one embodiment, a method includes forming a first dielectric layer over a substrate. The method further comprises structuring the first dielectric layer. The method further comprises producing a first metallization structure in and along a top side of the structured first dielectric layer, wherein the first metallization structure has first conductive structure elements, each of which comprises a first conductive via and a first conductive line, the first conductive via being in the first dielectric layer is located and the first conductive line extends along the top of the first dielectric layer and is electrically connected to the respective first conductive via, wherein the first conductive lines in a plan view each have a curve shape and have no corners. The method further comprises producing a second dielectric layer over the structured first dielectric layer and the first metallization structure. The method further comprises structuring the second dielectric layer. The method further comprises producing a second metallization structure in the structured second dielectric layer, the second metallization structure having second conductive vias in the second dielectric layer, the second conductive vias each being electrically connected to a respective first conductive line of the first conductive structure elements.

Embodiments may have one or more of the following features. The method further comprises: producing bond pads over the second dielectric layer and the second metallization structure, wherein the bond pads are connected to the second conductive vias; Bonding a first module and a second module to the bond pads, the first module having a logic chip and the second module having a memory chip; Encapsulating the first and second modules in an encapsulation material; Removing the substrate; and separating the encapsulation material, the first and the second metallization structure and the first and the second dielectric layer. After the singulation, the method further comprises bonding the singulated structure to a package substrate, the package substrate being arranged on a side of the first and second metallization structure and the first and second dielectric layer opposite the first and second module. The first conductive lines each comprise copper and the second dielectric layer comprises a polymer.

Features of various embodiments have been described above so that those skilled in the art may better understand aspects of the present invention. It should be understood by those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same goals and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications therein without departing from the spirit and scope of the present invention.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 63/015775 [0001]

Claims (20)

Package structure with: a first integrated circuit die; and a redistribution structure bonded to the first integrated circuit die, the redistribution structure comprising: a first dielectric layer, a first metallization structure in the first dielectric layer, the first metallization structure having a plurality of first conductive structure elements, the first conductive structure elements each comprising a first conductive via and a first conductive line, the first conductive via is located in the first dielectric layer and the first conductive line is arranged over the first dielectric layer and is electrically connected to the respective first conductive via, the first conductive lines each having a curve shape in a plan view, a second dielectric layer over the first dielectric layer and the first metallization structure, and a second metallization structure in the second dielectric layer, the second metallization structure having a plurality of second conductive structure elements, the second conductive structure elements each comprising a second conductive via in the second dielectric layer, the second conductive via each over a respective first conductive line are arranged and are electrically connected to this. Package structure according to Claim 1 , wherein the second metallization structure is arranged closer to the first integrated circuit die than the first metallization structure. Package structure according to Claim 1 or 2 further comprising a package substrate bonded to a first side of the redistribution structure, wherein the first integrated circuit die is bonded to a second side of the redistribution structure and the first metallization structure is arranged closer to the first side of the redistribution structure than the second metallization structure is. Package structure according to Claim 3 wherein the package substrate is bonded to the first side of the redistribution structure with a first group of conductive interconnection elements and the first integrated circuit die is bonded to the second side of the redistribution structure with a second group of conductive interconnection elements. Package structure according to Claim 4 further comprising: an underfill between the first integrated circuit die and the second side of the redistribution structure, the underfill enclosing the second group of conductive interconnect elements; and an encapsulation material on the second side of the redistribution structure and on sidewalls of the first integrated circuit die and the underfill. The package structure of claim 1, wherein a first angle is formed by a first plane and a second plane, the first plane and the second plane intersecting a first of the plurality of first conductive structure elements and perpendicular to a main surface of the second dielectric layer wherein the first plane extends from a center line of a first conductive via of the first of the plurality of first conductive structure elements to a center line of the second conductive via which is arranged over and connected to the first of the plurality of first conductive structure elements, and the second plane from the centerline of the second conductive via disposed over and connected to the first of the plurality of first conductive features along a first portion of the first conductive line of the first of the plurality of first conductors Like structural elements extends, wherein the first angle is 30 ° to 150 °. Package structure according to one of the preceding claims, wherein the first conductive lines of the plurality of first conductive structure elements each have no corners in the plan view. Package structure according to one of the preceding claims, wherein the first conductive lines each comprise copper and the second dielectric layer comprises a polymer. Package structure according to Claim 8 wherein the second dielectric layer comprises polybenzoxazole (PBO), a polyimide or benzocyclobutene (BCB). A package structure comprising: a first package component comprising: a first module and a second module, wherein the first module comprises a logic chip and the second module comprises a memory chip, and a first redistribution structure with metallization structures in dielectric layers, wherein a first side of the first redistribution structure is physically and electrically connected to the first and the second module and a first metallization structure of the metallization structures in a first dielectric layer of the dielectric layers, the first metallization structure having first conductive structure elements each comprising a first conductive via and a first conductive line, the first conductive via is in the first dielectric layer and the first conductive line above the first dielectric layer is arranged and is electrically connected to the respective first conductive via, wherein the first conductive lines in a plan view each have a curve shape and have no corners; and a second package component having a package substrate bonded to a second side of the first redistribution structure, the second side opposing the first side. Package structure according to Claim 10 wherein the first redistribution structure further comprises: a second dielectric layer over the first dielectric layer and the first metallization structure; and a second metallization structure in the second dielectric layer, the second metallization structure having second conductive structure elements each comprising a second conductive via in the second dielectric layer, the second conductive via being each arranged over a respective first conductive line and electrically with this are connected. Package structure according to Claim 11 wherein the first conductive line connects the first conductive via directly to the second conductive via. Package structure according to Claim 11 or 12th wherein the second metallization structure is arranged closer to the first and the second module than the first metallization structure. Package structure according to one of the Claims 11 until 13th wherein the first conductive lines each comprise copper and the second dielectric layer comprises a polymer. Package structure according to one of the Claims 11 until 14th wherein the first package component further comprises: an underfill between the first module, the second module, and the first side of the first redistribution structure, the underfill extending along first sidewalls of the first and second modules, the first sidewalls of the first and of the second module are facing each other; and an encapsulation material on the first side of the first redistribution structure and on second side walls of the first and second modules, the second side walls of the first and second modules facing away from each other. Package structure according to Claim 15 wherein tops of the first module, the second module, the underfill, and the encapsulation material are coplanar. Procedure with the following steps: Forming a first dielectric layer over a substrate; Patterning the first dielectric layer; Producing a first metallization structure in and along a top side of the structured first dielectric layer, the first metallization structure having first conductive structure elements each comprising a first conductive via and a first conductive line, the first conductive via being located in the first dielectric layer and the first conductive line is arranged along the upper side of the first dielectric layer and is electrically connected to the respective first conductive via, the first conductive lines each having a curve shape in a plan view and having no corners; Producing a second dielectric layer over the structured first dielectric layer and the first metallization structure; Patterning the second dielectric layer; and Producing a second metallization structure in the structured second dielectric layer, the second metallization structure having second conductive vias in the second dielectric layer, the second conductive vias each being electrically connected to a respective first conductive line of the first conductive structure elements. Procedure according to Claim 17 10, further comprising: forming bond pads over the second dielectric layer and the second metallization structure, the bond pads being connected to the second conductive vias; Bonding a first module and a second module to the bond pads, the first module having a logic chip and the second module having a memory chip; Encapsulating the first and second modules in an encapsulation material; Removing the substrate; and separating the encapsulation material, the first and the second metallization structure and the first and the second dielectric layer. Procedure according to Claim 18 which further comprises: after the dicing, bonding the diced structure to a package substrate, wherein the package substrate is arranged on a side of the first and second metallization structure and the first and second dielectric layer opposite the first module and the second module is. Method according to one of the Claims 17 until 19th wherein the first conductive lines each comprise copper and the second dielectric layer comprises a polymer.

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