DE102020121589A1 - Surge protection arrangement - Google Patents

Abstract

Shown and described is an overvoltage protection arrangement (1), in particular for protecting electronic devices that have a power semiconductor, with a varistor (2), with a power semiconductor (3) and with a logic circuit (4), the varistor (2) having a Has rated voltage which is lower than the nominal voltage, the power semiconductor (3) being arranged electrically in series with the varistor (2), the control input (5) of the power semiconductor (3) being connected directly or indirectly to the logic circuit (4), wherein the power semiconductor (3) is deactivated when the nominal voltage is applied to the overvoltage protection arrangement (1) and is activated by the logic circuit (4) at the beginning of an overvoltage event, so that when the power semiconductor (3) is conductive, a current through the varistor (2) and the power semiconductor (3) flows, and the power semiconductor (3) is deactivated again by the logic circuit (4) in the course of the overvoltage event is fourth.

Description

The invention relates to an overvoltage protection arrangement, in particular for protecting electronic devices which have a power semiconductor, with a varistor as an overvoltage component, a power semiconductor and a logic circuit.

From the DE 10 2016 2011 628 A1 An overvoltage protection arrangement is known in which a spark gap or a gas arrester as an overvoltage component is connected in parallel with a separate extinguishing path, if necessary, a semiconductor switch controlled by a logic circuit being arranged in the extinguishing path. The input of the logic circuit is connected to an optical monitoring element that detects the presence of an arc in the overvoltage protection element. When an arc is present, the semiconductor switch is activated via the logic circuit so that the current, which initially only flows through the ignited spark gap or the ignited gas discharge tube, flows via the parallel extinguishing path with the semiconductor switch. If the arc in the overvoltage component is extinguished, the semiconductor switch is deactivated, so that the flow of current via the extinguishing path is also interrupted.

Overvoltage protection arrangements or overvoltage protection devices are intended to protect systems and electrical devices that are connected to supply networks from transient overvoltages that endanger the electrical insulation of the systems and connected devices. Depending on the location and purpose of use, different surge protection devices are used, which differ from one another with regard to their respective protection level, among other things.

The protection level characterizes the ability of an overvoltage protection device to limit a pending overvoltage to a residual voltage. In order for an electrical device to be protected to be reliably protected from harmful overvoltages, the protection level of the overvoltage protection device used must be adapted accordingly to the dielectric strength or insulation strength of the device to be protected. The residual voltage that occurs on the surge protection device while a leakage current is flowing must therefore be lower than the maximum voltage that may be applied to the device to be protected.

If an electronic device with a relatively low dielectric strength is to be protected by an overvoltage protection arrangement, because the electronic device has a power semiconductor in the input, for example, an overvoltage protection device with a correspondingly low protection level must be selected. At the same time, however, it must also be ensured that the response voltage of the overvoltage protection device is so high that it is at a sufficient distance from the operating voltage of the supply network to prevent the overvoltage protection device from responding in the event of operationally permissible temporary overvoltages.

With conventional electrical devices such as transformers and motors, as well as with electrical installations in the form of cables, switches and connectors, the distance between the dielectric strength of the devices against transient overvoltages and the operating voltage is relatively large. If the dielectric strength of a device against transient overvoltages is, for example, 5 kV at a nominal operating voltage of 400 volts, an overvoltage protection device with a protection level of 1.5 kV can be used without any problems, since the distance between the protection level and both the nominal operating voltage and the dielectric strength is sufficiently large .

Such overvoltage protection devices can have different types of overvoltage components. Typical examples are suppressor diodes, varistors, gas-filled surge arresters (GDT) and spark gaps as well as various combinations of these components. All of these components differ in terms of their characteristic discharge behavior and their performance. In the event of leakage, powerful surge protection arrangements based on spark gaps or varistors can generate residual voltages that are a multiple of the actual nominal operating voltage.

As stated above, such high residual voltage values are not critical in robust electrical installations and devices, whereas in semiconductor-based electronic devices they can lead to the destruction or damage of the devices, since their dielectric strength is significantly lower. In overvoltage protection devices that are intended to protect devices with semiconductors, varistors and spark gaps cannot easily be used as overvoltage components.

Overvoltage protection arrangements with overvoltage components in which the residual voltage is lower in the event of a discharge, such as suppressor diodes or gas-filled surge arresters, on the other hand, have the disadvantage that they generate very high follow-up currents up to the order of magnitude of short-circuit currents when operating voltages are applied. This can lead to the surge device itself gets destroyed. If, in addition to the overvoltage protection arrangement, an overcurrent protection arrangement is provided, by means of which the overvoltage component is protected from destruction by the flowing follow current, the flow of a high follow current leads to the intended response of the overcurrent protection arrangement and thus to a failure of the operating voltage. In both cases, the availability of the electrical system or the electrical device is limited, so that the actual aim of the surge protection arrangement, to keep the electrical device or the electrical system in operation, is missed.

The present invention is therefore based on the object of providing an overvoltage protection arrangement described at the outset which is particularly suitable for protecting electronic devices that have a power semiconductor. The overvoltage protection arrangement should have both a relatively high discharge capacity and the lowest possible protection level.

This object is achieved in the overvoltage protection arrangement according to the invention with the features of claim 1. The overvoltage protection arrangement has a varistor, a power semiconductor and a logic circuit, the power semiconductor being arranged electrically in series with the varistor and the control input of the power semiconductor being connected directly or indirectly to the logic circuit. The varistor is designed in such a way that it has a rated voltage that is lower than the nominal voltage of the overvoltage protection arrangement.

The rated voltage of the varistor is the maximum voltage that may be applied to the connection terminals of the varistor during operation at which the varistor is still in the defined, non-conductive state. The state in which a maximum of 1 mA current flows through the varistor as leakage current is regarded as a defined, non-conductive state.

Since the varistor in the overvoltage protection arrangement according to the invention deliberately has a rated voltage that is lower than the nominal voltage, this would result in a current greater than 1 mA flowing through the varistor if the nominal voltage was applied to the overvoltage protection arrangement. The varistor would then no longer be in normal operation, since the varistor would not be insulating when the nominal voltage was applied.

In the overvoltage protection arrangement according to the invention, a varistor dimensioned in this way is therefore connected in series with a power semiconductor which is deactivated when the mains voltage is applied to the overvoltage protection arrangement, so that no current flows through the series connection of varistor and power semiconductor. To achieve the desired discharge function, the power semiconductor is activated by the logic circuit at the beginning of an overvoltage event, so that when the power semiconductor is then conductive, a current flows through the varistor and the power semiconductor. This limits the overvoltage to a value that is below the protection level of the electronic device to be protected, even if it has a power semiconductor in its input.

Relatively large leakage currents can also flow via the varistor without the residual voltage dropping across the varistor exceeding the dielectric strength of the electronic device to be protected. If the overvoltage pulse to be diverted has decayed so far that the overvoltage is within the tolerance range of the nominal voltage, the power semiconductor is deactivated again by the logic circuit. This renewed blocking of the power semiconductor can take place in particular at the end of the overvoltage event, when the value of the overvoltage has correspondingly reduced.

For a supplementary explanation of the behavior of a varistor at different nominal voltages or at different leakage currents, see 1 typical voltage-current characteristics are shown for a plurality of varistors which have different nominal values. The current i is plotted on the X axis and the voltage V is plotted logarithmically on the Y axis. First of all, two areas can be identified from the characteristic curve of the individual varistors. The leakage current range is marked with "A", which represents normal operation when a varistor is used as an overvoltage component. If there is no overvoltage at the varistor, the lowest possible current should flow through the varistor. A leakage current of 1 mA is defined as the limit value, which is still regarded as a non-conductive state.

The second area, marked “B”, is the working area of the varistor. If there is an overvoltage, the varistor becomes low-resistance, so that a leakage current flows through the varistor. Depending on the level of the leakage current, the voltage drop across the varistor also increases somewhat, with a significant increase in voltage not occurring until the end of the working range. The end of the working range is determined by the maximum protection level and the associated surge current.

In 1 the voltage-current characteristic of a varistor with a nominal value of 320 is marked as an example. If a leakage current of 1,000 A flows through such a varistor, a leakage current drops across the varistor Residual voltage of approx. 900 V, which is sufficient as a protection level for an electronic device with a power semiconductor. The voltage-current characteristic curve of the varistor also shows that the rated voltage of the varistor, i.e. the voltage at which a maximum of 1 mA leakage current flows through the varistor, is only around 450 V. With a nominal operating voltage of 400 volts, operationally permissible temporary overvoltages would therefore often result in a leakage current flowing through the varistor, which could damage the varistor or at least reduce the service life of the varistor.

If, for example, an operating voltage of 800 V were applied to the varistor, then the voltage-current characteristic according to FIG 1 that a current of approx. 100 A would then flow through the varistor, which would result in immediate destruction of the varistor. In the overvoltage protection arrangement according to the invention, this is prevented in that the varistor is connected in series with a power semiconductor which is deactivated at the nominal voltage applied to the overvoltage protection arrangement, i.e. at 800 V in the example described above, so that no Electricity flows.

Out 1 It can also be seen that without the series connection of the varistor and power semiconductor according to the invention, a varistor with a nominal value of 550 would have to be used so that only a current of less than 1 mA flows through the varistor when an operating voltage of, for example, 800 V is applied. If a leakage current of 1000 A flows through such a varistor, a residual voltage of approx. 1.75 kV drops across the varistor, which could destroy the electronic device to be protected.

The fact that the overvoltage protection arrangement according to the invention has a varistor whose rated voltage is lower than the nominal voltage of the overvoltage protection arrangement ensures that the overvoltage protection arrangement has both a high discharge capacity and a low protection level. The fact that a power semiconductor is connected in series with the varistor dimensioned in this way prevents an excessively high leakage current from flowing through the varistor when the nominal voltage is applied, which would lead to the destruction of the varistor. In the overvoltage protection arrangement according to the invention, a varistor is used as the overvoltage component which is actually not suitable for the specified nominal operating voltage of the overvoltage protection arrangement.

According to the invention, in an overvoltage protection arrangement with a specific nominal voltage, a varistor is used which, according to its voltage-current characteristic, has a 1 mA point at which the varistor voltage drop across the varistor is lower than the nominal voltage. The varistor is preferably selected so that, according to its voltage-current characteristic, it has a 1 mA point at which the varistor voltage drop across the varistor is a maximum of 90%, preferably a maximum of 60%, in particular a maximum of 40% of the nominal voltage. With a nominal voltage of the overvoltage protection arrangement of 600 V, for example, the varistor is selected so that the rated voltage is less than 600 V, in particular is only a maximum of 540 V, preferably only 360 V or even only 240 V.

If the power semiconductor is activated by the logic circuit in the overvoltage protection arrangement according to the invention, a leakage current begins to flow via the series connection of varistor and power semiconductor when an overvoltage is present. Power semiconductors usually have a current carrying capacity of a few 100 A. In addition, power semiconductors are known which, through a suitable input override beyond the nominal parameters, briefly achieve a current carrying capacity of a few kA ( DE 10 2010 006 525 B4 ). Such power semiconductors, which have a particularly high current-carrying capacity, are, however, relatively expensive and, as a rule, also relatively large.

According to a preferred embodiment of the invention, it is therefore provided that at least one overvoltage component, in particular a spark gap or a gas-filled surge arrester (GDT), is connected in parallel to the power semiconductor, so that the parallel connection of the power semiconductor and overvoltage component is arranged electrically in series with the varistor. The power semiconductor is energetically coordinated with the overvoltage component connected in parallel in such a way that the overvoltage component connected in parallel becomes conductive before the power semiconductor is overloaded due to the current flowing through it, i.e. before the current carrying capacity of the power semiconductor is exceeded.

The coordination between the two parallel current paths, that is to say the current path with the power semiconductor and the current path with the overvoltage component, can take place passively, in particular through suitable dimensioning of the response voltage of the overvoltage component. If a gas-filled surge arrester is used as the surge component, the coordination between the power semiconductor and the gas-filled surge arrester can be carried out in this way be designed so that the leakage current or the current pulse to be diverted initially flows through the power semiconductor and then commutates on this due to the delayed ignition of the gas-filled surge arrester.

According to a preferred embodiment in this regard, the power semiconductor is deactivated again by the logic circuit after the start of an overvoltage event after a first part of the leakage current has flowed through the power semiconductor, so that the power semiconductor becomes highly resistive. The voltage drop across the power semiconductor is then used to ignite the overvoltage component connected in parallel by selecting the response voltage of the overvoltage component so that the overvoltage component ignites due to the voltage drop across the high-resistance power semiconductor connected in parallel.

According to an alternative embodiment of the overvoltage protection arrangement, in which an overvoltage component is also connected in parallel to the power semiconductor, an ignition device is provided which is used to ignite the overvoltage component and which is activated when the current flowing through the varistor and / or the voltage dropping across the varistor reaches a limit value exceeds or exceed. The triggering device is thus triggered as a function of the current flowing through the varistor or the voltage drop across the varistor, for the detection of which the overvoltage protection arrangement then has a corresponding current measuring unit or a voltage measuring unit.

According to a further alternative embodiment, in which an ignition device serving to ignite the overvoltage component is also provided, this ignition device is coupled to the current path in which the power semiconductor is arranged that the overvoltage component due to the current flowing through the current path when the power semiconductor is conductive flows, is ignited. In this embodiment, additional detection or measurement of the current or a falling voltage is therefore not required. The ignition of the parallel overvoltage component is thus initiated directly by the leakage current flowing through the power semiconductor. For this purpose, the ignition device can preferably have a corresponding transformer which generates a high-voltage pulse from the flowing leakage current or the change in current to trigger a spark gap or a gas-filled surge arrester in the parallel branch.

In order to protect the power semiconductor from excessive load from the leakage current flowing through it, the power semiconductor is operated as a switch in such a way that it is switched from the blocking to the conductive state and vice versa as quickly as possible. The switching edges, i.e. the times in which the power semiconductor is partially conductive, are kept as low as possible, which limits the energy consumption in the power semiconductor. For this purpose, a driver is preferably arranged between the control input of the power semiconductor and the output of the logic circuit, so that the control input of the power semiconductor is connected to the logic circuit not directly, but indirectly via the driver. With the aid of such a driver, which is also referred to as a gate driver, the power semiconductor can be switched over particularly quickly. The person skilled in the art is familiar with various driver circuits which can be used depending on the desired conditions of use. The driver can be designed both as a discrete and as an integrated electronic circuit.

The driver and also the logic circuit are preferably designed in such a way that the power semiconductor is activated so quickly at the beginning of an overvoltage event that the overvoltage component connected in parallel with the power semiconductor becomes conductive before the leakage voltage drop across the overvoltage protection arrangement has reached 200% of the nominal voltage. For this purpose, the coordination between the power semiconductor and the overvoltage component connected in parallel is preferably carried out with the aid of an ignition device, which in particular has a magnetic-electrical voltage converter or a piezoceramic voltage converter, so that rapid ignition of the overvoltage component connected in parallel can be achieved.

As previously stated, the power semiconductor is deactivated by the logic circuit in the course of the overvoltage event. If the overvoltage protection arrangement has an overvoltage component connected in parallel to the power semiconductor, the power semiconductor is deactivated after the overvoltage component has been ignited, so that the surge current to be diverted only flows through the ignited overvoltage component. Preferably, in addition to the end of the overvoltage event, the power semiconductor is activated again by the logic circuit, so that the current path via the overvoltage component is again connected in parallel to the current path via the power semiconductor. This leads to the fact that the current commutates again on the current path connected in parallel and having the power semiconductor, and the current through the overvoltage component is extinguished. In order to re-ignite the overvoltage component To avoid the ignition device and in particular a transformer provided as part of the ignition device, the transformer can be designed to be controllable with regard to its transmission behavior. For this purpose, a third winding can be provided, for example, which is then short-circuited when only the line follow current flows through the power semiconductor. The short-circuiting of the third winding then prevents the transformer from generating an ignition pulse which would lead to re-ignition of the overvoltage component.

Since the power semiconductor is only activated again by the logic circuit at the end of the overvoltage event, the surge current to be diverted no longer flows, but only the significantly lower line follow-up current via the parallel current path and thus via the power semiconductor. This ensures that the current then flowing via the power semiconductor does not lead to an overload of the power semiconductor. By deactivating the power semiconductor again, a flowing line follow current can then be finally interrupted.

The final disconnection or deactivation of the power semiconductor, with which a line follow current is interrupted, can be controlled by the logic circuit in that a monitoring element is used to check whether an arc is still pending in the overvoltage component. For example, an optical monitoring element can be used for this purpose. In order to reduce the proportion of required components, however, a preferred embodiment of the invention provides that the power semiconductor is activated by the logic circuit for a certain period of time at the end of the overvoltage event and is then automatically deactivated. This means that the use of additional monitoring elements can be dispensed with. The respective period of time can be predetermined by the logic circuit or determined depending on the application. The duration can, however, also be calculated from certain parameters of the overvoltage protection arrangement, in particular from characteristic values of the overvoltage component and / or the power semiconductor and of the network in which the overvoltage protection arrangement is arranged.

According to a further preliminary embodiment of the invention, the overvoltage protection arrangement has a voltage measuring unit that detects the voltage applied to the overvoltage protection arrangement, the power semiconductor being activated at the beginning of an overvoltage event when the voltage measured by the voltage measuring unit exceeds a limit value. The power semiconductor is thus activated on the basis of a measured increased voltage.

According to a further advantageous embodiment, a current measuring unit is provided which detects the current flowing through the overvoltage component, the power semiconductor being reactivated by the logic circuit when the current measured by the current measuring unit falls below a limit value. The renewed activation of the power semiconductor therefore takes place as a function of the current that flows through the overvoltage component, whereby it can be determined whether the current is still the surge current to be diverted or a system follow-up current. The renewed activation of the power semiconductor at the end of the overvoltage event can additionally also take place taking into account the voltage measured by the voltage measuring unit and also taking into account a predetermined time period. For example, the power semiconductor is reactivated by the logic circuit when the measured current and / or the measured voltage has fallen below a threshold value for a certain period of time. This is then interpreted as the end of the actual overvoltage event, so that the power semiconductor can be activated again in order to interrupt a line follow current or to extinguish the arc pending in the overvoltage component.

As has been explained above, the second activation of the power semiconductor takes place preferably for a predefined or predefinable or specific period of time. In order to ensure that the arc in the overvoltage component has been extinguished during the renewed activation of the power semiconductor, on the one hand the duration can be selected to be relatively long. As an alternative to this, it can be provided that, after the second deactivation of the power semiconductor, an analysis of the applied voltage and / or of the current flowing through the overvoltage component takes place. This makes it possible to check whether the intended deletion process was successful, i. E. H. mains follow current no longer flows through the overvoltage protection arrangement. If the analysis reveals that the arc was not extinguished successfully, so that a line follower current is still flowing, the power semiconductor is activated again and then deactivated, i.e. the extinguishing process is carried out again. The time period during which the power semiconductor is activated again can deviate from the previously selected or determined time period, in particular it can be selected to be shorter.

The logic circuit that activates and deactivates the power semiconductor can be can for example be a microcontroller. However, one or more state memories, such as RS flip-flops, can also be used as the logic circuit, so that the logic circuit has at least one bistable multivibrator.

It was previously stated that the overvoltage protection arrangement preferably has an ignition device with which a spark gap connected in parallel with the power semiconductor or a gas-filled surge arrester can be ignited. The ignition device can, for example, have a trigger electrode as is well known from the prior art. In this case, the ignition device can in particular also have a transmitter in addition to the trigger electrode.

IGBTs or MOSFETs are preferably used as power semiconductors. However, other fast-switching elements, such as thyristors, can also be used. A microcontroller is preferably used as the logic circuit in the overvoltage protection arrangement according to the invention, the voltage of which can be supplied via the applied mains voltage, an internal or external voltage source or the voltage of the overvoltage event.

• 1 ein Diagramm der Spannungs-Stromkennlinien für eine Mehrzahl von Varistoren,
• 2 ein vereinfachtes Schaltbild eines ersten Ausführungsbeispiels der erfindungsgemäßen Überspannungsschutzanordnung,
• 3 ein vereinfachtes Schaltbild eines zweiten Ausführungsbeispiels der erfindungsgemäßen Überspannungsschutzanordnung,
• 4 ein vereinfachtes Schaltbild eines weiteren Ausführungsbeispiels der erfindungsgemäßen Überspannungsschutzanordnung,
• 5 ein Schaltbild eines Ausführungsbeispiels der Überspannungsschutzanordnung, ähnlich dem Ausführungsbeispiel gemäß 4, und
• 6 ein Schaltbild eines weiteren Ausführungsbeispiels der Überspannungsschutzanordnung, ähnlich dem Ausführungsbeispiel gemäß 5

In particular, there are a large number of possibilities for designing and developing the overvoltage protection arrangement according to the invention. For this purpose, reference is made both to the patent claims and to the following description of preferred exemplary embodiments in conjunction with the drawing. Show in the drawing

• 1 a diagram of the voltage-current characteristics for a plurality of varistors,
• 2 a simplified circuit diagram of a first embodiment of the overvoltage protection arrangement according to the invention,
• 3rd a simplified circuit diagram of a second embodiment of the overvoltage protection arrangement according to the invention,
• 4th a simplified circuit diagram of a further embodiment of the overvoltage protection arrangement according to the invention,
• 5 a circuit diagram of an embodiment of the overvoltage protection arrangement, similar to the embodiment according to 4th , and
• 6th a circuit diagram of a further embodiment of the overvoltage protection arrangement, similar to the embodiment according to FIG 5

The 2 to 4th each show a greatly simplified circuit diagram of an exemplary embodiment of the overvoltage protection arrangement according to the invention 1 . The surge protection arrangement 1 in particular has a varistor 2 , a power semiconductor 4th and a logic circuit 5 which can be, for example, a microcontroller or a simplified logic in the form of a status memory. How out 2 can be seen is the control input 5 of the power semiconductor 3rd directly to the exit 6th the logic circuit 4th connected. Because the power semiconductor 3rd electrically in series with the varistor 2 is arranged, also flows in one to the overvoltage protection arrangement 1 pending voltage that is greater than the rated voltage of the varistor 2 is only then a current through the varistor 2 when the power semiconductor 3rd is activated so that it is switched on.

The control of the power semiconductor 3rd through the logic circuit 4th takes place in such a way that the power semiconductor 3rd at the overvoltage protection arrangement 1 pending nominal voltage of the overvoltage protection arrangement 1 is deactivated so that no current through the power semiconductor 3rd and the varistor 2 flows even if the applied nominal voltage is greater than the rated voltage of the varistor 2 is. At the beginning of an overvoltage event, the power semiconductor becomes 3rd through the logic circuit 4th activated, so that then a leakage current through the series connection of varistor 2 and power semiconductors 3rd flows through the low resistance of the varistor 2 the pending overvoltage is limited to a value that is below the dielectric strength of the electronic device to be protected, even if it has a power semiconductor in the input.

About the varistor 2 Relatively large leakage currents can also flow without this via the varistor 2 falling residual voltage exceeds the dielectric strength of the electronic device to be protected. If the overvoltage pulse to be diverted has decayed so far that the overvoltage is within the tolerance range of the nominal voltage, the power semiconductor becomes 3rd from the logic circuit 4th deactivated again. This renewed locking of the power semiconductor 3rd can occur in particular at the end of the overvoltage event, when the value of the overvoltage has been reduced accordingly. Since then there is no more current through the varistor 2 flows, the flow of a system follow current and thus the destruction of the varistor 2 prevented.

This in 3rd The simplified circuit diagram shown here differs from the one in 2 shown circuit diagram that in the embodiment according to 3rd the power semiconductor 3rd another surge component in parallel is switched, which in the illustrated embodiment is a spark gap 7th acts. Alternatively, a gas-filled surge arrester can also be used as the surge component 8th are used, as in the embodiments according to 5 and 6th is shown. In this embodiment, the varistor 2 the parallel connection of power semiconductors 3rd and spark gap 7th or gas-filled surge arrester 8th connected in series. The power semiconductor 3rd and the spark gap connected in parallel 7th are energetically coordinated with each other in such a way that the spark gap 7th becomes conductive before the power semiconductor 3rd is overloaded due to the leakage current flowing through it.

According to the embodiment shown in 4th is shown is an ignition device for energetic coordination 9 provided in such a way with the current path 10 , in which the power semiconductor 3rd is arranged, is coupled that the spark gap 7th due to the current flowing through the current path 10 flows, is ignited. The intentional ignition of the spark gap 7th then leads to the leakage current from the current path 10 with the power semiconductor 3rd on the current path 11 with the spark gap 7th commutes. This is the case with the 4th illustrated embodiments a transformer 12th provided together with an ignition electrode 13th the igniter 9 forms.

After the spark gap has ignited 7th the surge current to be diverted then flows through the spark gap that has been ignited 7th and no longer through the power semiconductor 3rd . To one after the discharge process in the spark gap 7th The power semiconductor is used to extinguish any pending arc 3rd at the end of the overvoltage event from the logic circuit 4th reactivated so that the flowing line follow current from the current path 11 with the spark gap 7th on the current path 10 with the power semiconductor 3rd commutes. By deactivating the power semiconductor again 3rd a flowing line follow current can then be finally interrupted. As a result, the line follow current from the current path 11 on the current path 10 is commutated, the arc is extinguished in the spark gap 7th .

As shown in the schematic representation 5 can be seen, the overvoltage protection arrangement 1 in this embodiment one more driver 14th on that between the exit 6th the logic circuit 4th and the control input 5 of the power semiconductor 3rd is arranged. With the help of the driver 14th can be achieved that the power semiconductor 3rd can be brought from the blocking to the fully conductive state and vice versa as quickly as possible, thereby reducing the energy consumption in the power semiconductor 3rd and thus its burden is reduced.

This schematic representation also shows a voltage measuring unit 15th and a current measuring unit 16 as part of the surge protection arrangement 1 . With the voltage measuring unit 15th can affect the overvoltage protection arrangement 1 pending voltage can be detected, so that the power semiconductor 3rd then through the logic circuit 4th is activated when the voltage measuring unit 15th detected voltage exceeds a limit value. With the help of the current measuring unit 16 becomes over the ignited gas-filled surge arrester 8th flowing stream captured. A renewed activation of the power semiconductor 3rd at the end of the overvoltage event can then be triggered when the from the current measuring unit 16 The recorded current falls below a limit value, which is taken as a sign that only a system follow current and no longer the leakage current is flowing.

In addition to the in 5 voltage measuring unit shown 15th and the current measuring unit 16 can also be provided a further current measuring unit, the through the varistor 2 flowing current recorded. A current measuring unit can also be provided, which is a supplement to the voltage measuring unit 15th serves to detect an overvoltage event.

From the schematic representation of the logic circuit 4th in 5 can be seen that the logic circuit 4th several input variables can be supplied, which are derived from the analog or digital analysis of current changes or voltage changes and / or current levels or voltage levels and the comparison with limit values. In addition, the logic circuit 4th also have a timing element which is provided for the power semiconductor 3rd to activate at the end of the overvoltage event for a specified period of time. During this period of time, this changes the current path 11 via the gas-filled surge arrester 8th the current path 10 about the power semiconductor 3rd connected in parallel so that the current is on the current path 10 commutated, and one in the gas-filled surge arrester 8th pending arc extinguishes.

In 6th Figure 3 is a simplified circuit diagram of one embodiment of the surge protection arrangement 1 shown, its structure initially according to the circuit diagram 5 corresponds to. In addition, a circuit is shown here as an example, with which the transmission behavior of the transformer 12th is controllable. By controlling the transformer 12th is to prevent the gas-filled surge arrester 8th is re-ignited by an ignition pulse, if over the again activated power semiconductor 3rd only the line follow current should flow to one in the gas-filled surge arrester 8th extinguish pending arc.

This is what the transformer instructs 12th first a third winding 17th on, which is arranged on the side of the secondary winding. This third winding 17th can across the diode bridge 18th be short-circuited so that then from the transformer 12th no more ignition pulse at the ignition electrode 13th is generated, which leads to a re-ignition of the gas-filled surge arrester 8th would lead. For short-circuiting the diode bridge 18th is a second power semiconductor 19th provided by a simplified logic circuit, namely an AND gate 20th with an inverted input 21 is controlled. Here, too, is between the AND element 20th and the control input of the second power semiconductor 19th a driver 22nd arranged to enable rapid switching of the power semiconductor 19th to enable.

How out 6th can be seen is the inverted input 21 of the AND element 20th with the output of the voltage measuring unit 15th connected while the other input 23 of the AND element 20th with the output of the logic circuit 4th connected is. For the aforementioned condition that there is no longer any overvoltage, the power semiconductor 3rd however by the logic circuit 4th is still activated, so that a gas-filled surge arrester 8th pending arc can be extinguished is shown at the inverted input 21 of the AND element 20th a logical "0" and at the other input 23 a logical "1", so that at the output 24 of the AND element 20th a logical "1" is pending. This leads to activation of the second power semiconductor 19th and thus to a short circuit of the third winding 17th over the diode bridge 18th .

Regarding the in the 2 to 6th It should be pointed out that the simplified circuits shown here always represent only one circuit for a unidirectional system. However, the present invention is not restricted to this, but can also be used in a bidirectional system. In this case, control would accordingly be implemented twice or suitable rectifiers would be used.

List of reference symbols

1.

Surge protection arrangement

2.

Varistor

3.

Power semiconductors

4th

Logic circuit

5.

Control input

6th

output

7th

Spark gap

8th.

ÜSaG

9.

Ignition device

10.

Current path

11.

Current path

12th

transformer

13th

Ignition electrode

14th

driver

15th

Voltage measuring unit

16.

Current measuring unit

17th

3. winding

18th

Diode bridge

19th

Power semiconductors

20th

AND element

21.

inverted input

22nd

driver

23

other entrance

24

output

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• DE 1020162011628 A1 [0002]
• DE 102010006525 B4 [0023]

Claims (16)

Overvoltage protection arrangement (1), in particular for protecting electronic devices that have a power semiconductor, with a varistor (2), with a power semiconductor (3) and with a logic circuit (4), the varistor (2) having a rated voltage that is lower than the rated voltage, wherein the power semiconductor (3) is arranged electrically in series with the varistor (2), wherein the control input (5) of the power semiconductor (3) is connected directly or indirectly to the logic circuit (4), wherein the power semiconductor (3) is deactivated when the nominal voltage is applied to the overvoltage protection arrangement (1) and is activated by the logic circuit (4) at the beginning of an overvoltage event, so that when the power semiconductor (3) is conductive, a current through the varistor (2) and the power semiconductor (3) flows, and wherein the power semiconductor (3) is deactivated again by the logic circuit (4) in the course of the overvoltage event. Overvoltage protection arrangement (1) according to Claim 1 , characterized in that the varistor (2) has, according to its voltage-current characteristic, a 1 mA point at which the varistor voltage drop across the varistor (2) is less than the nominal voltage. Overvoltage protection arrangement (1) according to Claim 2 , characterized in that the varistor (2) has a 1 mA point according to its voltage-current characteristic, at which the varistor voltage dropping across the varistor (2) is a maximum of 90%, preferably a maximum of 60%, in particular a maximum of 40% of the nominal voltage. Overvoltage protection arrangement (1) according to one of the Claims 1 to 3rd , characterized in that at least one overvoltage component (7, 8), in particular a spark gap (7) or a gas-filled surge arrester (8), is connected in parallel to the power semiconductor (3), so that the parallel connection of the power semiconductor (3) and the overvoltage component (7 , 8) is arranged electrically in series with the varistor (2), and that the power semiconductor (3) is energetically coordinated with the overvoltage component (7, 8) connected in parallel in such a way that the overvoltage component (7, 8) connected in parallel becomes conductive before the power semiconductor (3) is overloaded due to the current flowing through it. Overvoltage protection arrangement (1) according to Claim 4 , characterized in that the coordination between the power semiconductor (3) and the overvoltage component (7, 8) connected in parallel takes place passively by suitable dimensioning of the response voltage of the overvoltage component (7, 8). Overvoltage protection arrangement (1) according to Claim 4 , characterized in that the power semiconductor (3) is deactivated again by the logic circuit (4) after the start of an overvoltage event, so that the power semiconductor (3) has a high resistance, and that the response voltage of the overvoltage component (7, 8) is selected so that the overvoltage component (7, 8) becomes conductive due to the voltage dropping across the high-resistance power semiconductor (3) connected in parallel. Overvoltage protection arrangement (1) according to one of the Claims 1 to 4th , characterized in that an ignition device is provided which is used to ignite the overvoltage component (7, 8) and is activated when the current flowing through the varistor (2) and / or the voltage drop across the varistor (2) exceeds a limit value. Overvoltage protection arrangement (1) according to one of the Claims 1 to 4th , characterized in that an ignition device (9) serving to ignite the overvoltage component (7, 8) is provided which is coupled to the current path (10) in which the power semiconductor (3) is arranged that the overvoltage component (7 , 8) is ignited due to the current which flows through the current path (10) when the power semiconductor (3) is conducting. Overvoltage protection arrangement (1) according to Claim 8 , characterized in that the ignition device (9) has a magneto-electrical voltage converter (12) or a piezoceramic voltage converter. Overvoltage protection arrangement (1) according to Claim 9 , characterized in that the magneto-electrical voltage converter (12) or the piezoceramic voltage converter can be controlled with regard to its transmission behavior. Overvoltage protection arrangement (1) according to one of the Claims 1 to 10 , characterized in that a driver (14) is arranged between the control input (5) of the power semiconductor (3) and the output (6) of the logic circuit (4). Overvoltage protection arrangement (1) according to Claim 11 , characterized in that the power semiconductor (3) is activated so quickly at the beginning of an overvoltage event by the logic circuit (4) and the driver (14) and the power semiconductor (3) so energetically with the overvoltage component (7, 8) connected in parallel it is coordinated that the overvoltage component (7, 8) connected in parallel becomes conductive before the discharge voltage dropping across the overvoltage protection arrangement (1) has reached 200% of the nominal voltage. Overvoltage protection arrangement (1) according to one of the Claims 4 to 12th , characterized in that the power semiconductor (3) is reactivated at the end of the overvoltage event by the logic circuit (4) for a predefined or predefinable period of time or for a variable period of time dependent on parameters and then deactivated again. Overvoltage protection arrangement (1) according to one of the Claims 1 to 13th , characterized in that a voltage measuring unit (15) is provided which detects the voltage applied to the overvoltage protection arrangement (1) and that the power semiconductor (3) is activated at the beginning of an overvoltage event when the voltage measured by the voltage measuring unit (15) has a Exceeds limit. Overvoltage protection arrangement (1) according to Claim 13 or 14th , characterized in that a current measuring unit (16) is provided which detects the current flowing through the overvoltage component (7, 8) and that the power semiconductor (3) is reactivated when the current measured by the current measuring unit (16) reaches a limit value falls below. Overvoltage protection arrangement (1) according to Claim 14 or 15th , characterized in that several input variables can be fed to the logic circuit (4) which are derived from the analog or digital analysis of current changes or voltage changes and / or current levels or voltage levels and the comparison with limit values.

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