DE102020100353B3 - Process for the production of a back-contacted solar cell and a back-contacted solar cell - Google Patents

Abstract

The invention relates to a method for producing a rear-side-contacted solar cell (10), a surface structure with a grid of columns and rows running orthogonally being generated on a rear side (16) of a semiconductor substrate (12), a plurality of elevations ( 18) and depressions (20) are provided, which are arranged in such a way that elevations and depressions alternate both in the course along each column and in the course along each row, the rear side of the semiconductor substrate being doped in such a way that n -Type-doped regions (22) and p-type-doped regions (24) are generated, which each extend along columns of the grid, and that viewed along each row, at least in regions, all elevations are either exclusively n-type-doped regions or p-type doped regions, electrodes (30, 32) for making electrical contact with the doped Be rich are generated, each electrode being assigned to either an n-type doped region or a p-type doped region, and where busbars are produced for electrically connecting the electrodes, the busbars being designed such that each busbar only has electrodes Connects areas of the same doping. The invention also relates to a rear-side-contacted solar cell.

Description

The invention relates to a method for producing a rear-side-contacted solar cell, as well as a rear-side-contacted solar cell.

Solar cells are known to serve as photovoltaic elements for converting light into electrical energy. Charge carriers that are generated during the absorption of light in a semiconductor substrate are separated and directed into areas of different polarity, e.g. at a pn junction between an emitter area that has a first doping type, e.g. n-type or p-type (for Generation of a first polarity), and a base region, which has an opposite doping type (for generating an opposite polarity). Solar cells with highly doped layers are z. B. as HJT solar cells (HJT = Hetero Junction Technology), HIT solar cells (HIT = Heterojunction with Intrinsic Thin layer), TOPCon solar cells (TOPCon = Tunnel Oxide Passivated Contact) or as POLO solar cells (POLO = polysilicon on oxide) Known solar cells. The charge carriers generated and separated in this way can be fed to an external circuit via emitter contacts which contact the emitter region and base contacts which contact the base region.

Solar cells are known in which contacts of one polarity are arranged on the front side and contacts of the opposite polarity are arranged on the rear side. In order to minimize losses resulting from shading by the contacts on the front side, rear contact solar cells have been developed in which both types of contact, i.e. the emitter contacts and the base contacts, are arranged on a rear side of the semiconductor substrate. For example, solar cells have been developed with comb-shaped, nested metal contacts (so-called “contact fingers” or electrodes) of both polarity types arranged on their rear surface. Such solar cells are usually referred to as IBC solar cells (interdigitated backcontact).

In such IBC solar cells, the electrodes of a respective polarity are usually electrically connected to one another via one or more busbars in order to collectively feed the charge carriers generated to an external circuit. These busbars run orthogonally to the electrodes and must therefore cross the electrodes of the other polarity. In order to avoid a short circuit between busbars of one polarity and the electrodes of the other polarity, it is known to interrupt the electrodes locally at the intersections. However, such a contact interruption usually leads to a loss of efficiency of the solar cell. From the US 2015/0 380 571 A1 and the WO 2014/117 216 A1 Rear-side-contacted solar cells with busbars arranged transversely to doping areas are known. The US 2015/0 380 571 A1 discloses recesses along columns for the same dopant type and the WO 2014/117 216 A1 discloses contacts arranged alternately in columns and rows orthogonal thereto for n-type-doped and p-type-doped regions. It is also known to provide an insulating layer between busbars and electrodes of different polarity. However, the application of such an insulating layer is generally only possible with comparatively complex mask processes, which increases the production costs of the solar cell.

On this basis, the present invention is concerned with the task of providing an inexpensive solar cell with a high degree of efficiency.

This object is achieved by a method for producing a rear-side-contacted solar cell, which comprises the method steps according to claim 1, as well as by a rear-side-contacted solar cell according to the independent claim 14.

According to the method, a semiconductor substrate is first provided which has a front side and a rear side. In particular, the semiconductor substrate can be a silicon wafer. In a further step, a surface structure in the form of a grid of columns and rows running orthogonally thereto is then produced on the rear side of the semiconductor substrate, a plurality of flatly extending elevations and depressions being provided in the grid. In this respect, a surface structure is produced on the rear side of the semiconductor substrate with a multiplicity of regions that are lower with respect to a reference plane and regions that are higher with respect to the reference plane. The elevations and depressions are arranged in such a way that elevations and depressions alternate both in the course along each column and in the course along each row. In other words, a surface structure comprising a plurality of flatly extending elevations and depressions is produced on the rear side of the semiconductor substrate, elevations and depressions alternating, so to speak, in a checkerboard pattern. It is possible for the grid to extend over the entire extent of the rear side of the semiconductor substrate. It is also possible that the grid extends only over a partial area of the extent of the rear side of the semiconductor substrate.

In principle, the elevations and depressions can have any basic shape. However, it is preferred if the elevations and depressions, viewed orthogonally on the rear side of the solar cell, have a square or rectangular or round or oval basic shape, that is to say are delimited by a square or rectangular or round or oval contour.

According to the method, in a further step the rear side of the semiconductor substrate is doped in such a way that regions with n-type doping (for generating a first polarity) and regions with p-type doping (for generating a second, opposite polarity) are generated. Depending on the doping of the semiconductor substrate, the doped regions then in particular either form emitter regions of the solar cell or a so-called back surface field. The doping can take place, for example, by means of laser doping. According to the method, the doping takes place in such a way that the n-type doped regions and the p-type doped regions each extend along columns of the grid. In particular, the doping takes place in such a way that the n-type doped regions and the p-type doped regions each extend in an elongated, preferably linear manner, along columns of the grid, in particular along the entire longitudinal extent of the respective column. In this respect, the doped regions preferably each extend over a plurality of elevations and depressions in the course along a column. The doped regions then have periodic height differences in the course along their respective longitudinal extent. Doping is preferably carried out in such a way that n-type doped regions and p-type doped regions do not touch one another. In this respect, a respective width of the doped regions, that is to say an extension orthogonal to their longitudinal extension, is in particular less than a column width of the grid.

According to the method, doping is also carried out in such a way that viewed along each row of the grid, at least in regions, i.e. at least over a subset of the columns of a row, but in particular over the entire length of the row, all elevations are either exclusively n-type doped Areas or exclusively p-type doped areas. In this respect, viewed along each line, at least in certain areas, only areas with the same doping are located on the raised surface level of the elevations. However, this does not rule out the fact that outside the grid with areas doped in this way there are further grid areas or other material protrusions which have no doping or a different type of doping.

In a further step of the method, electrodes for making electrical contact with the doped regions are then produced. The electrodes are produced in such a way that each electrode is assigned either to an n-type doped area or a p-type doped area and only makes contact with this area. The electrodes are designed in particular to discharge the charge carriers extracted in the semiconductor substrate at the pn junction between the emitter region and the base. The electrodes are preferably designed in the form of metal electrodes. For example, it is conceivable that the electrodes are produced by means of screen printing or inkjet printing. Alternatively, the electrodes can also be produced galvanically or by means of physical vapor deposition (PVD).

The electrodes preferably extend elongated, in particular linearly, along the longitudinal extent of the doped region assigned to them, that is to say along columns of the grid. In particular, the electrodes extend over the entire longitudinal extent of the doped region assigned to them. In this case, the electrodes preferably extend over several elevations and depressions in the course along a column. The electrodes follow the height profile of the underlying semiconductor substrate, so that the height of an electrode surface changes periodically in the course along each column.

Since, viewed along each line, at least in sections, all elevations exclusively comprise areas with the same doping (i.e. either n-type doping or p-type doping), only electrodes with the same polarity are located on the at least in sections along each line increased surface level of the elevations. This makes it possible to electrically connect the electrodes of the same polarity to one another in a simple manner along a row and thus to collectively feed the charge carriers removed by the electrodes to an external circuit.

For this purpose, in a further step of the method, current busbars, so-called “busbars”, are produced, which are designed such that each current busbar either only connects electrodes from n-type doped areas or only electrodes from p-type doped areas . The busbars are designed in such a way that each busbar only electrically connects electrodes of the same polarity to one another. In particular, the busbars are thus arranged in such a way that they run at the level of the elevations. Then the electrode sections which are arranged in the depressions are not contacted. The busbars preferably extend essentially transversely to the direction of the columns, in particular along rows of the Grid, so in particular orthogonal to a longitudinal extension of the doped areas.

Overall, such a method thus makes it possible to electrically connect electrodes of the same polarity to one another in a simple manner. Due to the special surface structure, it is in particular not absolutely necessary to provide additional insulation layers in order to avoid a short circuit between busbars of one polarity and electrodes of the opposite polarity. In addition, before the busbars are applied and soldered, an insulating layer, e.g. in the form of a lacquer or paste, can be applied, which only covers and insulates the deeper fingers. Due to the different levels, with a suitable choice of the insulating layer, the application of the insulating layer is also possible without a mask.

In this way, the process costs for the production of a back-contact solar cell can be reduced considerably. In addition, it is also not necessary to interrupt the electrodes in sections, which has a positive effect on the efficiency of a solar cell produced in this way.

The production of the busbars includes in particular the application of the busbars and the electrical contacting of the busbars with the electrodes. In this case, electrical contact can be made in particular by materially connecting a respective busbar to the electrodes assigned to it, for example by means of soldering and / or welding and / or bonding. For example, the busbars can be metal wires, in particular tinned copper wires.

The rear side of the semiconductor substrate is preferably doped in such a way that n-type doped regions and p-type doped regions, viewed along each row, alternate periodically from column to column. Then, viewed along each row, all elevations comprise either exclusively n-type doped regions or exclusively p-type doped regions and all depressions accordingly comprise either exclusively p-type doped regions or exclusively n-type doped regions. In this respect, electrodes of regions of one doping type, viewed along a line, lie at the same height, while the electrodes of regions of the other doping type are at a different height. In such a configuration with doping alternating from column to column, a distance between the electrodes of the same polarity (pitch) is reduced, which increases the efficiency of the solar cell.

It is particularly preferred if doping takes place in such a way that n-type doped regions and p-type doped regions, viewed along each row, alternate from column to column and that the n-type doped regions and the p- Type-doped regions each extend along the entire extent of a respective column of the grid. In this respect, n-type doped regions and p-type doped regions, viewed along each row, alternate in the same way from column to column.

In order to further simplify contacting the electrodes of the same polarity by the busbars, it is also preferred if the surface structure is generated in such a way that all elevations lie on a common first surface level and all depressions lie on a common second surface level. In other words, the surface structure is generated in particular in such a way that the elevations lie in a first plane and the depressions lie in a second plane, the second plane being lower than the first plane with respect to a reference plane. In this respect, the surface structure has at least two height levels (z-direction). It is important that at the end of the process only the electrodes on the higher or the highest level are not covered by the insulating varnish.

The surface structure can be produced, for example, by means of a material-removing process. In particular, the surface structure is generated by means of ablation and / or etching. A particularly preferred embodiment of the method provides that, in order to generate the surface structure, an etch-resistant layer is first applied, which is selectively removed in a subsequent intermediate step by means of laser ablation or, alternatively, by a photolithographic method. In particular, the etch-resistant layer is selectively ablated in such a way that a grid of columns and rows running orthogonally is generated, a plurality of areas with ablated etch-resistant layer and areas with an existing etch-resistant layer being provided in the grid, and the areas with ablated etch-resistant layer Layer and the areas with an existing etch-resistant layer are arranged in such a way that areas with removed etch-resistant layer and areas with existing etch-resistant layer alternate both in the course along each column and in the course along each row. The surface structure is then produced in an etching step following the laser ablation step. This takes place in particular in that, during the etching step, more material is removed in the areas with removed etch-resistant layer than in the areas with an existing etch-resistant layer Layer. In this respect, local depressions are produced on the rear side of the semiconductor substrate in the areas with the removed etch-resistant layer. Remnants of the etch-resistant layer can optionally be removed in a further process step. Such a method makes it possible to generate a defined height profile on the rear side of the semiconductor substrate in a comparatively simple and inexpensive manner.

Alternatively, the etch-resistant layer can be made by means of a mask or z. B. can only be applied locally with an inkjet printer. The intermediate step of local selective removal is then omitted.

In order to further reduce the risk of undesired contacting of busbars of one polarity with electrodes of the opposite polarity, it can be advantageous if the electrodes are produced in such a way that a thickness of the electrodes, in particular a thickness of the electrode sections arranged in the depressions, is smaller in terms of amount as a height offset between the elevations and depressions. To this extent, the electrodes are generated in particular in such a way that an extension of the electrodes along the surface normal to the rear side is smaller in terms of amount than a height difference between elevations and depressions along the surface normal to the rear side. In other words, the electrodes are generated in particular in such a way that an electrode surface of an electrode which is arranged in a depression does not protrude over an edge of an adjacent elevation of the semiconductor substrate. It is important that the heights of the electrode surfaces differ.

Even if, as explained above, it is basically not absolutely necessary to provide an insulating layer between busbars of one polarity and electrodes of opposite polarity, it can still be advantageous to apply an insulating layer made of an electrically insulating material before producing the busbars. This can further reduce the risk of an undesired short circuit. An insulating layer is preferably applied in such a way that the electrode sections arranged in the depressions, preferably exclusively these, are covered at least in sections by the insulating layer in such a way that these electrode sections are electrically insulated from busbars located above them. In this case, a thickness of the insulating layer is set in particular such that a surface of the insulating layer does not protrude beyond an edge of an adjacent elevation of the semiconductor substrate. The insulating layer must only not cover the electrode surface of the higher or highest electrodes. The insulating layer is allowed to cover the edge of the semiconductor substrate and also the entire semiconductor substrate. The insulating layer can be applied, for example, by applying a material formulation which, after application, forms an electrically insulating layer. For example, the material formulation can be in the form of a paste or lacquer, comprising an electrically insulating material. Due to the surface structure of the semiconductor substrate, it is possible to selectively apply the insulating layer only in the depressions, even without a mask, which considerably reduces the process costs. For example, it is conceivable that a lacquer made of an electrically insulating material is applied by means of spin coating. The thickness of the lacquer is preferably chosen so that the surface of the higher electrodes is not covered.

The object set out at the beginning is also achieved by a rear-side-contacted solar cell which is produced in particular by means of a method explained above. The features and advantages explained above in connection with the method can also be used to design the solar cell.

The rear-side-contacted solar cell comprises a semiconductor substrate, in particular in the form of a silicon wafer, with a front side and a rear side. On its rear side, the semiconductor substrate has a surface structure with a grid of columns and rows running orthogonally thereto, a plurality of flatly extending elevations and depressions being provided in the grid. The elevations and depressions are arranged in such a way that elevations and depressions alternate both in the course of each column and in the course along each row. In this respect, elevations and depressions are in particular arranged in a checkerboard pattern.

The semiconductor substrate also has n-type doped regions and p-type doped regions on its rear side, the n-type doped regions and the p-type doped regions each extending along columns of the grid. The n-type doped regions and the p-type doped regions preferably each extend over a plurality of elevations and depressions in the course along a respective column, in particular over the entire extent of the column.

The n-type-doped areas and the p-type-doped areas are arranged in such a way that viewed along each line of the grid, at least in some areas, but in particular over the entire extent of the line, all elevations are either exclusively n-type-doped Areas or exclusively p-type doped areas include. However, this does not rule out the fact that outside the grid with areas doped in this way there are further grid areas or other functional areas of the solar cell which have no doping or a different type of doping.

The solar cell also includes electrodes, in particular in the form of metal electrodes, which contact the doped regions. Each electrode is assigned to either an n-type doped area or a p-type doped area and only makes contact with this area. The electrodes preferably extend along a longitudinal extension of the doped region assigned to them.

For the electrical connection of the electrodes, busbars are provided, the busbars being designed such that each busbar connects either only electrodes from n-type doped areas or only electrodes from p-type doped areas. In particular, the busbars run along lines of the grid, that is to say in particular orthogonally to a longitudinal extension of the electrodes.

The efficiency of the solar cell is particularly high when areas with n-type doping and areas with p-type doping alternate periodically from column to column when viewed along each row. It is particularly preferred if n-type-doped regions and p-type-doped regions, viewed along each row, alternate from column to column and the n-type-doped regions and p-type-doped regions along the entire length Extend extension of a respective column of the grid.

It is also preferred if all of the elevations are on a common first surface level and all of the depressions are on a common second surface level. The semiconductor substrate then has two height levels. However, it is also possible for the semiconductor substrate to have more than two height levels.

In order to further reduce the risk of undesired contact between busbars of one polarity and electrodes of the opposite polarity, it is also preferred if a thickness of the electrodes, in particular a thickness of the electrodes of the electrode sections arranged in the depressions, is less in terms of amount than a height offset between the Elevations and depressions.

For this purpose it can also be advantageous if an insulating layer is provided. In this case, the insulating layer is designed and arranged in particular in such a way that it electrically insulates electrode sections which are arranged in the depressions from busbars located above them. The insulating layer is preferably designed and arranged in such a way that it covers the electrode sections arranged in the depressions, in particular exclusively these, at least in sections.

In order to further improve a light yield and thus an efficiency of the solar cell, the semiconductor substrate can optionally have an anti-reflection layer on its front side.

The invention is explained in more detail below with reference to the figures.

• 1 Skizzierte Darstellung eines Bereichs einer rückseitenkontaktierten Solarzelle in einer perspektivischen Ansicht bei Blick auf die Rückseite der Solarzelle; und
• 2a
• bis 2d Skizzierte Darstellungen zur Erläuterung einer Ausgestaltung des Verfahrens zur Herstellung einer rückseitenkontaktierten Solarzelle gemäß 1.

Show it:

• 1 Sketched representation of a region of a rear-side-contacted solar cell in a perspective view when looking at the rear side of the solar cell; and
• 2a
• to 2d Sketched representations to explain an embodiment of the method for producing a rear-side-contacted solar cell according to FIG 1 .

In the following description and in the figures, the same reference symbols are used for identical or corresponding features.

The 1 shows a sketched representation of a region of a solar cell with contact on the back 10 , in short as a solar cell 10 designated. The solar cell 10 comprises a semiconductor substrate 12th with a front 14th and a back 16 . The semiconductor substrate is exemplary and preferred 12th in the form of an, in particular doped (n-type or p-type) silicon wafer.

To explain the geometric relationships, a Cartesian coordinate system (x, y, z) is shown in the figures. In the example shown, one runs from the rear 16 of the semiconductor substrate 12th spanned plane parallel to the xy plane. In this respect, a surface normal runs on the back 16 parallel to the z-axis.

The 2a to 2d each show the solar cell 10 at different stages of its manufacturing process, the solar cell being 10 or a corresponding preliminary stage of the solar cell 10 is shown in a top view (representations on the left), in a sectional view when viewed along the y-axis (central representations) and in a sectional view when viewed along the x-axis (representations on the right).

As in 1 shown schematically, has the semiconductor substrate 12th at its back 16 a surface structure with a large number of flatly extended elevations 18th and depressions 20th on. The surveys 18th and depressions 20th are arranged in a grid of columns y (running parallel to the y-axis in the figures) and rows x running orthogonally thereto (running parallel to the x-axis in the figures) or form this grid. There are the surveys 18th and depressions 20th arranged in such a way that there are elevations both in the course of each column y and in the course along each row x 18th and depressions 20th alternate periodically (in 2a , left representation highlighted by different shades). In other words, elevations alternate 18th and depressions 20th in the example shown, from a checkerboard pattern, so to speak. All elevations are exemplary and preferred 18th on a common first surface level and all depressions 20th lie on a common second surface level (cf. 2a , center illustration).

The elevations are exemplary and preferred 18th and depressions 20th the same basic form. How out 2a clearly show the surveys 18th and the wells 20th in the example shown, one in the direction of view orthogonally to the rear 16 of the semiconductor substrate 12th considers the basic rectangular shape. An example is an extension of the surveys 18th and depressions 20th in column direction y greater than an extension in row direction x. In the case of embodiments not shown, the elevations 18th and depressions 20th also have other basic shapes, for example square or round or oval.

As from the 1 and 2 B can be seen, has the semiconductor substrate 12th on its rear side n-type doped regions 22nd and p-type doped regions 24 on. The n-type doped areas 22nd and the p-type doped regions 24 each extend longitudinally along the entire length of the columns y of the grid (cf. 2 B , left illustration). In this respect, the doped areas extend 22nd , 24 in the course along each column over several elevations 18th and depressions 20th (see. 2 B , right illustration).

How out 2 B the doped areas can be seen 22nd , 24 arranged in such a way that n-type doped regions 22nd and p-type doped regions 24 alternate periodically from column to column. Consequently, viewed along each line x, all comprise bumps 18th either exclusively n-type doped areas 22nd or exclusively p-type doped regions 24 (see. 2 B , middle illustration). A width of each doped area 22nd , 24 is smaller than a column width.

The n-type doped areas 22nd and the p-type doped regions 24 serve as emitter areas 26th or as a back surface field 28 . Assuming that the semiconductor substrate 12th has an n-type doping and the base of the solar cell 10 forms the p-type doped regions 24 the emitter areas 26th and the n-type doped regions 22nd the back surface field 28 . Here are the n-type doped areas 22nd preferably more n-type doped than the semiconductor substrate 12th itself. However, it is also possible that the semiconductor substrate 12th has an n-type doping. Then the functions of the areas change 22nd and 24 corresponding.

As a rule, the surface is passivated after doping. This so-called passivation layer may have to be opened before the electrodes or the contact fingers are applied.

In order to dissipate charge carriers that occur when solar radiation is absorbed in the semiconductor substrate 12th and at the pn junction between the emitter area 26th and semiconductor substrate 12th (Base) are extracted are the doped areas 22nd , 24 each by means of electrodes 30th , 32 electrically contacted. Each is doped areas 22nd , 24 one electrode each 30th , 32 assigned to which exclusively this area 22nd , 24 contacted.

As from the 1 and 2c can be seen that the electrodes run 30th , 32 in the example shown, elongated along the longitudinal extent of the doped region assigned to them 22nd , 24 (i.e. along columns y of the grid). The electrodes 30th , 32 follow the height profile of the underlying semiconductor substrate along each column y 12th . In this respect, the electrodes 30th , 32 along its length there are periodic height differences (cf. 2c , right illustration). How out 2c , middle illustration shows is a thickness 34 of the electrodes 30th , 32 preferably less in terms of amount than a height offset 36 between the surveys 18th and depressions 20th .

In that, as explained above, there are areas with n-type doping 22nd and regions with p-type doping 24 alternate periodically from column to column, the electrodes lie 30th same polarity along each line viewed at the same height level while the electrodes 32 of the other polarity are at a different height level (cf. 2c , middle illustration). This enables the electrodes 30th , 32 of the same polarity in a simple manner along a line x and so that of the electrodes 30th , 32 discharged charge carriers collected to be able to lead an external circuit

To this end, the solar cell has 10 Busbars 38 which, in the example shown, are orthogonal to a longitudinal extension of the electrodes 30th , 32 extend, i.e. run along a respective line x of the grid (cf. 2d , in 1 not shown). The busbars make contact 38 only those sections of the electrodes 30th , 32 which on the surveys 18th are arranged and thus - as explained above - exclusively electrodes 32 of areas 24 with the same doping. The electrodes of areas 22nd with opposite doping are viewed along the respective row x in the depressions 20th arranged and are thus from the busbars 38 not affected (cf. 2d , middle illustration).

Optionally, the solar cell 10 also an insulating layer 40 include, which is designed to reside in the depressions 20th arranged electrode sections 42 opposite an overlying busbar 38 electrically isolate. For this purpose, the insulating layer 40 by way of example and preferably designed and arranged in such a way that they only have the in the depressions 20th arranged electrode sections 42 at least partially covered (cf. 2d ).

In order to increase a light yield, the semiconductor substrate 12th at its front 14th optionally an anti-reflective layer 44 exhibit.

An embodiment of the method for producing such a rear-side-contacted solar cell is described below 10 with reference to the 2a to 2d explained.

According to the method, first of all the semiconductor substrate 12th provided.

In a subsequent method step, the surface structure explained above is then encompassing the elevations arranged in a checkerboard pattern 18th and depressions 20th on the back side 16 of the semiconductor substrate 12th generated (cf. 2a) . By way of example and preferably, the surface structure is produced by first applying an etch-resistant layer on the rear side 16 of the semiconductor substrate 12th is applied and this is then selectively ablated in a subsequent step, for example by means of laser ablation or another method, in such a way that a large number of areas with ablated etch-resistant layer (later form the depressions 20th ) and areas with an existing etch-resistant layer (later form the elevations 18th ) is generated, areas with removed etch-resistant layer, areas with existing etch-resistant layer alternating in a checkerboard pattern. The surface structure is then produced in an etching step following the laser ablation step. This takes place in that, in the course of the etching step, more material of the semiconductor substrate is removed in the areas with removed etch-resistant material 12th is removed than in the areas with an existing etch-resistant layer. In this respect, local material recesses arise on the rear side in the areas where the etch-resistant layer has been removed 16 of the semiconductor substrate 12th showing the wells 20th form.

In a further process step, the back is then 16 of the semiconductor substrate 12th doped in such a way that the above-described n-type doped regions 22nd and p-type doped regions 24 be generated. For example, doping can take place by means of laser doping.

In a subsequent process step, the electrodes are then 30th , 32 generated, for example by means of screen printing or inkjet printing. Preferably the electrodes are 30th , 32 designed as metal electrodes, each elongated along the doped area assigned to them 22nd , 24 extend (cf. c ).

In a subsequent process step, the busbars are then 38 generated. The busbars can be exemplary and preferred 38 be metal wires (for example tinned copper wires), which are each initially arranged along a row x and then with those sections of the electrodes 30th , 32 electrically connected, which on the bumps 18th are arranged. In this case, an electrical connection is preferably established via a material connection between the electrodes 30th , 32 and the respective busbar 38 produced, for example by means of soldering, welding or bonding.

Optionally, before creating the busbars 38 an insulating layer in an additional process step 40 can be applied from an electrically insulating material. The insulating layer is exemplary and preferred 40 applied in such a way that they only have those electrode sections 42 which in the depressions 20th are arranged, covered and thus these electrode sections 42 opposite busbars above 38 electrically isolated.

Claims (18)

A method for producing a rear-side-contacted solar cell (10) comprising the following steps: a) generating a surface structure on a rear side (16) of a semiconductor substrate (12), in particular a silicon wafer, with a grid of columns (y) and rows running orthogonally thereto (x), a plurality of elevations (18) and depressions (20) being provided in the grid, the elevations (18) and depressions (20) being arranged in such a way that both in the course along each column (y) as well as alternating elevations (18) and depressions (20) along each line (x); b) Doping of the rear side (16) of the semiconductor substrate (12) to produce n-type doped regions (22) and p-type doped regions (24), doping taking place in such a way that the n-type doped regions Regions (22) and the p-type doped regions (24) each extend along columns (y) of the grid and that, viewed at least in areas along each row (x) of the grid, all elevations (18) are either exclusively n-type comprise doped regions (22) or exclusively p-type doped regions (24); c) Generating electrodes (30,32), in particular in the form of metal electrodes, for making electrical contact with the doped regions (22,24), each electrode (30,32) being either an n-type doped region (22) or a p-type doped region (24) is assigned and contacted only this; d) generating busbars (38) for the electrical connection of the electrodes (30,32), the busbars (38) being designed in such a way that each busbar (38) either only has electrodes (30) of n-type doped regions ( 22) or only electrodes (32) of p-type doped regions (24) connects. Procedure according to Claim 1 wherein the doping takes place in such a way that n-type doped regions (22) and p-type doped regions (24) alternate from column to column viewed along each row (x). Method according to one of the Claims 1 or 2 , the surface structure being produced in such a way that all of the elevations (18) lie on a first surface level and all of the depressions (20) lie on a second surface level. Method according to one of the preceding claims, wherein in step a) an etch-resistant layer is first applied, which is selectively removed in a subsequent intermediate step by means of laser ablation, and wherein the surface structure is produced by a subsequent etching step. Method according to one of the preceding claims, wherein the electrodes (30, 32) are produced in such a way that a thickness (34) of the electrodes (30, 32) is less in terms of amount than a height offset (36) between the elevations (18) and depressions ( 20). Method according to one of the preceding claims, wherein before the production of the busbars (38) an insulating layer (40) is applied in such a way that the electrode sections (42) arranged in the depressions (20) are covered at least in sections by the insulating layer (40). Method according to one of the preceding claims, wherein the surface is passivated after the doping. Method according to one of the preceding claims, wherein the doping is carried out by depositing highly doped layers, in particular made of amorphous silicon. Procedure according to Claim 8 , an intrinsic amorphous silicon layer being present under the highly doped layers, which passivates the lightly doped semiconductor substrate surface. Method according to one of the Claims 1 to 7th , the doping being carried out by depositing highly doped layers, in particular made of polycrystalline silicon. Procedure according to Claim 10 , wherein under the highly doped layers a dielectric layer, in particular a tunnel oxide, passivates the lightly doped semiconductor substrate surface. Method according to one of the Claims 1 to 7th , the two differently doped regions being characterized by a combination of the method steps Claim 1 and one or more of the Claims 8 to 11 he follows. Method according to one of the Claims 1 to 7th wherein the doping takes place in such a way that suitable dopants are introduced into the semiconductor substrate (12) or that heterojunction doping or doping with a tunnel oxide and selective contacts is produced. Back-side-contacted solar cell (10), in particular produced by means of a method according to one of the preceding claims, comprising a semiconductor substrate (12), in particular silicon wafer, with a front side (14) and a rear side (16), the semiconductor substrate (12) on its Rear side (16) has a surface structure with a grid of columns (y) and rows (x) running orthogonally thereto, a plurality of elevations (18) and depressions (20) being provided in the grid, the elevations (18) and Depressions (20) are arranged in such a way that elevations (18) and depressions (20) alternate both in the course along each column (y) and in the course along each row (x), the semiconductor substrate (12) on its rear side (16) n-type doped regions (22) and p-type doped Having regions (24), the n-type doped regions (22) and the p-type doped regions (24) each extending along columns y of the grid and the n-type doped regions (22) and the p-type doped regions (24) are arranged in such a way that, viewed at least in regions along each line x of the grid, all elevations (18) either exclusively n-type doped regions (22) or exclusively p-type doped regions ( 24), the doped regions (22,24) being electrically contacted by means of electrodes (30,32), each electrode (30,32) being either an n-type doped region (22) or a p-type doped region Area (24) is assigned and only makes contact with this, and wherein busbars (38) are provided for the electrical connection of the electrodes (30,32), the busbars (38) being designed such that each busbar (38) either only electrodes (30) of n-type doped regions (22) or n ur electrodes (32) of p-type doped regions (24) connects. Solar cell (10) with contact on the back Claim 14 wherein n-type doped regions (22) and p-type doped regions (24), viewed along each row (x), alternate from column to column. Back-side-contacted solar cell (10) according to one of the Claims 14 or 15th wherein all of the elevations (18) are on a first surface level and all of the depressions (20) are on a second surface level. Back-side-contacted solar cell (10) according to one of the Claims 14 to 16 wherein a thickness (34) of the electrodes (30, 32) is smaller in terms of amount than a height offset (36) between the elevations (18) and depressions (20). Back-side-contacted solar cell (10) according to one of the Claims 14 to 17th , further comprising an insulating layer (40) which is designed and arranged in such a way that it electrically insulates electrode sections (42), which are arranged in the depressions (20), from busbars (38) lying above them.

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