DE102019216557A1 - MEASURES TO ENABLE CHANNEL FEEDING IN THE DIGITAL TRANSMISSION - Google Patents

Abstract

Embodiments provide a data transmitter of a communication system, wherein the data transmitter is configured to receive a data bit sequence, wherein the data transmitter is configured to carry out forward error correction coding based on the data bit sequence in order to obtain a sequence of systematic bits and the sequence of systematic bits associated error correction bits, the data bit sequence and the sequence of systematic bits being identical, the data transmitter being configured to transmit a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block being a sequence of reference bits and the Sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the sequence of error correction bits, the d em block of systematic bits is assigned, can be decoded independently of other error correction bits or blocks of error correction bits.

Description

Embodiments of the present invention relate to a data transmitter, a data receiver, a communication system and corresponding methods which enable channel tracking during the transmission of data. Some exemplary embodiments relate to measures to enable channel tracking in the case of digital transmission.

In [5] an extension for the Wireless M-Bus [4] is described, according to which error correction information, which is obtained by turbo coding the user data, is appended to a data message of the Wireless M-Bus, the data message of the wireless M-Bus is preceded by an additional synchronization word.

However, the concept shown in [5] has the disadvantage that in a time-variant communication channel, the previously performed channel estimation for the demodulation of the error correction information is no longer valid, so that there is a loss of performance in the subsequent turbo decoding.

The present invention is therefore based on the object of improving the existing situation.

This problem is solved by the independent patent claims.

Advantageous further developments can be found in the dependent claims.

Embodiments provide a data transmitter of a [e.g. wireless] communication system, wherein the data transmitter is configured to transmit a data bit sequence [e.g. N data bits] [e.g. or from a device connected to the data transmitter [e.g. a sensor]], wherein the data transmitter is configured to perform forward error correction coding based on the data bit sequence to generate a sequence of systematic bits and error correction bits associated with the sequence of systematic bits [e.g. a sequence of error correction bits; e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical, the data transmitter being configured to transmit a signal, the signal comprising a first transmission bit block and a second transmission bit block, the first transmission bit block [e.g. known to a data receiver] comprises a sequence of reference bits and the sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of [e.g. contiguous] systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the error correction bits [e.g. the sequence of error correction bits], which is assigned to the block of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits.

In embodiments, the block of systematic bits comprises a real subset of the systematic bits of the sequence of systematic bits.

In exemplary embodiments, the at least one block of contiguous error correction bits each comprises a real subset of the error correction bits.

In exemplary embodiments, the data transmitter is configured to take over the sequence of systematic bits unchanged and coherent in the order in the first transmission bit block.

In exemplary embodiments, the sequence of reference bits is known to the data transmitter, the data transmitter being configured to transfer the sequence of reference bits unchanged in the sequence and coherently into the first transmission bit block.

In exemplary embodiments, the first transmission bit block is structured in accordance with a communication protocol or communication standard.

In exemplary embodiments, the communication protocol / communication standard can be the wireless M-Bus. For example, the Wireless M-Bus is in the European Standard EN 13757 Are defined. For example, the Wireless M-Bus is in German Standard DIN EN 13757-4 "Communication systems for meters and their remote reading - Part 4: Meter reading via radio (remote reading of meters in the SRD band").

In exemplary embodiments, the first transmission bit block can be received by a data receiver that operates in accordance with the communication protocol or communication standard, independently of the second transmission bit block.

In exemplary embodiments, the second transmission bit block goes beyond the communication protocol or the communication standard.

In embodiments, the second transmit bit block follows the first transmit bit block [e.g. temporal].

In embodiments, the first transmission bit block and the second transmission bit block [e.g. temporally] arranged immediately adjacent to one another.

In exemplary embodiments, the forward error correction coding is turbo coding, LDPC coding or convolutional coding.

In exemplary embodiments, the second transmission bit block has at least one sequence of additional reference bits.

In embodiments, a sequence of additional reference bits [e.g. in addition to the sequence of reference bits of the first transmission bit block] the at least one sequence of additional reference bits is arranged in the second transmission bit block in such a way that the sequence of additional reference bits is arranged adjacent to the first transmission bit block.

For example, the sequence of additional reference bits can be arranged at a start or end of the second transmission bit block, so that the sequence of additional reference bits is arranged adjacent to the first transmission bit block.

In embodiments, the data transmitter is configured to transmit a first forward error correction coding for a first block of the data bit sequence [e.g. first block of contiguous data bits] [e.g. wherein the first block of the data bit sequence comprises part of the data bit sequence] to obtain a first block of systematic bits and at least one block of contiguous error correction bits associated with the first block of systematic bits, the data transmitter being configured to receive a second Forward error correction coding for a second block of the data bit sequence [e.g. second block of contiguous data bits] to obtain a second block of systematic bits and at least one block of contiguous error correction bits associated with the block of systematic bits, the first forward error correction coding and the second forward error correction Coding can be carried out independently of each other.

In exemplary embodiments, the data transmitter is configured to take over the respective blocks of contiguous error correction bits in the order unchanged and contiguous in the second transmission bit block.

In exemplary embodiments, the respective blocks of contiguous error correction bits are not interleaved.

In exemplary embodiments, the respective blocks of related error correction bits are only interleaved in each case.

In embodiments, the second transmit bit block comprises a sequence of additional reference bits [e.g. in addition to the sequence of reference bits of the first transmission bit block], the sequence of additional reference bits being arranged immediately adjacent to a block of contiguous error correction bits which is assigned to a block of the data bit sequence which is arranged at the beginning of the data bit sequence.

In embodiments, the data transmitter is configured to transmit a third forward error correction coding for a third block of the data bit sequence [e.g. third block of contiguous data bits] to obtain a third block of systematic bits and at least one block of contiguous error correction bits associated with the third block of systematic bits, the first forward error correction coding and the second forward error correction Coding and the third forward error correction coding are carried out independently of one another, blocks of contiguous error correction bits that are assigned to immediately adjacent blocks of the data bit sequence being arranged immediately adjacent or with only a block of reference bits in between in the second transmit bit block.

In embodiments, the at least one block of contiguous error correction bits that is assigned to the first block of systematic bits is a first block of contiguous error correction bits, the at least one block of contiguous error correction bits that is assigned to the second block of systematic bits is a second Block of contiguous error correction bits.

For example, in the first forward error correction coding for the first block of the data bit sequence, the first block of systematic bits and a first block of contiguous error correction bits, which is assigned to the first block of systematic bits, arise, with the second forward error correction Coding for the second block of the data bit sequence, the second block of systematic bits and a second block of contiguous error correction bits, which is assigned to the second block of systematic bits, can arise.

In exemplary embodiments, the at least one block of contiguous error correction bits that is assigned to the first block of systematic bits comprises a first block of contiguous error correction bits and a second block of contiguous error correction bits, the at least one block of contiguous error correction bits associated with the second block of systematic bits comprising a third block of contiguous error correction bits and a fourth block of contiguous error correction bits.

For example, during the first forward error correction coding for the first block of the data bit sequence, the first block of systematic bits and a first block of contiguous error correction bits and a second block of contiguous error correction bits that are assigned to the first block of systematic bits can arise, wherein in the second forward error correction coding for the second block of the data bit sequence, the second block of systematic bits and a third block of contiguous error correction bits and a fourth block of contiguous error correction bits, which are assigned to the second block of systematic bits, can arise.

In exemplary embodiments, blocks of contiguous error correction bits, which are assigned to immediately adjacent blocks of systematic bits, are arranged in the second transmission bit block in the second transmission bit block, or with only one block of reference bits in between, are arranged in the second transmission bit block.

In embodiments, a block of reference bits is arranged in the second transmit bit block between blocks of contiguous error correction bits which are assigned to the same block of the data bit sequence [e.g. brought in].

In embodiments, the blocks of contiguous error correction bits assigned to a respective block of the data bit sequence are arranged in the second transmission bit block in such a way that each of these blocks of contiguous error correction bits is directly adjacent to a sequence of additional reference bits or another block of contiguous error correction bits corresponding to one of the respective block of Data bit sequence is assigned to the preceding block of the data bit sequence, is arranged.

In embodiments, the first block of contiguous error correction bits in the second transmission bit block is arranged immediately adjacent to a first sequence of additional reference bits, and the third block of contiguous error correction bits is arranged immediately adjacent to the first block of contiguous error correction bits, the second block of contiguous Error correction bits is arranged in the second transmission bit block immediately adjacent to a second sequence of additional reference bits, and wherein the fourth block of contiguous error correction bits is arranged immediately adjacent to the second block of contiguous error correction bits.

In embodiments, a sequence of additional reference bits is arranged in the second transmission bit block between the first block of contiguous error correction bits and the second block of contiguous error correction bits, the third block of contiguous error correction bits being arranged directly adjacent to the first block of contiguous error correction bits, the fourth Block of contiguous error correction bits is arranged immediately adjacent to the second block of contiguous error correction bits.

In embodiments, a first sequence of additional reference bits between the first block of contiguous error correction bits and the second block of contiguous error correction bits is arranged in the second transmission bit block, wherein in the second transmission bit block a second sequence of additional reference bits between the third block of contiguous error correction bits and the fourth Block of contiguous error correction bits is arranged.

In embodiments, the first block of contiguous error correction bits and the second block of contiguous error correction bits are arranged immediately adjacent to spaced-apart sequences of additional reference bits in the second transmit bit block, the third block of contiguous error correction bits and the fourth block of contiguous error correction bits immediately in the second transmit bit block are arranged adjacent to spaced apart sequences of additional reference bits.

Further exemplary embodiments create a data transmitter of a [eg wireless] communication system which is configured to receive a data bit sequence [eg N data bits] [eg generate or receive from a device connected to the data transmitter [eg a sensor]], the data sender is configured to divide the data bit sequence into at least two blocks, wherein the data transmitter is configured to carry out an independent forward error correction coding based on a respective block of the data bit sequence, in each case a block of systematic bits and in each case at least one block of related error correction bits, which is assigned to the respective block of systematic bits, the respective block of systematic bits being identical to the respective block of the data bit sequence, the data transmitter being configured to transmit a signal, the signal having a first transmission bit block and having a second transmission bit block, the first transmission bit block having a sequence of reference bits and the data bit sequence or a concatenated version of the respective blocks of systematic bits, the concatenated version of the respective blocks of systematic bits and the data bit sequence being identical, the second transmission bit block being the respective Having blocks of error correction bits.

Further embodiments provide a data transmitter of a [e.g. wireless] communication system, wherein the data transmitter is configured to transmit a data bit sequence [e.g. N data bits] [e.g. or from a device connected to the data transmitter [e.g. a sensor]], wherein the data transmitter is configured to perform forward error correction coding based on the data bit sequence to generate a sequence of systematic bits and error correction bits associated with the sequence of systematic bits [e.g. a sequence of error correction bits; e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical, the data transmitter being configured to transmit a signal, the signal comprising a first transmission bit block and a second transmission bit block, the first transmission bit block being a [e.g. a data receiver known] sequence of reference bits and the sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of [e.g. related] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits from the error correction bits [e.g. from the sequence of error correction bits] can be decoded independently of other error correction bits or another group of error correction bits.

In embodiments, the block of systematic bits comprises a real subset of the systematic bits of the sequence of systematic bits.

In exemplary embodiments, the at least one group of error correction bits each comprises a real subset of the error correction bits.

In exemplary embodiments, the data transmitter is configured to carry out the forward error correction coding step by step, so that a respective group of error correction bits of the error correction bits is produced in each step of the forward error correction coding.

In embodiments, a block of systematic bits of the sequence of systematic bits together with a first group of error correction bits, which arises in a first step of the forward error correction coding, can be decoded, independently of another group of error correction bits in one of the subsequent steps the forward error correction coding arises.

In exemplary embodiments, groups of error correction bits following the first group of error correction bits, which arise in the steps of the forward error correction coding following the first step of the forward error correction coding, are only possible together with groups of error correction bits which are used in the preceding steps of the forward error correction. Error correction coding was created and, together with the blocks of systematic bits assigned to the respective groups of error correction bits, can be decoded independently of another group of error correction bits that arise in one of the subsequent steps of the forward error correction coding.

In exemplary embodiments, the forward error correction coding is convolutional coding or LDPC coding.

In exemplary embodiments, a respective group of error correction bits is arranged in the second transmission bit block adjacent to a sequence of additional reference bits or adjacent to a group of error correction bits, which in a step of the forward direction immediately preceding the step in which the respective group of error correction bits arose. Error correction coding came into being.

In embodiments, error correction bits of a respective group of error correction bits are arranged in the second transmission bit block in such a way that each of these error correction bits is arranged immediately adjacent to reference bits or immediately adjacent to another error correction bit of the same group of error correction bits or directly adjacent to an error correction bit of another group of error correction bits in a step of the forward error correction coding immediately preceding the step in which the respective group of error correction bits was created.

Further exemplary embodiments create a data transmitter of a [eg wireless] communication system, wherein the data transmitter is configured to receive a data bit sequence [eg N data bits] [eg to generate or from one with the data transmitter connected device [e.g. sensor]], wherein the data transmitter is configured to perform forward error correction coding based on the data bit sequence in order to obtain a sequence of systematic bits and the sequence of systematic bits associated with error correction bits [e.g. a sequence of error correction bits; eg M error correction bits], the data bit sequence and the sequence of systematic bits being identical, the data transmitter being configured to transmit a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block being a first sequence of Reference bits, the sequence of systematic bits and a second sequence of reference bits, wherein the sequence of systematic bits is interrupted by the second sequence of reference bits, so that a first part of the sequence of systematic bits [eg temporally] before the second sequence of reference bits is arranged and a second part of the sequence of systematic bits [eg temporally] is arranged after the second sequence of reference bits, the second transmission bit block having the error correction bits, a block of [eg contiguous] systematic bits of the sequence of systematic bits together with at least one block of related error corr ekturbits of the error correction bits [eg the sequence of error correction bits], which is assigned to the block of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits.

In exemplary embodiments, the data transmitter is configured to take over the respective parts of the sequence of systematic bits in the order unchanged and coherently in the first transmission bit block.

Further embodiments provide a data receiver of a [e.g. wireless] communication system, wherein the data receiver is configured to receive a signal comprising a first transmission bit block and a second transmission bit block, the first transmission bit block comprising a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to a data bit sequence to be transmitted with the signal, the second transmission bit block having error correction bits assigned to the sequence of systematic bits, the data receiver being configured to carry out a channel estimation based on the received sequence of reference bits, the data receiver being configured to generate a sequence, which received a block of [eg contiguous] systematic bits of the received sequence of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits that are assigned to the received block of systematic bits, independently of other received error correction bits or received blocks of error correction bits to decode to a block of the data bit sequence, the data receiver being configured to carry out forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits assigned to the reencoded block of systematic bits, wherein the data receiver is configured to track the channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.

Further exemplary embodiments provide a data receiver of a [wireless] communication system, the data receiver being configured to receive, in a first mode, a first signal having a first transmission bit block, the first transmission bit block having a sequence of reference bits and a data bit sequence, wherein the data receiver is configured to receive, in a second mode, a second signal comprising a first transmit bit block and a second transmit bit block, the first transmit bit block comprising a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits is identical to a data bit sequence to be transmitted with the second signal, the second transmission bit block having error correction bits assigned to the sequence of systematic bits, the data receiver being configured to carry out a channel estimation based on the received sequence of reference bits, wherein the data reception r is configured to generate a sequence comprising a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits that are assigned to the received block of systematic bits, independently of other received error correction bits or received blocks of error correction bits to decode to a block of the data bit sequence, the data receiver being configured to carry out forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits assigned to the reencoded block of systematic bits, wherein the data receiver is configured to track a channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.

In embodiments, the received block of systematic bits comprises a real one Subset of the systematic bits of the received sequence of systematic bits.

In exemplary embodiments, the at least one received block of contiguous error correction bits each comprises a real subset of the received error correction bits.

In embodiments, the first transmission bit block is according to a communication protocol or communication standard [e.g. Wireless-M-Bus].

In exemplary embodiments, the second transmission bit block goes beyond the communication protocol or the communication standard.

In embodiments, the second transmit bit block follows the first transmit bit block [e.g. temporal].

In embodiments, the first transmit bit block and the second transmit bit block [e.g. temporally] arranged immediately adjacent to one another.

In exemplary embodiments, the forward error correction coding is turbo coding, LDPC coding or convolutional coding.

In embodiments, the sequence of systematic bits comprises a first block of systematic bits and a second block of systematic bits, the error correction bits at least one block of contiguous error correction bits assigned to the first block of systematic bits and at least one block of related error correction bits assigned to the second block of systematic bits contiguous error correction bits.

• - Decodieren einer Sequenz, die den zumindest einen der Blöcke von Fehlerkorrekturbits, der unmittelbar benachbart zu dem Block von Referenzbits angeordnet ist, und einen der Blöcke der Folge von systematischen Bits, der dem zumindest einen der Blöcke von Fehlerkorrekturbits, der unmittelbar benachbart zu dem Block von Referenzbits angeordnet ist, zugeordnet ist, umfasst, um einen jeweiligen Block der Datenbitfolge zu erhalten,
• - Durchführen einer Vorwärts-Fehler-Codierung des jeweiligen Blocks der Datenbitfolge, um einen reencodierten Block von systematischen Bits und zumindest einen dem reencodierten Block von systematischen Bits zugeordneten reencodierten Block von Fehlerkorrekturbits zu erhalten,
• - Verwenden des reencodierten Blocks von systematischen Bits und des zumindest einen reencodierten Blocks von Fehlerkorrekturbits als Referenzbits für die Kanalschätzung.

In embodiments, the second transmission bit block comprises at least one sequence of additional reference bits, wherein the data receiver is configured to update or restart the channel estimation based on the sequence of additional reference bits, wherein the data receiver is configured to perform the channel estimation based on at least one of the blocks of error correction bits, which is arranged immediately adjacent to the sequence of additional reference bits, to be tracked

• Decoding of a sequence which includes the at least one of the blocks of error correction bits which is arranged immediately adjacent to the block of reference bits, and one of the blocks of the sequence of systematic bits which corresponds to the at least one of the blocks of error correction bits which is immediately adjacent to the block is arranged by reference bits, is assigned, comprises in order to receive a respective block of the data bit sequence,
• - Carrying out forward error coding of the respective block of the data bit sequence in order to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits assigned to the reencoded block of systematic bits,
• Using the reencoded block of systematic bits and the at least one reencoded block of error correction bits as reference bits for the channel estimation.

Further embodiments provide a data receiver of a [e.g. wireless] communication system, wherein the data receiver is configured to receive a signal comprising a first transmission bit block and a second transmission bit block, the first transmission bit block comprising a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to a data bit sequence to be transmitted with the signal, the second transmission bit block having error correction bits assigned to the sequence of systematic bits, the data receiver being configured to carry out a channel estimation based on the received sequence of reference bits, the data receiver being configured to generate a sequence, which received a block of [eg contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits, which is assigned to the received block of systematic bits, independently of other received error correction bits or received groups of error correction bits to decode to a block of the data bit sequence wherein the data receiver is configured to carry out a forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and a reencoded group of error correction bits assigned to the reencoded block of systematic bits, the data receiver configured to track the channel estimate based on the reencoded group of systematic bits and the reencoded group of error correction bits.

Further exemplary embodiments create a communication system with a data transmitter according to one of the exemplary embodiments described herein and a data receiver according to one of the exemplary embodiments described herein.

Further exemplary embodiments create a communication system with a first A data transmitter configured to receive a data bit sequence and to transmit a first signal having only a first transmission bit block, the first transmission bit block comprising a sequence of reference bits and the data bit sequence received from the first data transmitter; a second data transmitter according to one of the exemplary embodiments described herein, which is configured to transmit a second signal; and a data receiver according to one of the exemplary embodiments described herein.

In exemplary embodiments, the first data transmitter does not transmit a second transmission bit block with error correction bits for the data bit sequence received.

In exemplary embodiments, the respective first transmission bit block is structured in accordance with a communication protocol or communication standard, the second transmission bit block going beyond the communication protocol or the communication standard.

Further exemplary embodiments provide a communication system with a first data transmitter which is configured to receive a data bit sequence and to transmit a first signal which has only a first transmission bit block, the first transmission bit block comprising reference data and the data bit sequence received from the first data transmitter; a second data transmitter according to one of the exemplary embodiments described herein, which is configured to transmit a second signal, and a data receiver which is configured to receive the first signal and the second signal, the data receiver being configured to only transmit the respective to process the first transmission bit block in order to obtain the respective data bit sequence.

In embodiments, the second transmission bit block is not taken into account by the data receiver.

In exemplary embodiments, the data receiver operates in accordance with a communication protocol or communication standard, the respective first transmission bit block being structured in accordance with the communication protocol or communication standard, the second transmission bit block going beyond the communication protocol or the communication standard.

In exemplary embodiments, the data receiver is a first data receiver, the communication system having a second data receiver in accordance with one of the exemplary embodiments described herein.

Further exemplary embodiments provide a method for sending a signal. The method includes a step of obtaining a data bit sequence. The method further comprises a step of performing, based on the data bit sequence, forward error correction coding to generate a sequence of systematic bits and error correction bits associated with the sequence of systematic bits [e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical. The method further comprises a step of transmitting a signal, the signal comprising a first block of transmit bits and a second block of transmit bits, the first block of transmit bits [e.g. known to a data receiver] comprises a sequence of reference bits and the sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of [e.g. contiguous] systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the error correction bits, which is assigned to the block of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits.

Further exemplary embodiments provide a method for sending a signal. The method includes a step of obtaining a data bit sequence. The method further comprises a step of performing, based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and the sequence of systematic bits assigned error correction bits [eg M error correction bits], the data bit sequence and the sequence of systematic bits are identical. The method further comprises a step the transmission of a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block [e.g. known to a data receiver] having a sequence of reference bits and the sequence of systematic bits, and the second transmission bit block having the error correction bits, a Block of [eg contiguous] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits can be decoded from the error correction bits, independently of other error correction bits or other groups of error correction bits.

Further exemplary embodiments provide a method for sending a signal. The method includes a step of obtaining a data bit sequence. The method further comprises a step of performing, based on the data bit sequence, forward error correction coding to generate a sequence of systematic bits and error correction bits associated with the sequence of systematic bits [e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical. The method further comprises a step of transmitting a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits is interrupted by the second sequence of reference bits, so that a first part of the sequence of systematic bits [e.g. temporal] is placed before the second sequence of reference bits and a second part of the sequence of systematic bits [e.g. temporally] after that of the second sequence of reference bits, the second transmission bit block comprising the error correction bits, a block of [e.g. related] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits can be decoded from the error correction bits, independently of other error correction bits or other groups of error correction bits.

Further exemplary embodiments provide a method for receiving a signal. The method comprises a step of receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to one to be transmitted with the signal Is a data bit sequence, the second transmission bit block having error correction bits assigned to the sequence of systematic bits. The method further comprises a step of performing a channel estimation based on the received sequence of reference bits. The method further comprises a step of decoding a sequence comprising a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits, which is assigned to the received block of systematic bits, independently of other received error correction bits or received blocks of error correction bits to decode to a block of the data bit sequence. The method further comprises a step of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and at least one reencoded block of systematic bits and error correction bits assigned to the reencoded block of systematic bits, Updating the channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.

Further exemplary embodiments provide a method for receiving a signal. The method comprises a step of receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to one to be transmitted with the signal Is a data bit sequence, the second transmission bit block having error correction bits assigned to the sequence of systematic bits. The method further comprises a step of performing a channel estimation based on the received sequence of reference bits. The method further comprises a step of decoding a sequence which contains a received block of [eg contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits, which is assigned to the received block of systematic bits, comprises decoding independently of other received error correction bits or received groups of error correction bits in order to obtain a block of the data bit sequence. The method further comprises a step of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits. The method further comprises a step of updating the channel estimation based on the reencoded block of systematic bits and the reencoded group of error correction bits.

Further exemplary embodiments provide a method for receiving a signal. The method comprises a step of receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits being through the second sequence of reference bits is interrupted, so that a first part of the sequence of systematic bits [e.g. temporal] is placed before the second sequence of reference bits and a second part of the sequence of systematic bits [e.g. temporally] is arranged after the second sequence of reference bits, the second transmission bit block having the error correction bits. The method further comprises a step of performing a channel estimation based on the received first sequence of reference bits and the received second sequence of reference bits. The method further comprises a step of decoding a sequence comprising a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits, which is assigned to the received block of systematic bits, independently of other received error correction bits or received groups of error correction bits to decode to a block of the data bit sequence to obtain. The method further comprises a step of performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits. The method further comprises a step of updating the channel estimation based on the reencoded block of systematic bits and the reencoded group of error correction bits.

• 1 ein schematisches Blockschaltbild eines Systems mit einem oder mehreren Datensendern und einem Datenempfänger;
• 2 eine schematische Ansicht einer Anordnung einer Folge von Referenzbits und einer Datenbitfolge mit den Datenbits wie sie als zu übertragene Sendebitfolge bei einem einfachen Übertragungssystem ohne Vorwärts-Fehlerkorrektur zum Einsatz kommt;
• 3 eine schematische Ansicht einer Erzeugung eines Sendesignals mit der zu übertragenden Sendebitfolge ohne Vorwärts-Fehlerkorrektur (Codierung) aus 2;
• 4 eine schematische Ansicht einer Erzeugung eines Sendesignals mit einer zu übertragenden Sendebitfolge mit Vorwärts-Fehlerkorrektur und Interleaving;
• 5 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit auf einer Vorwärts-Fehlerkorrektur (Codierung) basierenden Fehlerkorrekturbits, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 6 eine schematische Ansicht einer inneren Struktur der Turbo-Codierung;
• 7 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit auf einer Turbo-Codierung basierenden Fehlerkorrekturbits, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 8 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit auf einer Vorwärts-Fehlerkorrektur (Codierung) basierenden Fehlerkorrekturbits und zusätzlichen Folgen von Referenzbits, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 9 eine schematische Darstellung der für die Kanalschätzung zugeordneten Folgen von Referenzbits für die zu übertragende Sendebitfolge aus 8;
• 10 eine schematische Ansicht einer Erzeugung einer Folge von codierten Bits mit Blöcken von codierten Bits (z.B. codierte Teilsequenzen), die einzeln codiert sind, sowie eine auf den Blöcken von codierten Bits basierende iterative Kanalnachführung;
• 11 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit auf Vorwärts-Fehlerkorrektur (Codierung) basierenden Fehlerkorrekturbits, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 12 eine schematische Ansicht einer zu übertragenden Sendebitfolge mit dem ersten Sendebitblock aus 11 und einem zweiten Sendebitblock, der gegenüber 11 eine andere Anordnung der Blöcke von Fehlerkorrekturbits und der eine Folge 320 von zusätzlichen Referenzbits aufweist;
• 13 eine schematische Ansicht einer zu übertragenden Sendebitfolge mit dem ersten Sendebitblock aus 11 und einem zweiten Sendebitblock, der dem ersten Sendebitblock vorangestellt ist;
• 14 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit auf Vorwärts-Fehlerkorrektur (Codierung) basierenden Fehlerkorrekturbits, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 15 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge, wobei in 15 nur der Schritt der Einfügung einer Folge von zusätzlichen Referenzbits in der zweiten Sendebitblock der Sendebitfolge gezeigt ist, der sich von dem in 14 gezeigten Schritt der Einfügung einer Folge von zusätzlichen Referenzbits unterscheidet;
• 16 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge, wobei in 16 nur der Schritt der Einfügung von mehreren Folgen von zusätzlichen Referenzbits in der zweiten Sendebitblock der Sendebitfolge gezeigt ist, der sich von dem in 14 gezeigten Schritt der Einfügung einer Folge von zusätzlichen Referenzbits unterscheidet;
• 17 eine schematische Ansicht einer resultierenden Sendebitfolge nach dem Einbringen von drei Folgen von zusätzlichen Referenzbits, wobei verglichen mit 16 ein Abstand zwischen Blöcken von Fehlerkorrekturbits, die dem gleichen Block der Sendebitfolge zugeordnet sind, vergrößert ist;
• 18 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit auf einer Vorwärts-Fehlerkorrektur (Codierung) basierenden Fehlerkorrekturbits, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 19 eine schematische Ansicht einer iterativen Vorwärts-Fehlerkorrekturcodierung einer Datenbitfolge;
• 20 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit zusätzlichen Fehlerkorrekturbits, die auf einer iterativen Vorwärts-Fehlerkorrektur (Codierung) basieren, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 21 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit zusätzlichen Fehlerkorrekturbits, die auf einer iterativen Vorwärts-Fehlerkorrektur (Codierung) basieren, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 22 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit zusätzlichen Fehlerkorrekturbits, die auf einer iterativen Vorwärts-Fehlerkorrektur (Codierung) basieren, wobei die Sendebitfolge rückwärtskompatibel zu einer uncodierten Sendebitfolge ist;
• 23 eine schematische Ansicht einer Erzeugung einer zu übertragenden Sendebitfolge mit Fehlerkorrekturbits, die auf einer Vorwärts-Fehlerkorrektur (Codierung) basieren;
• 24 ein Flussdiagramm eines Verfahrens zum Senden eines Signals, gemäß einem ersten Ausführungsbeispiel;
• 25 ein Flussdiagramm eines Verfahrens zum Senden eines Signals, gemäß einem zweiten Ausführungsbeispiel;
• 26 ein Flussdiagramm eines Verfahrens zum Senden eines Signals, gemäß einem dritten Ausführungsbeispiel;
• 27 ein Flussdiagramm eines Verfahrens zum Empfangen eines Signals, gemäß einem ersten Ausführungsbeispiel;
• 28 ein Flussdiagramm eines Verfahrens zum Empfangen eines Signals, gemäß einem zweiten Ausführungsbeispiel; und
• 29 ein Flussdiagramm eines Verfahrens zum Empfangen eines Signals, gemäß einem dritten Ausführungsbeispiel.

Exemplary embodiments of the present invention are described in more detail with reference to the accompanying figures. Show it:

• 1 a schematic block diagram of a system with one or more data transmitters and a data receiver;
• 2 a schematic view of an arrangement of a sequence of reference bits and a data bit sequence with the data bits as it is used as a transmission bit sequence to be transmitted in a simple transmission system without forward error correction;
• 3 a schematic view of a generation of a transmission signal with the transmission bit sequence to be transmitted without forward error correction (coding) 2 ;
• 4th a schematic view of a generation of a transmission signal with a transmission bit sequence to be transmitted with forward error correction and interleaving;
• 5 a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on a forward error correction (coding), the transmission bit sequence being backward compatible with an uncoded transmission bit sequence;
• 6th a schematic view of an internal structure of turbo coding;
• 7th a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on turbo coding, the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence;
• 8th a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on a forward error correction (coding) and additional sequences of reference bits, the transmission bit sequence being backward compatible with an uncoded transmission bit sequence;
• 9 a schematic representation of the sequences of reference bits assigned for the channel estimation for the transmission bit sequence to be transmitted 8th ;
• 10 a schematic view of a generation of a sequence of coded bits with blocks of coded bits (for example coded partial sequences) which are individually coded, as well as an iterative channel tracking based on the blocks of coded bits;
• 11 a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backward compatible with an uncoded transmission bit sequence;
• 12th a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block 11 and a second transmission bit block opposite 11 another arrangement of the blocks of error correction bits and the one sequence 320 of additional reference bits;
• 13th a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block 11 and a second transmit bit block preceding the first transmit bit block;
• 14th a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backward compatible with an uncoded transmission bit sequence;
• 15th a schematic view of a generation of a transmission bit sequence to be transmitted, wherein in 15th only the step of inserting a sequence of additional reference bits in the second transmission bit block of the transmission bit sequence is shown, which differs from the one in 14th shown step of inserting a sequence of additional reference bits;
• 16 a schematic view of a generation of a transmission bit sequence to be transmitted, wherein in 16 only the step of inserting several sequences of additional reference bits in the second transmission bit block of the transmission bit sequence is shown, which differs from that in 14th shown step of inserting a sequence of additional reference bits;
• 17th a schematic view of a resulting transmission bit sequence after the introduction of three sequences of additional reference bits, being compared to 16 a distance between blocks of error correction bits assigned to the same block of the transmission bit sequence is increased;
• 18th a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on a forward error correction (coding), the transmission bit sequence being backward compatible with an uncoded transmission bit sequence;
• 19th a schematic view of an iterative forward error correction coding of a data bit sequence;
• 20th a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence;
• 21 a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence;
• 22nd a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence;
• 23 a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits which are based on a forward error correction (coding);
• 24 a flowchart of a method for sending a signal, according to a first embodiment;
• 25th a flowchart of a method for sending a signal, according to a second embodiment;
• 26th a flowchart of a method for sending a signal, according to a third embodiment;
• 27 a flowchart of a method for receiving a signal, according to a first embodiment;
• 28 a flowchart of a method for receiving a signal, according to a second embodiment; and
• 29 a flowchart of a method for receiving a signal, according to a third embodiment.

In the following description of the exemplary embodiments of the present invention, elements that are the same or have the same effect are provided with the same reference symbols in the figures, so that their descriptions can be interchanged with one another.

1 shows a schematic block diagram of a communication system with one or more data transmitters 100_1-100_n , n ≥ 1, and a data receiver 110 .

In the in 1 The communication system shown can be a data transmitter, for example the data transmitter 100_1 , be designed to receive a signal 120 (eg a first signal) with data to be transmitted (eg a data packet) to the data receiver 110 to send. The data recipient 110 can be designed to the signal 120 to receive to get the data.

Another data sender, e.g. the data sender 100_2 , can be designed to receive a further signal 122 (eg second signal) with data to be transmitted (eg a data packet) to the data receiver 110 to send. The data recipient 110 can be designed to the further signal 122 to receive to get the data.

As in 1 is shown by way of example, a data transmitter, such as the data transmitter 100_1 , a transmitter (or transmitter module, or transmitter) 102 have, which is designed to the signal 120 to send. The sending facility 102 can with an antenna 104 (or an antenna array) of the data transmitter 100_1 be connected. Optionally, the data sender 100_1 also a receiving device (or receiving module, or receiver) 106 which is designed to receive a signal. The receiving device 106 can with the antenna 104 or a further (separate) antenna (or a (separate) antenna array) of the data transmitter 100_1 be connected. The data sender 100_1 can also have a combined transceiver.

The data recipient 110 can be a receiving device (or receiving module, or receiver) 116 have, which is designed to the signal 120 to recieve. The receiving device 116 can with an antenna 114 (or an antenna array) of the data receiver 110 be connected. The data recipient can optionally 110 also a Transmitting device (or transmitting module, or transmitter) 112 which is designed to send a signal. The sending facility 112 can with the antenna 114 or a further (separate) antenna (or a (separate) antenna array) of the data receiver 110 be connected. The data recipient 110 can also have a combined transceiver.

For example, the data sender 100_1 be a participant in the communication system, such as an end point or a sensor node (e.g. heating meter), while the data receiver 110 can be a base station of the communication system. A communication system typically comprises at least one data receiver 110 (e.g. base station) and a large number of data transmitters 100_1-100_n (e.g. participants). Of course it is also possible that the data sender 100_1 is a base station of the communication system, while the data receiver 110 is a participant in the communication system. It is also possible that both the data sender 100_1 as well as the data recipient 110 Participants in the communication system are. It is also possible that both the data sender 100_1 as well as the data recipient 110 Base stations of the communication system are.

Uncoded and encoded transmission of data bits in a data packet

Predominantly in older transmission systems, for example kept simple for reasons of complexity and / or cost, a data packet with useful data to be transmitted (for example data bits) is often transmitted without error protection, ie without coding introducing redundancy. In the following, d ₁ , d ₂ ,... D _N denotes a sequence of N data bits to be transmitted (or a data bit sequence). This sequence can, among other things, already contain check bits of a cyclic redundancy check (also CRC bits), which are not included in the forward error correction coding in the context of this description.

Since the exact start of a transmission, i.e. the start of the transmission of a data packet, is often unknown in the receiver (e.g. data receiver), the data bits are preceded by a reference sequence (also preamble, training sequence or synchronization sequence) which the receiver knows in advance, as described in 2 is shown.

Shows in detail 2 a schematic view of an arrangement of a sequence 201 of reference _{bits r 1} , r ₂ , ... r _L and a data bit sequence 202 with the data bits d ₁ , d ₂ , ... d _N , as used as a transmission bit sequence to be transmitted (eg data packet) in a simple transmission system without forward error correction (coding).

If the receiver detects the sent reference sequence 201 (e.g. sequence of reference bits), it interprets the subsequent received signal section as that of the data bits (e.g. the data bit sequence 202 ) associated signal and demodulates it in order to recover the transmitted data bits. The reference sequence 201 serves on the one hand to detect (locate) a transmission signal; in the case of coherent demodulation, the reference sequence allows 201 in addition, a channel estimation (which is the prerequisite for coherent demodulation).

3 shows a schematic view of a generation of a transmission signal with the transmission bit sequence to be transmitted without forward error correction (coding) 2 . In a first step 210 the sequence is mapped (e.g. bit-to-symbol assignment) 201 from reference bits to reference symbols 212 and the data bit sequence 201 on data symbols 214 . In a second step 216 the reference symbols are modulated 212 and data symbols 214 to get a reference signal 218 and a data signal 220 to obtain. It should be noted that a reference signal 218 can also be generated “directly” without being able to be derived from a sequence of explicitly specified reference bits.

In the case of signal transmission via radio channels, at least part of the received signal is often disturbed by noise and / or interference, so that not all data symbols can be correctly demodulated and thus at least some of the bits sent are incorrect. Without additional error protection coding, a single bit error results in the entire data packet having to be discarded as defective.

In modern digital transmission systems, the user data to be transmitted (e.g. data bit sequence 202 ) is subjected to a coding in the form of a forward error correction (FEC) prior to transmission. Although this brings redundancy in the form of additional (parity) bits to be transmitted, the overall reliability of the transmission is considerably increased. Since many codings are prone to burst errors, the coded bits are usually subjected to interleaving. After interleaving, originally adjacent coded bits are usually further apart in the sequence than originally. 4th shows the corresponding process steps of such an efficient transmission system.

Shows in detail 4th a schematic view of a generation of a transmission signal with a transmission bit sequence to be transmitted with forward error correction and interleaving. In a first step 208 takes place based on a data bit sequence 202 (e.g. sequence of data bits), a forward error coding to a sequence 203 of coded bits. In a second step 209 the coded bits of the sequence are interleaved 203 of coded bits to make a sequence 204 of interleaved, coded bits. In a third step 210 a mapping (eg bit-to-symbol assignment) of a sequence takes place 201 from reference bits to reference symbols 212 and the consequence 204 from interleaved, coded bits to data symbols 214 . In a fourth step 216 the reference symbols are modulated 212 and data symbols 214 to get a reference signal 218 and a data signal 220 to obtain.

In particular, the groups of turbo codes [2] and LDPC codes, with the actually achievable channel utilization, are close to the theoretically possible channel capacity, the so-called "Shannon limit" and are therefore of enormous practical importance for highly efficient transmission systems. In addition to turbo and LDPC codes, convolutional codes are established as forward error correction, but with less efficiency.

Further development of existing standards with backwards compatibility

Many older standards, such as the Wireless M-Bus [1] intended for radio transmission, transmit the data bits without forward error correction, e.g. following a reference sequence known in the receiver (e.g. data receiver). Without this being relevant in the exemplary embodiments, a so-called header can also be inserted between the reference and data symbols, which header can contain control information, such as the length of the following data bit sequence. By using differential detection [3], the data bits can be recovered in the receiver in the form of incoherent demodulation, which often makes explicit channel estimation or channel tracking avoidable. In this way, receivers with comparatively low complexity and thus low costs can be implemented.

In the course of further technical development, the aim is to significantly increase the efficiency of data transmission systems with the help of modern processes. As indicated above, this can advantageously be done by coding the data bits to be transmitted 202 (e.g. data bit sequence) based on a forward error correction. While such procedures are mostly used in the development of new standards (e.g. communication standards), backward compatibility may have to be taken into account when developing existing standards, as there is often a large number of old devices in circulation that are not impaired in their function should.

Specifically, reference is made in the following to an existing transmission system (e.g. communication system) which uses the data bits as in 3 transmits uncoded. Whether or not a header area (e.g. consisting of header bits) with control information is inserted between reference and data bits is irrelevant for the following explanations, so that this is not taken into account for the sake of clarity. Any check bits (CRC bits) that may be present are added to the data bits to be transmitted and are also not shown separately below.

It is the characteristic of a forward error correction that this introduces redundancy, ie that the number of coded bits (encoder output sequence) is greater than the number of uncoded data bits (encoder input sequence). This redundancy creates a certain error tolerance in the event of incorrect demodulation of the coded bits. Is an original system in accordance with 3 without coding, this system can be decisively improved in its efficiency by coding by transmitting additional (redundant) bits. In order to be backwards compatible with systems without redundancy bits, the data bit sequence should be transmitted unchanged even when using a coding with possibly subsequent interleaving.

5 shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence. As in 5 can be seen in a first step 302 , based on the data bit sequence 202 with N data bits, a forward error correction (coding) can be carried out to one of the data bit sequence 202 of M error correction bits (e.g. redundancy bits). In a second step 308 can result in nesting 306 of M error correction bits are made to a sequence 310 of M interleaved error correction bits.

As in 5 can be seen form a sequence 201 of reference bits, the data bit sequence 202 and the consequence 310 of M interleaved error correction bits, the transmission bit sequence to be transmitted, with a first transmission bit block 200 the transmission bit sequence that the sequence 201 of reference bits and the data bit sequence 202 includes, is backwards compatible with an "existing" communication system (or communication protocol), while a second transmission bit block 300 the transmission bit sequence that the sequence 310 of M interleaved error correction bits, the "Existing" communication system expanded by a forward error correction.

In other words, 5 shows schematically a system with coding, which is backwards compatible with an "old" system without coding. First the N data bits (e.g. data bit sequence 202 ) subjected to forward error correction coding. The prerequisite for this is that the original N data bits (e.g. data bit sequence 202 ) are generated in the same order as at the encoder input. In addition, M redundancy bits are used in the coding 306 (also called parity bits or error correction bits). The subsequent interleaving is to be designed in such a way that only the redundancy bits are interleaved, the data bits (e.g. data bit sequence 202 ), however, can be left unchanged in their order. It can be seen that according to this procedure 5 the first N bits after the reference bits exactly match those of the uncoded method 3 correspond.

A receiver using the old (uncoded) method processes the first N data bits after the reference sequence has been detected 202 and ignores the following interleaved redundancy bits 310 . A receiver according to the new method processes after the detection of the reference sequence 201 the entire sequence consisting of N data bits and M redundancy bits. Decoding this sequence of length M + N results in a significantly higher error tolerance in the event of faulty demodulation (bit errors) of part of the receive sequence. The concept of backward compatibility is to be understood as meaning that a new, longer sequence is transmitted (sent), the first part of which (corresponding to the reference sequence and the first N data bits) is identical to that of the original system without coding.

• - Codierung: Die ersten N Bits der codierten Sequenz entsprechen genau den Eingangsbits des Encoders (d.h. den N Datenbits 202).
• - Interleaving: Der Interleaver belässt die ersten N Bits der codierten Sequenz, welche den N Datenbits 202 entsprechen, unverändert an ihren Positionen und verschachtelt lediglich die folgenden Redundanzbits 306.

As mentioned above, the following requirements exist to ensure backward compatibility:

• - Coding: The first N bits of the coded sequence correspond exactly to the input bits of the encoder (ie the N data bits 202 ).
• - Interleaving: The interleaver leaves the first N bits of the coded sequence, which are the N data bits 202 correspond, unchanged in their positions and only interleaves the following redundancy bits 306 .

Any coding in which the coded bit sequence contains the data bit sequence as a subset can therefore be considered as forward error correction. This is particularly the case with turbo codes and LDPC codes.

Some of the exemplary embodiments described below relate to a turbo coding representative of a coding, at the output of which systematic bits and parity bits are generated. It should be noted, however, that the present invention is not limited to such exemplary embodiments. Rather, all codes that contain systematic bits as part of the coded bit sequence come into consideration, such as, inter alia. the important and practice-relevant group of LDPC codes.

6th Fig. 10 shows a schematic view of an internal structure of the turbo coding 240 . From the data bits 202 which at the entrance of the turbo coding 240 are present, three bit sequences are generated: The so-called "systematic bits" 304 , which are identical to the data bits 202 are. Also a first sequence 306_1 of parity bits, which by means of a recursive convolutional code based on a first generator polynomial 242 from the data bits 202 be generated. A third path creates a second sequence 306_2 of parity bits. For this purpose, the data bits on the input side are interleaved internally in a turbo code 246 subjected, whereby their order is scrambled. The data bits scrambled in this way are subjected to a second recursive convolutional coding based on a second generator polynomial 244 subjected.

The special feature of turbo coding (in contrast to the usual convolutional coding) is that the data bits on the input side 202 represent part of the coded bit sequence on the output side (where they represent as systematic bits 304 are designated). This feature makes the use of turbo coding suitable for the in 7th illustrated procedure.

Shows in detail 7th a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on turbo coding, the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence. In a first step 302 can be based on the data bit sequence 202 with N data bits, a turbo coding can be performed to form a sequence 304 of systematic bits and two of the sequence 304 sequences assigned by systematic bits 306_1 and 306_2 of error correction bits (e.g. parity bits). The consequence 304 of systematic bits is here identical to the data bit sequence 202 . In a second step 308 can be a nesting of the two episodes 306_1 and 306_2 of error correction bits are carried out to produce a sequence 310 from nested error correction bits (e.g. parity bits).

As in 7th can be seen form a sequence 201 of reference bits, the result 304 of systematic bits and the consequence 310 of interleaved error correction bits, the transmission bit sequence to be transmitted, with a first transmission bit block 200 the transmission bit sequence that the sequence 201 of reference bits and the sequence 304 comprised of systematic bits, is backwards compatible with an “existing” communication system (or communication protocol), while a second transmission bit block 300 the transmission bit sequence that the sequence 310 of interleaved error correction bits, the "existing" communication system is expanded to include forward error correction.

In other words, 7th shows an extension of an uncoded system to an efficient system with turbo coding, with the N systematic bits 304 which correspond to the data bits 202 correspond to the reference sequence 201 to be ordered. Only then are the interleaved parity bits 310 of the turbo encoder added. This means that on the one hand "old" receivers can continue to be used, which only use the first N data bits 304 after the reference sequence and consider the following bits 310 to ignore. However, new, more powerful receivers (e.g. data receivers) process the entire sequence shown. The turbo decoding used ensures a significantly increased transmission security even with heavily disturbed channels.

Receivers (e.g. data receivers) with low complexity often demodulate the input signal incoherently. Differential detection can be used here, depending on the modulation method used. This does not require any explicit channel estimation or channel tracking and is very robust against changes in the transmission channel, such as those that occur, for example, due to a frequency offset between the transmitter (e.g. data transmitter) and receiver (e.g. data receiver) or with time-variant fading channels.

Forward error correction coding (e.g. turbo coding or LDPC coding) enables the data to be transmitted much more efficiently, but only develops its benefits with coherent demodulation of the received signal. This requires that channel estimation be performed. If the coherence time of a transmission channel is shorter than the duration of the transmitted transmission signal, i.e. if the channel changes significantly from the receiver's point of view during the transmission duration of the received signal, a one-time channel estimation (e.g. based on the preceding reference symbols) is no longer sufficient. Rather, a channel tracking, i.e. an update of the channel estimate at sufficiently short time intervals, is then required. The maximum permissible update period depends directly on the coherence time of the transmission channel, i.e. the time in which the channel can be viewed as approximately unchanged.

• (1) Eine Bewegung von Sender, Empfänger oder von sonstigen Objekten, an denen die Funkwellen gestreut werden. Der Kanal ist aus physikalischer Sicht zeitvariant.
• (2) Ein Frequenzversatz zwischen Sender und Empfänger, auch Frequenzoffset genannt. Der physikalische Kanal selbst muss hierbei nicht notwendigerweise zeitvariant sein, er ist es jedoch aus der Sicht des Empfängers durch den Frequenzversatz.

Two main effects ensure a channel that is time-variant from the recipient's point of view:

• (1) Movement of the transmitter, receiver or other objects on which the radio waves are scattered. From a physical point of view, the channel is time-variant.
• (2) A frequency offset between transmitter and receiver, also known as a frequency offset. The physical channel itself does not necessarily have to be time-variant, but from the point of view of the receiver it is due to the frequency offset.

In real systems there is always a deviation between the transmitter and receiver frequency, e.g. due to tolerances of the crystal oscillators. An essential measure in the receiver is therefore usually to estimate the frequency offset on the basis of the received signal and to compensate it accordingly. However, this frequency offset estimate is subject to unavoidable inaccuracies (estimation errors) which depend on the interference with the received signal. If, for example, a data sequence with a length of 128 bytes (1024 bits) is transmitted at a symbol rate of 10 kS / s (assumption: one symbol per bit), the transmission time of the data packet without coding is approx.0.1 s Hz would already lead to a phase shift of approx. 36 degrees between the first and last symbol of the data packet. In the case of 1/3 rate coding, the data packet is accordingly lengthened by a factor of 3, so that for the assumptions made there is now a phase rotation of approximately 108 degrees between the first and last transmitted symbol.

This example with realistically chosen system parameters makes it clear that forward error correction coding (e.g. turbo coding or LDPC coding), which requires coherent demodulation to achieve the desired coding gain, in a system with the above assumptions necessarily requires channel tracking within the data packet , even if there is no mobility of the participants.

In summary, an existing transmission standard without forward error correction (e.g. in accordance with 3 ) in many cases only expediently backwards compatible with forward error correction coding (e.g. turbo coding or LDPC coding) if this is accompanied by channel tracking within the data packet.

Channel tracking principle

• • entweder ebenfalls im Empfänger vorab bekannt sein (zusätzliche Referenzsymbole, jedoch außerhalb der Präambel),
• • oder im Empfänger im Verlauf der Demodulation und Decodierung oder teilweisen Decodierung (Teil-Decodierung) nach und nach ermittelt werden.

The updating of an (initial) channel estimate is referred to as channel tracking. As mentioned above, the initial channel estimation is based on a transmission symbol sequence known in advance in the receiver (referred to here as a reference (symbol) sequence or sequence of reference bits) which, for example, precedes the data sequence (preamble). The channel estimation is updated in principle according to the same method, but instead of or in addition to the known reference symbols, further symbols are included in the channel estimation. These symbols can

• • Either also be known in advance in the recipient (additional reference symbols, but outside the preamble),
• • or are gradually determined in the receiver in the course of demodulation and decoding or partial decoding (partial decoding).

• • hinsichtlich eines ersten, zusammenhängenden Teils der Sendesymbole rückwärtskompatibel zum ursprünglichen System ist, und
• • Codierung, Interleaving und Einführung weiterer Referenzsymbole so gestaltet werden, dass empfängerseitig eine fortlaufende Kanalnachführung für eine kohärente Demodulation und Vorwärts-Fehlerkorrektur-Decodierung möglich ist.

The exemplary embodiments described below show how a digital transmission system without forward error correction of the data can be expanded by forward error correction coding (e.g. turbo coding, LDPC coding, convolutional coding) so that the new transmission system

• • is backward compatible with the original system with regard to a first, coherent part of the transmission symbols, and
• • Coding, interleaving and introduction of further reference symbols are designed in such a way that continuous channel tracking for coherent demodulation and forward error correction decoding is possible on the receiver side.

The coding per se (e.g. Turbo or LDPC) as well as the basic methods of how a channel estimation is carried out in the receiver on the basis of known or estimated transmission symbols are known to the person skilled in the art, so that a detailed description of this is dispensed with.

It should be mentioned again at this point that any checksum (CRC) that may be present is not regarded as a measure for forward error correction in the context of this description. Check bits are assigned to the data bits here.

Insertion of additional reference symbols outside the range of the uncoded data symbols

In order to enable channel tracking or updating of the channel estimate, one or more sequences with additional reference bits (for example sequences of reference bits) can be inserted into the sequence of interleaved error correction bits (for example parity bits). It is essential to leave the area of the data bits or symbols and the preceding reference bits or symbols unchanged, as shown in FIG 8th is illustrated.

8th shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding) and additional sequences of reference bits, the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence. In a first step 302 can be based on the data bit sequence 202 , a forward error correction (coding) (e.g. turbo coding) can be performed to a sequence 304 of systematic bits and two of the sequence 304 sequences assigned by systematic bits 306_1 and 306_2 of error correction bits (e.g. parity bits). The consequence 304 of systematic bits is here identical to the data bit sequence 202 . In a second step 308 can be a nesting of the two episodes 306_1 and 306_2 of error correction bits are carried out to produce a sequence 310 from nested error correction bits (e.g. parity bits). In a third step 312 can have two consequences 320_1 and 320_2 of additional reference bits in the range of the sequence 310 of interleaved error correction bits. In detail can be a first consequence 320_1 of additional reference bits of the sequence 310 preceded by interleaved error correction bits (e.g. parity bits), while a second sequence 320_2 of additional reference bits between the sequence 310 of interleaved error correction bits can be inserted, so that the result 310 of interleaved error correction bits by the second sequence 320_2 is interrupted by additional reference bits. Here a first part 310_1 the consequence 310 of interleaved error correction bits before the second sequence 320_2 be arranged by additional reference bits, while a second part 310_2 the consequence 310 of interleaved error correction bits after the second sequence 320_2 can be arranged by additional reference bits.

As in 8th can be seen, a first transmission bit block 200 the result of the transmission bit sequence to be transmitted 201 of reference bits and the sequence 304 of systematic bits, while the second transmission bit block 300 the first episode 320_1 of additional reference bits, the first part 310_1 the consequence 310 of interleaved error correction bits, the second sequence 320_2 of additional reference bits and the second part 310_2 the consequence 310 comprised of interleaved error correction bits.

In the schematic representation of 8th are therefore two examples 320_1 and 320_2 of additional reference bits in the sequence 310 of the interleaved parity bits inserted. These additional reference sequences significantly shorten the maximum distance between data or parity bits and the respectively closest reference sequence compared to the case where only the preamble is used as the only reference sequence, as shown in FIG 9 is shown.

Shows in detail 9 a schematic representation of the sequences of reference bits assigned for the channel estimation for the transmission bit sequence to be transmitted 8th . As in 8th can be seen, a channel estimate for a first part of the systematic bits 304 based on the episode 201 of reference bits of the first send bit block 200 take place while a channel estimation for a second part of the systematic bits 304 based on the first episode 320_1 of additional reference bits of the second transmission bit block 300 can be done. A channel estimate for a first part of the first part 310_1 the consequence 310 of interleaved error correction bits can be based on the first sequence 320_1 of additional reference bits of the second transmission bit block 300 take place while a channel estimation for a second part of the first part 310_1 the consequence 310 of interleaved error correction bits based on the second sequence 320_2 of additional reference bits of the second transmission bit block 300 can be done. A channel estimate for the second part 310_2 the consequence 310 of interleaved error correction bits can be based on the second sequence 320_2 of additional reference bits of the second transmission bit block 300 respectively.

This in 9 The example shown shows the addition and insertion of two additional reference sequences 320_1 and 320_2 in front of or in the area of the interleaved parity bits 310 As a result, three chronologically different positions are now available in the receiver for a channel estimation. The receiver can now either permanently assign one of the three available channel estimates, advantageously the closest one, to each unknown data or parity bit, as shown in FIG 9 is shown, or the receiver can interpolate between the three available channel estimates and assign an interpolated and thus individual channel estimate to each data or parity bit.

In the case of exemplary embodiments, unlike in the above example, only one or more than two additional reference sequences can of course also be inserted. In the latter case, the length of the reference sequences can be the same or different. An additional reference sequence can also be transmitted after the interleaved parity bits, i.e. as the end of the transmitted sequence.

In exemplary embodiments, one or more additional reference sequences can be inserted into the sequence of the interleaved parity bits and / or added to the beginning or end thereof.

In exemplary embodiments, the area of the preamble and the data symbols can remain unchanged compared to uncoded transmission (preservation of backward compatibility). This takes place in that the systematic bits occurring during the coding are arranged directly one behind the other in an unchanged sequence in relation to the data bit sequence.

In embodiments, the bits or symbols of the reference sequences are known in advance in the receiver or can be determined from information previously transmitted and recovered in the receiver (e.g. from header information).

Division of the data bit sequence into partial sequences and separate coding of these partial sequences

The channel estimation or channel update considered in the exemplary embodiments is based on the knowledge of transmitted bits or symbols in the receiver.

Section 1 shows how additional reference bits known in advance can be introduced into the transmission sequence, on the basis of which the channel estimation can take place. Due to the required backward compatibility, however, no additional reference sequence can be introduced into the area of the uncoded data bits, so that in the case of long data packets there is a comparatively large distance between the data bits located in the middle of this area and the closest reference sequence.

This circumstance, which may be very disadvantageous for channel estimation in time-variant channels, is improved by the exemplary embodiments described below. These describe the use of coded bits that are initially unknown in the receiver, but estimated in the course of the demodulation and decoding of a partial reception sequence, as the basis for an iterative channel estimation.

In embodiments, one of the in 1 shown data sender, e.g. the data sender 100_1 , be configured to based on the data bit sequence 202 perform forward error correction coding to a sequence 304 of systematic bits and the sequence 304 of systematic Error correction bits assigned to bits 310 to get, with the data bit sequence 202 and the consequence 304 of systematic bits are identical, the data transmitter is configured to send a signal 120 send out, taking the signal 120 a first send bit block 200 and a second transmit bit block 300 having, the first transmission bit block 200 one episode 201 of reference bits and the sequence 304 of systematic bits, and wherein the second transmission bit block 300 the error correction bits 310 wherein a block of systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the sequence of error correction bits, which is assigned to the block of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits.

In embodiments, the in 1 The data receiver shown can be configured to receive a signal 120 to receive the a first transmission bit block 200 and a second transmit bit block 300 having, the first transmission bit block 200 one episode 201 of reference bits and a sequence 304 of systematic bits, the sequence of systematic bits 304 identical to a data bit sequence to be transmitted with the signal 202 is, where the second transmission bit block 300 the consequence 304 error correction bits assigned by systematic bits 310 having, the data receiver 110 is configured to based on the received sequence 201 of reference bits to perform a channel estimation, the data receiver 110 is configured to have a sequence containing a received block of systematic bits of the received sequence 304 of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits 310 associated with the received block of systematic bits comprises decoding independently of other received error correction bits or received blocks of error correction bits in order to obtain a block of the data bit sequence, the data receiver 110 is configured to carry out forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits assigned to the reencoded block of systematic bits, wherein the data receiver 110 is configured to track the channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.

The exact functionality of the data transmitter 110_1 and / or the data receiver is used in the following with reference to the 10 to 18th illustrated embodiments explained in more detail. In 10 First, the underlying basic principle is explained and based on this in 11 to 18th the various embodiments.

10 shows a schematic view of a generation of a sequence of coded bits with blocks of coded bits (for example coded partial sequences) which are individually coded, as well as an iterative channel tracking based on the blocks of coded bits.

In one step on the sender side 330 can parts (e.g. blocks) 202_1 , 202_3 and 202_3 a data bit sequence 202 individually encoded to form individually encoded blocks 206_1 , 206_2 and 206_3 of coded data bits (coded partial sequences).

In a first step on the recipient side 332 can be based on one of the first block 206_1 block preceded by coded data bits 201 of reference bits, a channel estimate for demodulation of the first block 206_1 of coded data bits. Furthermore, in the first recipient-side step 332 the first block 206_1 of encoded data bits based on the channel estimate are demodulated, decoded and reencoded (dt. re-encoded) to form a first reencoded (dt. re-encoded) block 206_1 of encoded data bits.

In a second step on the recipient side 334 can, based on the block 201 of reference bits and the first reencoded block 206_1 of coded data bits, a channel estimate for demodulation of the second block 206_2 of coded data bits. Furthermore, in the second recipient-side step 334 the second block 206_2 of encoded data bits based on the channel estimate are demodulated, decoded and reencoded (dt. re-encoded) to form a second reencoded (dt. re-encoded) block 206_2 of encoded data bits.

In relation to 10 it should be pointed out that the steps of “nesting and deinterleaving” (interleaving and deinterleaving) are not explicitly shown for reasons of clarity. These steps are considered part of “encoding” and “decoding” in the broader sense.

As in the upper part of 10 shown are the data bits 202 initially in blocks 202_1 , 202_2 and 202_3 broken down by data bits (eg data bit partial sequences), which are each coded separately. In the picture, “Cod. Teilsequenz "the already coded and interleaved bits of a data bit partial sequence. In the following, lower part of the 10 the processing in the receiver is shown. The initial channel estimation in the first step 330 (Step 1a) takes place exclusively on the basis of the reference bits. This channel estimate is used for the coherent demodulation of the bits of the first block 206_1 of coded data bits (coded partial sequence 1) are used. After demodulation, the bits of the first block 206_1 of coded bits (coded partial sequence 1) decoded and then reencoded (step 1b), which now gives estimates for the first block 206_1 of coded data bits (coded partial sequence 1) are present, including a coding gain. Assuming a correct decoding result, an extended sequence of known bits is now available in the receiver, including the block 201 of reference bits and the first reencoded block 206_1 of coded bits (coded partial sequence 1). The second step is based on this 334 (Step 2a) an update of the channel estimate for the demodulation, decoding and re-encoding (Step 2b) of the second block 206_2 of coded data bits (coded partial sequence 2), which can then be regarded as known. It is easy to see that in this way the entire transmission sequence, consisting of any number of partial sequences, can be processed iteratively, with the channel estimate being updated again and again after each iteration step (channel tracking).

Since according to 10 If already coded and nested partial sequences are appended to one another, the method in this form is not backwards compatible and therefore does not meet the requirements in this regard.

• - Die Datenbitfolge 202 (z.B. Sequenz der Datenbits) kann in eine geeignete Anzahl von Blöcken von Datenbits (z.B. Datenbit-Teilsequenzen) aufgeteilt werden.
• - Jeder Block von Datenbits (z.B. jede Datenbit-Teilsequenz) kann mit einer Vorwärts-Fehlerkorrektur-Codierung (z.B. Turbo-Codierung) separat und unabhängig von den anderen Blöcken von Datenbits codiert werden.
• - Die systematischen Bits aller Blöcke von codierten Datenbits (z.B. codierten Teilsequenzen) können gruppiert, direkt aneinander angefügt und unmittelbar nach der Folge 201 von Referenzbits (z.B. Referenzsequenz) angeordnet werden. Es erfolgt keine Verschachtelung der systematischen Bits, sodass diese nach Gruppierung identisch zur gesamten Datenbitfolge 202 sind.
• - Die Fehlerkorrekturbits (z.B. Paritätsbits) aller Blöcke von codierten Datenbits (z.B. codierten Teilsequenzen) können gruppiert, aneinander angefügt und nach der Folge aller systematischen Bits angeordnet werden.
• - Eine eventuelle Verschachtelung (Interleaving) der Fehlerkorrekturbits (z.B. Paritätsbits) wird Teilsequenz für Teilsequenz separat durchgeführt und nicht Teilsequenzübergreifend.
• - In die Sequenz der Fehlerkorrekturbits (z.B. Paritätsbits), vor Beginn der Fehlerkorrekturbits und/oder am Ende der Fehlerkorrekturbits können an geeigneter Position bzw. an geeigneten Positionen zusätzliche Referenzsequenzen (z.B. gemäß Abschnitt 1) eingefügt werden.

Therefore, in exemplary embodiments, a transmission bit sequence to be transmitted can have a first transmission bit block, which is backward compatible with an “existing” communication system (or communication protocol), and a second transmission bit block, which extends the “existing” communication system by a forward error correction based on one or more the following steps:

• - The data bit sequence 202 (eg sequence of data bits) can be divided into a suitable number of blocks of data bits (eg data bit partial sequences).
• - Each block of data bits (for example each data bit partial sequence) can be coded separately and independently of the other blocks of data bits with forward error correction coding (for example turbo coding).
• - The systematic bits of all blocks of coded data bits (eg coded partial sequences) can be grouped, attached directly to one another and immediately after the sequence 201 of reference bits (e.g. reference sequence). The systematic bits are not interleaved, so that, after grouping, they are identical to the entire data bit sequence 202 are.
• The error correction bits (eg parity bits) of all blocks of coded data bits (eg coded partial sequences) can be grouped, appended to one another and arranged according to the sequence of all systematic bits.
• A possible interleaving of the error correction bits (eg parity bits) is carried out part-sequence for part-sequence separately and not across part-sequence.
• - In the sequence of error correction bits (e.g. parity bits), before the beginning of the error correction bits and / or at the end of the error correction bits, additional reference sequences (e.g. according to section 1) can be inserted at a suitable position or positions.

11 shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.

In a first step 340, the data bit sequence 202 be divided into at least two blocks 202_1-202_i, i ≥ 2. In 11 it is assumed here by way of example that the data bit sequence 202 in three blocks 202_1 , 202_2 and 202_3 is divided. The following description of 11 however, it can be used in a corresponding manner if the data bit sequence is divided into a different number of blocks.

In a second step 342 can, based on the first block 202_1 of the data bit sequence, a first forward error correction coding can be carried out to form a first block 304_1 of systematic bits and a first block 310_1 of contiguous error correction bits belonging to the first block 304_1 of systematic bits allocated to get. Furthermore, in the second step 342 , based on the second block 202_2 of the data bit sequence, a second forward error correction coding can be carried out to form a second block 304_2 of systematic bits and a second block 310_2 of contiguous error correction bits belonging to the second block 304_2 of systematic bits allocated to get. Furthermore, in the second step 342 , based on the third block 202_3 of the data bit sequence, a third forward error correction coding can be carried out to a third block 304_3 of systematic bits and a third block 310_3 of contiguous error correction bits belonging to the third block 304_3 of systematic bits allocated to get.

In a third step 344, the blocks 304_1 , 304_2 and 304_3 of systematic bits grouped (e.g. concatenated) to form a sequence 304 of systematic bits that are identical to the data bit sequence 202 is. As in 11 can be seen, the first transmission bit block thus comprises the sequence 201 of reference bits and the sequence 304 of systematic bits, while the second transmit bit block 300 the blocks 310_1 , 310_2 and 310_3 comprised of error correction bits.

In a fourth step 346 can (optionally) add one or more blocks of additional reference bits to the second transmit bit block 300 inserted.

The in 11 The embodiment shown, the second transmission bit block comprises, for example, a sequence 320 of additional reference bits at the beginning of the second transmission bit block 300 is arranged. In the second send bit block 300 is the first block 310_1 of error correction bits immediately adjacent to the sequence 320 arranged by additional reference bits, the second block 310_2 of error correction bits immediately adjacent to the first block 310_1 of error correction bits is arranged, and wherein the third block 310_3 of error correction bits immediately adjacent to the second block 310_2 of error correction bits is arranged.

In other words, 11 illustrates the method schematically for the case of a division of the data sequence (e.g. data bit sequence 202 ) in three data partial sequences 202_1 , 202_2 and 202_3 and with the addition of an additional reference sequence 320 in the area between data and parity bits.

In the example chosen, the data bit sequence (data bit sequence 202 ) so in three data partial sequences (e.g. blocks 202_1 , 202_2 and 202_3 ), which are coded separately. The systematic bits of each partial sequence are then added to one another and these are placed after the reference bits. The same happens as in 11 illustrated with the three sequences of parity bits (e.g. blocks 310_1 , 310_2 and 310_3 error correction bits). Furthermore, an additional reference sequence is used in the example chosen 320 (see section 1) between the range of systematic bits 304 and the range of parity bits 310_1 , 310_2 and 310_3 inserted.

• - Die erste Kanalschätzung erfolgt
  • • für den ersten Block 304_1 von systematischen Bits („systematischen Bits 1“) z.B. auf Basis der Folge 201 von Referenzbits (z.B. Präambel),
  • • für den ersten Block 310_1 von Fehlerkorrekturbits(„Paritätsbits 1“) z.B. auf Basis der vorab bekannten Folge 320 von zusätzlichen Referenzbits (z.B. zusätzliche Referenzsequenz).
• - Anschließend werden der erste Block 304__1 von systematischen Bits („systematische Bits 1“) sowie der erste Block 310_1 von Fehlerkorrekturbits(„Paritätsbits 1“) demoduliert und der zugehörige Block 202_1 der Datenbitfolge (z.B. Datenbit-Teilsequenz 1) decodiert. Ist das Decodierergebnis korrekt, lassen sich durch Re-Encodierung der erste Block 304_1 von systematischen Bits („systematische Bits 1“) sowie der erste Block 310_1 von Fehlerkorrekturbits(„Paritätsbits 1“) ermitteln. Hierbei wird der Decodiergewinn genutzt, d.h. die Zuverlässigkeit der Schätzwerte für die o.g. Bits ist nach der Decodierung deutlich höher als vor der Decodierung (d.h. direkt nach der Demodulation).
• - Die zweite Kanalschätzung, gültig für den zweiten Block 304_2 von systematischen Bits („systematischen Bits 2“) sowie für den zweiten Block 310_2 von Fehlerkorrekturbits („Paritätsbits 2“), erfolgt auf Basis des nunmehr (zusätzlich zur ersten Kanalschätzung) bekannten ersten Blocks 304_1 von systematischen Bits („systematische Bits 1“) und des ersten Blocks 310_1 von Fehlerkorrekturbits(„Paritätsbits 1“), welche im ersten Schritt noch unbekannt waren.
• - Anschließend werden der zweite Block 304_2 von systematischen Bits („systematischen Bits 2“) sowie der zweite Block 310_2 von Fehlerkorrekturbits („Paritätsbits 2“) demoduliert, und der zugehörige zweite Block 202_2 der Datenbitfolge (Datenbit-Teilsequenz 2) decodiert etc.

This procedure in accordance with exemplary embodiments enables the receiver to estimate or update the transmission channel several times within the entire data packet. This is done using the example chosen as follows:

• - The first channel estimation takes place
  • • for the first block 304_1 of systematic bits ("systematic bits 1"), for example on the basis of the sequence 201 of reference bits (e.g. preamble),
  • • for the first block 310_1 of error correction bits ("parity bits 1"), for example on the basis of the sequence known in advance 320 of additional reference bits (e.g. additional reference sequence).
• - Then the first block 304__1 of systematic bits (“systematic bits 1”) and the first block 310_1 of error correction bits ("parity bits 1") and the associated block 202_1 the data bit sequence (e.g. data bit partial sequence 1) is decoded. If the decoding result is correct, the first block can be re-encoded 304_1 of systematic bits ("systematic bits 1") as well as the first block 310_1 of error correction bits ("parity bits 1"). The decoding gain is used here, ie the reliability of the estimated values for the above-mentioned bits is significantly higher after decoding than before decoding (ie directly after demodulation).
• The second channel estimate, valid for the second block 304_2 of systematic bits ("systematic bits 2") as well as for the second block 310_2 of error correction bits (“parity bits 2”), takes place on the basis of the now known first block (in addition to the first channel estimate) 304_1 of systematic bits ("systematic bits 1") and the first block 310_1 of error correction bits ("parity bits 1"), which were still unknown in the first step.
• - Then the second block 304_2 of systematic bits ("systematic bits 2") and the second block 310_2 demodulated by error correction bits ("parity bits 2"), and the corresponding second block 202_2 the data bit sequence (data bit partial sequence 2) decoded etc.

It is easy to see that the channel estimation can be successively updated in this way and the distance between the respectively known bits on the basis of which the channel estimation is made and the area in which the channel estimation is used in the context of the demodulation does not keep increasing but rather, for example, can be kept constant. A time-variant channel can therefore be followed with a slight delay (compared to the entire data packet length) by continuously updating the channel estimate, in particular if a division into a larger number of data bit partial sequences takes place.

The above exemplary embodiment shows the idea according to the invention for dividing the data sequence into three data bit partial sequences. This example is for illustrative purposes only. The breakdown the data sequence can in principle be made up of any number of partial data sequences. The length of a partial data sequence depends on the expected coherence time of the channel, for example on an expected frequency offset or a maximum assumed movement speed of the transmitter and / or receiver and / or scattered objects.

Arrangement of the parity bit sequences

While the blocks of the systematic bits (partial sequences of the systematic bits) have to be arranged in the same order for reasons of backward compatibility as the blocks of the data bit sequence (data bit partial sequences), ie "systematic bits 1", "systematic bits 2" etc. , the order of the blocks of the error correction bits (sequences of the parity bits) can also be changed, possibly in combination with a different position of the additional reference sequence. This is exemplified in 12th shown.

Shows in detail 12th a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block 200 out 11 and a second transmission bit block opposite 11 a different arrangement of the blocks 310_1 , 310_2 and 310_3 of error correction bits and the one sequence 320 of additional reference bits. As in 12th can be seen, the consequence 320 of additional reference bits at one end of the second transmit bit block 300 be arranged, the first block 310_1 of error correction bits immediately adjacent to the sequence 320 of additional reference bits can be arranged, the second block 310_2 of error correction bits immediately adjacent to the first block 310_1 of error correction bits can be arranged, and wherein the third block 310_3 of error correction bits immediately adjacent to the second block 310_2 of error correction bits can be arranged.

In the example according to 12th is the additional reference sequence 320 placed at the end of the transmitted data and the blocks 310_1 , 310_2 and 310_3 of error correction bits (parity bit sequences) in reverse order with respect to the indexing of the blocks 202_1 , 202_2 and 202_3 the data bit sequence (data bit partial sequences).

In this example, the channel estimate would be updated in the receiver in the direction from outside to inside. This is in 12th below by corresponding direction arrows 350 and 352 indicated.

The additional reference sequence 320 could instead of after the first block 310_1 of error correction bits ("parity bits 1") also between the first block 310_1 of error correction bits ("parity bits 1") and the second block 310_2 of error correction bits ("parity bits 2").

• - zumindest die zur ersten codierten Datenbit-Teilsequenz gehörende Sequenz der Paritätsbits (erster Block 310_1 von Fehlerkorrekturbits) unmittelbar an eine Referenzsequenz 320 (Präambel oder zusätzliche Referenzsequenz gemäß Abschnitt 1) angrenzt, sowie
• - die Paritätsbit-Sequenzen (Blöcke von Fehlerkorrekturbits) direkt aufeinander folgender Datenbit-Teilsequenzen (Blöcke der Datenbitfolge) aneinander angrenzen oder sich zwischen diesen nur zusätzliche Referenzsequenzen befinden.

The decisive factor with regard to the possible arrangements of the blocks of error correction bits (eg parity bits) is that

• - At least the sequence of parity bits belonging to the first coded data bit partial sequence (first block 310_1 error correction bits) directly to a reference sequence 320 (Preamble or additional reference sequence according to section 1), as well as
• - the parity bit sequences (blocks of error correction bits) directly following one another data bit partial sequences (blocks of the data bit sequence) border one another or there are only additional reference sequences between them.

In previous examples, the parity bit sequences (blocks of error correction bits) were arranged in such a way that the first parity bit sequence (first block 310_1 ) to an additional reference sequence 320 adjoins. Alternatively, the first parity bit sequence can also be placed in front of the reference bits already present in the original (uncoded) system. This is in 13th shown.

Shows in detail 13th a schematic view of a transmission bit sequence to be transmitted with the first transmission bit block 200 out 11 and a second transmission bit block 300 , which is the first send bit block 200 is prefixed. In the second send bit block 300 can the first block 310_1 of error correction bits can be arranged so that the first block 310_1 of error correction bits immediately adjacent to the sequence 201 of reference bits of the first transmission bit block 200 is arranged. The second block 310_2 of error correction bits can be immediately adjacent to the first block 310_1 of error correction bits, the third block 310_3 of error correction bits immediately adjacent to the second block 310_2 of error correction bits can be arranged.

In other words, the parity bit sequences (blocks of error correction bits) can then, as in 13th is shown, in chronologically reversed order before the reference bits 201 be arranged so that in the receiver a successive channel estimation from "inside" to "outside" 350 , 352 , starting with the reference bits 201 , can be done.

Dotting

In many practical transmission systems, a sequence is punctured after coding in order to achieve a desired coding rate with high granularity. Such puncturing is also at Embodiments possible, but the systematic bits should generally be excluded from puncturing in order to meet the requirement for backward compatibility.

Subdivision of the parity bit sequences into parity bit partial sequences

Depending on the code rate, in practical applications the number of parity bits can be significantly higher than the number of systematic bits, for example at least twice as large. This means that the step size when updating the channel estimate can be significantly larger in the area of the parity bits than in the area of the systematic bits, as is also shown in the schematic representation according to FIG 11 is visible. In other words, the distance between the range of the known bits on the basis of which the channel estimation takes place and the range in which this estimated value is used for the demodulation is different in the range of the systematic bits and the parity bits. In the case of channels whose coherence time is short compared to the transmission time of a parity bit partial sequence, this circumstance can lead to a loss of performance, since the channel estimation “lags too far behind” the respective demodulation time.

In order to avoid this disadvantageous situation, the parity bit sequences can be subdivided into several parity bit partial sequences. This is illustrated in the following exemplary embodiment, in which a subdivision into two partial sequences takes place, as is shown below with reference to FIG 14th is explained.

14th shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.

In a first step 340, the data bit sequence 202 be divided into at least two blocks 202_1-202_i, i ≥ 2. In 14th it is assumed here by way of example that the data bit sequence 202 in three blocks 202_1 , 202_2 and 202_3 is divided. The following description of 14th however, it can be used in a corresponding manner if the data bit sequence is divided into a different number of blocks.

In a second step 342, based on the first block 202_1 of the data bit sequence, a first forward error correction coding can be carried out to form a first block 304_1 of systematic bits and two blocks 310_1 and 310_2 of contiguous error correction bits belonging to the first block 304_1 of systematic bits assigned to get. Furthermore, in the second step 342 , based on the second block 202_2 of the data bit sequence, a second forward error correction coding can be carried out to form a second block 304_2 of systematic bits and two blocks 310_3 and 310_4 of contiguous error correction bits belonging to the second block 304_2 of systematic bits assigned to get. Furthermore, in the second step 342 , based on the third block 202_3 of the data bit sequence, a third forward error correction coding can be carried out to a third block 304_3 of systematic bits and two blocks 310_5 and 310_6 of contiguous error correction bits belonging to the third block 304_3 of systematic bits assigned to get.

In a third step 344, the blocks 304_1 , 304_2 and 304_3 of systematic bits are grouped (e.g. concatenated) to form a sequence 304 of systematic bits that are identical to the data bit sequence 202 is. As in 14th can be seen, the first transmission bit block thus comprises the sequence 201 of reference bits and the sequence 304 of systematic bits, while the second transmission bit block 300 comprises the six blocks 310_1-310_6 comprised of error correction bits.

In a fourth step 346 can (optionally) add one or more blocks of additional reference bits to the second transmit bit block 300 inserted.

The in 14th The embodiment shown comprises the second transmission bit block 300 an example of a first episode 320_1 of additional reference bits at the beginning of the second transmission bit block 300 is arranged, and a second sequence 320_2 of additional reference bits that are in the middle between the six blocks 310_1-310_6 of error correction bits is arranged. Here the first block 310_1 of error correction bits immediately adjacent to the first sequence 320_1 of additional reference bits, the third block 310_3 of error correction bits immediately adjacent to the first block 310_1 of error correction bits is arranged, the second block 310_2 of error correction bits immediately adjacent to the second sequence 320_2 of additional reference bits is arranged, and wherein the fourth block 310_4 of error correction bits immediately adjacent to the second block 310_2 of error correction bits is arranged.

In other words, in 14th shows how the parity bits generated by coding a data bit partial sequence (block of the data bit sequence) are divided into, for example, two partial sequences ("a" and "b"), which are divided into 14with "Parity bits 1a" and "Parity bits 1b", "Parity bits 2a" and “Parity bits 2b” etc. are identified (ie two (or more) blocks of error correction bits are generated for each block of the data bit sequence in the forward error correction coding). In addition, there is a second, additional reference sequence compared to the previous examples 320_2 (additional reference sequence 2) inserted. The parity bits belonging to a data bit partial sequence (block of the data bit sequence), e.g. parity bits 1a (first block 310_1 of error correction bits) and parity bits 1b (second block 310_2 error correction bits) are not transmitted directly one after the other, but grouped in such a way that all parity bit partial sequences “a” (1a, 2a, 3a) are arranged first and then all partial sequences “b” (1b, 2b, 3b).

A subdivision of the parity bit sequences into more than two partial sequences is possible.

It can be seen that according to 14th the step sizes for updating the channel estimate are thereby smaller in the area of the parity bits than without subdivision into parity bit partial sequences “a” and “b”. In the example shown, the receiver carries out initial channel estimates based on the preamble 201 , additional reference sequence 1 (first episode 320_1 of additional reference bits) and additional reference sequence 2 (second sequence 320_2 of additional reference bits). Then the “systematic bits 1” are demodulated (first block 304_1 of systematic bits), "parity bits 1a" (first block 310_1 error correction bits) as well as "parity bits 1b" (second block 310_2 of error correction bits), which are arranged immediately after the reference sequences known in advance (first and second block of additional reference bits). This means that the data bit partial sequence 1 (first block 202_1 the data bit sequence). After subsequent re-encoding of the associated decoded bits (if there are no errors), the "systematic bits 1" (first block 304_1 of systematic bits), "parity bits 1a" (first block 310_1 error correction bits) as well as "parity bits 1b" (second block 310_2 error correction bits) are now known and can be used as a basis for the further channel estimates.

Alternative arrangements of the parity bit partial sequences

According to a first variant, an additional reference sequence (for example a sequence of additional reference bits (in addition to the reference bits of the first transmission bit block)) can be introduced in the area of the parity bits (error correction bits), as shown in FIG 15th is shown.

Shows in detail 15th a schematic view of a generation of a transmission bit sequence to be transmitted, wherein in 15th just the step 346 the insertion of a sequence of additional reference bits in the second transmission bit block of the transmission bit sequence is shown, which differs from the in 14th shown step of inserting a sequence of additional reference bits differs.

As in 15th can be seen, the consequence 320 of additional reference bits in the second transmission bit block 300 between the blocks 310_1-310_6 of error correction bits, blocks of error correction bits that are assigned to a block of the data bit sequence that is arranged at the beginning of the data bit sequence (= first block 202_1 the data bit sequence), immediately adjacent to the sequence 320 of additional reference bits are arranged. In detail the first block 310_1 of error correction bits and the second block 310_2 of error correction bits in each case immediately adjacent to the sequence 320 be arranged by additional reference bits. Blocks of error correction bits that are assigned to a block of the data bit sequence which immediately follows the block of the data bit sequence which is arranged at the beginning of the data bit sequence (= second block 202_2 the data bit sequence) can be directly adjacent (or only with one further sequence of additional reference bits in between) to the first block 310_1 of error correction bits and the second block 310_2 of error correction bits, etc. That is, the third block 310_3 of error correction bits can be immediately adjacent to the first block 310_1 of error correction bits, the fifth block 310_5 of error correction bits immediately adjacent to the third block 310_3 of error correction bits can be arranged. The fourth block can do the same 310_4 of error correction bits immediately adjacent to the second block 310_2 of error correction bits, the sixth block 310_6 of error correction bits immediately adjacent to the fourth block 310_4 of error correction bits can be arranged.

In other words, according to a further exemplary embodiment, the respective parity bit partial sequences “a” (for example blocks of error correction bits with odd indices) and “b” (for example blocks of error correction bits with even indices) can also according to FIG 15th to be ordered. (The steps up to generating the coded bits are in 15th not shown for reasons of clarity.) In this case, only one additional reference sequence (eg sequence of additional reference bits) may be required. Optionally, of course, several sequences of additional reference bits can also be introduced into the second transmission bit block.

The steps of iterative channel estimation take place in the area of the systematic bits (e.g. blocks 304_1-304_3 of systematic bits) in in a positive direction in time (e.g. based on the sequence 201 of reference bits), while in the area of parity bits (e.g. blocks 310_1-310_6 of error correction bits) on both sides of the additional reference sequence (sequence 320 of additional reference bits) away (in both the positive and negative direction in terms of time). This is by the three direction arrows 350 , 352 , 354 in the lower part of 15th illustrated.

According to a second variant, several additional reference sequences (e.g. sequences of additional reference bits) can be introduced into the second transmission bit block, with one of the additional reference sequences between the parity bit partial sequences a ‟(e.g. blocks of error correction bits with odd indices) and“ b ”(e.g. Blocks of error correction bits with even indices) can be introduced (or arranged) in the second transmission bit block, as shown in FIG 16 is shown.

Shows in detail 16 a schematic view of a generation of a transmission bit sequence to be transmitted, wherein in 16 just the step 346 the insertion of several sequences of additional reference bits in the second transmission bit block of the transmission bit sequence, which differs from the one in 14th shown step of inserting a sequence of additional reference bits differs.

As in 16 can be seen, three consequences 320_1 , 320_2 and 320_3 of additional reference bits in the second transmission bit block 300 between the blocks 310_1-310_6 are introduced by error correction bits, with one of the three sequences 320_1 , 320_2 and 320_3 of additional reference bits can be arranged between two blocks of error correction bits which are assigned to the same block of the data bit sequence. So can a first episode 320_1 of additional reference bits between the first block 310_1 of error correction bits and the second block 310_2 of error correction bits, a second sequence 320_2 of additional reference bits between the third block 310_3 of error correction bits and the fourth block 310_4 of error correction bits, and a third sequence 320_3 of additional reference bits between the fifth block 310_5 of error correction bits and the sixth block 310_6 be arranged by error correction bits.

In other words, according to a further exemplary embodiment, further additional reference sequences can also be arranged between the parity bit partial sequences belonging to one another “a” (e.g. blocks of error correction bits with odd indices) and “b” (e.g. blocks of error correction bits with even indices). These can each lie between the two parity bit partial sequences “a” and “b”, advantageously (but not necessarily) also in the middle, as shown in FIG 16 is shown as an example.

The steps of iterative channel estimation take place in the area of the systematic bits (e.g. blocks 304_1-304_3 of systematic bits) in a positive temporal direction (e.g. based on the sequence 201 of reference bits), while in the area of parity bits (blocks 310_1-310_6 of error correction bits) on both sides based on the respective additional reference sequences (sequences 320_1 , 320_2 and 320_3 of additional reference bits) away (in both the positive and negative direction in terms of time). This is indicated by the seven direction arrows 350-362 in the lower part of 16 illustrated.

According to a third variant, several additional reference sequences (e.g. sequences of additional reference bits) with enlarged (e.g. maximized) intervals between the respective associated parity bit partial sequences "a" (e.g. blocks of error correction bits with odd indices) and "b" (e.g. blocks of error correction bits) can be used with even indices), as shown in 17th is shown.

Shows in detail 17th a schematic view of a resulting transmission bit sequence after the introduction of three sequences 320_1 , 320_2 and 320_3 of additional reference bits, being compared with 16 a distance between blocks of error correction bits which are assigned to the same block of the transmission bit sequence is increased.

As in 17th can be seen, a first block 310_1 of error correction bits and a second block 310_2 of error correction bits immediately adjacent to spaced apart sequences 320_1 and 320_2 of reference bits, with a third block 310_3 of error correction bits and a fourth block 310_4 of error correction bits immediately adjacent to spaced apart sequences 320_2 and 320_3 of reference bits can be arranged, and where a fifth block 310_5 of error correction bits and a sixth block 310_6 of error correction bits immediately adjacent to spaced apart sequences 320_1 and 320_3 of reference bits can be arranged.

In other words, 17th shows a further advantageous arrangement of the parity bit partial sequences (for example blocks of error correction bits) in the presence of fading channels. If an additional reference sequence (e.g. sequence of additional reference bits) is inserted after a maximum of two parity bit partial sequences (e.g. blocks of error correction bits), each parity bit partial sequence (e.g. block of error correction bits) is immediately adjacent to one Reference sequence and the sequence of the parity bit partial sequences does not matter. Thus, the parity bit partial sequences can in principle be arranged in any order.

If, in addition to a pure frequency offset, a time-variant fading channel (due to the movement of the transmitter and / or receiver and / or scattered objects) is to be expected, this can result in drops in the reception level over time-related areas. In this case, it is advantageous to use the two parity bit partial sequences "a" (e.g. blocks of error correction bits with odd indices) and "b" (e.g. blocks of error correction bits with even indices), which each belong to the same coded data bit partial sequence, in terms of time to be positioned far apart from one another in order to reduce the probability that two parity bit partial sequences belonging together (eg blocks of error correction bits) are impaired at the same time as a result of a shrinkage dip, as exemplified in FIG 17th is shown.

Division into more than two parity bit partial sequences

In the 14th to 17th Exemplary embodiments are shown for a division of the parity bits belonging to a data bit partial sequence (eg block of the data bit sequence) into N _P = 2 parity bit partial sequences (“a” and “b”) (eg blocks of error correction bits). The parity bits belonging to each data bit partial sequence (eg block of the data bit sequence) can also be divided into more than two parity bit partial sequences (eg blocks of error correction bits). In the case of fading channels, these can be positioned in such a way that the parity bit partial sequences belonging to the same coded data bit partial sequence are arranged as far apart in time as possible from one another. 18th shows an example of a configuration for N _P = 4 when using two additional reference sequences.

Shows in detail 18th a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits based on forward error correction (coding), the transmission bit sequence being backward compatible with an uncoded transmission bit sequence.

In a first step 340, the data bit sequence 202 be divided into at least two blocks 202_1-202_i, i ≥ 2, with the in 18th It is assumed, by way of example, that the data bit sequence 202 in three blocks 202_1 , 202_2 and 202_3 is divided. However, the following description can be applied in a corresponding manner if the data bit sequence is divided into a different number of blocks.

In a second step 342 can, based on the first block 202_1 of the data bit sequence, a first forward error correction coding can be carried out to form a first block 304_1 of systematic bits and four blocks 310_1-310_4 of error correction bits belonging to the first block 304_1 of systematic bits assigned to get. Furthermore, in the second step 342 , based on the second block 202_2 of the data bit sequence, a second forward error correction coding can be carried out to form a second block 304_2 of systematic bits and four blocks 310_5-310_8 of error correction bits assigned to the second block 304_2 of systematic bits assigned to get. Furthermore, in the second step 342 , based on the third block 202_3 of the data bit sequence, a third forward error correction coding can be carried out to a third block 304_3 of systematic bits and four blocks 310_9-310_12 of error correction bits belonging to the third block 304_3 of systematic bits assigned to get.

In a third step 344, the blocks 304_1 , 304_2 and 304_3 of systematic bits are grouped (e.g. concatenated) to form a sequence 304 of systematic bits that are identical to the data bit sequence 202 is. As in 18th can be seen, comprises the first transmission bit block 200 thus a consequence 201 of reference bits and the sequence 304 of systematic bits (represented as a sequence of blocks 304_1 , 304_2 and 304_3 of systematic bits), while the second transmission bit block 300 which comprises twelve blocks 310_1-310_12 of error correction bits.

In a fourth step 346 can (optionally) have one or more episodes 320_1 and 320_2 of additional reference bits in the second transmission bit block 300 inserted.

The in 18th Exemplary embodiment shown are two sequences 320_1 and 320_2 of additional reference bits in the second transmission bit block 300 brought in. In this case, those blocks of error correction bits that are assigned to a block of the data bit sequence that is arranged at the beginning of the data bit sequence (= block 202_1 of the data bit sequence), immediately adjacent to the sequences 320_1 and 320_2 be arranged by additional reference bits, for example the blocks 310_1 and 310_3 of error correction bits immediately adjacent to the first sequence 320_1 of additional reference bits and the blocks 310_2 and 310_4 of error correction bits immediately adjacent to the second sequence 320_2 of additional reference bits. Blocks of error correction bits that are assigned to a block of the data bit sequence which follows the block of the data bit sequence which is arranged at the beginning of the data bit sequence (= block 202_2 the data bit sequence) can be arranged immediately adjacent to the blocks of the error correction bits that are assigned to the block of the data bit sequence that is arranged at the beginning of the data bit sequence.

In other words, the in 18th The exemplary embodiment shown, the parity bit partial sequences (e.g. blocks of error correction bits) belonging to a data bit partial sequence (e.g. block of the data bit sequence) can be arranged with the greatest possible distance from one another, with the proviso that in the receiver a successive decoding starting directly from one Reference sequence (for example sequence of additional reference bits) can be made. This results in more time diversity per data bit partial sequence than when using, for example, only two parity bit partial sequences.

• - Aufteilung der Datenbit-Sequenz (z.B. Datenbitfolge 202) in direkt aufeinander folgende Datenbit-Teilsequenzen (Blöcke der Datenbitfolge), welche separat codiert (z.B. Vorwärts-Fehlerkorrektur codiert (z.B. Turbo-/LDPC-/Faltungscodiert)) werden (Codierung der Teilsequenzen (Blöcke der Datenbitfolge) unabhängig voneinander).
• - Anordnung der Sequenzen der systematischen Bits (z.B. Blöcke von systematischen Bits) der codierten Datenbit-Teilsequenzen dergestalt, dass deren gesamte Folge identisch zur gesamten uncodierten Datenbitsequenz (z.B. Datenbitfolge) ist.
• - Anordnung der Paritätsbits (z.B. Blöcke von Fehlerkorrekturbits) der codierten Datenbit-Teilsequenzen dergestalt, dass
  • o zumindest die zur ersten Datenbit-Teilsequenz (z.B. ersten Block der Datenbitfolge) gehörende Paritätsbit-Sequenz (z.B. Block von Fehlerkorrekturbits) unmittelbar an eine Referenzsequenz (Präambel oder zusätzliche Referenzsequenz, vgl. Abschnitt 1) angrenzt, sowie
  • o die Paritätsbit-Sequenzen (z.B. Blöcke von Fehlerkorrekturbits) direkt aufeinander folgender Datenbit-Teilsequenzen (z.B. Blöcken der Datenbitfolge) direkt aneinander angrenzen oder sich zwischen diesen nur zusätzliche Referenzsequenzen befinden (siehe z.B. 11, 12 und 13).
• - Unterteilung der Paritätsbit-Sequenzen in jeweils mehrere (z.B. zwei) Paritätsbit-Teilsequenzen (z.B. Blöcke von Fehlerkorrekturbits), wobei die Paritätsbit-Teilsequenzen direkt aufeinander folgender Datenbit-Teilsequenzen (z.B. Blöcken der Datenbitfolge) direkt aneinander angrenzen oder sich zwischen diesen nur zusätzliche Referenzsequenzen befinden (siehe 14 und 15).
• - Einfügen von zusätzlichen Referenzsequenzen (z.B. Folgen von zusätzlichen Referenzbits) jeweils zwischen die beiden Paritätsbit-Teilsequenzen (z.B. Blöcken von Fehlerkorrekturbits) einer codierten Datenbit-Teilsequenz, wobei die Anzahl der zusätzlichen Referenzsequenzen der Anzahl der Datenbit-Teilsequenzen (z.B. Blöcken der Datenbitfolge) entspricht (siehe 16). Die genaue Anordnung der Paritätsbit-Teilsequenzen relativ zueinander ist dabei beliebig, da jede von ihnen immer unmittelbar an eine zusätzliche Referenzsequenz angrenzt. Für Schwundkanäle ist eine Anordnung vorteilhaft, in welcher die beiden Paritätsbit-Teilsequenzen „a“ (z.B. Blöcke von Fehlerkorrekturbits mit ungeraden Indizes) und „b“ (z.B. Blöcke von Fehlerkorrekturbits mit geraden Indizes) (die zu jeweils derselben codierten Datenbit-Teilsequenz gehören) möglichst weit voneinander getrennt positioniert werden.
• - Anordnung der zu einer Datenbit-Teilsequenz (z.B. Block der Datenbitfolge) gehörenden Paritätsbit-Teilsequenzen (z.B. Blöcke von Fehlerkorrekturbits) dergestalt, dass jede dieser Paritätsbit-Teilsequenzen entweder an eine zusätzliche Referenzsequenz (z.B. Folge von zusätzlichen Referenzbits) oder an eine (beliebige) Paritätsbit-Teilsequenz einer der (der betrachteten Datenbit-Teilsequenz) vorangehenden Datenbit-Teilsequenzen direkt angrenzt (siehe z.B. 17 und 18).

In embodiments, a transmission bit sequence to be transmitted [for example with a first transmission bit block, which is backward compatible with an "existing" communication system (or communication protocol), and a second transmission bit block, which extends the "existing" communication system to include forward error correction], based on a or more of the following steps:

• - Division of the data bit sequence (e.g. data bit sequence 202 ) in directly successive data bit partial sequences (blocks of the data bit sequence), which are coded separately (e.g. forward error correction coded (e.g. turbo / LDPC / convolution coded)) (coding of the partial sequences (blocks of the data bit sequence) independently of one another).
• Arrangement of the sequences of the systematic bits (for example blocks of systematic bits) of the coded data bit partial sequences in such a way that their entire sequence is identical to the entire uncoded data bit sequence (for example data bit sequence).
• - Arrangement of the parity bits (eg blocks of error correction bits) of the coded data bit partial sequences in such a way that
  • o at least the parity bit sequence (e.g. block of error correction bits) belonging to the first data bit partial sequence (e.g. first block of the data bit sequence) directly adjoins a reference sequence (preamble or additional reference sequence, see Section 1), and
  • o the parity bit sequences (e.g. blocks of error correction bits) directly adjoining one another in consecutive data bit partial sequences (e.g. blocks of the data bit sequence) or there are only additional reference sequences between them (see e.g. 11 , 12th and 13th ).
• - Subdivision of the parity bit sequences into several (e.g. two) parity bit partial sequences (e.g. blocks of error correction bits), with the parity bit partial sequences of directly successive data bit partial sequences (e.g. blocks of the data bit sequence) directly adjacent to one another or only additional reference sequences between them are located (see 14th and 15th ).
• - Insertion of additional reference sequences (e.g. sequences of additional reference bits) between the two parity bit partial sequences (e.g. blocks of error correction bits) of a coded data bit partial sequence, the number of additional reference sequences corresponding to the number of data bit partial sequences (e.g. blocks of the data bit sequence) (please refer 16 ). The exact arrangement of the parity bit partial sequences relative to one another is arbitrary, since each of them is always directly adjacent to an additional reference sequence. For fading channels an arrangement is advantageous in which the two parity bit partial sequences "a" (e.g. blocks of error correction bits with odd indices) and "b" (e.g. blocks of error correction bits with even indices) (which each belong to the same coded data bit partial sequence) be positioned as far apart from each other as possible.
• - Arrangement of the parity bit partial sequences (e.g. blocks of error correction bits) belonging to a data bit partial sequence (e.g. block of the data bit sequence) in such a way that each of these parity bit partial sequences is linked either to an additional reference sequence (e.g. sequence of additional reference bits) or to any (any) Parity bit partial sequence directly adjoins one of the data bit partial sequences preceding (the data bit partial sequence under consideration) (see e.g. 17th and 18th ).

Interleaver design that enables iterative decoder-supported channel tracking

In section 2 the data bits to be transmitted (e.g. data bit sequence 202 ) divided into data bit partial sequences (e.g. blocks). Their coding takes place in blocks and independently from block to block.

In the case of transmission channels that change very quickly, for example high mobility with a large Doppler spread, the coherence time of the radio channel is correspondingly short, so that very short block lengths would be required for a sufficiently frequent update of the channel estimate. In practice, however, the block length cannot be reduced at will because, on the one hand, with many common coding methods, each block is independent of its length In each case a fixed number of so-called tail bits (end bits) are to be added, whereby with decreasing block length the relative additional transmission effort due to a large number of tail bits increases in a disadvantageous manner. Furthermore, in the case of many codes, the power efficiency continues to decrease in the case of short block lengths, which reduces the coding gain.

For channels that change very quickly, it can therefore be more advantageous to use the data to be transmitted (= data bit sequence 202 ) to encode as an entire sequence (not divided into sub-blocks) and to interleave the encoded bits in such a way that a decoder-supported, iterative channel estimation can take place in the receiver. The decoder-supported, iterative channel estimation is described in detail in [4], for example, and is not detailed here. The decisive aspect is that the iterations take place with an update of the channel estimate within the coded block, in that iterative partial decodings of the data bit sequence are (can) carried out in the receiver.

• - die Codierung der Datenbitsequenz (z.B. Datenbitfolge 202) erfolgt dergestalt, dass dabei systematische Bits generiert werden und diese in unveränderter Reihenfolge nach den Referenzbits 201 übertragen werden (Anforderung der Rückwärtskompatibilität),
• - nur die Paritätsbits (welche z.B. nach den systematischen Bits übertragen werden) einer Verschachtelung unterzogen werden.

The exemplary embodiments described below thus basically follow the illustration according to FIG 5 , ie

• - the coding of the data bit sequence (e.g. data bit sequence 202 ) takes place in such a way that systematic bits are generated and these in an unchanged order after the reference bits 201 are transmitted (requirement of backward compatibility),
• - only the parity bits (which are transmitted after the systematic bits, for example) are interleaved.

In the previous exemplary embodiments, no special requirements were placed on the interleaving, which are related to a continuous update of the channel estimate. In contrast to this, features for the interleaving are specified in the following for exemplary embodiments which enable decoder-supported, iterative channel estimation on the receiver side.

First, requirements for a coding are described, which basically enable the use of decoder-supported, iterative channel estimation. In the following, only the parity bits (redundancy bits) are considered, since the systematic bits are defined by the condition of backward compatibility without a degree of freedom and interleaving is not permitted for them.

19th FIG. 11 shows a schematic view of an iterative forward error correction coding of a data bit sequence. After a coding step s, where s is a natural number greater than or equal to one, s ≥ 1, n _{s are} bits of the data bit sequence 202 already coded so that m _s n coded bits for the _s bits of the data bit 202 are present. After a further coding step s + 1, n are _{s + 1} bits of the data bit sequence 202 already coded so that m _s + C _{s + 1} coded bits for the n _{s + 1} bits of the data bit sequence 202 are present. During the further coding step s + 1, a group 310 _{s + 1} of C _{s + 1} error correction bits is accordingly generated.

In other words, it becomes a data bit sequence (e.g. data bit sequence 202 ) consisting of N bits. For an arbitrarily selectable step s of the coding process, a contiguous partial sequence beginning with the first data bit and having the length n _s <N bits is coded and from this a contiguous coded bit sequence ("parity bit group") of length m _s <M (M = number of Parity bits) have been generated. In the following step s + 1 of the coding process, D further data bits of the data bit sequence are coded (D≥1), so that n _{s + 1} = n _s + D (with n _{s + 1} N). In the course of the coding, a group of C _{s + 1} new (coded) parity bits is generated, ie m _{s + 1} = m _s + C _s + ₁ (m _{s + 1} M). The coding requirement is that the groups (310 _{s + 1} ) of C _{s + 1 parity bits newly generated from step s to s + 1 depend exclusively on the connected n s + 1} data bits that have been processed as a whole, as shown in FIG 19th is shown.

The coding requirement mentioned furthermore includes that, at the receiver end, partial decoding of the first n _s data bits in each time step s is possible with a coding gain if at least m _s coded parity bits and n _s systematic bits have been estimated in the receiver. An improvement in the performance can possibly be achieved if in the receiver m _{s, dec} > m _s coded parity bits can be estimated. The requirements mentioned can be met, for example, by the group of convolutional codes and by the group of LDPC codes.

Nesting / interleaving

The exemplary embodiment described here relates to the design of the interleaver in such a way that iterative decoder-supported decoding in the receiver is possible. _{For this purpose, the nesting of the group of C s} parity bits (e.g. error correction bits) generated in the coding in step s (with s> 1) is arranged for the transmission in such a way that it is directly linked to the group with C _{s generated in the previous step s-1 -1} parity bits (e.g. error correction bits) can be added. For s = 1, i.e. the first step of the coding process, the first group of the generated parity bits is positioned directly adjacent to an additional reference sequence.

20th shows a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.

As in 20th can be seen, lie after the iterative coding process (not shown in FIG 20th , see e.g. 19th ) of the data bit sequence groups 310_1 , 310_2 , 310_3 of error correction bits generated in successive steps of the iterative forward error correction coding. Optionally, the error correction bits of the groups 310_1 , 310_2 , 310_3 error correction bits are each nested within a group (ie not across groups) in a step 380 and are then introduced into the second transmission bit block.

As in 20th is shown according to an embodiment, in the second transmission bit block 300 the groups 310_1 , 310_2 , 310_3 of error correction bits can be arranged in such a way that a group of error correction bits, which were generated in a first step of the iterative forward error correction coding, are immediately adjacent to the sequence 320 of additional reference bits can be arranged, with a second group of 310_2 of error correction bits which were generated in a second step of the iterative forward error correction coding, immediately adjacent to the first group 310_1 of error correction bits can be arranged, with a third group of 310_3 of error correction bits which were generated in a third step of the iterative forward error correction coding, immediately adjacent to the second group 310_2 of error correction bits can be arranged.

The first send bit block 200 Due to the required backward compatibility, its structure naturally corresponds to the first send bit block from the previous exemplary embodiments (see e.g. 8th , 11-18 ).

In other words, 20th shows an exemplary embodiment for the case of groups of three, ie C _s = 3 (s = 1, 2, 3, ...), and the insertion of an additional reference sequence (for example a sequence of additional reference bits). The digits describe the indices of the parity bits (eg error correction bits). In the illustrated embodiment, the interleaving is de facto omitted (ie the input and output sequence of the interleaver are identical) and the parity bits (eg error correction bits) are added directly to the preceding, additional reference sequence after coding in the same order. Since a single coding _{step generates a group of C s} = 3 parity bits, these can be interchanged as required within the groups of three by an interleaver. Instead of the in 20th The sequence shown as an example {1,2,3, 4,5,6, 7,8,9, ...}, an interleaver can also have a different index sequence, such as the index sequence {3,2,1, 6 , 5,4, 9,8,7, ...}, without reducing the performance of the iterative channel tracking.

According to a further exemplary embodiment, the order of the parity bits can be reversed by the interleaver if the additional reference sequence (eg sequence 320 of additional reference bits) is located at the end of the transmitted bits, as shown in 21 is shown.

Shows in detail 21 shows a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence. In contrast to 20th is the consequence 320 of additional reference bits at one end of the second transmit bit block 300 brought into the same. The order in which the groups are set changes accordingly 310_1 , 310_2 and 310_3 of error correction bits in the second transmit bit block 300 are arranged.

In other words, 21 shows an alternative interleaving for the case of an additional reference sequence at the end of the transmitted bits, C = 3. In the embodiment according to 21 if the interleaver reverses the order of the parity bits, since the additional reference sequence (e.g. sequence 320 of additional reference bits), from which the channel estimation for the range of parity bits starts in the receiver, is located at the end of the transmitted bits. Here too, as explained for the previous exemplary embodiment, the order of the bits within the respective groups of three can additionally be selected as desired by the interleaver, without reducing the performance of the iterative channel tracking.

For the two exemplary embodiments 20th and 21 the essential feature of the nesting can be seen that the C _s = 3 parity bits of a (three) group "s" (310 _s ) directly to the previous and / or following group of three "s-1" (310 _s-1 ) or . "S + 1" (310 _{s + 1} ) is adjacent. The first group 310_1 can be an additional reference sequence (e.g. sequence 320 of additional reference bits) must be directly adjacent.

Insertion of several additional reference sequences with cancellation of the parity bit grouping

If several additional reference sequences (e.g. sequences of additional Reference bits), the grouping of the parity bits (eg error correction bits), ie the coherent arrangement of _{parity bits grouped by C s} from the coding step “s”, can be canceled by the interleaver. In order to take advantage of time diversity, it is advisable to separate the bits belonging to a parity bit group as far as possible from one another in terms of time in order to increase the system's ability to bridge deep fades and thus improve transmission reliability . 22nd shows in one embodiment the arrangement of the parity bits made by means of the interleaver in the bit sequence to be transmitted for the case of two additional reference sequences and a group length of C _s = 4 parity bits per coding step.

Shows in detail 22nd a schematic view of a generation of a transmission bit sequence to be transmitted with additional error correction bits which are based on an iterative forward error correction (coding), the transmission bit sequence being backwards compatible with an uncoded transmission bit sequence.

As in 22nd can be seen, lie after the iterative coding process (not shown in FIG 22nd , see e.g. 19th ) of the data bit sequence groups 310_1 and 310_2 of error correction bits generated in successive steps of the iterative forward error correction coding. Optionally, the error correction bits of the groups 310_1 and 310_2 of error correction bits are interleaved within the respective group in a step 380 and then introduced into the second transmission bit block.

As in 22nd is shown according to an embodiment, in the second transmission bit block 300 Error correction bits of a group of error correction bits that were generated in a first step of the iterative forward error correction coding, each immediately adjacent to a respective sequence 320_1 and 320_2 of additional reference bits, with error correction bits of a second group of 310_2 of error correction bits generated in a second step of the iterative forward error correction coding can each be arranged immediately adjacent to one of the error correction bits of the group of error correction bits generated in a first step of the iterative forward error correction coding.

For example, the groups 310_1 and 310_2 of error correction bits each have four error correction bits, as shown in FIG 22nd is indicated. In this case, two error correction bits of the first group can be used 310_1 of error correction bits immediately adjacent to one of two sequences 320_1 be arranged by additional reference bits, with one error correction bit of the second group 310_1 of error correction bits immediately adjacent to each error correction bit of the first group 310_1 of error correction bits can be arranged.

In other words, the arrangement of the four parity bits (in the example) per parity bit group is advantageously carried out in the exemplary embodiment before and after each of the two additional reference sequences (for example, sequences 320_1 and 320_2 of additional reference bits). The sequence of the groups, ie s = 1, s = 2 etc., is here with regard to the additional reference sequences from “inside” to “outside”, ie the bits of the first parity bit group (s = 1) are closest to the additional reference sequences . This is followed by the bits of the second parity bit group (s = 2) etc. Here, too, the bits within each parity bit group can be arranged as desired by the interleaver.

In embodiments, during interleaving, the parity bits (e.g. error correction bits) of a group (of error correction bits) can be arranged in such a way that each of these parity bits (e.g. error correction bits) is either connected to any additional reference sequence (e.g. sequence of additional reference bits) or to a any other parity bit (e.g. error correction bit) of the same group (of error correction bits) or to any parity bit (e.g. error correction bit) from a parity bit group (e.g. group of error correction bits) generated in a previous coding step.

Of course, this concept can be applied in an equivalent manner for different values of C (group size) and different numbers of additional reference sequences.

In embodiments, one of the in 1 shown data sender, e.g. the data sender 100_1 , be configured to based on the data bit sequence 202 perform forward error correction coding to a sequence 304 of systematic bits and the sequence 304 error correction bits assigned by systematic bits 310 to get, with the data bit sequence 202 and the consequence 304 of systematic bits are identical, the data transmitter is configured to send a signal 120 send out, taking the signal 120 a first send bit block 200 and a second transmit bit block 300 having, the first transmission bit block 200 one episode 201 of reference bits and the sequence 304 of systematic bits, and wherein the second transmission bit block 300 the error correction bits 310 having a block of systematic bits from the sequence 304 of systematic bits together with one of the block of systematic bits assigned group of error correction bits from the sequence of error correction bits can be decoded, independently of other error correction bits or other groups of error correction bits.

In embodiments, the in 1 The data receiver shown can be configured to receive a signal 120 to receive the a first transmission bit block 200 and a second transmit bit block 300 having, the first transmission bit block 200 one episode 201 of reference bits and a sequence 304 of systematic bits, the sequence of systematic bits 304 identical to a data bit sequence to be transmitted with the signal 202 is, where the second transmission bit block 300 the consequence 304 error correction bits assigned by systematic bits 310 having, the data receiver 110 is configured to based on the received sequence 201 of reference bits to perform a channel estimation, the data receiver 110 is configured to have a sequence containing a received block of systematic bits of the received sequence 304 of systematic bits and at least one group of error correction bits of the received sequence of error correction bits, which is assigned to the received block of systematic bits, independently of other received error correction bits or received groups of error correction bits to be decoded in order to obtain a block of the data bit sequence, the Data recipient 110 is configured to perform forward error coding based on the block of the data bit sequence in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits associated with the reencoded block of systematic bits, the data receiver being configured to track the channel estimate based on the reencoded block of systematic bits and the reencoded group of error correction bits.

• - Bereitstellen eines Interleavers (z.B. Paritätsbit-Interleaver) der so gestaltet ist, dass im Empfänger eine iterative decodergestützte Kanalnachführung durchführbar ist. Voraussetzung ist eine dafür geeignete Codierung.
• - Schrittweise Durchführung der Codierung der Datenbits (z.B. Datenbitfolge), so dass in jedem Codierschritt Gruppen von Paritätsbits (z.B. Fehlerkorrekturbits) (Gruppengröße:
  • mindestens 1 Bit) entstehen.
  • o Variante 1: Anordnung unter Beibehaltung der Gruppierung. Die Gruppen von Fehlerkorrekturbits können so angeordnet werden, dass eine in einem Schritt erzeugte Gruppe von Fehlerkorrekturbits jeweils entweder an eine zusätzliche Referenzsequenz (z.B. Folge von zusätzlichen Referenzbits) oder an die im vorherigen Codierungsschritt erzeugte Gruppe von Fehlerkorrekturbits direkt angrenzt (siehe z.B. 20 und 21).
  • o Variante 2: Anordnung ohne Beibehaltung der Gruppierung. Die zusammenhängende Anordnung der Fehlerkorrekturbits innerhalb einer Gruppe von Fehlerkorrekturbits kann aufgehoben werden. Die Paritätsbits einer Gruppe werden so angeordnet, dass jedes dieser Paritätsbits entweder an eine beliebige zusätzliche Referenzsequenz (z.B. Folge von zusätzlichen Referenzbits) oder an ein beliebiges anderes Fehlerkorrekturbit derselben Gruppe von Fehlerkorrekturbits oder an ein beliebiges Fehlerkorrekturbit aus einer in einem vorherigen Codierungsschritt erzeugten Gruppe von Fehlerkorrekturbits angrenzt (siehe z.B. 22).
• - Die Positionen der Paritätsbits (z.B. Fehlerkorrekturbits) innerhalb jeder Paritätsbit-Gruppe sind jeweils beliebig vertauschbar.

In embodiments, a transmission bit sequence to be transmitted [for example with a first transmission bit block, which is backward compatible with an "existing" communication system (or communication protocol), and a second transmission bit block, which extends the "existing" communication system to include forward error correction], based on a or more of the following steps:

• - Provision of an interleaver (eg parity bit interleaver) which is designed in such a way that iterative decoder-supported channel tracking can be carried out in the receiver. A suitable coding is required.
• - Step-by-step implementation of the coding of the data bits (e.g. data bit sequence) so that groups of parity bits (e.g. error correction bits) (group size:
  • at least 1 bit).
  • o Variant 1: arrangement while maintaining the grouping. The groups of error correction bits can be arranged in such a way that a group of error correction bits generated in one step is either directly adjacent to an additional reference sequence (e.g. sequence of additional reference bits) or to the group of error correction bits generated in the previous coding step (see e.g. 20th and 21 ).
  • o Variant 2: arrangement without retaining the grouping. The contiguous arrangement of the error correction bits within a group of error correction bits can be canceled. The parity bits of a group are arranged in such a way that each of these parity bits is linked either to any additional reference sequence (e.g. sequence of additional reference bits) or to any other error correction bit of the same group of error correction bits or to any error correction bit from a group of error correction bits generated in a previous coding step adjoins (see e.g. 22nd ).
• - The positions of the parity bits (eg error correction bits) within each parity bit group can be interchanged as required.

Insertion of additional reference sequences in the area of the systematic bits

The preceding exemplary embodiments were based on the requirement that the first part of the transmitted bits (= first transmission bit block 200 ), comprising reference bits and data bits, should remain unchanged despite the addition of additionally transmitted parity bits. This was ensured by the fact that, with a suitable code, the systematic bits correspond to the original data bits.

If the above requirement is weakened to the effect that only the order of the systematic bits has to correspond to that of the data bits (e.g. data bit sequence), one or more additional reference sequences can be inserted into the area of the systematic bits after this weaker condition. For this purpose, the sequence of the systematic bits is divided into two or more partial sequences and one or more additional reference sequences are inserted between them. The area of the parity bits is unaffected by this measure and can advantageously be designed in accordance with the ideas described above. Through the The channel estimation can be improved there by inserting additional reference sequences in the area of the systematic bits.

23 shows a schematic view of a generation of a transmission bit sequence to be transmitted with error correction bits which are based on forward error correction (coding). In a first step 302 can be based on the data bit sequence 202 , a forward error correction (coding) can be performed to a sequence 304 of systematic bits and one of the sequence 304 sequence assigned by systematic bits 306 of error correction bits (e.g. parity bits). The consequence 304 of systematic bits is here identical to the data bit sequence 202 . In a second step 308 can result in nesting 306 of error correction bits are carried out to produce a sequence 310 from nested error correction bits (e.g. parity bits). In a third step 312 can be a consequence 321 of additional reference bits between the sequence 304 of systematic bits are introduced, so that the consequence 304 of systematic bits is interrupted by the sequence of additional reference bits, so that a first part 305_1 the consequence 304 of systematic bits before the sequence 321 of additional reference bits is arranged and a second part 305_2 the sequence of systematic bits after the sequence 321 is arranged by additional reference bits.

The first send bit block 200 the transmission bit sequence to be transmitted therefore includes the sequence 201 of reference bits, the result 321 of further reference bits and those through the sequence 321 sequence divided into two by further reference bits 304 of systematic bits. The second send bit block 300 the transmission bit sequence to be transmitted comprises the sequence 310 of interleaved error correction bits and optionally one or more sequences of additional reference bits.

In other words, 23 shows an example of the insertion of an additional reference sequence in the area of the systematic bits.

In embodiments, one of the in 1 shown data sender, e.g. the data sender 100_1 , be configured to based on the data bit sequence 202 perform forward error correction coding to a sequence 304 of systematic bits and the sequence 304 error correction bits assigned by systematic bits 310 to get, with the data bit sequence 202 and the consequence 304 of systematic bits are identical, the data transmitter is configured to send a signal 120 send out, taking the signal 120 a first send bit block 200 and a second transmit bit block 300 having, the first transmission bit block 200 a first episode 201 of reference bits, the result 304 of systematic bits and a second sequence 321 of reference bits, the sequence 304 of systematic bits through the second sequence 321 is interrupted by reference bits, so that a first part 305_1 the consequence 304 of systematic bits is arranged before the second sequence of reference bits and a second part 304_2 the sequence of systematic bits is arranged [eg in time] after that of the second sequence of reference bits, the second transmission bit block 300 the error correction bits 310 wherein a block of systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the sequence of error correction bits, which is assigned to the block of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits.

In embodiments, one or more additional reference sequences (e.g. sequences of additional reference bits) can be inserted into the area of the systematic bits.

In embodiments, the order of the systematic bits can be retained (apart from the inserts).

In the case of exemplary embodiments, the exemplary embodiments described in the other sections can be used in the area of the parity bits (e.g. error correction bits) regardless of this.

Further embodiments

24 FIG. 6 shows a flow diagram of a method 600 for sending a signal. The method 600 comprises a step 602 of obtaining a data bit sequence. The method 600 further comprises a step 604 of performing, based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and the sequence of systematic bits assigned error correction bits [eg M error correction bits], the data bit sequence and the Sequence of systematic bits are identical. The method 600 further comprises a step 606 of transmitting a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and the sequence of systematic bits, and the second transmission bit block has the error correction bits, a block of [e.g. contiguous] systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the error correction bits, which is assigned to the block of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits is.

25th shows a flow diagram of a method 620 to send a signal. The procedure 620 includes one step 622 of obtaining a data bit sequence. The method also includes 620 one step 624 of carrying out, based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits [e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical. The method also includes 620 one step 626 the transmission of a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and the sequence of systematic bits [eg known to a data receiver], and the second transmission bit block having the error correction bits, a Block of [eg contiguous] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits can be decoded from the error correction bits, independently of other error correction bits or other groups of error correction bits.

26th shows a flow diagram of a method 640 to send a signal. The procedure 640 includes one step 642 of obtaining a data bit sequence. The method also includes 640 one step 644 of carrying out, based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits [e.g. M error correction bits], the data bit sequence and the sequence of systematic bits being identical. The method also includes 640 one step 646 transmitting a signal, the signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits being replaced by the second sequence is interrupted by reference bits, so that a first part of the sequence of systematic bits [e.g. temporally] is arranged before the second sequence of reference bits and a second part of the sequence of systematic bits [e.g. temporally] is arranged after that of the second sequence of reference bits, wherein the second transmission bit block has the error correction bits, wherein a block of [e.g. contiguous] systematic bits from the sequence of systematic bits together with a group of error correction bits assigned to the block of systematic bits can be decoded from the error correction bits, independently of other error correction bits or other groups of Error corr ekturbits.

27 shows a flow diagram of a method 700 to receive a signal. The procedure 700 includes one step 702 receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to a data bit sequence to be transmitted with the signal, the second transmission bit block of the sequence of systematic bits assigned to error correction bits. The method also includes 700 one step 704 performing a channel estimation based on the received sequence of reference bits. The method also includes 700 a step of decoding 706 a sequence comprising a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits associated with the received block of systematic bits, independently of other received error correction bits or received blocks of error correction bits to obtain a block of the data bit sequence. The method also includes 700 one step 708 performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and at least one reencoded block of systematic bits and error correction bits assigned to the reencoded block of systematic bits. The method also includes 700 one step 710 tracking the channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits.

28 shows a flow diagram of a method 720 to receive a signal. The procedure 720 includes one step 722 receiving a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to a data bit sequence to be transmitted with the signal, the second transmission bit block of the sequence of systematic bits assigned to error correction bits. The method also includes 720 a step of performing 724 a channel estimate based on the received sequence of reference bits. The method also includes 720 one step 726 of decoding a sequence which comprises a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits that is assigned to the received block of systematic bits, independent of other received error correction bits or groups of error correction bits received in order to obtain a block of the data bit sequence. The method also includes 720 one step 728 performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits. The method also includes 720 one step 730 tracking the channel estimate based on the reencoded block of systematic bits and the reencoded group of error correction bits.

29 shows a flow diagram of a method 740 to receive a signal. The procedure 740 includes one step 742 receiving a signal having a first transmit bit block and a second transmit bit block, the first transmit bit block having a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits being replaced by the second sequence of reference bits is interrupted, so that a first part of the sequence of systematic bits [eg temporally] is arranged before the second sequence of reference bits and a second part of the sequence of systematic bits [eg temporally] is arranged after that of the second sequence of reference bits, the second transmission bit block has the error correction bits. The method also includes 740 one step 744 performing a channel estimation based on the received first sequence of reference bits and the received second sequence of reference bits. The method also includes 740 one step 746 of decoding a sequence which comprises a received block of [e.g. contiguous] systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits that is assigned to the received block of systematic bits, independent of other received error correction bits or groups of error correction bits received in order to obtain a block of the data bit sequence. The method also includes 740 one step 748 performing, based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits. The method also includes 740 one step 750 tracking the channel estimate based on the reencoded block of systematic bits and the reencoded group of error correction bits.

• - ein potentiell zeitvarianter Übertragungskanal zwischen Sender und Empfänger vorliegt,
• - eine Aktualisierung der Schätzung dieses Kanals innerhalb eines übertragenen Datenpakets erforderlich oder vorteilhaft ist, insbesondere bei kohärenter Demodulation,
• - eine Codierung als Vorwärts-Fehlerkorrektur zum Einsatz kommt, welche u.a. sog. systematische Bits ausgibt (z.B. Turbo-Codes, LDPC-Codes), und/oder
• - eine Rückwärtskompatibilität eines Teils der zu übertragenen Daten zu einer uncodierten Übertragung (ohne Vorwärts-Fehlerkorrektur) gefordert wird.

Embodiments of the present invention are used in a system for the packet-wise transmission of data from a transmitter to a receiver. The concepts described herein apply to any transmission in which

• - there is a potentially time-variant transmission channel between sender and receiver,
• - an update of the estimate of this channel within a transmitted data packet is necessary or advantageous, in particular in the case of coherent demodulation,
• - A coding is used as forward error correction, which among other things outputs so-called systematic bits (eg turbo codes, LDPC codes), and / or
• - A backward compatibility of part of the data to be transmitted with an uncoded transmission (without forward error correction) is required.

A typical area of application is, for example, the transmission of a message in a digital radio communication system in which the transmission channel can be time-variant due to the movement of the transmitter and / or receiver and / or due to a frequency offset between the transmitter and receiver and in which, e.g. by using coherent demodulation, a ongoing estimation of the transmission channel is required.

Embodiments modify an existing transmission system, which so far has worked comparatively inefficiently without coding the data bits, through the use of turbo or LDPC codes, for example, so that the efficiency of the transmission system can be increased considerably. Additional redundancy information (parity bits) is transmitted, which, for reasons of backward compatibility, is sent after the bit sequence generated by the original system, for example. This means that "old devices" that are already in circulation can continue to receive the signals generated by the new process unchanged and unimpaired, while devices that are newly in circulation in the same system can take advantage of the high transmission efficiency, e.g. through turbo or LDPC coding. The focus here is not on the coding as such, but on the introduction of additional reference sequences on the one hand and the advantageous division of the data bit sequence to be transmitted and the appropriate arrangement of the coded bits on the other. Both measures serve to enable an update of the channel estimation within a data packet, without which a meaningful use of the above-mentioned coding method is not practical.

• 1.) die Aktualisierung der Kanalschätzung (Kanalnachführung) innerhalb von Datenpaketen und somit den Einsatz von z.B. Turbo- oder LDPC-Codes ermöglichen, wobei
• 2.) hinsichtlich eines ersten Teils der übertragenen Daten Rückwärtskompatibilität zu einer uncodierten Übertragung gewahrt bleibt.

Embodiments create data transmitters, data receivers, a communication system and corresponding methods, which

• 1.) enable the updating of the channel estimation (channel tracking) within data packets and thus the use of turbo or LDPC codes, for example, whereby
• 2.) With regard to a first part of the transmitted data, backward compatibility with an uncoded transmission is maintained.

Exemplary embodiments deal with measures in the transmission of data in a digital transmission system which enable channel tracking when time-variant transmission channels are present.

Although some aspects have been described in connection with a device, it goes without saying that these aspects also represent a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Analogously to this, aspects that have been described in connection with or as a method step also represent a description of a corresponding block or details or features of a corresponding device. Some or all of the method steps can be performed by a hardware device (or using a hardware Apparatus), such as a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some or more of the most important process steps can be performed by such an apparatus.

Depending on the specific implementation requirements, embodiments of the invention can be implemented in hardware or in software. The implementation can be carried out using a digital storage medium such as a floppy disk, a DVD, a Blu-ray disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or other magnetic memory or optical memory are carried out on the electronically readable control signals are stored, which can interact with a programmable computer system or cooperate in such a way that the respective method is carried out. Therefore, the digital storage medium can be computer readable.

Some exemplary embodiments according to the invention thus include a data carrier which has electronically readable control signals which are capable of interacting with a programmable computer system in such a way that one of the methods described herein is carried out.

In general, exemplary embodiments of the present invention can be implemented as a computer program product with a program code, the program code being effective to carry out one of the methods when the computer program product runs on a computer.

The program code can, for example, also be stored on a machine-readable carrier.

Other exemplary embodiments include the computer program for performing one of the methods described herein, the computer program being stored on a machine-readable carrier.

In other words, an exemplary embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer.

A further exemplary embodiment of the method according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the methods described herein is recorded. The data carrier, the digital storage medium or the computer-readable medium are typically tangible and / or non-perishable or non-transitory.

A further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents or represents the computer program for performing one of the methods described herein. The data stream or the sequence of signals can, for example, be configured to be transferred via a data communication connection, for example via the Internet.

Another exemplary embodiment comprises a processing device, for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.

Another exemplary embodiment comprises a computer on which the computer program for performing one of the methods described herein is installed.

Another embodiment according to the invention comprises a device or a System that is designed to transmit a computer program for performing at least one of the methods described herein to a receiver. The transmission can take place electronically or optically, for example. The receiver can be, for example, a computer, a mobile device, a storage device or a similar device. The device or the system can, for example, comprise a file server for transmitting the computer program to the recipient.

In some exemplary embodiments, a programmable logic component (for example a field-programmable gate array, an FPGA) can be used to carry out some or all of the functionalities of the methods described herein. In some exemplary embodiments, a field-programmable gate array can interact with a microprocessor in order to carry out one of the methods described herein. In general, in some exemplary embodiments, the methods are performed by any hardware device. This can be universally applicable hardware such as a computer processor (CPU) or hardware specific to the method such as an ASIC.

The devices described herein can be implemented, for example, using a hardware apparatus, or using a computer, or using a combination of a hardware apparatus and a computer.

The devices described herein, or any components of the devices described herein, can be implemented at least partially in hardware and / or in software (computer program).

For example, the methods described herein can be implemented using hardware apparatus, or using a computer, or using a combination of hardware apparatus and a computer.

The methods described herein, or any components of the methods described herein, can be carried out at least in part by hardware and / or by software.

The embodiments described above are merely illustrative of the principles of the present invention. It is to be understood that modifications and variations of the arrangements and details described herein will be apparent to other skilled persons. It is therefore intended that the invention be limited only by the scope of protection of the following patent claims and not by the specific details presented herein with reference to the description and explanation of the exemplary embodiments.

List of reference symbols

CRC

Cyclic Redundancy Check

FEC

Forward Error Correction

LLR

Log likelihood ratio

bibliography

• [1] Wireless M-Bus, European standard EN 13757
• [2] Berrou, C., Glavieux, A., Thitimajshima, P .: "Near Shannon limit error correcting coding and decoding", Proc. IEEE Intern. Conf. on Communications, Geneva, Switzerland, May 1993, 1064-1070 .
• [3] Karl-Dirk Kammeyer, "News Transfer", 3rd edition, BG Teubner Verlag, Stuttgart 2004 .
• [4] DE 102018206132 A1
• [5] EP 3 072 308 B1

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• DE 102018206132 A1 [0267]
• EP 3072308 B1 [0267]

Non-patent literature cited

• Standard EN 13757 [0013]
• Standard DIN EN 13757-4 [0013]
• EN 13757 [0267]
• Berrou, C., Glavieux, A., Thitimajshima, P .: "Near Shannon limit error correcting coding and decoding", Proc. IEEE Intern. Conf. on Communications, Geneva, Switzerland, May 1993, 1064-1070 [0267]
• Karl-Dirk Kammeyer, "News Transfer", 3rd edition, B.G. Teubner Verlag, Stuttgart 2004 [0267]

Claims (63)

Data transmitter (100_1) of a communication system, wherein the data transmitter (100_1) is configured to receive a data bit sequence (202), wherein the data transmitter (100_1) is configured to perform forward error correction coding based on the data bit sequence (202) to obtain a sequence (304) of systematic bits and error correction bits (310) associated with the sequence (304) of systematic bits , the data bit sequence (202) and the sequence (304) of systematic bits being identical, wherein the data transmitter (100_1) is configured to transmit a signal (120), the signal (120) having a first transmission bit block (200) and a second transmission bit block (300), wherein the first transmission bit block (200) comprises a sequence (201) of reference bits and the sequence (304) of systematic bits, and wherein the second transmission bit block (300) comprises the error correction bits (310), wherein a block (304_1) of systematic bits of the sequence (304) of systematic bits together with at least one block (310_1; 310_1-310_2) of contiguous error correction bits of the error correction bits (310) which is assigned to the block (304_1) of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits. Data transmitter (100_1) according to the preceding claim, wherein the block (304_1) of systematic bits comprises a real subset of the systematic bits of the sequence (304) of systematic bits, and / or wherein the at least one block (310_1; 310_1-310_2) of contiguous error correction bits each comprises a real subset of the error correction bits (310). Data transmitter (100_1) according to one of the preceding claims, wherein the data transmitter (100_1) is configured to accept the sequence (304) of systematic bits in the order unchanged and coherent in the first transmission bit block (200). Data transmitter (100_1) according to one of the preceding claims, wherein the data transmitter (100_1) knows the sequence (201) of reference bits, the data transmitter (100_1) being configured to transmit the sequence (201) of reference bits unchanged and contiguous in the sequence to take over the first transmission bit block (200). Data transmitter (100_1) according to one of the preceding claims, wherein the first transmission bit block (200) is constructed in accordance with a communication protocol or communication standard. Data sender (100_1) Claim 5 wherein the first transmission bit block (200) can be received by a data receiver that operates in accordance with the communication protocol or communication standard, independently of the second transmission bit block (300). Data sender (100_1) Claim 5 or 6th , wherein the second transmission bit block (300) goes beyond the communication protocol or the communication standard. Data transmitter (100_1) according to one of the preceding claims, wherein the second transmission bit block (300) follows the first transmission bit block (200). Data transmitter (100_1) according to one of the preceding claims, wherein the first transmission bit block (200) and the second transmission bit block (300) are arranged directly adjacent to one another. Data transmitter (100_1) according to one of the preceding claims, wherein the forward error correction coding is turbo coding, LDPC coding or convolutional coding. Data transmitter (100_1) according to one of the preceding claims, wherein the second transmission bit block (300) has at least one sequence (320; 320_1-320_2) of additional reference bits. Data sender (100_1) Claim 11 , wherein a sequence (320; 320_1) of additional reference bits of the at least one sequence (320; 320_1-320_2) of additional reference bits is arranged in the second transmission bit block (300) so that the sequence (320; 320_1) of additional reference bits is adjacent is arranged to the first transmission bit block (200). Data transmitter (100_1) according to one of the preceding claims, wherein the data transmitter (100_1) is configured to carry out a first forward error correction coding for a first block (202_1) of the data bit sequence (202) in order to generate a first block (304_1) of systematic Bits and at least one block (310_1; 310_1-310_2) of contiguous error correction bits, which is assigned to the first block (304_1) of systematic bits, the data transmitter (100_1) being configured to provide a second forward error correction coding for to carry out a second block (202_2) of the data bit sequence (202) in order to carry out a second block (304_2) of systematic bits and at least one block (310_2; 310_3-310_4) of contiguous error correction bits, which is assigned to the second block (304_2) of systematic bits , to obtain, wherein the first forward error correction coding and the second forward error correction coding are performed independently of one another. Data sender (100_1) Claim 13 , wherein the data transmitter (100_1) is configured to take over the respective blocks (310_1-310_2; 310_1-310_4) of contiguous error correction bits in the order unchanged and contiguous in the second transmission bit block (300). Data sender (100_1) after one of the Claims 13 to 14th , the respective blocks (310_1-310 2; 310_1-310_4) of contiguous error correction bits not being interleaved, or wherein the respective blocks (310_1-310_2; 310_1-310_4) of contiguous error correction bits are each only interleaved, Data sender (100_1) after one of the Claims 13 to 15th , the second transmission bit block (300) having a sequence (320) of additional reference bits, the sequence (320) of additional reference bits being arranged directly adjacent to a block (304_1) of contiguous error correction bits which corresponds to a block (202_1) of the data bit sequence ( 202) is assigned, which is arranged at a start of the data bit sequence (202). Data sender (100_1) after one of the Claims 13 to 16 , wherein the data transmitter (100_1) is configured to carry out a third forward error correction coding for a third block (202_3) of the data bit sequence (202) to include a third block (304_3) of systematic bits and at least one block (310_3; 310_5 -310_6) of contiguous error correction bits, which is assigned to the third block (310_3) of systematic bits, the first forward error correction coding, the second forward error correction coding and the third forward error correction coding being carried out independently of one another blocks of contiguous error correction bits, which are assigned to immediately adjacent blocks of the data bit sequence (202), are arranged immediately adjacent or only with a block of reference bits in between in the second transmit bit block. Data sender (100_1) after one of the Claims 13 to 17th , the at least one block of contiguous error correction bits associated with the first block (304_1) of systematic bits being a first block (310_1) of contiguous error correction bits, the at least one block of contiguous error correction bits associated with the second block (304_2) of systematic bits is allocated, is a second block (310_2) of contiguous error correction bits. Data sender (100_1) after one of the Claims 13 to 17th , wherein the at least one block of contiguous error correction bits associated with the first block (304_1) of systematic bits comprises a first block (310_1) of contiguous error correction bits and a second block (310_2) of contiguous error correction bits, the at least one block of contiguous error correction bits associated with the second block (304_2) of systematic bits, a third block (310_3) of contiguous error correction bits and a fourth block (310_4) of contiguous error correction bits. Data sender (100_1) Claim 19 wherein in the second transmission bit block (300) blocks of contiguous error correction bits, which are assigned to immediately adjacent blocks of systematic bits, are arranged immediately adjacent or with only a block of reference bits in between in the second transmission bit block (300). Data sender (100_1) Claim 19 wherein a block of reference bits is arranged in the second transmission bit block (300) between blocks of contiguous error correction bits which are assigned to the same block of the data bit sequence (202). Data sender (100_1) Claim 19 In the second transmission bit block (300) the blocks of contiguous error correction bits assigned to a respective block of the data bit sequence (202) are arranged in such a way that each of these blocks of contiguous error correction bits is immediately adjacent to a sequence of additional reference bits or another block of contiguous error correction bits, which is assigned to a block of the data bit sequence (202) preceding the respective block of the data bit sequence (202). Data sender (100_1) Claim 19 , wherein the first block (310_1) of contiguous error correction bits in the second transmission bit block (300) is arranged directly adjacent to a first sequence (320_1) of additional reference bits, and wherein the third block (310_3) of contiguous error correction bits directly is arranged adjacent to the first block (310_1) of contiguous error correction bits, the second block (310_2) of contiguous error correction bits in the second transmission bit block (300) being arranged immediately adjacent to a second sequence (320_2) of additional reference bits, and the fourth Block (310_4) of contiguous error correction bits is arranged immediately adjacent to the second block (310_2) of contiguous error correction bits. Data sender (100_1) Claim 19 , wherein in the second transmission bit block (300) a sequence (320) of additional reference bits is arranged between the first block (310_1) of contiguous error correction bits and the second block (310_2) of contiguous error correction bits, the third block (310_3) of contiguous error correction bits is arranged directly adjacent to the first block (310_1) of contiguous error correction bits, the fourth block (310_4) of contiguous error correction bits being arranged directly adjacent to the second block (310_2) of contiguous error correction bits. Data sender (100_1) Claim 19 , wherein in the second transmission bit block (300) a first sequence (320_1) of additional reference bits between the first block (310_1) of contiguous error correction bits and the second block (310_2) of contiguous error correction bits is arranged, wherein in the second transmission bit block (300) a second sequence (320_2) of additional reference bits is arranged between the third block (310_3) of contiguous error correction bits and the fourth block (310_4) of contiguous error correction bits. Data sender (100_1) Claim 19 , the first block (310_1) of contiguous error correction bits and the second block (310_2) of contiguous error correction bits being arranged in the second transmission bit block (300) immediately adjacent to spaced-apart sequences (320_1, 320_2) of additional reference bits, wherein in the second transmission bit block (300) the third block (310_3) of contiguous error correction bits and the fourth block (310_4) of contiguous error correction bits are arranged directly adjacent to spaced-apart sequences (320_2, 320_3) of additional reference bits. Data transmitter (100_1) of a communication system, wherein the data transmitter (100_1) is configured to receive a data bit sequence (202), wherein the data transmitter (100_1) is configured to divide the data bit sequence (202) into at least two blocks (202_1, 202_2), wherein the data transmitter (100_1) is configured to carry out an independent forward error correction coding based on a respective block (202_1, 202_2) of the data bit sequence (202) in order to in each case a block (304_1, 304_2) of systematic bits and in each case at least one Block (310_1, 310_2; 310_1-310_2, 310_3-310_4) of contiguous error correction bits, which is assigned to the respective block (304_1, 304_2) of systematic bits, the respective block (304_1, 304_2) of systematic bits being identical to the respective block (202_1, 202_2) of the data bit sequence (202), wherein the data transmitter (100_1) is configured to transmit a signal (120), the signal having a first transmission bit block and a second transmission bit block, wherein the first transmission bit block comprises a sequence of reference bits and the data bit sequence (202) or a concatenated version of the respective blocks of systematic bits, the concatenated version of the respective blocks of systematic bits and the data bit sequence (202) being identical, wherein the second transmission bit block comprises the respective blocks of error correction bits. Data transmitter (100_1) of a communication system, wherein the data transmitter (100_1) is configured to receive a data bit sequence (202), wherein the data transmitter (100_1) is configured to perform forward error correction coding based on the data bit sequence (202) to obtain a sequence (304) of systematic bits and error correction bits (310) associated with the sequence (304) of systematic bits , the data bit sequence (202) and the sequence (304) of systematic bits being identical, wherein the data transmitter (100_1) is configured to transmit a signal (120), the signal (120) having a first transmission bit block (200) and a second transmission bit block (300), wherein the first transmission bit block (200) comprises a sequence (201) of reference bits and the sequence (304) of systematic bits, and wherein the second transmission bit block (300) comprises the error correction bits (310), wherein a block (304_1) of systematic bits from the sequence (304) of systematic bits together with a group (310_1), assigned to the block (304_1) of systematic bits, of error correction bits from the error correction bits (310) independently of other error correction bits or another group is decodable by error correction bits. Data sender (100_1) Claim 28 , wherein the block (304_1) of systematic bits comprises a real subset of the systematic bits of the sequence (304) of systematic bits, and / or wherein the at least one group (310_1) of error correction bits each comprises a real subset of the error correction bits (310). Data sender (100_1) after one of the Claims 28 to 29 , wherein the data transmitter (100_1) is configured to carry out the forward error correction coding step by step, so that in each step of the forward error correction coding a respective group (310_1, 310_2) of error correction bits of the error correction bits (310) is produced. Data sender (100_1) Claim 30 , wherein a block (304_1) of systematic bits of the sequence (304) of systematic bits can be decoded together with a first group (310_1) of error correction bits, which arises in a first step of the forward error correction coding, independently of another group of error correction bits that arise in one of the subsequent steps of forward error correction coding. Data sender (100_1) after one of the Claims 30 to 31 , groups (310_2) of error correction bits following the first group (310_1) of error correction bits, which arise in the steps of forward error correction coding following the first step of forward error correction coding, only together with groups (310_1) of error correction bits , which arose in the preceding steps of the forward error correction coding, and together with the respective groups (310_1) of error correction bits assigned blocks (304_1) of systematic bits can be decoded, independently of another group of error correction bits, which in one of the subsequent steps of the Forward error correction coding will arise. Data sender (100_1) after one of the Claims 28 to 32 , wherein the forward error correction coding is convolutional coding or LDPC coding. Data sender (100_1) after one of the Claims 28 to 33 , wherein in the second transmission bit block (300) a respective group (310_1, 310_2) of error correction bits is arranged adjacent to a sequence (320) of additional reference bits or adjacent to a group of error correction bits that are assigned to the step in which the respective Group of error correction bits was created, the immediately preceding step of forward error correction coding was created. Data sender (100_1) after one of the Claims 28 to 33 , wherein in the second transmission bit block (300) error correction bits of a respective group (310_1, 310_2) of error correction bits are arranged such that each of these error correction bits is immediately adjacent to reference bits or immediately adjacent to another error correction bit of the same group of error correction bits or immediately adjacent to an error correction bit Another group of error correction bits is arranged, which arose in a step of the forward error correction coding immediately preceding the step in which the respective group of error correction bits was created. Data transmitter (100_1) of a communication system, wherein the data transmitter (100_1) is configured to receive a data bit sequence (202), wherein the data transmitter (100_1) is configured to perform forward error correction coding based on the data bit sequence (202) to obtain a sequence (304) of systematic bits and error correction bits (310) associated with the sequence (304) of systematic bits , the data bit sequence (202) and the sequence (304) of systematic bits being identical, wherein the data transmitter (100_1) is configured to transmit a signal (120), the signal (120) having a first transmission bit block (200) and a second transmission bit block (300), the first transmission bit block (200) having a first sequence (201) of reference bits, the sequence (304) of systematic bits and a second sequence (321) of reference bits, the sequence (304) of systematic bits being replaced by the second sequence (321 ) is interrupted by reference bits, so that a first part (305_1) of the sequence (304) of systematic bits is arranged before the second sequence (321) of reference bits and a second part (305_2) of the sequence (304) of systematic bits is arranged after the the second sequence (321) of reference bits is arranged, wherein the second transmission bit block (300) comprises the error correction bits (310), wherein a block (304_1) of systematic bits of the sequence (304) of systematic bits together with at least one block (310_1; 310_1-310_2) of contiguous error correction bits of the error correction bits (310) which is assigned to the block (304_1) of systematic bits, can be decoded independently of other error correction bits or blocks of error correction bits. The data transmitter (100_1) according to the preceding claim, wherein the data transmitter (100_1) is configured to assign the respective parts (305_1,305_2) of the sequence (304) of systematic bits in the order unchanged and contiguous in the first transmission bit block (200) take. Data receiver (110) of a communication system, wherein the data receiver (110) is configured to receive a signal (120) having a first transmission bit block (200) and a second transmission bit block (300), the first transmission bit block (200) a sequence (201) of reference bits and a Sequence (304) of systematic bits, the sequence (304) of systematic bits being identical to a data bit sequence (202) to be transmitted with the signal, the second transmission bit block (300) of the sequence (304) of systematic bits associated with error correction bits ( 310), wherein the data receiver (110) is configured to carry out a channel estimation based on the received sequence of reference bits, wherein the data receiver (110) is configured to generate a sequence containing a received block of systematic bits of the received sequence of systematic Bits and at least one received block of contiguous error correction bits of the received error correction bits that correspond to the received block of systematisc hen bits are assigned, comprises decoding independently of other received error correction bits or received blocks of error correction bits in order to obtain a block of the data bit sequence, the data receiver (110) being configured to transmit a forward error for the block of the data bit sequence (202) -Coding to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits associated with the reencoded block of systematic bits, the data receiver (110) being configured to receive the channel estimate based on the reencoded block of systematic bits and the to track at least one reencoded block of error correction bits. Data receiver (110) of a communication system, wherein the data receiver (110) is configured to receive, in a first mode, a first signal having a first transmission bit block, the first transmission bit block having a sequence of reference bits and a data bit sequence, the data receiver (110) being configured in order to receive, in a second mode, a second signal (120) comprising a first transmission bit block (200) and a second transmission bit block (300), the first transmission bit block (200) being a sequence of reference bits and a sequence (304) of has systematic bits, the sequence (304) of systematic bits being identical to a data bit sequence (202) to be transmitted with the second signal (120), the second transmission bit block (300) of the sequence (304) of systematic bits assigned to error correction bits (310 ) having, wherein the data receiver (110) is configured to perform a channel estimation based on the received sequence of reference bits, wherein the data receiver (110) is configured to receive a sequence comprising a received block of systematic bits of the received sequence of systematic bits and at least one received block of contiguous error correction bits of the received error correction bits associated with the received block of systematic bits, to decode independently of other received error correction bits or received blocks of error correction bits in order to obtain a block of the data bit sequence, wherein the data receiver (110) is configured to carry out forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits assigned to the reencoded block of systematic bits, wherein the data receiver (110) is configured to track a channel estimate based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits. Data receiver (110) according to one of the Claims 38 to 39 wherein the received block of systematic bits comprises a real subset of the systematic bits of the received sequence of systematic bits, and / or wherein the at least one received block of contiguous error correction bits each comprises a real subset of the received error correction bits. Data receiver (110) according to one of the Claims 38 to 40 , wherein the first transmission bit block is structured according to a communication protocol or communication standard. Data receiver (110) Claim 41 , wherein the second transmission bit block goes beyond the communication protocol or the communication standard. Data receiver (110) according to one of the Claims 38 to 42 , the second transmission bit block following the first transmission bit block. Data receiver (110) according to one of the Claims 38 to 43 , wherein the first transmission bit block and the second transmission bit block are arranged immediately adjacent to one another. Data receiver (110) according to one of the Claims 38 to 44 , the forward error correction coding being turbo coding, LDPC coding or convolutional coding. Data receiver (110) according to one of the Claims 38 to 45 wherein the sequence of systematic bits comprises a first block of systematic bits and a second block of systematic bits, the error correction bits at least one block of contiguous error correction bits assigned to the first block of systematic bits and at least one block of contiguous error correction bits. Data receiver (110) Claim 46 wherein the second transmit bit block comprises at least one sequence of additional reference bits, wherein the data receiver (110) is configured to update or restart the channel estimation based on the sequence of additional reference bits, wherein the data receiver (110) is configured to perform the channel estimation based on at least one of the blocks of error correction bits which is arranged immediately adjacent to the sequence of additional reference bits, by decoding a sequence which includes the at least one of the blocks of error correction bits which is arranged immediately adjacent to the block of reference bits, and one of the blocks of the sequence of systematic bits, which is assigned to the at least one of the blocks of error correction bits which is arranged immediately adjacent to the block of reference bits, in order to obtain a respective block of the data bit sequence, Coding of the respective block of the D atenbitsequence in order to obtain a reencoded block of systematic bits and at least one reencoded block of error correction bits assigned to the reencoded block of systematic bits, using the reencoded block of systematic bits and the at least one reencoded block of error correction bits as reference bits for the channel estimation. Data receiver (110) of a communication system, wherein the data receiver (110) is configured to receive a signal (120) having a first transmission bit block (200) and a second transmission bit block (300), the first transmission bit block (200) a sequence (201) of reference bits and a Sequence (304) of systematic bits, the sequence (304) of systematic bits being identical to a data bit sequence (202) to be transmitted with the signal (120), the second transmission bit block (300) of the sequence (304) of systematic bits has associated error correction bits (310), wherein the data receiver (110) is configured to perform a channel estimation based on the received sequence of reference bits, wherein the data receiver (110) is configured to include a sequence comprising a received block of systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits associated with the received block of systematic bits, regardless of to decode other received error correction bits or received groups of error correction bits in order to obtain a block of the data bit sequence, wherein the data receiver (110) is configured to carry out forward error coding for the block of the data bit sequence in order to obtain a reencoded block of systematic bits and a reencoded group of error correction bits associated with the reencoded block of systematic bits, wherein the data receiver (110) is configured to track the channel estimate based on the reencoded group of systematic bits and the reencoded group of error correction bits. Communication system, with the following features: a data transmitter (100_1), according to one of the Claims 1 to 38 , and a data receiver (110) according to one of the Claims 39 to 48 . Communication system, having the following features: a first data transmitter which is configured to receive a data bit sequence and to transmit a first signal which has only a first transmission bit block, the first transmission bit block being a sequence of reference bits and the data bit sequence received from the first data transmitter having a second data transmitter (100_1) after one of the Claims 1 to 37 configured to transmit a second signal and a data receiver (110) according to one of the Claims 39 to 48 . Communication system according to Claim 50 , wherein the first data transmitter does not transmit a second transmission bit block with error correction bits for the received data bit sequence. Communication system according to Claim 50 or 51 , wherein the respective first transmission bit block is constructed according to a communication protocol or communication standard, wherein the second transmission bit block goes beyond the communication protocol or the communication standard. Communication system, with the following features: a first data transmitter which is configured to receive a data bit sequence and to transmit a first signal which has only a first transmission bit block, wherein the first transmission bit block comprises reference data and the data bit sequence received from the first data transmitter, to a second data transmitter (100_1) one of the Claims 1 to 38 configured to transmit a second signal, and a data receiver configured to receive the first signal and the second signal, the data receiver configured to process only the respective first transmit bit block to the respective data bit sequence receive. Communication system according to Claim 53 , wherein the second transmission bit block is not taken into account by the data receiver. Communication system according to Claim 53 or 54 , the data receiver operating in accordance with a communication protocol or communication standard, the respective first transmission bit block being structured in accordance with the communication protocol or communication standard, the second transmission bit block going beyond the communication protocol or the communication standard. Communication system according to one of the Claims 53 to 55 , wherein the data receiver is a first data receiver, wherein the communication system comprises a second data receiver (110) according to one of Claims 39 to 48 having. A method (600) for sending a signal, the method comprising: Obtaining (602) a data bit sequence, Carrying out (604), based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits, the data bit sequence and the sequence of systematic bits being identical, Sending (606) a signal, the signal having a first send bit block and a second send bit block, wherein the first transmission bit block comprises a sequence of reference bits and the sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of systematic bits of the sequence of systematic bits together with at least one block of contiguous error correction bits of the error correction bits which is assigned to the block of systematic bits can be decoded independently of other error correction bits or blocks of error correction bits. A method (620) for sending a signal, the method comprising: Obtaining (622) a data bit sequence, Carrying out (624), based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits, the data bit sequence and the sequence of systematic bits being identical, Transmitting (626) a signal, the signal having a first block of transmit bits and a second block of transmit bits, wherein the first transmission bit block comprises a sequence of reference bits and the sequence of systematic bits, and wherein the second transmission bit block comprises the error correction bits, wherein a block of systematic bits from the sequence of systematic bits can be decoded together with a group of error correction bits assigned to the block of systematic bits from the error correction bits, independently of other error correction bits or other groups of error correction bits. A method (640) for sending a signal, the method comprising: Obtaining (642) a data bit sequence, Carrying out (644), based on the data bit sequence, a forward error correction coding in order to obtain a sequence of systematic bits and error correction bits assigned to the sequence of systematic bits, the data bit sequence and the sequence of systematic bits being identical, Sending (646) a signal, the signal comprising a first block of transmit bits and a second block of transmit bits, the first block of transmit bits comprising a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits being defined by the second sequence of reference bits is interrupted so that a first part of the sequence of systematic bits is arranged before the second sequence of reference bits and a second part of the sequence of systematic bits is arranged after that of the second sequence of reference bits, the second transmission bit block being the error correction bits having, wherein a block of systematic bits from the sequence of systematic bits can be decoded together with a group of error correction bits assigned to the block of systematic bits from the error correction bits, independently of other error correction bits or other groups of error correction bits. A method (700) for receiving a signal, the method comprising: Receiving (702) a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to a data bit sequence to be transmitted with the signal, wherein the second transmission bit block has the sequence of systematic bits associated with error correction bits, performing (704) a channel estimation based on the received sequence of reference bits, decoding (706) a sequence comprising a received block of systematic bits of the received sequence of systematic bits and at least one The received block of contiguous error correction bits of the received error correction bits assigned to the received block of systematic bits comprises, independently of other received error correction bits or received blocks of error correction bits, in order to obtain a block of the data bit sequence, Perform (708), based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and at least one reencoded block of systematic bits and error correction bits assigned to the reencoded block of systematic bits, tracking (710) the channel estimation based on the reencoded block of systematic bits and the at least one reencoded block of error correction bits. A method (720) for receiving a signal, the method comprising: Receiving (722) a signal having a first transmission bit block and a second transmission bit block, the first transmission bit block having a sequence of reference bits and a sequence of systematic bits, the sequence of systematic bits being identical to a data bit sequence to be transmitted with the signal, wherein the second transmission bit block has error correction bits assigned to the sequence of systematic bits, Performing (724) a channel estimation based on the received sequence of reference bits, Decoding (726) a sequence comprising a received block of systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits associated with the received block of systematic bits, independent of other received error correction bits or received groups of error correction bits in order to obtain a block of the data bit sequence, Carrying out (728), based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits, Tracking (730) the channel estimate based on the reencoded block of systematic bits and the reencoded group of error correction bits. A method (740) for receiving a signal, the method comprising: Receiving (742) a signal comprising a first block of transmit bits and a second block of transmit bits, the first block of transmit bits comprising a first sequence of reference bits, the sequence of systematic bits and a second sequence of reference bits, the sequence of systematic bits being replaced by the second sequence is interrupted by reference bits, so that a first part of the sequence of systematic bits is arranged before the second sequence of reference bits and a second part of the sequence of systematic bits is arranged after that of the second sequence of reference bits, the second transmission bit block having the error correction bits, Performing (744) a channel estimation based on the received first sequence of reference bits and the received second sequence of reference bits, Decoding (746) a sequence comprising a received block of systematic bits of the received sequence of systematic bits and at least one group of error correction bits of the received error correction bits associated with the received block of systematic bits, independent of other received error correction bits or groups received of error correction bits in order to obtain a block of the data bit sequence, Carrying out (748), based on the block of the data bit sequence, a forward error coding in order to obtain a reencoded block of systematic bits and a reencoded group of systematic bits and error correction bits assigned to the reencoded block of systematic bits, Tracking (750) the channel estimate based on the reencoded block of systematic bits and the reencoded group of error correction bits. Computer program for carrying out the method according to one of the Claims 57 to 62 .

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