DE102018123563B4 - Method for inter-core communication in a multi-core processor - Google Patents

Abstract

Multi-core processors are increasingly being used to increase the performance of in-vehicle control units. Multi-core processors use global memory to cope with the increasing number of functions and the coordination of the individual processor cores. This creates the need for data exchange between the processor cores. With regard to inter-core communication between individual processor cores, the use of global memories is associated with slow read and write accesses or with long waiting times. This puts the implementation of functional safety at risk. The method according to the invention faces the requirements of optimal memory utilization for increasing the performance of multi-core processors and real-time mapping of time-critical functions. For this purpose, processor cores are assigned different priorities according to the safety relevance of the functions performed. Program code and data from high-priority processor cores are stored in their local memories. Read and memory access to local memory represents the fastest possible data transfer between a processor core and a memory. The inter-core communication takes place in such a way that higher-priority processor cores only have to access their own local memory through efficient memory management.

Description

Technical field

The present invention relates to a method for inter-core communication in an in-vehicle control unit with a multi-core processor.

State of the art

With the increasing electrification of vehicles, but also through the further development of driver assistance systems, entertainment systems and autonomous driving, more and more functions are being created that are carried out within a vehicle by the vehicle's internal control units. This requires increasingly powerful control units. In-vehicle control units, for example engine control units, are largely standardized in terms of their housing shape and pin assignment in the vehicle industry, with the aim of reducing development and manufacturing costs. In order to meet the increasing performance requirements while maintaining the necessary installation space, multi-core processors are used, with an increase in the number of processor cores focusing on increasing the performance of the processor. In terms of components, multi-core processors consist of the processor cores, which in turn have an arithmetic unit, arithmetic registers or memory areas, a control unit and memory management, memories and caches and other peripherals. The individual components of the multi-core processor are interconnected via a bus system. Based on the drawing 1 the basic structure of the memory management of current multi-core processors is shown. A multi-core processor ( 1 ) contains a certain number of processor cores ( 2A , 2 B , 2Z) which each have a local storage ( 3A , 3B , 3Z) feature. In-vehicle control devices in particular have a processor architecture based on the Harvard architecture, with data and command memories being physically and logically separated from one another. The advantage is that data and commands can be processed simultaneously. The individual processor cores ( 2A , 2 B , 2Z) therefore have a program memory interface ( 4A , 4B , 4Z) and a data storage interface ( 5A , 5B , 5Z) . Within the program memory interface ( 4A , 4B , 4Z) there is local storage in the form of local program RAM and within the data storage interface ( 5A , 5B , 5Z) there is local storage in the form of local data ram ( 6A , 6B , 6Z) . The individual processor cores ( 2A , 2 B , 2Z) can on their own local storage ( 3A , 3B , 3Z) directly and via a bus system ( 7 ) to the local store ( 3A , 3B , 3Z) additional processor cores ( 2A , 2 B , 2Z) or global storage ( 8th ) access. Global storage ( 8th ) can in turn be stored in a data storage unit ( 9 ) and a program storage unit ( 10th ) be divided. Furthermore, data storage unit ( 9 ) and program storage unit ( 10th ) be partitioned, the data storage unit ( 9 ) function-related individual data RAM ( 9A , 9B , 9Z) , as well as the program storage unit ( 10th ) individual program RAM ( 10A , 10B , 10Z) can have. A plurality of processor cores to increase the performance of the multi-core processor, due to the abundance of the functions available, require mutual memory access between processor cores, hereinafter referred to as inter-core communication. However, the inter-core communication can only contribute to an adequate increase in performance if the individual memories and the memory accesses are used optimally. The allocation of the program code and data is of particular importance for this. With a large amount of data, a high need for data exchange and a large number of functions and information in the internal control unit network, the use of global memories in relation to increasing the storage capacity is state of the art. However, global memories have disadvantages regarding the optimal performance of multi-core processors and the real-time ability to perform functions. Due to the large number of functions that are implemented in modern vehicles, data generated by the vehicle is often evaluated by several functions from different areas of application. For example, data from the wheel speed sensor are required for vehicle speed, emergency brake assist and navigation, among other things. If several processor cores want to access global memory at the same time, waiting times arise due to the limited reproducible data transfer rate and the effect of competing memory access.

Studies with regard to the performance of multi-core processors as a function of memory management in current processors for vehicle-internal control units show that an increase in the processor cores does not necessarily result in a linear increase in the performance of the processor ( Jungklass, Philipp; Berekovic, Mladen: Effects of concurrent access to embedded multicore microcontrollers with hard real-time demands, 13th International Symposium on Industrial Embedded Systems, 6 June 2018, Graz, Austria ). Accordingly, competing access to data RAM or program RAM from global memory or competing access to local memory of the processor core memory suffer the greatest performance losses in multi-core processors. Depending on the processor structure and memory structure, a linear increase in performance with an increase in processor cores is only possible Exclusive memory access of the processor cores to global memory or with exclusive access of a processor core to its own local memory possible.

Competing memory access, especially in connection with functional security, leads to long waiting times in the processor computing processes. With regard to the development of assistance systems and autonomous driving, data from radar sensors or cameras are increasingly becoming safety-relevant functions. Security-related functions are usually time-critical and have a high real-time requirement. In vehicles, the safety levels of functions are defined using the ISO26262 safety standard. Different safety levels according to ASIL (automotive safety integration level) are mapped. The levels indicate the severity and frequency of a malfunction and make special demands on the probability of failure. Due to the safety-related subdivision of the functions, a function portfolio of an in-vehicle control unit now contains some safety-critical and very many non-safety-critical functions. The conflict that now arises is referred to as “mixed criticality” and describes that different functions within the control device have different priorities due to their security level. Using the example of the wheel speed sensors, this means that the data of the sensor, sorted according to priority, should be evaluated in a time-critical manner by the functions of the emergency brake assistant and the vehicle speed rather than for navigation. According to ISO26262, static priority orders are permitted for this, as they are already fulfilled in system architectures for the automotive industry. Nevertheless, the information to be transported within the in-vehicle control unit network increases faster than the functions that can be implemented. When using global memories within a multi-core processor, in addition to the problem of competing memory access from different cores, there is still the effect that data and program code from and for functions with different security levels are mixed in a memory. On the one hand, this complicates the prioritization of functions and data processing, and on the other hand, safety-critical functions have the same waiting times and delays as non-safety-relevant functions. In order to be able to map the necessary security levels, partitions on global memories are increasingly used.

It is also important that when data is copied from one processor core for processing into another processor core, it is compared with one another in order to maintain the coherence of the data and the memory. Additional information is added to the actual information, which is used to transmit and ensure data transmission. With a corresponding amount of information and a limited bandwidth, transmission bottlenecks can also occur. This effect is called overhead.

In order to increase the performance of in-vehicle control units using multi-core processors, in addition to the performance of the individual cores, effective memory management is also required to obtain an optimal performance yield. In the published application WO 2017/056725 A1 For this purpose, an in-vehicle control device is presented, which contains the data communication between processor cores of a multi-core processor, wherein individual processor cores have different functional security levels.

In one embodiment, a high security level is assigned to a processor core. Security levels are transferred in priorities. The high priority processor core processes data from a low priority processor core. For this purpose, a global memory is used, which is also partitioned, the processor core with high priority each having a partition on the global data RAM and the global program RAM and the processor core with low priority another global data RAM partition and another global program RAM partition are assigned. In order to increase efficiency, avoidable copying processes are substituted for functions with high priority. Instead of writing the data from the data RAM of the processor core with low priority, which is to be processed by the processor core with a high security level, over the bus into its partition in the global memory, then copying it into the local storage unit of the processor core with high priority, so that it can then read the data in its data RAM and process it further, the data from the local data RAM of the processor core with low priority is sent directly to the global partition of the processor core with high priority via an established data transfer. In the simplest case, this can also be done via the bus system, the writing process into the own local storage unit and the subsequent copying process to the local target storage unit being omitted. However, data transfer is still subject to delays due to memory access to global memory. In an alternative embodiment, data transfer via a direct connection by means of direct memory access (“Direct Memory Access” (DMA)) is therefore proposed. In this embodiment, the low priority processor core writes data to its local one Data RAM and establishes a DMA between its local data RAM and the global data RAM partition of the processor core with high priority. This reads the data from its data RAM partition of the global memory into its local data RAM and processes it further.

The direct transfer of function-specific data from a processor core of lower priority to the partition of the global data RAM of a processor core with higher priority reduces the delay due to fewer copying processes into the global memory and at the same time reduces the risk of overhead. Since a processor core has exclusive access to the partition assigned to it within a global memory, it can read out the data as required and at the same time comply with the security standards, since mixing with data of other priorities on the global memory is prevented.

The current state of the art for effective performance in vehicle-internal control units with multi-core processors through efficient memory management achieves an improvement in that processor cores are assigned a priority, depending on the necessary or intended safety standards of the functions that they are to perform. To meet the real-time requirements of prioritized functions, RAM partitions on global memories are divided into processor-related partitions. Processor cores have exclusive access to the local storage unit assigned to them. Required data from other processor cores can be written directly into the corresponding global data RAM partition. To further optimize the data transfer, a DMA can be set up to write the data into the global memory.

However, the required data must still be read from the target processor core from the global memory. Reading from and writing to the global memory are still the slowest copying processes in inter-core communication in multi-core processors. In addition, the transfer speeds that can be achieved are particularly dependent on the speed of the respective memory. A processor core only achieves the highest speed if it exclusively accesses its own local memory. In general, inter-core communication always poses a threat to the real-time capability of a system and should therefore take as short a time as possible.

In order to meet the requirement of optimizing the data transmission speed in the case of inter-core communication in multi-core processors in vehicle-internal control units and to ensure the real-time capability of executing safety-relevant functions, the following invention is proposed.

Object of the invention

The object of the invention is to provide a method for inter-core communication in a multi-core processor, which ensures the real-time requirement of functional safety according to ISO26262 through efficient memory management.

Solution of the task

The object is achieved by a method for inter-core communication in a multi-core processor according to claim 1, further embodiments result from the features of the subclaims.

Presentation and advantages of the invention

The inventive method for inter-core communication in a multi-core processor describes an optimized memory management for data transmission between processor cores. To implement the method, a multi-core processor with at least two processor cores is required, each of which has at least one local memory directly connected to the arithmetic unit of the processor core and is connected to one another via a network. The local memories can be divided both physically and logically into a program memory interface and a data storage interface. The program memory interface can contain a program RAM. The data storage interface can contain one or more data RAM, via which data is exchanged between the processor cores. The network can be designed as a bus system, wherein the bus system can consist of one or more bus lines. The multi-core processor usually contains other components, such as further storage units and caches, additional peripherals and interfaces for communication with other systems or input and output devices. In an advantageous embodiment, the further components additionally include one or more global memories, one or more program RAM and one or more data RAM, which are part of the global memory. Priorities are assigned to the individual processor cores, so that each processor core has a higher or lower priority to other processor cores in the multi-core processor. The priorities can be assigned according to the ISO26262 security standards. Furthermore, data of particularly time-critical or security-relevant functions are relevant allocated according to priority, in the local memories of the respective processor cores. This has the advantage of minimal waiting time for the data transfer and data processing of these functions, since processor cores have the fastest read and write access to their own local memory. Corresponding data are also separated from other data in accordance with the requirements of functional safety and mixing of the data is prevented. The additional use of global memories has the advantage that program code and data of functions without or with low security relevance or priority can be stored in corresponding collective memories.

For the method according to the invention for inter-core communication in a multi-core processor, a distinction is made between two basic applications. In the first case, a processor core to which a high priority is assigned performs a function for the process of which data from a further processor core to which a lower priority is assigned are required. With a view to an optimal processing speed of the function from the high-priority processor core, the program code of the function in the program RAM of the local memory and the data in the data RAM of the local memory of this processor core are allocated. Required data from the processor core with lower priority is written by this into the data RAM of the local memory of the processor core with high priority. When the writing process is finished, the processor core reads the data from the corresponding data RAM of its local memory with high priority and executes the function. The processor core with high priority does not have to read the required data from a global memory, which can result in a waiting time, but only access its own local memory. In the second case, a processor core, which is assigned a lower priority, performs a function for the process of which data from a further processor core, which is assigned a higher priority, are required. With regard to an optimal processing speed of the function from the processor core with a lower priority, the program code of the function is allocated in the program RAM of the local memory and the data in the data RAM of the local memory of this processor core. Required data from the processor core with higher priority is copied from this into the data RAM of its local memory. The processor core with lower priority then reads the required data from the data RAM of the local memory of the processor core with higher priority and processes it further in the process of the function to be carried out. The processor core with high priority, which should provide data for a processor core with low priority, does not have to copy data into a global memory or the local memory of another processor core, but only briefly accesses its own local memory for the copying process. It generally applies to the method according to the invention that processor cores, which are to provide data for other processor cores with a higher priority, always write this data into the local memory of the processor cores with higher priority, and that processor cores which are to provide data for processor cores with a lower priority, write this data to their own local storage. Processor cores, which process data from a higher priority processor core, read them from the local memory of the processor core with higher priority and processor cores, which process data from a lower priority processor core, read them from their local memory. Thus, processor cores with higher priorities only access their own local memory during inter-core communication, which results in minimal interruptions or waiting times for these processor cores.

In an advantageous embodiment of the method according to the invention, direct memory access is set up for writing data from one processor core to the local memory of another processor core. The bus participation during write processes on processor cores with a higher priority is prioritized here by a DMA controller, which entails a further increase in the transmission speed of the data.

In a further advantageous embodiment, the processor cores each have two data RAMs in their local memories, so that a local data RAM of the processor core can be used for communication with other components and / or processor cores, and the other local data RAM can be used for continuous data processing or that several processor cores can write data into the data RAM of the processor core, whereby competing memory access is prevented or its effect is reduced.

Embodiments

Further features, possible applications and advantages of the invention result from the following description of exemplary embodiments of the invention with reference to the schematically illustrated drawings.

• 1: eine Zwischenkernkommunikation zwischen drei Prozessorkernen, welche jeweils einen lokalen Speicher aufweisen, wobei je ein Prozessorkern mit höchster und ein Prozessorkern mit mittlerer Priorität Daten von einem Prozessorkern mit niedriger Priorität verarbeiten.
• 2: eine Zwischenkernkommunikation zwischen drei Prozessorkernen, welche jeweils einen lokalen Speicher aufweisen, wobei zwei Prozessorkerne Daten von einem Prozessorkern mit höchster Priorität verarbeiten.
• 3: eine Zwischenkernkommunikation zwischen drei Prozessorkernen, welche jeweils einen lokalen Speicher aufweisen, wobei ein Prozessorkern mit höchster Priorität Daten von einem Prozessorkern mit mittlerer Priorität verarbeitet und gleichzeitig ein Prozessorkern mit niedriger Priorität Daten aus dem Prozessorkern mit mittlerer Priorität verarbeitet.
• 4: eine Zwischenkernkommunikation zwischen drei Prozessorkernen, welche jeweils zwei lokale Daten-RAM in ihren lokalen Speichern aufweisen, wobei je ein Prozessorkern mit höchster und ein Prozessorkern mit mittlerer Priorität Daten von einem Prozessorkern mit niedriger Priorität verarbeiten.
• 5: eine Zwischenkernkommunikation zwischen drei Prozessorkernen, welche jeweils zwei lokale Daten-RAM in ihren lokalen Speichern aufweisen, wobei ein Prozessorkern mit höchster Priorität Daten von einem Prozessorkern mit mittlerer Priorität verarbeitet und gleichzeitig ein Prozessorkern mit niedriger Priorität Daten aus dem Prozessorkern mit mittlerer Priorität verarbeitet.

Here show:

• 1 : Inter-core communication between three processor cores, each of which has a local memory, one processor core with the highest and one Processor core with medium priority Process data from a processor core with low priority.
• 2nd : Inter-core communication between three processor cores, each of which has a local memory, two processor cores processing data from a processor core with the highest priority.
• 3rd : Inter-core communication between three processor cores, each of which has a local memory, wherein a processor core with highest priority processes data from a processor core with medium priority and at the same time a processor core with low priority processes data from the processor core with medium priority.
• 4th : Inter-core communication between three processor cores, each of which has two local data RAMs in their local memories, one processor core with the highest priority and one processor core with the medium priority processing data from a processor core with the lower priority.
• 5 : Inter-core communication between three processor cores, each with two local data RAMs in their local memories, whereby a processor core with highest priority processes data from a processor core with medium priority and at the same time a processor core with low priority processes data from the processor core with medium priority.

In the illustrated embodiments, the inter-core communication is shown as an example for a multi-core processor of an in-vehicle control device with three processor cores of different priority. A first processor core is responsible for communication with other systems or input / output devices, e.g. via CAN / Ethernet. A low priority is assigned to this processor core. A second processor core is responsible for the execution of safety-relevant functions and therefore has the highest priority. A third processor core is responsible for system monitoring and fault diagnosis. A relatively high priority is assigned to this processor core. In all figures, the first processor core ( 2A) the lowest, the second processor core ( 2 B) the highest and the third processor core ( 2Z) a medium priority.

In 1 is the method according to the invention for inter-core communication between the three processor cores ( 2A , 2 B , 2Z) which each have a local storage ( 3A , 3B , 3Z) have shown, wherein the second processor core ( 2 B) with the highest and the third processor core ( 2Z) with medium priority data from the first processor core ( 2A) Process with low priority. The first processor core ( 2A) in a first step ( S1 ) the highest priority data in the data RAM ( 6B) local storage ( 3B) of the second processor core ( 2 B) . In a second step ( S2 ) writes the first processor core ( 2A) the other data in the data RAM ( 6Z) local storage ( 3Z) the third processor core ( 2Z) . Is the writing process for the second processor core ( 2 B) completed, it reads the corresponding data in a further step ( S3 ) via its data storage interface ( 5B) out. The third processor core reads analogously ( 2Z) the data in a further step ( S4 ) via its data storage interface ( 5Z) out. In the following steps ( S5 , S6 , S7 ) process all processor cores ( 2A , 2 B , 2Z) Data from their local stores ( 3A , 3B , 3Z) .

In 2nd is the method according to the invention for inter-core communication between the three processor cores ( 2A , 2 B , 2Z) which each have a local storage ( 3A , 3B , 3Z) shown, the first and third processor core ( 2A , 2Z) , both of which have a lower priority than the second processor core ( 2 B) have data from the second processor core ( 2 B) to process. The second processor core ( 2 B) writes the required data in a first and a second step ( S1 , S2 ) in the data RAM ( 6B) its local storage ( 3B) . Then the other two processor cores read ( 2A , 2Z) the data from the data RAM ( 6B) local storage ( 3B) of the second processor core ( 2 B) from (S3, S4). In the following steps ( S5 , S6 , S7 ) process all processor cores ( 2A , 2 B , 2Z) Data from their local stores ( 3A , 3B , 3Z) .

In 3rd is the method according to the invention for inter-core communication between the three processor cores ( 2A , 2 B , 2Z) which each have a local storage ( 3A , 3B , 3Z) have, shown, the first processor core ( 2A) , which has the lowest priority, and the second processor core ( 2 B) , which has the highest priority, data from the third processor core ( 2Z) , which has the medium priority. In a first and a second step ( S1 , S2 ) writes the third processor core ( 2Z) the required data in the data RAM ( 6Z) its local storage ( 3Z) and in the data RAM ( 6B) local storage ( 3B) of the second processor core ( 2 B) . In the next two steps ( S3 , S4 ) reads the first processor core ( 2A) Local storage data ( 3Z) the third processor core ( 2Z) and the second processor core ( 2 B) reads data from its local storage ( 3B) . In the following steps ( S5 , S6 , S7 ) process all processor cores ( 2A , 2 B , 2Z) Data from their local stores ( 3A , 3B , 3Z) .

In 4th is the method according to the invention for inter-core communication between the three processor cores ( 2A , 2 B , 2Z) , which each have two data RAM ( 6A , 6B , 6Z) in their local stores ( 3A , 3B , 3Z) have shown, wherein the second processor core ( 2 B) with the highest and the third processor core ( 2Z) with medium priority data from the first processor core ( 2A) Process with low priority. The first processor core ( 2A) in a first step ( S1 ) the highest priority data in a data RAM ( 6B) of the second processor core ( 2 B) . In a second step ( S2 ) writes the first processor core ( 2A) the other data in a data RAM ( 6Z) the third processor core ( 2Z) . Is the writing process for the second processor core ( 2 B) completed, it reads the corresponding data in a further step ( S3 ) via its data storage interface ( 5B) out. The third processor core reads analogously ( 2Z) the data in a further step ( S4 ) via its data storage interface ( 5Z) out. The steps for data processing ( S5 , S6 , S7 ) are in all processor cores ( 2A , 2 B , 2Z) executed in parallel by the respective other local data RAM ( 6A , 6B , 6Z) which are not involved in inter-core communication.

In 5 is the method according to the invention for inter-core communication between the three processor cores ( 2A , 2 B , 2Z) , which each have two data RAM ( 6A , 6B , 6Z) in their local stores ( 3A , 3B , 3Z) have, shown, the first processor core ( 2A) , which has the lowest priority, and the second processor core ( 2 B) , which has the highest priority, data from the third processor core ( 2Z) , which has the medium priority. In a first and a second step ( S1 , S2 ) writes the third processor core ( 2Z) the required data in a data RAM ( 6Z) its local storage ( 3Z) and data RAM ( 6B) local storage ( 3B) of the second processor core ( 2 B) . The inter-core communication between the third processor core ( 2Z) and the second processor core ( 2 B) direct memory access via a DMA controller ( 11 ) is set up so that data transfer to the processor core is of the highest priority ( 2 B) for transmission on the bus line system ( 7 ) is prioritized. In the next two steps ( S3 , S4 ) reads the first processor core ( 2A) Local storage data ( 3Z) the third processor core ( 2Z) and the second processor core ( 2 B) reads data from its local storage ( 3B) . The steps for data processing ( S5 , S6 , S7 ) are in all processor cores ( 2A , 2 B , 2Z) executed in parallel by the respective other local data RAM ( 6A , 6B , 6Z) which are not involved in inter-core communication.

Reference list

1

Multi-core processor

2A, 2B, 2Z

Processor core

3A, 3B, 3Z

local memory

4A, 4B, 4Z

Program memory interface

5A, 5B, 5Z

Data storage interface

6A, 6B, 6Z

local data RAM

7

Bus system

8th

global storage

9, 9A, 9B, 9Z

global data RAM

10, 10A, 10B, 10Z

global program RAM

11

DMA controller

S1

first write

S2

second write

S3

first reading

S4

second reading

S5

first data processing

S6

second data processing

S7

third data processing

Claims (6)

Method for inter-core communication in a multi-core processor, the multi-core processor having at least two processor cores, the processor cores being assigned a priority depending on the security standards of the functions which they are intended to perform, the priorities being assigned in accordance with the security standards in accordance with ISO 26262, so that particularly time-critical ones or security-related functions have a higher priority, the processor cores being connected to one another and to other components of the multi-core processor via a network, so that data transfer between the processor cores to one another and the components is possible, each processor core having at least its own local memory, the Processor cores are assigned different priorities, so, if a processor core with a higher priority needs data from a processor core with a lower priority, the processor core with the higher priority processes data from the processor core with the lower priority, in the form that the processor core with the lower priority does the necessary data writes over the network to the local memory of the processor core with the higher priority, the processor core with the higher priority reads the data from its local memory and processes the data, or if a processor core with a lower priority writes data from a processor core with a higher one Priority is required, the processor core with the lower priority processes data from the processor core with the higher priority, in the form that the processor core with the higher priority writes the required data into its local memory, the processor core with the lower priority that Reads data from the local memory of the processor core with the higher priority and processes the data further, wherein direct memory access can be set up for writing data from one processor core to the local memory of another processor core. Procedure according to Claim 1 , characterized in that further components of the multi-core processor include one or more global memories and / or one or more program RAM and / or one or more data RAM, so that data and program code with low priority are stored and / or processed on these components . Procedure according to Claim 1 or 2nd , characterized in that the local memory of a processor core is a memory which is physically and electrically connected directly to the processor core. Method according to one of the preceding claims, characterized in that the network consists of one or more bus systems, so that data and information are exchanged between the processor cores, their local memories and the remaining components of the multi-core processor. Device which is set up, a method according to one of the Claims 1 to 4th to execute. Vehicle with a device after Claim 5 .

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