DE102018105868A1 - Method for producing a semiconductor-based pressure sensor - Google Patents

Abstract

A method for producing a semiconductor-based pressure sensor having a plurality of layers arranged on one another, comprising the steps of: providing the plurality of layers producing an electrode by etching an electrode layer by means of a two-stage etching process, wherein the two-stage etching process provides that in one the first step is an anisotropic etching process for producing at least one first recess (4) with side walls (4a) perpendicular to a first surface of the electrode layer (2aa) and an anisotropic wet chemical KOH etching process in a second step following the first step to produce at least one second recess (5) having side walls (5a) tapering towards a second surface of the electrode layer (2ab) facing away from the first surface of the electrode layer (2aa), - aligning a first layer (1) with the electrode layer (2); - Add the first layer (1) with the electrode layer (2).

Description

The invention relates to a method for producing a semiconductor-based, in particular capacitive pressure sensor, a semiconductor-based, in particular capacitive pressure sensor obtainable by the method and a semiconductor-based, in particular capacitive pressure sensor.

Semiconductor-based pressure sensors, sometimes referred to as MEMS pressure sensors, are regularly constructed of stacked layers, especially silicon layers, and are fabricated using techniques commonly used in semiconductor technology, such as silicon deposition. Etching processes, oxidation method, implantation method, bonding method and / or coating method produced. In this case, the individual layers, as well as possibly provided between adjacent layers connecting layers, e.g. Isolation layers, according to their function in the sensor prepared or structured.

Such semiconductor-based pressure sensors usually include components which may be subject to mechanical stress. An example of this are functional elements of electromechanical transducers integrated in the pressure sensors, which are exposed to a mechanical load which is dependent on the measured variable to be detected and which is converted by the transducer into an electrical variable dependent on the measured variable.

Mechanical loads inevitably cause mechanical stresses on the individual structural elements and / or other structural elements connected to individual structural elements. This poses no problem as long as the loads do not exceed a load limit, which is often specified for the sensor as an overload resistance. However, it often happens in practice that sensors are subjected to overloading.

The risk of overloading is esp. In differential pressure sensors particularly large, which are used to measure pressure differences Δp between two compared to the pressure difference Ap large pressures p1, p2. Since these sensors must be sensitive enough to be able to measure the pressure difference Δp superimposed on the smaller system pressure corresponding to the two pressures, one-sided overloads, in which only one side of a measuring diaphragm of the differential pressure sensor is subjected to a high pressure, are nonexistent counteracts the counter-pressure acting on the opposite side of the measuring diaphragm, a problem. Here, notch stresses occur in particular at so-called "acute" angles. The notch stresses that occur are the greater, the sharper the angle. Such notch stresses can cause stress cracks or even stress fractures in the event of overloading.

An example of this is capacitive semiconductor-based pressure sensors, in particular differential pressure sensors, for metrological detection of the print size, which comprises a plurality of layers arranged on one another, in particular silicon layers whose layers comprise at least a first layer and an electrode layer arranged on the first layer, wherein an electrode defined at least in sections is generated by a single recess in the electrode layer. Depending on the specific embodiment of the pressure sensor, the generation of the recess results in different acute angles between the side walls of the recess and a corresponding plane adjoining the recess. In the case of capacitive pressure sensors in which (exclusively) a KOH etching process is used to produce the recess, for example, an acute angle arises between the side walls of the recess produced by KOH etching and a plane in which a surface of the first layer is located. 54.7 °, whereas in capacitive pressure sensors in which for generating the recess (exclusively) a reactive ion etching (hereinafter also RIE for "reactive ion etching", abbreviated) is used, for example, creates an acute angle between the side walls by means of RIE generated recess and a plane in which a surface of a recess bounding the layer is, of about 90 °.

Both at the acute angle of 54.7 ° and 90 °, occur at a corresponding pressure load notch stresses, so that it can come in a sufficiently large load case, for example. In the overload case, stress cracks or stress fractures.

The invention is therefore based on the object to minimize the notch stress occurring at pressure sensors at acute angles.

The object is achieved by the method according to claim 1, the semiconductor-based pressure sensor obtainable by the method according to claim 7 and the semiconductor-based pressure sensor according to claim 8.

• - Bereitstellen der mehreren Lagen, insbesondere Siliziumlagen, die zumindest eine erste Lage und eine Elektrodenlage umfassen;
• - Erzeugen einer zumindest abschnittsweise definierten Elektrode durch Ätzen der Elektrodenlage mittels eines zweistufigen Ätzprozesses, wobei der zweistufige Ätzprozess vorsieht, dass in einem ersten Schritt ein anisotroper Ätzprozess zum Erzeugen zumindest einer ersten Aussparung mit in Bezug zu einer ersten Oberfläche der Elektrodenlage im Wesentlichen rechtwinkligen Seitenwänden und in einem zweiten dem ersten Schritt nachfolgenden Schritt ein anisotroper nasschemischer KOH-Ätzprozess zur Erzeugung zumindest einer an die erste Aussparung anschließenden zweiten Aussparung mit sich zu einer der ersten Oberfläche der Elektrodenlage abgewandten zweiten Oberfläche der Elektrodenlage hin konisch verjüngenden Seitenwänden durchgeführt wird;
• - Ausrichten der ersten Lage zu der Elektrodenlage, wobei die erste Aussparung zu einer ersten Oberfläche der ersten Lage hin orientiert wird und die Seitenwände der ersten Aussparung einen ersten Winkel α von in etwa 90° zu einer Ebene, in der die erste Oberfläche der ersten Lage liegt, bilden;
• - Fügen der ersten Lage mit der Elektrodenlage derartig, dass ein an die erste Aussparung angrenzendes randseitig umlaufendes Verbindungselement der Elektrodenlage mit einem auf der ersten Oberfläche der ersten Lage entsprechenden Randbereich gefügt wird.

The inventive method for producing a semiconductor-based, in particular capacitive pressure sensor, in particular differential pressure sensor with a plurality of layers arranged on one another, in particular silicon layers, comprises the following steps:

• - Providing the plurality of layers, in particular silicon layers, comprising at least a first layer and an electrode layer;
• Generating an at least partially defined electrode by etching the electrode layer by means of a two-stage etching process, wherein in a first step an anisotropic etching process for producing at least a first recess with respect to a first surface of the electrode layer substantially rectangular side walls and in a second step following the first step, an anisotropic wet-chemical KOH etching process is carried out to produce at least one second recess adjoining the first recess with sidewalls tapering towards a second surface of the electrode layer facing away from the first surface of the electrode layer;
• - Aligning the first layer to the electrode layer, wherein the first recess is oriented toward a first surface of the first layer and the side walls of the first recess at a first angle α from about 90 ° to a plane in which the first surface of the first layer is located;
• Joining the first layer to the electrode layer in such a way that a connecting element of the electrode layer surrounding the peripheral edge is joined to an edge region corresponding to the first surface of the first layer.

According to the invention, a combination of an anisotropic etching process for the production of vertical sidewalls and an anisotropic wet-chemical KOH etching process is used, wherein first by means of the anisotropic etching process, a first part of the recess and connect by means of the anisotropic wet-chemical KOH etching process, a second part of the Recess is generated. As a result, the usually resulting acute angle can be avoided by the corresponding angle is increased, so that the adverse notch stresses are reduced. In accordance with the method according to the invention, furthermore, the use of the KOH etching process with high reproducible structure fidelity and as a cost-effective batch process is possible.

A first advantageous embodiment of the method according to the invention provides that the electrode layer is provided by an electrically conductive cover layer, which is separated from an electrically conductive carrier layer at least by an insulating layer, in particular an oxide layer, and by means of the two-stage etching processes, the first and second recess in the electrically conductive cover layer is etched, wherein an etching depth of the first and second recess is selected such that the second recess protrudes on the head side at least to the insulation layer and a second angle between the side walls of the second recess and a plane in which the insulation layer is located of about 125.3 °. In particular, the embodiment can provide that by etching the first and second recesses, the edge-side connecting element and the inner sectionally defined electrode are produced in the electrically conductive cover layer and the connecting element is electrically separated by the first and second recesses from the inner electrode.

An alternative second embodiment of the method according to the invention provides that the electrode layer is provided by at least one electrically conductive layer comprising a semiconductor material, in particular a silicon, and the first and second recesses are etched into the electrically conductive layer by means of the two-stage etching process, wherein an etching depth the first and second recess is selected such that on the second surface of the electrode layer, the inner sectionally defined electrode is generated, which preferably occupies at least a width of 50%, particularly preferably of 60% with respect to a total width of the electrode layer. In particular, the embodiment can provide that by etching the first and second recesses, the edge element in the electrode layer is produced and the connecting element is electrically connected to the inner electrode.

A further advantageous embodiment of the method according to the invention provides that a reactive ion etching process or a variant modified therefrom, in particular a reactive ion etching process, is used for the anisotropic etching process.

The invention further relates to a semiconductor-based, in particular capacitive pressure sensor, in particular differential pressure sensor with a plurality of layers arranged on one another, in particular silicon, which is obtainable by the method according to the invention.

• - mehrere aufeinander angeordnete Lagen, insbesondere Siliziumlagen, die zumindest eine erste Lage und eine Elektrodenlage umfassen;
• - eine in der Elektrodenlage befindliche erste Aussparung mit in Bezug zu einer ersten Oberfläche der Elektrodenlage im Wesentlichen rechtwinkligen Seitenwänden;
• - eine in der Elektrodenlage an die erste Aussparung angrenzende zweite Aussparung mit sich zu einer der ersten Oberfläche abgewandten zweiten Oberfläche der Elektrodenlage hin konisch verjüngenden Seitenwänden;
• - zumindest ein in der Elektrodenlage befindliches an die erste Aussparung angrenzendes randseitig umlaufendes Verbindungselement;
• - eine Fügeschicht, die die Elektrodenlage über das Verbindungselement mit einem auf der ersten Oberfläche der ersten Lage befindlichen entsprechenden Randbereich fügt, so dass die Seitenwände der ersten Aussparung im Wesentlichen einen ersten Winkel α von in etwa 90° zu einer Ebene, in der die erste Oberfläche der ersten Lage liegt, bilden.

The invention further relates to a semiconductor-based, in particular capacitive pressure sensor, in particular a differential pressure sensor comprising at least:

• - Several successive layers, in particular silicon layers, which comprise at least a first layer and an electrode layer;
• - A located in the electrode layer first recess with respect to a first Surface of the electrode layer substantially right-angled side walls;
• a second recess adjoining the first recess in the electrode layer, with side walls tapering conically toward a second surface of the electrode layer facing away from the first surface;
• - At least one in the electrode layer befindliches adjacent to the first recess peripheral edge connecting element;
• a joining layer which inserts the electrode layer via the connecting element with a corresponding edge region situated on the first surface of the first layer, such that the side walls of the first recess have a substantially first angle α from about 90 ° to a plane in which the first surface of the first layer is formed.

An advantageous first embodiment of the semiconductor-based pressure sensor according to the invention provides that the electrode layer comprises an electrically conductive cover layer, at least one insulating layer and an electrically conductive Trägerläge, wherein the electrically conductive cover layer is separated by the at least one insulating layer of the electrically conductive carrier layer, and the first and the second recess is etched into the electrically conductive cover layer, wherein an etching depth of the first and second recess is dimensioned such that the second recess protrudes on the head side at least to the insulation layer and a second angle β between the side walls of the second recess and a plane in which the insulation layer is located, of approximately 125.3 °. In particular, the embodiment can provide that the electrically conductive cover layer has an edge-side connecting element and the inner sectionally defined electrode, wherein the connecting element is separated by the first and second recess of the inner electrode, in particular electrically.

An alternative embodiment of the semiconductor-based pressure sensor according to the invention provides that the electrode layer comprises an electrically conductive layer comprising a semiconductor material, in particular a silicon, the first and second recesses being etched into the electrically conductive layer and an etching depth of the first and second recesses being dimensioned in this way in that the sectionally defined electrode is produced on the second surface of the electrode layer, wherein the electrode preferably occupies at least a width of 50%, particularly preferably of 60% in relation to a total width of the electrode layer. In particular, the embodiment can provide that the edge-side connecting element and the sectionally defined electrode are electrically connected.

• 1: einen schematischen Teilausschnitt von einem aus dem Stand der Technik bekannten halbleiterbasierten kapazitiven Drucksensor zur Verdeutlichung der an spitzen Winkeln auftretenden Problematik von Kerbspannungen,
• 2: einen schematischen Teilausschnitt von einem halbleiterbasierten kapazitiven Drucksensor, bei dem das erfindungsgemäße Verfahren angewendet wurde,
• 3: einen Längsschnitt durch einen Teil eines aus dem Stand der Technik bekannten halbleiterbasierten kapazitiven Drucksensors, und
• 4: einen Längsschnitt durch einen Teil eines erfindungsgemäßen halbleiterbasierten kapazitiven Drucksensors.

The invention will be explained in more detail with reference to the following drawings. It shows:

• 1 FIG. 2: shows a schematic partial section of a semiconductor-based capacitive pressure sensor known from the prior art for clarifying the problem of notch stresses occurring at acute angles, FIG.
• 2 FIG. 2 is a schematic partial section of a semiconductor-based capacitive pressure sensor to which the method according to the invention has been applied.
• 3 FIG. 3: a longitudinal section through part of a semiconductor-based capacitive pressure sensor known from the prior art, and FIG
• 4 FIG. 2: a longitudinal section through part of a semiconductor-based capacitive pressure sensor according to the invention. FIG.

1 shows a schematic partial section of a semiconductor-based capacitive pressure sensor to illustrate the problem of notch stresses occurring at acute angles. This is in 1 an example of a pressure sensor with several layers arranged on each other 1 . 2 shown. A first location 1 , which serves as a measuring membrane, which depends on a first surface of the measuring membrane 1aa supplied first pressure and a second surface of the measuring diaphragm 1ab supplied second pressure corresponding deformed, and two electrode layers 2 , each comprising at least one electrode and each in a circumferential edge region pressure-tight with the first layer via a bonding layer 6 are joined. In this case, both the entire electrode layer 2 serve as an electrode as well as only a section-wise defined part of the electrode layer. In order to supply the first and second pressure of the measuring membrane accordingly, the two electrode layers 2 in each case a single recess or recess 10 which define a pressure chamber for the first and second pressure, respectively.

Usually, the recesses are made exclusively by means of an anisotropic etching process, for example a KOH etching process, from an electrode layer 2 serving silicon wafer, in which a potassium hydroxide solution is used for etching. Due to the crystal orientation of the silicon wafer, a typical first angle of about 54.7 ° for the KOH etching arises between the side walls of the recess and a surface of the silicon wafer. If, in a step following the etching step, the etched silicon wafer is joined with a further silicon wafer serving as a first layer, this angle is produced at the joint connection or joining layer 6 , so that it comes at this point to increased notch stresses (indicated by F _notch ).

2 shows a schematic partial section of a semiconductor-based capacitive pressure sensor, in which the inventive method has been applied to reduce the notch stresses. Here were the recesses 4 . 5 produced by a two-stage etching process. In the two-stage etching process, initially substantially perpendicular to the first surface of the electrode layer 2aa etched into the silicon wafer by means of an anisotropic etching process. The first anisotropic etching step becomes the first angle α between the side walls of the first recess 4a and the level, in which also a fügeschicht 6 for joining the electrode layer 2 with the first layer is raised to about 90 °. By increasing the angle to about 90 °, the notch stresses occurring in the joined state at this edge can be reduced. By reducing the notch stresses that occur, the normal force (in 4 by Fnom exemplified) and thus increases the nominal bursting strength of the pressure sensor. Connected to the first etching step is a second etching step, in which by an anisotropic wet-chemical etching process, for example. KOH etching process, to the first recess 4 adjacent second recess 5 is made to define the electrode.

An alternative method also known from the prior art for producing the recess 10 in a pressure sensor constructed of a multi-layered electrode sheet is shown in FIG 3 shown. Here, for example, from an SOI wafer (English: Silicon on insulator), which has a layer structure, comprising an electrically conductive cover layer 2a , an isolation situation 2 B and one through the insulation layer 2 B from the top layer 2a separate electrically conductive carrier layer 2c , comprising, the electrically conductive cover layer 2a by an anisotropic etching process, prepared in such a way that the electrically conductive cover layer 2a an outside surrounding connecting element 9 and at least one of them through the recess 10 or etching trench separate internal electrode 3 having. As an anisotropic etching process, a reactive ion etching process is regularly used for this purpose. To the electrode electrically from the outside surrounding connecting element 9 to separate, an etching depth is determined such that the recess or the etching trench extends to the insulating layer. Due to the choice of the etching process, an angle of approximately 90 ° arises at the edge between the electrically conductive layer and the insulation layer, so that at this point increased notch stresses (indicated by F _notch ) can occur.

4 shows a longitudinal section through a portion of a semiconductor-based capacitive pressure sensor according to the invention, which consists of a multilayer electrode layer 2a . 2 B . 2c is constructed. Here were the recesses 4 . 5 again produced by a two-stage etching process. In the two-stage etching process, initially substantially perpendicular to the first surface of the electrode layer 2aa in the electrically conductive cover layer 2a etched in by means of an anisotropic etching process, so that the first recess 4 arises. Connected to the first etching step is a second etching step, in which by an anisotropic wet-chemical etching process, for example. KOH etching process, to the first recess 4 adjacent second recess 5 is made to the electrode 3 define. The second anisotropic wet-chemical KOH etching step becomes a second angle β between the side walls of the second recess and a plane comprising the insulating layer, increased to about 125.3 °, so that in the joined state at this edge or the joining layer 6 occurring notch stresses are reduced. By reducing the notch stresses that occur, the nominal bursting strength (in 4 indicated by Fnom by way of example) of the pressure sensor.

LIST OF REFERENCE NUMBERS

1

First location

1aa

First surface of the first layer

1ab

Second surface of the first layer

2

electrode layer

2aa

First surface of the electrode layer

2ab

Second surface of the electrode layer

2a

Electrically conductive cover layer

2 B

insulation layer

2c

Electrically conductive carrier layer

3

electrode

4

First recess

4a

Side walls of the first recess

5

Second recess

5a

Side walls of the second recess

6

Add layer

9

connecting member

10

Recess according to the prior art

t

etch depth

α

First angle

β

Second angle

Claims (12)

Method for producing a semiconductor-based, in particular capacitive pressure sensor, in particular differential pressure sensor with a plurality of layers arranged on one another, in particular silicon layers, comprising the following steps: - providing the plurality of layers, in particular silicon layers, comprising at least a first layer (1) and an electrode layer (2); - Generating an at least partially defined electrode (3) by etching the electrode layer (2) by means of a two-stage etching process, wherein the two-stage etching process provides that in an initial step, an anisotropic etching process for generating at least a first recess (4) with respect to a first surface of the electrode layer (2aa) substantially rectangular side walls (4a) and in a second step following the first step an anisotropic wet-chemical KOH etching process for generating at least one of the first recess (4) adjoining the second recess (5) to one the first surface of the electrode layer (2aa) facing away from the second surface of the electrode layer (2ab) is performed towards conically tapered side walls (5a); - Aligning the first layer (1) to the electrode layer (2), wherein the first recess (5) is oriented towards a first surface of the first layer (1aa) and the side walls of the first recess (4a) has a first angle (α) from about 90 ° to a plane in which the first surface of the first layer (1aa) is located; - Joining the first layer (1) to the electrode layer (2) in such a way that a connecting element (9) of the electrode layer (2) surrounding the peripheral edge (4) adjoins the first layer (1aa) on the first surface Edge area is added. Method according to Claim 1 in which the electrode layer (2) is provided by an electrically conductive cover layer (2a) which is separated from an electrically conductive carrier layer (2c) by at least one insulating layer (2b), in particular an oxide layer, and the first and second layers by means of the two-step etching processes second recess (4, 5) is etched into the electrically conductive cover layer (2a), wherein an etching depth (t) of the first and second recess (4, 5) is selected such that the second recess (5) at the head side at least to the insulation layer (2b) protrudes and a second angle (β) between the side walls of the second recess (5a) and a plane in which the insulating layer (2b) is located, of about 125.3 ° results. Method according to the preceding claim, wherein by etching the first and second recesses (4, 5) the edge-side connecting element (9) and the inner sectionally defined electrode (3) are produced in the electrically conductive cover layer (2a) and the connecting element (9 ) Is separated by the first and second recess (4, 5) of the inner electrode (3), in particular electrically. Method according to Claim 1 wherein the electrode layer (2) is provided by at least one electrically conductive layer comprising a semiconductor material, in particular a silicon, and the first and second recesses (4, 5) are etched into the electrically conductive layer by means of the two-stage etching process, wherein an etching depth ( t) of the first and second recess (4, 5) is selected such that on the second surface of the electrode layer (2ab), the inner sectionally defined electrode (3) is generated, which is preferably at least a width of 50%, particularly preferably of 60 % with respect to a total width of the electrode layer (2). Method according to the preceding claim, wherein by etching the first and second recess (4, 5) in the electrode layer (2) edge-side connecting element (9) is generated and the connecting element (9) is electrically connected to the inner electrode (3) , Method according to one or more of the preceding claims, wherein for the anisotropic etching process, a reactive Ionenätzverfahren or a variant thereof modified, in particular a reactive lonentiefenätzverfahren is used. Semiconductor-based, in particular capacitive pressure sensor, in particular differential pressure sensor with a plurality of layers arranged on one another, in particular silicon layers, obtainable by the method according to FIG Claim 1 and or Claim 2 or obtainable by the method according to Claim 1 and or Claim 4 , Semiconductor-based, in particular capacitive pressure sensor, in particular differential pressure sensor at least comprising: - a plurality of layers arranged on one another, in particular silicon layers, which comprise at least a first layer (1) and an electrode layer (2); - A in the electrode layer (2) located first recess (4) with respect to a first surface of the electrode layer (2aa) substantially rectangular side walls (4a); - A in the electrode layer (2) to the first recess (4) adjacent the second recess (5) facing away from the first surface second surface of the electrode layer (2ab) towards conically tapered side walls (5a); - At least one in the electrode layer (2) befindliches to the first recess (4) adjacent peripheral edge connecting element (9); a joining layer (6) which inserts the electrode layer (2) via the connecting element (9) with a corresponding edge area located on the first surface of the first layer (1aa), so that the Side walls of the first recess (4a) substantially a first angle (α) of approximately 90 ° to a plane in which the first surface of the first layer (1aa) is formed. Semiconductor-based pressure sensor after Claim 8 , wherein the electrode layer (2) comprises an electrically conductive cover layer (2a), at least one insulating layer (2b) and an electrically conductive Trägerläge (2c), wherein the electrically conductive cover layer (2a) by the at least one insulating layer (2b) of the electrically conductive support layer (2c) is separated, and the first and second recesses (4, 5) are etched in the electrically conductive cover layer (2a), wherein an etching depth (t) of the first and second recesses (4, 5) is dimensioned such in that the second recess (5) protrudes at least towards the insulating layer (2b) on the head side, and a second angle (β) between the side walls of the second recess (5a) and a plane in which the insulating layer (2b) lies is approximately 125 , 3 ° results. Semiconductor-based pressure sensor according to the preceding claim, wherein the electrically conductive cover layer (2a) has an edge-side connecting element (9) and the inner sectionally defined electrode (3), wherein the connecting element (9) through the first and second recess (4, 5) of the internal electrode (3), in particular electrically separated. Semiconductor-based pressure sensor after Claim 8 wherein the electrode layer (2) comprises an electrically conductive layer comprising a semiconductor material, in particular a silicon, wherein the first and second recesses (4, 5) are etched into the electrically conductive layer and an etching depth (t) of the first and second recesses ( 4, 5) is dimensioned such that on the second surface of the electrode layer (2ab) the sectionally defined electrode (3) is generated, wherein the electrode preferably at least a width of 50%, particularly preferably of 60% with respect to a total width of Electrode layer (2) occupies. Semiconductor-based pressure sensor according to the preceding claim, wherein the edge-side connecting element (9) and the sectionally defined electrode (3) are electrically connected.

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