DE102017101471A1 - SYNCHRONOUS COMMUNICATION FROM SLAVE TO SLAVE - Google Patents

Abstract

Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, concatenated network. Slave nodes can provide upstream or downstream data directly to or from other slave nodes without first having to route data slots through the master node.

Description

CROSS-REFERENCE TO RELATED APPLICATION

 The present application claims priority to US Provisional Patent Application No. 62 / 289,051, filed Jan. 29, 2016, entitled "SYNCHRONOUS SLAVE-TO-SLAVE COMMUNICATIONS". This priority application is hereby incorporated by reference in its entirety.

STATE OF THE ART

 With decreasing size of electronic components and increasing performance expectations, more components are being incorporated into previously uninstrumented or less instrumented devices. In some environments, the communication infrastructure used to exchange signals between these components (e.g., in a vehicle) has thick and heavy cable bundles.

BRIEF DESCRIPTION OF THE DRAWINGS

 By referring to the following detailed description in conjunction with the accompanying drawings, embodiments will be readily understood. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

1 FIG. 10 is a block diagram of an exemplary two-wire communication system according to various embodiments. FIG.

2 FIG. 12 is a block diagram of a node transceiver operating in a node of the system of FIG 1 may be included, according to various embodiments.

3 is a representation of a part of a communication in the system of 1 used synchronization control frame according to various embodiments.

4 is a representation of one for communication in the system of 1 used superframes according to various embodiments.

5 shows exemplary formats for a synchronization control frame in various modes of operation of the system 1 according to various embodiments.

6 shows exemplary formats for a synchronization control frame in various modes of operation of the system 1 according to various embodiments.

7 FIG. 14 is a block diagram of various components of the bus protocol circuits of FIG 2 according to various embodiments.

8th - 11 show examples of information exchange on a two-wire bus according to various embodiments of the bus protocols described herein.

12 FIG. 12 shows a ring topology for the two-wire bus and a unidirectional communication scheme thereon according to various embodiments. FIG.

13 schematically shows a device that in the system of 1 can serve as a node or host, according to various embodiments.

14 FIG. 12 shows an example of information exchange on a two-wire bus according to various embodiments of the bus protocols described herein.

15 FIG. 10 is a block diagram of an arrangement in which a slave node is coupled to an energy storage device and a peripheral device, according to various embodiments.

16 shows an embodiment of the system of 1 together with a flowchart of a method that may be performed by a host to selectively route audio in the system.

17 FIG. 10 is a flowchart of a method performed by a slave node during the selective routing of audio in the system as in FIG 16 can be embodied in accordance with various embodiments.

18 shows an embodiment of the system of 1 in which a slave node has a wireless transceiver as a peripheral device.

19 shows an embodiment of the system of 1 in which a host is coupled to a wireless transceiver.

20 - 23 show exemplary arrangements of a microphone, a microphone cable and an audio receiving device, which in the system of 1 may be included, according to various embodiments.

24 shows an arrangement in which a slave node is in the vicinity of an antenna coupled to a roof of a vehicle, according to various embodiments.

25 shows an arrangement of several types of audiovisual equipment as slave nodes in the system of 1 according to various embodiments.

26 shows a robot arm and an arrangement of the system of 1 to facilitate communication between sensors and actuators of the robotic arm according to various embodiments.

27 Figure 13 is a block diagram of an arrangement of components of the system 100 with send and receive mailboxes according to various embodiments.

28 FIG. 12 shows an arrangement of slave nodes and associated peripheral devices in a vehicle according to various embodiments. FIG.

29 FIG. 12 is a block diagram of an arrangement of elements of the system of FIG 1 and a bus monitor according to various embodiments.

30 FIG. 10 is a flowchart of a method for starting the operation of a bus monitor according to various embodiments.

31 gives an example of how upstream data slots can be used for slave to slave communication, according to various embodiments.

32 - 35 show UPMASKn registers with which slave to slave communication can be supported, according to various embodiments.

36 FIG. 10 shows a local upstream slot offset register with which slave to slave communication can be supported, according to various embodiments.

37 gives an example of how downstream data slots may be used for slave to slave communication, according to various embodiments.

38 - 41 show DNMASKn registers with which slave to slave communication can be supported, according to various embodiments.

42 FIG. 10 shows a local downstream slot offset register with which slave to slave communication may be supported, according to various embodiments.

43 FIG. 12 shows a local downstream slot register and its bit descriptions that can support slave to slave communication, according to various embodiments.

44 and 45 show non-slave-to-slave arrangements (left) and slave-to-slave arrangements for various communication scenarios according to various embodiments.

46 - 55 show an example of slave to slave communication on a multi-node daisy-chain bus according to various embodiments.

56 - 65 show another example of slave to slave communication on a multi-node daisy-chain bus according to various embodiments.

DETAILED DESCRIPTION

 With decreasing size of electronic components and increasing performance expectations, more components are being incorporated into previously uninstrumented or less instrumented devices. This trend towards increased instrumentation has conventionally been limited by the communication infrastructure used to exchange signals between components. For example, the proliferation of sensors such as microphones, cameras, etc. in automobiles (and other closed and / or mobile systems such as robotic systems) has resulted in an excessive amount of wiring between components. This excessive wiring is accompanied by an increase in system complexity and weight and a decrease in efficiency and reliability.

Described herein are communication systems that provide low latency TDM (Time Division Multiplexing) communication over a two-wire bus (e.g., a twisted pair). In these systems bidirectional synchronous data (eg, digital audio), clock and synchronization signals can be provided through the two-wire bus, which supports direct point-to-point connections between nodes on the bus, and allows multiple concatenated nodes to be connected at different locations. Contribute or consume channel content. These communication systems allow for downstream traffic (e.g., from a master node to a last slave node), upstream traffic (e.g., to a master node from a slave node), and power transmission over the same two-wire bus.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, wherein like numerals indicate like parts throughout, and in which is shown by way of illustration embodiments which may be practiced. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is therefore not to be interpreted in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn in a manner most helpful to the understanding of the claimed subject matter. However, the order of description should not be construed as inferring that these operations are necessarily order-dependent. In particular, these operations can not be performed in the presentation order. Described operations may be performed in a different order than the described embodiment. In additional embodiments, various additional operations may be performed and / or operations described may be omitted.

For the purposes of the present disclosure, the term "A and / or B" means (A), (B) or (A and B). For the purposes of the present disclosure, the term "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A , B and C).

Various components may be mentioned or illustrated herein in singular form (e.g., a "processor", a "peripheral device", etc.), but this is for convenience of discussion only, and any elements mentioned in the singular may comprise several such elements in accordance with the present teachings.

The description uses the terms "in one embodiment" or "in embodiments", which may each refer to one or more of the same or different embodiments. Further, the terms "comprising,""containing,""having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, the term "circuitry" may refer to or comprise: an application specific integrated circuit (ASIC), an electronic circuit and optical circuit, a processor (shared, dedicated or grouped), and / or a memory ( shared, dedicated or grouped), executing one or more software or firmware programs, a combinational logic circuit, and / or other suitable hardware that provides the described functionality. A master node may also be referred to herein as a master "device"; Similarly, a slave node may be referred to herein as a slave "device".

All of the embodiments described herein may be practiced in accordance with any suitable related embodiments disclosed in any of the prior patent submissions whose priority claims the present application. In particular, any of the embodiments of the Automotive Audio Bus (A2B) system disclosed in any of the prior art submissions may be implemented in any combination with the embodiments described herein. For example, power switching and diagnostics may be included in the two-wire communication systems described herein, as discussed in US Provisional Application No. 61 / 845,542, filed July 12, 2013. In another example, decoders may be included in the two-wire communications systems described herein, as discussed in US Provisional Application No. 61 / 843,902, filed 8/7/2013. In another example, digital phase detectors may be included in the two-wire communication systems described herein, as discussed in US Provisional Application No. 61 / 843,896, filed July 8, 2013. In another example, the two-wire communication systems described herein may include the state machine functionality discussed in US Provisional Application No. 61 / 843,891, filed 8/7/2013.

1 FIG. 10 is a block diagram of an exemplary half duplex two-wire communication system. FIG 100 according to various embodiments. The system 100 includes a host 110 , a master node 102 and at least one slave node 104 , In 1 three slave nodes (0, 1 and 2) are shown. The illustration of three slave nodes 104 in 1 is just an example and the system 100 can have one, two or more slave nodes as desired 104 include.

The master node 102 can via a two-wire bus 106 with the slave nodes 104 communicate. The bus 106 can use different two-wire bus connections between adjacent nodes on the bus 106 to connect the nodes on the bus 106 in a concatenated manner. For example, the bus 106 as in 1 represented a connection comprising the master node 102 to the slave node 0, a link coupling the slave node 0 to the slave node 1, and a link coupling the slave node 1 to the slave node 2. The connections of the bus 106 each may be formed of a single twisted pair (eg, an unshielded twisted pair).

The host 110 may include a processor that is the master node 102 programmed and as the origin and receiver of various on the bus 106 transmitted payload acts. In particular, the host can 110 the master of I2S communication (Inter-Integrated Circuit Sound) being on the bus 106 happens. The host 110 may be via an I2S / TDM bus and / or an I / C (Inter-Integrated Circuit) bus to the master node 102 communicate. In some embodiments, the master node 102 a transceiver (eg, the one referred to below with reference to FIG 2 discussed node transceivers 120 ), which is located in a housing of the host 110 located. The master node 102 can be over the I2C bus for configuration and read back by the host 110 be programmable and can be designed to clock, synchronization and framing for all slave nodes 104 to create. In some embodiments, expansion of the I2C control bus may occur between the host 110 in the master node 102 in the over the bus 106 transmitted data streams are embedded, causing the host 110 directly to registers and status information for the one or more slave nodes 104 It also allows communication from I2C to I2C over distance to it's host 110 to allow the peripherals 108 to control.

The master node 102 may be "downstream signals" (eg, data signals, power signals, etc., sent from the master node 102 away on the bus 106 be transmitted) and "upstream signals" (eg on the bus 106 in the direction of the master node 102 to be transmitted). The master node 102 can be a clock signal for synchronous data transmission over the bus 106 provide. As used herein, "synchronous data" may include data that is continuous with a fixed time interval between two successive transmissions to / from the same node on the bus 106 be streamed (eg audio signals). In some embodiments, this may be done by the master node 102 provided clock signal from a master node 102 through the host 110 derived I2S input. A slave node 104 can be an addressable network connection point that is a possible destination for downstream on the bus 106 or upstream on the bus 106 represents transmitted data frames. One Slave node 104 may also represent a possible source of downstream or upstream data frames. The system 100 can transfer control information and other data in both directions via the bus 106 allow from one node to the next. One or more of the slave nodes 104 You can also go through the bus 106 transmitted signals are supplied with power.

In particular, each of the master node 102 and the slave node 104 a positive upstream port (referred to as "AP"), a negative upstream port (referred to as "ON"), a downstream positive port (referred to as "BP") and a downstream negative port (referred to as "BN") ). The positive and negative downstream ports of a node may be coupled to the positive and negative upstream ports of the adjacent downstream node, respectively. As in 1 shown, the master node 102 include a positive and negative upstream port, but these ports can not be used; in other embodiments, the master node 102 do not include a positive and negative upstream connection. The last slave node 104 on the bus 106 (in 1 the slave node 2) may include a positive and negative downstream port, but these ports can not be used; in other embodiments, the last slave node 104 on the bus do not include a positive and negative downstream connection.

As will be discussed in detail below, the master node 102 periodically send a synchronization control frame downstream, optionally together with data corresponding to one or more of the slave nodes 104 are determined. For example, the master node 102 all 1024 Bit (representing a superframe) with a frequency of 48 kHz will send a synchronization control frame, resulting in an effective bit rate on the bus 106 of 49.152 Mbps. Other rates may be supported, including, for example, 44.1 kHz. The synchronization control frame may be the slave node 104 allow to identify the beginning of each superframe, and also, in combination with physical layer coding / signaling, may allow each slave node 104 allow his internal operating clock off the bus 106 derive. The synchronization control frame may include a preamble for signaling the start of synchronization as well as control fields representing various addressing modes (eg, normal, broadcast, discovery), configuration information (eg, writing to registers of the slave nodes 104 ), Transmission of I2C information, remote control of certain GPIO (multi-purpose input / output) pins to the slave node 104 and other services. A portion of the synchronization control frame following the preamble and payload data may be scrambled to reduce the likelihood that information in the synchronization control frame will be held for a new preamble and to flatten the spectrum of related electromagnetic emissions.

The synchronization control frame can be between the slave node 104 (optionally together with other data provided by the master node 102 but in addition or as an alternative to one or more upstream slave nodes 104 or from a slave node 104 himself can come) until he is the last slave node 104 (ie the slave node 2 in 1 reached by the master node 102 as the last slave node 104 has been configured or itself as the last slave node 104 has identified. Upon receipt of the synchronization control frame, the last slave node may be 104 send a synchronization response frame followed by any data it is allowed to send (eg, a 24-bit audio sample in a designated timeslot). The synchronization response frame can then be upstream between slave nodes 104 (optionally together with data from downstream slave nodes 104 ), and based on the synchronization response frame, each slave node 104 be able to identify any time slot in which the slave node 104 is allowed to send.

In some embodiments, one or more of the slave nodes 104 in the system 100 with a peripheral device 108 be coupled and communicate with it. For example, a slave node 104 be designed as described below using I2S, Pulse Density Modulation (PDM), TDM and / or I2C protocols data from the associated peripheral device 108 to read and / or write data in these. Although the "peripheral device" 108 can be mentioned here in the singular, this is simply for easier discussion, and a single slave node 104 may be coupled to zero, one or more peripheral devices. Examples of peripheral devices included in the peripheral device 108 may include a DSP (Digital Signal Processor), a FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), an ADC (Analog to Digital Converter), a DAC (Digital to Analog Converter) Codec, a microphone, a microphone array, a speaker, an audio amplifier, a protocol analyzer, an accelerometer or other motion sensor, an ambient condition sensor (eg, a temperature, humidity and / or gas sensor), a wired or wireless communication transceiver, a display device ( eg a Touchscreen display), a user interface component (eg, a button, dial, or other control), camera (eg, a video camera), storage device, or any other suitable device that transmits and / or receives data. Several examples of various peripheral device configurations are discussed in detail here.

In some embodiments, the peripheral device 108 include any device configured for Inter-Integrated Circuit Sound (I2S) communication; the peripheral device 108 can over the I2S protocol with the assigned slave node 104 communicate. In some embodiments, the peripheral device 108 include any device configured for Inter-Integrated Circuit Sound (I2C) communication; the peripheral device 108 can over the I2C protocol with the assigned slave node 104 communicate. In some embodiments, a slave node 104 with no peripheral device 108 be coupled.

A slave node 104 and its associated peripheral device 108 may be contained in separate housings and coupled by means of a wired or wireless communication link or may be contained in a common housing. For example, as a peripheral device 108 connected speaker with the hardware for an associated slave node 104 (eg, those referred to below with reference to 2 discussed node transceiver 120 ), so that the hardware for the associated slave node 104 contained in a housing containing other speaker components. The same may apply to any type of peripheral device 108 be valid.

As discussed above, the host can 110 using multi-channel I2S and I2C communication protocols with the master node 102 communicate and control him. In particular, the host can 110 via I2S data to a (not shown) frame buffer in the master node 102 send, and the master node 102 can read data from the frame buffer and the data on the bus 106 send. Analogously, the master node 102 over the bus 106 store received data in the frame buffer and then transfer the data to the host via I2S 110 send.

Every slave node 104 can have internal control registers that are controlled by submissions from the master node 102 can be configured. In the following, a number of such registers will be discussed in detail. Every slave node 104 can receive downstream data and resend the data further downstream. Every slave node 104 may receive and / or generate upstream data and / or forward data upstream and / or add data to an upstream transaction.

Communication on the bus 106 can be done in periodic superframes. Each superframe may begin with a downstream synchronization control frame; in periods of downstream transmission (also referred to as "downstream parts"), upstream transmission (also referred to as "upstream parts") and no transmission (the bus 106 not controlled); and shortly before the transmission of another downstream synchronization control frame. The master node 102 can (by the host 110 ) with a number of downstream parts leading to one or more of the slave nodes 104 and a number of upstream parts for receiving one or more of the slave nodes 104 be programmed. Every slave node 104 can (through the master node 102 ) with a number of downstream parts representing the bus 106 down to a number of downstream parts to be consumed, a number of upstream parts containing the bus 106 to be forwarded, and a number of upstream parts in which the slave node 104 from the slave node 104 from the associated peripheral device 108 received data can be programmed. Communication on the bus 106 will be described in more detail below with reference to 2 - 12 discussed.

Each of the master node 102 and the slave node 104 A transceiver can be used to manage communication between components of the system 100 include. 2 is a block diagram of a node transceiver 120 which is in a node (eg the master node 102 or a slave node 104 ) of the system 100 from 1 may be included, according to various embodiments. In some embodiments, in each of the nodes of the system 100 a node transceiver 120 and the node transceiver 120 may be supplied via a master or MSTR pin, a control signal to indicate whether the node transceiver 120 as master (eg if the MSTR pin is high) or slave (eg if the MSTR pin is low) should act.

The node transceiver 120 can be an upstream transceiver 122 and a downstream transceiver 124 include. The upstream transceiver 122 can with the above with respect to 1 coupled positive and negative upstream connection and the downstream transceiver 124 can with the above with respect to 1 coupled positive and negative downstream connection. In some embodiments, the upstream transceiver may 122 and the downstream transceiver 124 each Differenzsignalisierungs- or DS transceiver be. In some embodiments, the upstream transceiver may 122 a low voltage DS or LVDS transceiver, and the downstream transceiver 124 may be an LVDS transceiver. Every node in the system 100 can by bus 106 AC coupled, and data signals can be on the bus 106 (eg via the upstream transceiver 122 and / or the downstream transceiver 124 ) using a predetermined form of DS (eg LVDS or Multipoint LVDS (MLVDS) or similar signaling) with appropriate coding to provide timing information over the bus 106 (eg, differential Manchester encoding, biphase tag coding, Manchester coding, non-return-to-zero, inverted (NRZI) encoding, or any other suitable coding). In some embodiments, the bus may 106 provided by a coaxial cable, and the upstream and downstream signals may be asymmetrical signals driving the coaxial cable.

The upstream transceiver 122 and the downstream transceiver 124 can with the bus protocol circuits 126 communicate, and the bus protocol circuits 126 can in addition to other components with a phase locked loop (PLL) 128 and voltage regulator circuits 130 communicate. If the node transceiver 120 can be powered up, the voltage regulator circuits 130 put a signal "power supply good" from the PLL 128 is used as a power-on reset.

As mentioned above, one or more of the slave nodes 104 in the system 100 Power received simultaneously with data on the bus 106 is transmitted. For power distribution (which is optional because some of the slave nodes 104 can be designed to be supplied only local power supply), the master node 102 a DC bias on the bus connection between the master node 102 and 0 to the slave node (eg by connecting one of the downstream ports to a voltage source provided by a voltage regulator and the other downstream to ground). The DC bias may be a predetermined voltage, such as 5V, 8V, the voltage of a car battery, or a higher voltage. Each successive slave node 104 may selectively tap its upstream bus connection (eg, using the voltage regulator circuits 130 ) Recover power. With this power supply you can use the slave node 104 itself (and optionally one or more with the slave node 104 coupled peripheral devices 108 ) provide power. A slave node 104 can also selectively connect the bus downstream for the next slave node 104 in the line either with the recovered power supply from the upstream bus connection or from a local power supply. For example, slave node 0 may receive the DC bus on the upstream bus connection 106 use to supply power to the slave node 0 itself and / or to one or more associated peripheral devices 108 regain and / or the slave node 0 can supply power from its upstream bus connection 106 regain its downstream bus connection 106 pretension.

Thus, in some embodiments, each node in the system may 100 supply power to the following downstream node via a downstream bus connection. The power supply of nodes can be performed in a sequenced manner. After discovering and configuring slave node 0 over the bus 106 can be the master node 102 For example, instruct slave node 0, its downstream bus connection 106 Supplying power to power the slave node 1; After the slave node 1 is discovered and configured, the master node 102 instruct the slave node 1, its downstream bus connection 106 Supply power to supply power to the slave node 2 (and so on) for additional to the bus 106 coupled slave nodes 104 , In some embodiments, one or more of the slave nodes 104 be powered locally instead of being supplied with power from or in addition to their upstream bus connection. In some such embodiments, one can use the local power source for a given slave node 104 power one or more downstream slave nodes.

In some embodiments, upstream filtering circuitry may be provided 132 between the upstream transceiver 122 and the voltage regulator circuits 130 be arranged, and downstream filtering circuits 131 can be between the downstream transceiver 124 and the voltage regulator circuits 130 be arranged. As every connection of the bus 106 Can carry AC (signal) and DC (power) components, the upstream filtering circuits 132 and the downstream filtering circuits 131 disconnect the AC and DC components, the AC components to the upstream transceiver 122 and the downstream transceiver 124 feed and the DC components to the voltage regulator 130 respectively. AC couplings on the line side of the upstream transceiver 122 and downstream transceiver 124 essentially isolate the transceivers 122 and 124 from the DC component on the line to allow fast bidirectional communication. As discussed above, the DC power component may be tapped and the upstream filtering circuitry may be tapped 132 and the downstream filtering circuits 131 For example, a ferrite, a common mode choke, or an inductor may be included around the voltage regulator circuits 130 to reduce supplied AC component. In some embodiments, the upstream filtering circuitry may 132 in the upstream transceiver 122 contained, and / or the downstream filtering circuits 131 can in the downstream transceiver 124 be included; in other embodiments, the filtering circuitry may be external to the transceivers 122 and 124 are located. Backflow can be from the upstream filtering circuits 122 and the downstream filtering circuits 131 provided by a VSSN terminal provided by the node transceiver 120 through to VSS (eg ground). The upstream filtering circuits 132 and the downstream filtering circuits 131 may include DC voltage connections for both power connection and reverse connection.

The node transceiver 120 can be a transceiver 127 for I2S, TDM and PDM communication between the node transceiver 120 and an external device 155 include. Although the "external device 155 Can be mentioned here in the singular, this is simply for ease of illustration and there may be multiple external devices via the I2S / TDM / PDM transceiver 127 with the node transceiver 120 communicate. As is known in the art, the I2S protocol is used to carry pulse code modulated (PCM) information (eg, between audio chips on a circuit board). As used herein, "I2S / TDM" may refer to an extension of the I2S stereo (two-channel) content to multiple channels using TDM. As is known in the art, PDM may be used in sigma-delta converters, and in particular, the PDM format may represent an over sampled 1-bit sigma-delta ADC signal prior to decimation. The PDM format is often used as the output format for digital microphones. The I2S / TDM / PDM transceiver 127 can deal with the bus protocol circuits 126 and pins for communication with the external device 155 are in communication. In 2 there are six pins BCLK, SYNC, DTX [1: 0] and DRX [1: 0]; the BCLK pin can be used for an I2S-bit clock, the SYNC pin can be used for an I2S frame synchronization signal and the pins DTX [1: 0] and DRX [1: 0] are used to send and receive Data channels used. Although in 2 two send pins (DTX [1: 0]) and two receive pins (DRX [1: 0]) are shown, any desired number of receive and / or transmit pins can be used.

If the node transceiver 120 in the master node 102 is included, the external device 155 the host 110 and the I2S / TDM / PDM transceiver 127 can (in terms of BCLK and SYNC) provide an I2S slave that receives data from the host 110 received and data in sync with an I2S interface clock of the host 110 to the host 110 can send. In particular, an I2S frame synchronization signal on the SYNC pin may be input from the host 110 be received, and the PLL 128 can generate clocks with this signal. If the node transceiver 120 in a slave node 104 is included, the external device 155 one or more peripheral devices 108 and the I2S / TDM / PDM transceiver 127 can provide an I2S clock master (for BCLK and SYNC), I2S communication with the peripheral device 108 can control. In particular, the I2S / TDM / PDM transceiver may 127 provide an I2S frame sync signal on the SYNC pin as output. Register in the node transceiver 120 can determine which and how many I2S / TDM channels as data slots over the bus 106 be sent. A register for the TDM mode (TDMMODE) in the node transceiver 120 may store a value of how many TDM channels will fit between consecutive SYNC pulses on a TDM transmit or receive pin. Together with knowledge of the channel size, the node transceiver can 120 automatically set the BCLK rate to match the amount of bits in the sample time (eg 48 kHz).

The node transceiver 120 can be a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157 include. Although the "external device 157 May be mentioned here in the singular, this is for ease of illustration only, and there may be multiple external devices via the I2C transceiver 129 with the node transceiver 120 communicate. As is known in the art, the I2C protocol uses clock (SCL) and data (SDA) lines to provide data transfer. The I2C transceiver 129 can deal with the bus protocol circuits 126 and pins for communication with the external device 157 are in communication. In 2 four pins ADR1, ADR2, SDA and SCL are shown; ADR1 and ADR2 can be used to modify the I2C addresses that the node transceiver 120 used when the node transceiver 120 acting as an I2C slave (eg if it is in the master node 102 is included), and SDA and SCL are used for I2C serial data or serial clock signals. If the node transceiver 120 in the master node 102 is included, the external device 157 the host 110 and the I2C transceiver 129 can provide an I2C slave, the programming instructions from the host 110 can receive. In particular, a serial I2C clock signal may be input to the SCL pin as an input from the host 110 for register accesses. If the node transceiver 120 in a slave node 104 is included, the external device 157 a peripheral device 108 and the I2C transceiver 129 may provide an I2C master to allow the I2C transceiver to program one or more peripheral devices in accordance with instructions provided by the host 110 provided and over the bus 106 to the node transceiver 120 be sent. In particular, the I2C transceiver may 129 provide the serial I2C clock signal to the SCL pin as output.

The node transceiver 120 may be an interrupt request or IRQ pin in communication with the bus protocol circuits 126 include. If the node transceiver 120 via the I2C transceiver 129 in the master node 102 may contain the bus protocol circuits 126 event-driven interrupt requests towards the host via the IRQ pin 110 provide. If the node transceiver 120 in a slave node 104 is included (eg, when the MSTR pin is low), the IRQ pin may serve as a GPIO pin with interrupt request capability.

The system 100 can work in any of a number of different modes of operation. The nodes on the bus 106 may each have a register indicating which mode of operation is currently enabled. Below are descriptions of examples of different operating modes that can be implemented. In a standby mode, bus activity is reduced to allow global power savings; the only traffic required is a minimum downstream preamble for synchronizing the PLL of each node (eg, the PLL 128 ). In standby mode, read and write operations occur over the bus 106 unsupported. In a discovery mode of operation, the master node may 102 predetermined signals on the bus 106 send out and wait for appropriate answers to the topology of the bus 106 distributed slave nodes 104 to map. In a normal mode of operation, full register access to and from the slave nodes may occur 104 and access to and from peripheral devices 108 over the bus 106 be available. The normal mode can be global by the host 110 with or without synchronous upstream data and with or without synchronous downstream data.

3 is an illustration of part of a synchronization control frame 180 that communicates in the system 100 is used according to various embodiments. In particular, the synchronization control frame may 180 as discussed below for data clock recovery and PLL synchronization. Because communication over the bus 106 may take place in both directions, as mentioned above, communication may be multiplexed in time to downstream parts and upstream parts. In a downstream part, a synchronization control frame and downstream data from the master node 102 while in an upstream part, a synchronization response frame and upstream data from each of the slave nodes 104 to the master node 102 can be sent. The synchronization control frame 180 can be a preamble 182 and control data 184 include. Every slave node 104 can be designed to the preamble 182 of the received synchronization control frame 180 as a time base for dining the PLL 128 to use. To make this possible, a preamble follows 182 not the "rules" of valid control data 184 and thus can easily from the control data 184 be differentiated.

For example, in some embodiments, communication may be on the bus 106 using a differential Manchester encoding scheme of type clock first, transition to zero. According to such a coding scheme, each bit time starts with one clock transition. If the data value is zero, the coded signal transitions again in the middle of the bit time. If the data value is one, the encoded signal does not recur. In the 5 illustrated preamble 182 may violate the encoding protocol (eg, having clock transitions that do not occur at the beginning of bit times 5, 7, and 8), which means that the preamble 182 with no legal (eg correctly coded) pattern for the control data 184 can match. In addition, the preamble 182 can not be reproduced by a legal pattern of control data 184 taken and the bus 106 is forced high or low for a single bit time or for a multiple bit duration. In the 5 illustrated preamble 182 is merely exemplary, and the synchronization control frame 180 can other preambles 182 include, in any suitable manner against the control data 184 used coding can violate.

The bus protocol circuits 126 may include differential Manchester decoder circuitry resident on one of the bus 106 the recovered clock and the synchronization control frame 180 detect a frame sync indicator to the PLL 128 to send. In this way, the synchronization control frame 180 can be detected without using a system clock or a faster oversampling clock. Consequently, the slave nodes 104 a PLL synchronization signal from the bus 106 received without a crystal clock source to the slave node 104 to require.

As mentioned, communication can be on the bus 106 occur in periodic superframes. 4 is a representation of a superframe 190 according to various embodiments. As in 6 can show a superframe with a synchronization control frame 180 kick off. When the synchronization control frame 180 as a timing source for the PLL 128 is used, the frequency at which superframes are transmitted ("the superframe frequency") may be the same as the synchronization signal frequency. In some embodiments, where audio data is on the bus 106 the superframe frequency can be the same as that in the system 100 used audio sampling frequency (eg either 48 kHz or 44.1 kHz), but any suitable superframe frequency can be used. Every super frame 190 can be in periods of downstream transmission 192 , Periods of upstream transmission 194 and periods with no transmission 196 (eg if the bus 106 not controlled).

In 4 is the super frame 190 with an initial period of downstream transmission 192 and a later period of upstream transmission 194 shown. The period of the downstream transmission 192 can be a synchronization control frame 180 and X downstream data slots 198 include, where X can be zero. Essentially all the signals on the bus 106 may be line coded, and a synchronization signal downstream from the master node 102 to the last slave node 104 (eg the slave node 104C ) in the form of the synchronization preamble 182 in the synchronization control frame 180 is forwarded, as discussed above. Downstream can synchronous TDM data in the X downstream data slots 198 after the synchronization control frame 180 be included. The downstream data slots 198 can have the same width. As discussed above, the PLL 128 the clock that a node times to communicate over the bus 106 used, deploy. In some embodiments, where the bus 106 is used to transfer audio data, the PLL 128 operate at a multiple of the audio sampling frequency (eg 1024 Time the audio sampling frequency, resulting in 1024-bit clocks in each superframe).

The period of upstream transmission 194 can be a synchronization response frame 197 and Y upstream data slots 199 include, where Y can be zero. In some embodiments, each slave node 104 a part of the downstream data slots 198 consume. The last slave node (eg the slave node 2 in 1 ) can (after a predetermined response time stored in a register of the last slave node) with a synchronization response frame 197 reply. Upstream can synchronous TDM data through each slave node 104 in the upstream data slots 199 right after the synchronization response frame 197 to be added. The upstream data slots 199 can have the same width. A slave node 104 which is not the last slave node (eg, slave nodes 0 and 1 in 1 ), can receive the received synchronization response frame 197 replace with its own upstream response when reading one of its registers in the synchronization control frame 180 of the superframe 190 was requested or if a remote I2C read in the synchronization control frame 180 of the superframe 190 was requested.

The synchronization control frame 180 may begin any downstream transmission as discussed above. In some embodiments, the synchronization control frame may 180 64 bits long, but any other suitable length can be used. The synchronization control frame 180 can as mentioned above with the preamble 182 kick off. In some embodiments, when the synchronization control frame 180 through a slave node 104 to a downstream slave node 104 continues to be sent, the preamble 182 through the sending slave node 104 be generated instead of being sent again.

The control data 184 of the synchronization control frame 180 can include fields used to control transactions over the bus 106 used data. Examples of these fields are discussed below, and some embodiments are in 5 shown. In particular shows 5 exemplary formats for the synchronization control frame 180 in normal mode, I2C mode and discovery mode according to various embodiments. In some embodiments, in standby mode, a completely different preamble may be used 182 or a completely different synchronization control frame 180 be used so that the slave nodes 104 the entire synchronization control frame 180 only have to receive when a transition to normal mode is sent.

In some embodiments, the synchronization control frame may 180 comprise a count or CNT field. The CNT field may be of any suitable length (eg 2 Bit) and may be incremented (modulo the length of the field) from the value used in the previous superframe. A slave node 104 that receives a CNT value that is not expected may be programmed to return an interrupt.

In some embodiments, the synchronization control frame may 180 comprise a node addressing mode (NAM) field. The NAM field may be any suitable length (eg, 2 bits) and may be used to control access to registers of a slave node 104 over the bus 106 be used. In normal mode, registers of a slave node 104 based on the ID of the slave node 104 and the address of the register are read and / or written. Broadcast transactions are writes made by each slave node 104 should be taken. In some embodiments, the NAM field may provide four node addressing modes, including "none" (eg, data to no particular slave node 104 addressed), "normal" (eg data unicast to a specific slave node 104 which is specified in the address field discussed below), "broadcast" (eg to all slave nodes 104 addressed) and "discovery".

In some embodiments, the synchronization control frame may 180 include an I2C field. The I2C field may be of any suitable length (eg 1 bit) and may be used to indicate that the period of downstream transmission 192 includes an I2C transaction. The I2C field may indicate that the host 110 Has given instructions remotely to a peripheral device 108 access with respect to an associated slave node 104 acts as an I2C slave.

In some embodiments, the synchronization control frame may 180 include a node field. The node field may be of any suitable length (eg 4 bits) and may be used to indicate which slave node is being addressed for normal and I2C accesses. In discovery mode, this field can be used to identify a newly discovered slave node 104 in a node ID register of the slave node 104 be programmed. Every slave node 104 in the system 100 can be assigned a unique ID if the slave node 104 through the master node 102 is discovered as discussed below. In some embodiments, the master node has 102 no node id, while the master node 102 in other embodiments may have a node ID. In some embodiments, it is to the master node 102 on the bus 106 connected slave nodes 104 (eg the slave node 0 in 1 ) the slave node 0 and each successive slave node 104 has a number greater by 1 than the previous slave node. However, this is merely exemplary, and any suitable slave node identification system may be used.

In some embodiments, the synchronization control frame may 180 comprise a read / write or RW field. The RW field can be of any suitable length (eg, 1 bit) and can be used to control whether normal accesses are reads (eg, RW == 1) or writes (eg, RW == 0).

In some embodiments, the synchronization control frame may 180 include an address field. The address field may be of any suitable length (eg 8 bits) and may be used to address specific registers of a slave node 104 by the bus 106 be used. For I2C transactions, the address field may be replaced with I2C control values such as START / STOP, WAIT, RW and DATA VLD. For discovery transactions, the address field may have a predetermined value (eg, as in 5 shown).

In some embodiments, the synchronization control frame may 180 comprise a data field. The data field may be of any suitable length (eg 8 bits) and may be used for normal, I2C and broadcast writes. The RESPCYCS value multiplied by 4 can be used to determine how many cycles of a newly discovered node between the start of receiving the synchronization control frame 180 and the start of sending the synchronization response frame 197 should be allowed to pass. If the NAM field indicates discovery mode, the node address and data fields discussed below may be encoded as a RESPCYCS value which, when multiplied by a suitable optional multiplier (eg 4), time in bits from the end of the synchronization control frame 180 to start the synchronization response frame 197 angebibt. This can be a newly discovered slave node 104 determine the correct time slot for upstream transmission.

In some embodiments, the synchronization control frame may 180 include a cyclic redundancy check (CRC) field. The CRC field can be any suitable length (eg, 16 bits) and can be used to send a CRC value for the control data 184 of the synchronization control frame 180 after the preamble 182 be used. In some embodiments, the CRC may be calculated according to the CCITT CRC error detection scheme.

In some embodiments, at least a portion of the synchronization control frame 180 between the preamble 182 and scrambling the CRC field to lessen the likelihood that a sequence of bits in that interval will be periodic with the preamble 182 matches (and thus by the slave node 104 as the beginning of a new superframe 190 can be misinterpreted), and also to reduce electromagnetic emissions as mentioned above. In some such embodiments, the CNT field of the synchronization control frame 180 scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Various embodiments of the system described herein 100 can omit scrambling.

Other techniques can be used to ensure that the preamble 182 uniquely by the slave nodes 104 can be identified, or to reduce the likelihood that the preamble 182 at another location in the synchronization control frame 180 in addition to or instead of techniques such as scrambling and / or error coding as discussed above. For example, a longer synchronization sequence may be used so as to reduce the likelihood that a particular encoding of the remainder of the synchronization control frame 180 agrees with her. Additionally or alternatively, the remainder of the synchronization control frame may be structured such that the synchronization sequence can not occur, such as by placing fixed "0" or "1" values on appropriate bits.

The master node 102 can read and write requests to the slave nodes 104 send, including both for communication on the bus 106 specific requirements as well as I2C requirements. For example, the master node 102 Read and Write requests (specified using the RW field) (using the NAM and Node fields) to one or more designated slave nodes 104 send and can indicate if the request is for the bus 106 specific request for the slave node 104 , an I2C request for the slave node 104 or an I2C request that is to one with the slave node 104 at one or more I2C ports of the slave node 104 paired I2C-compatible peripheral device 108 is to forward.

Now with respect to upstream communication, the synchronization response frame can 197 start each upstream transmission. In some embodiments, the synchronization response frame may 197 a length of 64 Bit, but any other suitable length may be used. The synchronization response frame 197 may also include a preamble, as above with respect to the preamble 182 of the synchronization control frame 180 discussed, followed by a data part. At the end of a downstream transmission, the last slave node 104 on the bus 106 wait until the RESPCYCS counter has expired, and then transmit a synchronization response frame 197 start upstream. If an upstream slave node 104 the destination of a normal read or write transaction may be a slave node 104 its own synchronization response frame 197 generate and replace that received from downstream. If any slave node 104 no synchronization response frame at the expected time 197 from a downstream slave node 104 sees, generates the slave node 104 its own synchronization response frame 197 and start sending it upstream.

The data part of the synchronization response frame 197 may include fields containing data that provide response information to the master node 102 be returned. Examples of these fields are discussed below, and in 6 some embodiments are shown. In particular shows 6 exemplary formats for the synchronization response frame 197 in normal mode, I2C mode and discovery mode according to various embodiments.

In some embodiments, the synchronization response frame may 197 comprise a count or CNT field. The CNT field may be any suitable length (eg 2 bits) and may be used to transmit the value of the CNT field in the previously received synchronization control frame 180 be used.

In some embodiments, the synchronization response frame may 197 include an acknowledgment or ACK field. The ACK field may be of any suitable length (eg 2 Bit) and can be through a slave node 104 be inserted to one in the previous synchronization control frame 180 received command to confirm if this slave node 104 the synchronization response frame 197 generated. Exemplary indicators that can be transmitted in the ACK field would be Waiting, Confirming, Not Confirming (NACK) and Retrying. In some embodiments, the ACK field may be for transmission of an acknowledgment by a slave node 104 be measured to have received and processed a broadcast message (eg by sending a broadcast acknowledgment to the master node 102 is sent). In some embodiments, a slave node 104 also specify if the slave node 104 Has data to send (such as could be used for on-demand upstream transmissions, such as keypad or touchscreen non-TDM inputs, or prioritized upstream transmission, such as when the slave node 104 would like to report an error or emergency condition).

In some embodiments, the synchronization response frame may 197 include an I2C field. The I2C field may be any suitable length (eg, 1 bit) and may be used to transmit the value of the I2C field in the previously received synchronization control frame 180 be used.

In some embodiments, the synchronization response frame may 197 include a node field. The node field may be any suitable length (eg 4 bits) and may be used to send the ID of the slave node 104 be used, the synchronization response frame 197 generated.

In some embodiments, the synchronization response frame may 197 comprise a data field. The data field may be of any suitable length (eg 8 bits) and its value may depend on the type of transaction and the ACK response of the slave node 104 depend on the synchronization response frame 197 generated. For discovery transactions, the data field may include the value of the RESPCYCS field in the previously received synchronization control frame 180 include. If the ACK field indicates a NACK or if the synchronization response frame 197 responds to a broadcast transaction, the data field may receive a broadcast acknowledgment (BA) indicator (in which the last slave node 104 indicate whether the broadcast write was received without error), a Discovery Error (or Indicator) indicator (indicating whether a newly detected slave node 104 in a discovery transaction with an existing slave node 104 and a CRC error indicator (indicating whether a NACK was caused by a CRC error).

In some embodiments, the synchronization response frame may 197 include a CRC field. The CRC field can be any suitable length (eg 16 bits) and can be used to send a CRC value for the part of the synchronization response frame 197 between the preamble and the CRC field.

In some embodiments, the synchronization response frame may 197 include an interrupt request or IRQ field. The IRQ field may be of any suitable length (eg 1 bit) and may be used to indicate that an interrupt is from a slave node 104 was signaled.

In some embodiments, the synchronization response frame may 197 an IRQ node or IRQNODE field. The IRQNODE field can be of any suitable length (eg 4 bits) and can be used to send the ID of the slave node 104 that signaled the interrupt presented by the IRQ field. In some embodiments, the slave node adds 104 to generate the IRQ field its own ID in the IRQNODE field.

In some embodiments, the synchronization response frame may 197 comprise a second CRC or CRC-4 field. The CRC-4 field may be any suitable length (eg 4 bits) and may be used to send a CRC value for the IRQ and IRQNODE field.

In some embodiments, the synchronization response frame may 197 an IRQ field, an IRQNODE field and a CRC-4 field as the last bits of the synchronization response frame 197 (eg the last 10 bits). As discussed above, these interrupt-related fields may have their own CRC protection in the form of CRC-4 (and thus not protected by the previous CRC field). Every slave node 104 , the master node 102 must signal an interrupt, inserts its interrupt information into these fields. In some embodiments, a slave node 104 with a pending interrupt higher priority than any downstream slave node 104 have, in which an interrupt is pending. The last slave node 104 on the bus 106 (eg the slave node 2 in 1 ) can always fill these interrupt fields. If the last slave node 104 no interrupt pending, may be the last slave node 104 set the IRQ bit to zero and set the IRQNODE field to its node ID and provide the correct CRC-4 value. For convenience, a synchronization response frame may be used 197 which transmits an interrupt, referred to herein as an "interrupt frame".

In some embodiments, at least a portion of the synchronization response frame 197 between the preamble 182 and scrambling the CRC field to reduce emissions. In some such embodiments, the CNT field of the synchronization response frame 197 scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Various embodiments of the system described herein 100 can omit scrambling.

Other techniques can be used to ensure that the preamble 182 uniquely by the slave nodes 104 can be identified, or to reduce the likelihood that the preamble 182 elsewhere in the synchronization response frame 197 in addition to or instead of techniques such as scrambling and / or error coding as discussed above. For example, a longer synchronization sequence may be used so as to reduce the likelihood that a particular encoding of the remainder of the synchronization control frame 180 agrees with her. Additionally or alternatively, the remainder of the synchronization response frame may be structured such that the synchronization sequence can not occur, such as by placing fixed "0" or "1" values on appropriate bits.

7 Figure 4 is a block diagram of the bus protocol circuits 126 from 2 according to various embodiments. The bus protocol circuits 126 can control circuits 154 for controlling the operation of the node transceiver 120 according to the protocol described here for the bus 106 include. In particular, the control circuits 154 control the generation of synchronization frames for transmission (eg, synchronization control frames or synchronization response frames as discussed above), processing of received synchronization frames, and execution of control operations specified in received synchronization control frames. The control circuits 154 may include programmable registers as discussed below. The control circuits 154 may generate and receive synchronization control frames appropriate to received messages (eg, associated with a synchronization control frame when the bus protocol circuits 126 in a slave node 104 or from an I2C device when the bus protocol circuits 126 in a master node 102 contain) and set the framing to the different operating modes (eg normal, discovery, standby etc.).

If the node transceiver 120 Data for transmission on the bus 106 created, the preamble circuits can 156 be adapted to generate preambles for synchronization frames for transmission and to receive preambles from received synchronization frames. In some embodiments, a downstream synchronization control frame preamble may all 1024 Bit through the master node 102 be sent. As discussed above, one or more slave nodes 104 synchronize with the downstream synchronization control frame preamble and generate from the preamble local phase-locked master clocks.

The circuits 158 to insert the cyclic redundancy check (CRC) may be arranged to generate one or more CRCs for synchronization frames for transmission. Frame / Komprimierschaltkreise 160 may be configured to receive incoming data from the I2S / TDM / PDM transceiver 127 (eg from a transceiver 127 associated frame buffer) and / or the I2C transceiver 129 If necessary, compress the data and optionally generate parity check bits or error correction codes (ECC) for the data. A multiplexer (MUX) 162 may be a preamble from the preamble circuits 156 , Synchronization frames and multiplex data to a stream for transmission. In some embodiments, the transmission stream may be prior to transmission through scrambling circuitry 164 be scrambled.

For example, in some embodiments, the frame / compression circuits 160 apply a floating-point compression scheme. In such an embodiment, the control circuits 154 3 bits to indicate how many repeated sign bits are in the number, followed by a sign bit and N - 4 data bits, where N is the size of the over the bus 106 is to be transferred. The use of data compression can, if desired, be done by the master node 102 be configured.

In some embodiments, the node transceiver may be included in the node transceiver 120 incoming receive stream through the descrambling circuits 166 be descrambled. A demultiplexer (DEMUX) 168 can demultiplex the preamble, sync frame, and data from the receive stream. CRC checking circuits 159 On the receive side, received synchronization frames can check for the correct CRC. When the CRC test circuits 159 a CRC error in an incoming synchronization control frame 180 can identify the control circuits 154 be notified of the error and do not carry any control commands in the control data 184 of the synchronization control frame 180 out. When the CRC test circuits 159 a CRC error in an incoming synchronization response frame 197 can identify the control circuits 154 can be notified about the error and can send an interrupt for transmission to the host 110 in an interrupt frame. DeFrame / Dekomprimierschaltkreise 170 can accept received data, check their parity if necessary, if necessary perform error detection and correction (eg single error correction - double error detection (SECDED)), if necessary decompress the data and send the received data to the I2S / TDM / PDM transceiver 127 (eg a transceiver 127 associated frame buffer) and / or the I2C transceiver 129 write.

As discussed above, upstream and downstream data can be on the bus 106 in TDM data slots in a superframe 190 be transmitted. The control circuits 154 may include registers that manage these data slots on the bus 106 for which a number of examples are discussed below. When the control circuits 154 in a master node 102 can contain the values in these registers by the host 110 in the control circuits 154 be programmed. When the control circuits 154 in a slave node 104 can contain the values in these registers through the master node 102 in the control circuits 154 be programmed.

In some embodiments, the control circuitry may 154 include a register for downstream slots (DNSLOTS). If the node transceiver 120 in the master node 102 is included, this register can hold the values of the total number of downstream data slots. This register may also define the number of data slots required for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 in the master node 102 be used. In a slave node 104 This register can define the number of data slots, the downstream to the next slave node 104 before or after locally generated downstream slots are added, as discussed in more detail below with respect to LDNSLOTS.

In some embodiments, the control circuitry may 154 comprise a register of local downstream slots (LDNSLOTS). This register can be in the master node 102 be unused. In a slave node 104 This register can define the number of data slots that the slave node 104 use and will not resend. As an alternative, this register may define the number of slots that the slave node 104 to the downstream data link 106 can contribute.

In some embodiments, the control circuitry may 154 include a register for upstream slots (UPSLOTS). In the master node 102 For example, this register may hold the value of the total number of upstream data slots. This register may also define the number of slots that pass through the I2S / TDM / PDM transceiver 127 in the master node 102 used for I2S / TDM transmission. In a slave node 104 For example, this register may define the number of data slots forwarded upstream before the slave node 104 starts to add his own data.

In some embodiments, the control circuitry may 154 comprise a register of local upstream slots (LUPSLOTS). This register can be in the master node 102 be unused. In a slave node 104 This register can define the number of data slots that the slave node 104 to the data received from downstream before being sent upstream. This register may also define the number of data slots required for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 in the slave node 104 is used.

In some embodiments, the control circuitry may 154 comprise a register for broadcast downstream slots (BCDNSLOTS). This register can be in the master node 102 be unused. In a slave node 104 This register can define the number of broadcast data slots. In some embodiments, broadcast data slots may always come at the beginning of the data field. The data in the broadcast data slots can be from multiple slave nodes 104 can be used and managed by all slave nodes 104 regardless of whether they are used or not.

In some embodiments, the control circuitry may 154 comprise a slot format register (SLOTFMT). This register can define the format of data for upstream and downstream transmissions. The data size for the I2S / TDM / PDM transceiver 127 can also be determined by this registry. In some embodiments, valid data sizes include 8, 12, 16, 20, 24, 28, and 32 bits. This register may also include bits for enabling floating point compression for downstream and upstream traffic. If floating point compression is enabled, the I2S / TDM data size may be 4 bits larger than the data size over the bus 106 be. All nodes in the system 100 may have the same values for SLOTFMT when data slots are enabled, and the nodes may be programmed through a broadcast write so that all nodes are updated with the same value.

8th - 11 show examples of information exchange on the bus 106 according to various embodiments of the bus protocols described herein. In particular, show 8th - 11 Embodiments in which each slave node 104 with one or more speakers and / or one or more microphones as the peripheral device 108 is coupled. This is merely exemplary, as any desired arrangement of the peripheral device 108 according to the techniques described herein with each particular slave node 104 can be coupled.

To the beginning shows 8th Signaling and timing considerations for bidirectional communication on the bus 106 according to various embodiments. In the 8th pictured slave node 104 have different numbers of sensor / actuator elements, and thus different amounts of data can be sent to the different slave nodes 104 be sent or received by them. Specifically, the slave node 1 has two elements, the slave node 4 has four elements, and the slave node 5 has three elements, so that the through the master node 102 transmitted data comprises two time slots for the slave node 1, four timeslots for the slave node 4 and three timeslots for the slave node 5. Similarly, slave node 0 has three elements, slave node 2 has three elements, slave node 3 has three elements, slave node 6 has one element, and slave node 7 has four elements, such that these slave nodes 104 upstream transmitted data comprise the appropriate number of time slots. It should be noted that there is no injective correlation between elements and time slots. For example, one in the peripheral device 108 include a digital signal processor containing signals from the three microphones (and possibly also from the master node 102 or from other slave nodes 104 received information) to produce a single sample of data which, depending on the type of processing, could correspond to a single time slot or multiple timeslots.

In 8th sends the master node 102 a synchronization control frame (SCF) followed by data for speakers connected to specific slave nodes 104 (SD) are coupled. Each successive slave node 104 forwards the synchronization control frame and also forwards at least any for downstream slave nodes 104 certain data continues. A specific slave node 104 can forward all data or can for this slave node 104 remove certain data. If the last slave node 104 receives the synchronization control frame sends this slave node 104 the synchronization response frame (SRF), optionally followed by any data representing the slave node 104 to send. Each successive slave node 104 routes the synchronization response frame together with any data from downstream slave nodes 104 and optionally add data from one or more to the particular slave node 104 coupled microphones (MD). In the example of 8th sends the master node 102 Data for slave nodes 1, 4 and 5 (in 8th represented as active speakers) and receives data from slave nodes 7, 6, 3, 2 and 0 (in 8th shown as microphone arrays).

9 - 11 show various exemplary data transfer operations in the system 100 , In 9 - 11 the SCFs are shown as being synchronized in time between adjacent nodes, while the SRFs are shown as being time-delayed between adjacent nodes; this is for ease of illustration only, and both the SCF and the SRF may have similar time delays from node to node. Slot "Y" could also be part of the downstream data.

9 schematically shows the dynamic removal of data from a downstream transmission and insertion of data in an upstream transmission from the standpoint of the downstream transceiver 124 as seen from various embodiments. In 9 sends the master node 102 as in 8th a synchronization control frame (SCF), followed by data for the slave nodes 1, 4 and 5 (SD) in reverse order (eg data for the slave node 5 data for the slave node 4, which data for the slave node 1, etc.) (see the line labeled MASTER). When the slave node 1 receives this transmission, the slave node 1 removes its own data and passes only the data Synchronization control frame, followed by the data for the slave nodes 5 and 4, to the slave node 2 on. The slave nodes 2 and 3 forward the data unchanged (see the line labeled SLAVE 2) so that the data forwarded by slave node 1 is received by slave node 4 (see the row labeled SLAVE 3). The slave node 4 removes its own data and forwards only the synchronization control frame, followed by the data for the slave node 5, to the slave node 5, and similarly the slave node 5 removes its own data and passes only the synchronization control frame to the slave node 6 on. The slave node 6 forwards the synchronization control frame to the slave node 7 (see the row labeled SLAVE 6).

At this point, the slave node 7 sends the synchronization response frame (SRF) followed by its data (see the line labeled SLAVE 6) to the slave node 6. The slave node 6 forwards the synchronization response frame along with the data from slave Node 7 and its own data to the slave node 5 on, and the slave node 5 in turn derives the synchronization response frame together with the data from the slave nodes 7 and 6 to the slave node 4. The slave node 4 has none Add data and thus simply forward the data to the slave node 3 (see the line labeled SLAVE 3), which forwards the data along with its own data to the slave node 2 (see the line labeled SLAVE 2), which in turn forwards the data together with its own data to the slave node 1. The slave node 1 has no data to add and thus forwards the data to the slave node 0, which forwards the data along with its own data. As a result, the master node receives 102 the synchronization response frame, followed by the data from the slave node 7, 6, 3, 2, and 0 (see the row labeled MASTER).

10 shows another example of the dynamic removal of data from a downstream transmission and insertion of data into an upstream transmission from the standpoint of the downstream transceiver 124 as seen in 9 although in 10 the slave nodes 104 both with sensors and actuators as the peripheral device 108 are coupled, so that the master node 102 Data downstream to all slave nodes 104 sends and data from all slave nodes 104 receives back. Also, in 10 the data is ordered on the basis of the node address for which it is intended or from which it originated. The data slot labeled "Y" may be used for data integrity checking or data correction; in some embodiments, the data slot labeled "Y" may additionally or alternatively be included in the downstream data.

11 shows another example of the dynamic removal of data from a downstream transmission and insertion of data into an upstream transmission from the standpoint of the downstream transceiver 124 as seen in 9 although in 11 the data is transmitted downstream and upstream in sequential order rather than reverse order. Buffering in each slave node 104 allows selective addition, removal and / or forwarding of data.

As already discussed, each slave node 104 Remove data from downstream or upstream transmissions and / or add data to downstream or upstream transmissions. Thus, for example, the master node 102 to each of a number of slave nodes 104 send a separate sample of data and each such slave node 104 can remove its data sample and only forward data intended for downstream slaves. In contrast, a slave node 104 Data from a downstream slave node 104 receive and forward the data along with additional data. An advantage of transferring as little information as necessary is the amount of collective through the system 100 to reduce the amount of electricity consumed.

The system 100 can also broadcast broadcasts (and multicast transmissions) from the master node 102 to the slave nodes 104 support, specifically by configuring the downstream slot use of the slave nodes 104 , Every slave node 104 can process the broadcast transmission and send it to the next slave node 104 forward, although a particular slave node 104 "consume" the broadcast message (ie, not broadcast to the next slave node 104 forward) can.

The system 100 can also upstream transfers (eg from a certain slave nodes 104 to one or more other slave nodes 104 ) support. Such upstream transmissions may include unicast, multicast and / or broadcast upstream transmissions. With upstream addressing as discussed above with respect to downstream transmissions, a slave node may be discussed 104 based on the configuration of the upstream slot usage of the slave nodes 104 determining whether data is to be removed from an upstream transmission or not and / or whether an upstream transmission to the next upstream slave node 104 to forward or not. Thus, for example, the data may be passed through a particular slave node 104 to one or more other slave nodes 104 in addition to or instead of forwarding the data to the master node 102 to get redirected. Such slave-slave relationships can, for example, via the master node 102 be configured.

Thus, in various embodiments, the slave nodes 104 act as active / intelligent repeater nodes with the ability to selectively forward, drop and add information. The slave nodes 104 can generally perform such functions without necessarily decoding / examining all data as each slave node 104 knows the relevant timeslot (s) in which it will receive / send data, and therefore can remove data from or add data to a timeslot. Although the slave node 104 The slave nodes may not have to decode / examine all the data 104 typically clock the data they send / forward. This can be the robustness of the system 100 improve.

In some embodiments, the bus may 106 be designed for unidirectional communication in a ring topology. For example, shows 12 an arrangement 1200 with the master node 102 and four slave nodes 104 in a ring topology, showing signaling and timing considerations for unidirectional communication in the array 1200 according to various embodiments. In such embodiments, the transceivers may be 120 in the nodes comprise a receive-only transceiver (MASTER IN) and a transmit-only transceiver (MASTER OUT), rather than two bidirectional transceivers for upstream and downstream communication. At the in 12 The link layer synchronization scheme shown is sent by the master node 102 a synchronization control frame (SCF) 180 , where appropriate, "downstream" data 1202 for the three with different slave nodes 104 coupled speakers (the data for the various speakers may be arranged in any suitable order as described above with reference to FIG 8th - 11 and each successive slave node 104 directs the synchronization control frame 180 together with any "upstream" data from previous slave nodes 104 and "upstream" data from itself to "upstream" data 1204 (For example, the data from the eight different microphones may be arranged in any suitable order as described above with reference to FIG 8th - 11 discussed).

As described here, data may be in any of a number of ways between elements of the system 100 be transmitted. In some embodiments, data may be part of a set of synchronous data slots by a slave node 104 (eg using the data slots 199 ) upstream or through a slave node 104 or a master node 102 (eg using the data slots 198 ) are sent downstream. The volume of such data may be adjusted by changing the number of bits in a data slot or by including additional data slots. Data can also be obtained by inclusion in a synchronization control frame 180 or a synchronization response frame 197 in the system 100 be transmitted. Data transmitted in this way can provide I2C control data from the host 110 (with a response from a slave node 104 associated peripheral device 108 ); Access to registers of the slave nodes 104 (eg for discovery and configuration of slots and interfaces), the write access from the host 110 / Master node 102 to a slave node 104 and read access from a slave node 104 on the host 110 / Master node 102 may include; and event signaling via interrupts from a peripheral device 108 to the host 110 include. In some embodiments, GPIO pins may be used to convey information from a slave node 104 to the master node 102 used (for example, by the master node 102 polling the GPIO pins via I2C or by using a node transceiver 120 a slave node 104 generates an interrupt on an interrupt request pin). For example, in some such embodiments, a host 110 Information about I2C to the master node 102 send and the master node 102 can then send this information to the slave via the GPIO pins. It can handle any of the types of data discussed here, such as those over the bus 106 be transmitted using any one or more of these communication paths. There may be other types of data and data communication techniques in the system 100 be revealed.

Embodiments of the present disclosure may be implemented into a system using any suitable hardware and / or software for configuration as desired. 13 schematically shows a device 1300 that act as a host or node (eg a host 110 , a master node 102 or a slave node 104 ) in the system 100 can serve, according to various embodiments. In 13 is a number of components than in the device 1300 however, any one or more of these components may be omitted or duplicated as appropriate for the application.

In addition, the device can 1300 in various embodiments, one or more of the in 13 components not shown, but the device 1300 may include interface circuitry for coupling to the one or more components. For example, the device may 1300 no display device 1306 but may include display interface circuits (eg, a connector and driver circuits) to which a display device 1306 can be coupled. In another set of examples, the device may 1300 no audio input device 1324 or audio output device 1308 but may include audio input or audio output interface circuitry (eg, connectors and supporting circuitry) to which an audio input device 1324 or audio output device 1308 can be coupled.

The device 1300 may be the node transceiver 120 according to any of the embodiments disclosed herein for managing communication on the bus 106 when the device 1300 by bus 106 coupled. The device 1300 may be a processing device 1302 (eg, one or more processing devices) included in the node transceiver 120 contained or from the node transceiver 120 can be separated. As used herein, the term "processing device" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data stored in registers and / or memory can be stored. The processing device 1302 may include one or more digital signal processors (DSP), application specific integrated circuits (ASIC), central processing units (CPU), graphics processing units (GPU), crypto processors, or any other suitable processing device. The device 1300 can a memory 1304 which may itself comprise one or more memory devices, such as volatile memory (eg dynamic random access memory (DRAM)), nonvolatile memory (eg read only memory (ROM)), flash memory, solid state memory and / or a hard disk.

In some embodiments, the memory may 1304 be used to store a working copy and a permanent copy of programming instructions that cause the device 1300 any suitable one of the techniques disclosed herein. In some embodiments, machine-accessible media (including non-transitory computer-readable storage media), methods, systems, and apparatus for carrying out the techniques described above are illustrative examples of embodiments disclosed herein for communication over a two-wire bus. For example, on computer-readable media (eg the memory 1304 ) Instructions that are stored when passing through one or more in the processing device 1302 contained processing devices, cause the device 1300 performs any of the techniques disclosed herein.

In some embodiments, the device may 1300 another communication chip 1312 (eg one or more other communication chips). The communication chip 1312 may, for example, manage wireless communication to transfer data to and from the device 1300 be designed. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data using modulated electromagnetic radiation via a non-solid medium. It does not follow from the expression that the associated devices do not contain any wires, although in some embodiments they might not include any.

The communication chip 1312 can implement any of several wireless standards or protocols, including, but not limited to, IEEE (Institute for Electrical and Electronic Engineers) standards such as Wi-Fi (Family IEEE 802.11 ), the Standards IEEE 802.16 (eg IEEE 802.16 supplement from 2005), the LTE project (Long-Term Evolution) together with any additions, updates and / or revisions (eg the Advanced LTE project, the UMB project (Ultra Mobile Broadband) (also as "3GPP2"), etc.). With IEEE 802.16 Broadband Wireless Access (BWA) -based networks are commonly referred to as WiMAX networks, which stands for Worldwide Interoperability for Microwave Access, which is a certification grade for products that pass conformance and interoperability checks for the products IEEE 802.16 standards consist. The one or more communication chips 1312 may operate according to a GSM (Global System for Mobile Communication), GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System), HSPA (High Speed Packet Access), E-HSPA (Evolved HSPA) or an LTE network. The one or more communication chips 1312 may operate in accordance with EDGE (Enhanced Data for GSM Evolution), GERAN (GSM EDGE Radio Access Network), UTRAN (Universal Terrestrial Radio Access Network) or E-UTRAN (Evolved UTRAN). The one or more communication chips 1312 can according to CDMA (Code Division Multiple Access), TDMA (Time Division Multiple Access), DECT (Digital Enhanced Cordless Telecommunications), EV-DO (Evolution-Data Optimized) and derivatives thereof, as well as any other wireless protocols identified as 3G, 4G, 5G, and beyond. The communication chip 1312 may work in other embodiments according to other wireless protocols. The device 1300 can an antenna 1322 to enable wireless communication and / or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip 1312 wired communication using a protocol other than the protocol described herein for the bus 106 manage. Wired communication may include electrical, optical, or any other suitable communication protocol. Examples of wired communication protocols passing through the communication chip 1312 could be Ethernet, Controller Area Network (CAN), I2C, Media-Oriented Systems Transport (MOST), or any other suitable wired communication protocol.

As mentioned above, the communication chip 1312 include multiple communication chips. For example, a first communication chip 1312 be dedicated to shorter-range wireless communication, such as Wi-Fi or Bluetooth, and a second communication chip 1312 may be dedicated to longer range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, a first communication chip 1312 dedicated to wireless communication and a second communication chip 1312 can be dedicated to wired communication.

The device 1300 can battery / power supply circuits 1314 include. The battery / power supply circuits 1314 For example, one or more energy storage devices (eg, batteries or capacitors) and / or circuits may be coupled to couple components of the device 1300 with one of the device 1300 separate power source (eg mains power, voltage provided by a car battery, etc.). For example, the battery / power supply circuits 1314 the upstream filtering circuits 132 and the downstream filtering circuits 131 include, with reference to above 2 be discussed, and could by the bias on the bus 106 getting charged.

The device 1300 can be a display device 1306 include (or corresponding interface circuits as discussed above). The display device 1306 For example, it may include any visual indicators such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

The device 1300 may be an audio output device 1308 (or corresponding interface circuits as discussed above). The audio output device 1308 For example, it may include any device that generates an audible indicator, such as speakers, headsets, or earphones.

The device 1300 may be an audio input device 1324 include (or corresponding interface circuits as discussed above). The audio input device 1324 may include any device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (eg, instruments with a Musical Instrument Digital Interface (MIDI) output).

The device 1300 can be a GPS device 1318 (Global Positioning System) (or corresponding interface circuits, as discussed above). The GPS device 1318 may be in communication with a satellite based system and may be a location of the device 1300 received, as is known in the art.

The device 1300 can be another output device 1310 include (or corresponding interface circuits as discussed above). Examples of the other output device 1310 would be an audio codec, a video codec, a printer, a wired or wireless transmitter to provide information to other devices, or an additional storage device. In addition, any suitable peripheral devices discussed herein may be used 108 in the further output device 1310 be included.

The device 1300 can be another input device 1320 include (or corresponding interface circuits as discussed above). Examples of the further input device 1320 An accelerometer, a gyroscope, an imaging device, a keyboard, a cursor control device such as a mouse, a pen, a touchpad, a barcode reader, a QR code reader (Quick Response) or an RFID reader (radio frequency identification). Additionally, any suitable one of the sensors or peripheral devices discussed herein may be used 108 in the further input device 1320 be included.

Any suitable one of the above with respect to the device 1300 described display, input, output, communication or memory devices can be used as the peripheral device 108 in the system 100 serve. As an alternative or in addition, any of the above with respect to the device 1300 described display, input, output, communication or memory devices in a host (eg the host 110 ) or a node (eg a master node 102 or a slave node 104 ).

Decimation to support lower sample rates and use of multiple slots to support higher sampling rates

In some embodiments, the nodes of the bus 106 Support a single audio sample rate high bandwidth (eg 44.1 kHz-48 kHz). However, many digital audio signals can do this through the bus 106 supported full audio spectrum does not always require. For example, some audio noise canceling applications may use the full bandwidth for some of the over the bus 106 do not require transmitted audio signals. By decimating signals that do not require full bandwidth, multiple channels can be "packed" into a single audio stream and independently on the bus 106 to different slave nodes 104 be distributed. For example, a decimated audio stream may include multi-channel noise canceling streams, multi-channel active audio audio, or other lower bandwidth streams. For example, lower sampling rates than 40 kHz may be appropriate for human voice transmission, lower quality audio, and FM radio.

In an isochronous digital audio network (eg the bus 106 ) conventional approaches to providing multiple streams of audio usually require that all streams be provided at a sample rate selected by the needs of the highest audio bandwidth channel. All other channels can be forced to maintain this same high sampling audio rate, and therefore digital throughput can be wasted if this high sampling audio rate is not necessary. Since the overall digital bus throughput is limited, this conventional redundancy can reduce the number of possible channels to be transmitted.

If audio is decimated instead, the bus can 106 Allow transmission of multiple channels of audio in a single audio slot by adding the stream to the master node 102 multiplexed and one or more of the channels in the slave node 104 be listened to or received selectively.

When a digital audio signal has a higher sampling rate than the superframe rate of the bus 106 It is also possible to take the bus 106 to use the higher sampling rate by using the audio signal (eg in multiple data slots in a single superframe 190 ) is transmitted over several channels. For example, a slave node 104 use multiple data slots to transmit at a faster sampling rate than the superframe rate (eg, two data slots to double the superframe rate, four data slots to quadruple the superframe rate, etc.). For example, sampling rates in excess of 48 kHz may be desirable for higher quality audio (eg, professional audio) and DVD audio.

At twice and four times the sampling rates in a slave node 104 can support the master node 102 two or four times the amount of TDM data channels at its sampling frequency interface to the host 110 to use. To increase the sampling rate, multiple whole channels and / or fractions of a channel may be used.

In some embodiments, data may be for a single peripheral device 108 (which with a slave node 104 associated) a plurality of the downstream data slots 198 taking. This data may be, for example, audio data. In some embodiments, data may be from a single peripheral device 108 (the one with the slave node 104 associated) a plurality of the upstream data slots 199 taking. For example, shows 14 an example of information exchange on the two-wire bus 106 according to various embodiments of the bus protocols described herein. As in the line "SEND MASTER" by 14 a downstream data slot may be occupied by loudspeaker data determined for the loudspeaker associated with slave node 1, and two downstream data slots (SD2 (1) and SD2 (2)) may be occupied by loudspeaker data suitable for the associated with slave node 2 speakers are determined. The associated with slave node 2 Loudspeaker can thus receive data at twice the rate of the loudspeaker associated with slave node 1. Analogous use of multiple data slots may be in the upstream data slots 199 occur.

In some embodiments, a particular data slot may slot in the upstream data 199 a first superframe 190 Data from a first peripheral device during this particular data slot in the upstream data slots 199 a second superframe 190 May include data from a second, different peripheral device. For example, after the first sync response frame in the "MASTER RECEIVED" line of 14 2, the first upstream data slot may be occupied by microphone data from the microphone associated with slave node 1 and the second upstream data slot may be occupied by microphone data from microphone A associated with slave node 0 (MD0A). As after the second synchronization response frame in the "MASTER RECEIVED" line of 14 1, the first upstream data slot may again be occupied by microphone data from the microphone associated with slave node 1, but the second upstream data slot may be occupied by microphone data from microphone B associated with slave node 0 (MD0B). The microphone associated with slave node 1 can thus receive data on the bus 106 at twice the rate with slave nodes 104 provide associated microphones. Analogous use of multiple data slots may be in the downstream data slots 198 occur. Even though 14 For example, where multiple peripheral devices associated with the same slave node share a particular upstream data slot, in some embodiments, multiple peripheral devices associated with different slave nodes may share a particular upstream data slot.

As mentioned above, a slave node 104 over an I2S / TDM bus (eg using the I2S / TDM / PDM transceiver 127 of the node transceiver 120 ) with a peripheral device 108 coupled at a rate of less than the superframe rate with the peripheral device 108 communicate. A setting in the slave node 104 can determine by which factor the slave peripheral communication is reduced relative to the superframe rate (eg, by a factor of two, a factor of four, etc.), and several with the slave node 104 coupled peripheral devices 108 (or multiple channels to a single peripheral device 108 ) can become a communication slot between the slave node 104 and the master node 102 divide by time-multiplexing (eg, two peripheral devices 108 when placing data in a given communication slot between the master node 102 and the slave node 104 alternate). In some embodiments, if a peripheral device 108 With "reduced data rate" it takes a long time to get data to the slave node 104 to be returned when the data rate is reduced, the slave node 104 on a whole number of superframes before the time the data is sent to the master node 102 should be sent (where the integer in the slave node 104 is stored), a SYNC signal to the peripheral device 108 send.

In some embodiments, the I2S / TDM / PDM transceiver may 127 of the node transceiver 120 run at a reduced rate relative to the superframe rate. The allowable reduced rates at a 48 kHz superframe rate would be, for example, 24 kHz, 12 kHz, 6 kHz, 4 kHz, 3 kHz, 2.4 kHz, 2 kHz, 1.71 kHz and 1.5 kHz. The node transceiver 127 can send data through the I2S / TDM / PDM transceiver 127 be received upstream or downstream. The I2S / TDM / PDM transceivers 127 different of the slave nodes 104 can run at different rates. In some embodiments, the I2S / TDM / PDM transceiver may 127 of the master node 102 with the highest data rate in the system 100 to run.

In some embodiments, the data slots may be on the bus 106 be designed to be run at a full continuous audio rate (eg 48 kHz) or run at a reduced rate by using data slots for the superframes 190 that do not contain any data, are skipped (eg, if there are only "reduced sample rate" microphone nodes as peripheral devices 108 in the system 100 gives). This approach can save power by reducing the level of activity on the bus 106 is reduced without the channel bandwidth on the bus 106 to enlarge.

In some embodiments, the data slots may be on the bus 106 be designed to be run with a full continuous audio rate, or run at a reduced rate, by bus data slots for a particular slave node 104 be time-split into multiple I2S / TDM channels, with no data slots for superframes 190 to skip. This approach may be advantageous when using different types of peripheral devices 108 with slave nodes 104 on the bus 106 are coupled (eg one with a slave node 104 coupled multi-axis accelerometer, one with another slave node 104 coupled microphone or amplifier node, etc.). This approach can reduce the channel bandwidth on the bus 106 enlarge and save some electricity.

A knot on the bus 106 can have one or more registers (eg in memory 1304 ) for storing configuration information related to reduced rate operation. For example, an I2SRRATE register may define a field RRDIV with which the superframe rate may be divided down to the reduced I2S rate. For example, at a 48 kHz superframe rate, RRDIV may, in some embodiments, be for a reduced rate of 24 kHz, 12 kHz, 6 kHz, 4 kHz, 3 kHz, 2.4 kHz, 2 kHz, 1.71 kHz, or 1.5 kHz be set. The I2SRRATE register may also include a control bit RBUS, with slots of reduced data rate on the bus 106 can be enabled. In some embodiments, the I2SRRATE register may be defined as a master-only, auto-broadcast, to ensure that the value is the same in all nodes of a bus, while in other embodiments this need not be the case.

An I2SRATE register may include a field (eg, a 3-bit field) with which the slave node I2S / TDM rate is selected as an integer multiple of the superframe rate, or is a fraction of the superframe rate. The I2SRATE register may also include a REDUCE bit that handles the handling of RX data in a slave node 104 Increased rate is controlled by pinning reduction or duplication of I2S / TDM data to achieve the superframe rate. A SHARE field may allow sharing of data slots on the bus 106 allow.

An I2SRRCTL register can provide bits to a processing device 1302 of a node is allowed to keep track of a full rate frame containing new reduced rate samples. Setting an ENVLSB bit in the I2SRRCTL register may result in the least significant bit (LSB) of each data channel being set when a new sample is sent, and otherwise being cleared. Setting an ENXBIT bit in the I2SRRCTL register may result in an extra bit being used after the LSB of the data word of each data channel. This extra bit can be set when a new sample is sent and otherwise cleared. In some embodiments, the data word length may be less than the channel widths (eg, a 24-bit data word in a 32-bit I2S channel), and this additional bit may specify new samples (while the remaining bits in the channel still indicate erroneous data can). Setting an ENSTRB bit in the I2SRRCTL register can configure the ADR1 pin as a strobe that indicates the frame where data at a reduced rate is updated. Setting an ENCHAN bit in the I2SRRCTL register for a "full rate" node may configure the node to produce an additional I2S / TDM data channel to indicate the frame where reduced rate data will be updated.

An I2SRRSOFFS register may provide fields necessary to move the SYNC edge in a slave node 104 reduced rate can be used around superframe increments. The RRSOFFSET field of the I2SRRSOFFS register can store a value that is used to move the SYNC edge of a slave node 104 reduced rate used earlier by a number of superframes. With this register, the latency of reduced rate data can be minimized over the bus 106 be transferred if I2S / TDM RECEIVE data more than a superframe 190 Require access time. In some embodiments, in a slave node 104 reduced rate the active SYNC edge two superframes 190 occur before the data to the host 110 or another processor should be sent. Setting RRSOFFSET to N can cause the SYNC edge N superframe to appear earlier. The receive data can still be in the same superframe 190 on the bus 106 regardless of the RRSOFFSET value.

Transfer of auxiliary power and battery power

As already discussed, the slave nodes 104 Powered locally by their own power source and / or can power from the bus 106 extract. In some embodiments, a slave node 104 Extract auxiliary output current to power an amplifier, which can be used as a peripheral device 108 with the slave node 104 is associated to enough audio through the amplifier (and possibly in combination with other amplifiers connected to the same or other slave nodes 104 connected) to generate speakers to drive. The amplifier may be "intelligent" (eg with its own digital signal processing capability) or not (eg without digital signal processing).

Transferring auxiliary power over the bus 106 may be particularly advantageous in emergency situations where the primary local power source for a slave node 104 fails; For example, warning messages or other information can still be transmitted via the audio system in a vehicle. The extracting of auxiliary power from the bus 106 can also eliminate the costs associated with connecting and wiring a local power source to the slave node 104 (for example, in association with an active speaker) are associated.

In addition, in embodiments where the bus 106 Power for the slave nodes 104 delivers, the bus 106 Provide a power that supports local power storage (eg, to charge one or more batteries, capacitors, supercapacitors) and thereby provide additional local or phantom power to power one with a slave node 104 associated peripheral device 108 (eg an audio amplifier) makes it less necessary or unnecessary. In some embodiments, one can with the limited from the bus 106 coming stream a slave node 106 power having a local energy storage device, wherein the energy storage device provides the necessary energy in times of peak power demand while being charged at times of low power demand. This may be particularly advantageous when applied to high crest-factor audio signals. In some embodiments, a local battery may also be in locally powered slave nodes 104 be useful (eg to reduce the wire strength for the local power supply).

15 is a block diagram of an arrangement 1500 in which a slave node 104 with an energy storage device 1502 and a peripheral device 108 (eg a speaker) is coupled. In some embodiments, the slave node 104 Electricity from the bus 106 Extract (as above with reference to 1 and 2 discussed) and can at least partially store this power for storing energy in the energy storage device 1502 use. The energy storage device 1502 may include any suitable energy storage device, such as a capacitor or a battery. In particular, the node transceiver (not shown) may be 120 of the slave node 104 Power supply circuits 1314 for receiving a bias voltage via the bus 106 and for providing energy from the bias voltage for the energy storage device 1502 include. The slave node 104 can the energy storage device 1502 selectively use to the speaker 108 head for. In some embodiments, the slave node 104 the energy storage device 1502 Use selectively to supply power to the bus 106 to lay to another slave node 104 Provide electricity. The energy storage device 1502 may be to an amplifier, a transceiver and / or other components or peripheral devices 108 (eg, a digital signal processor, ADC, DAC, battery management circuitry, etc.).

Nodes with both a speaker and a microphone as peripheral devices

In some embodiments, a slave node 104 with a speaker as a peripheral device 108 (mostly using downstream communication), a microphone as a peripheral device 108 (mostly using upstream communication) or a combination of a speaker and a microphone (using both upstream and downstream communication, such as the bus 106 supported). The number of speakers and microphones for a slave node 104 may vary depending on the application and may be any suitable combination. Here are a number of examples of slave nodes 104 which are associated with both speakers and microphones as peripheral devices. In some of these embodiments, peripheral device communication circuitry (such as the I2S / TDM / PDM transceiver) may be used 127 , the I2C transceiver 129 or one or more GPIO pins with interrupt request capability) of a node transceiver 120 a slave node 104 communicate with at least one speaker and at least one microphone. The host 110 can (via the master node 102 ) Data on the bus 106 push to communicate with these devices and / or (via the master node 102 ) Data from the bus 106 to receive from these devices.

Detection in collisions

In some embodiments, where the system 100 Included in a vehicle is the bus 106 to provide a digital network as an aid to understanding vehicle integrity and severity of an accident during collisions. With microphones and / or other sensors (in the peripheral device 108 include) the state of the environment near the associated slave node 104 and the information collected may be sent upstream or downstream to an application seeking to gather information regarding the safety and integrity of the vehicle. Examples of other observations would include ultrasonic sensors, visual sensors or electromechanical sensors (eg accelerometers and gyros).

conferencing systems

In some embodiments, the system may 100 through a microphone that is connected to a slave node 104 (or multiple slave nodes 106 ), distribute sampled audio to a speaker connected to another slave node 104 (or several other slave nodes 104 ) is associated. For example, the bus 106 provided local microphone information in the vicinity of a vehicle (eg cars, limousines, buses, minivans, aircraft, etc.) distribute so that audio communication between passenger and driver, driver can be provided to back seat or between any pair of locations. Some embodiments of the system 100 can by one with any of the slave nodes 104 associated microphone sampled audio to many other slave nodes 104 in one by the bus 106 broadcast the provided audio network. The bus 106 can also transfer any other data between any two suitable points (eg messages, data files, content streams, etc.).

In some embodiments, a slave node 104 Peripheral device communications circuits (such as the I2S / TDM / PDM transceiver 127 , the I2C transceiver 129 of the node transceiver 120 or one or more GPIO pins with interrupt request capability) for communicating with a microphone and a conferencing user interface element (eg, as peripheral devices 108 ). A user can operate the conferencing user interface element when the user is listening to audio from another person's microphone 106 want to provide coupled device. The conference circuit user interface element may be, for example, a button, a gesture recognition device, a microphone (eg, coupled to a processing device that can perform speech recognition tasks, start / end conference call commands), or a designated part of a touch screen display. Upon actuation of the conferencing user interface element by a user, the slave node may 104 Data from the microphone upstream and / or downstream on the bus 104 for reception and / or reproduction by one or more other devices (eg nodes or the host 110 ) provide. In some embodiments, the host may 110 receive the microphone data and send it to another slave node for playback 104 on the bus 106 route. The slave node 104 may also provide routing of data in response to actuation of the conference circuit user interface element to indicate the source of the microphone data and / or the desired destination (s) for the microphone data.

For example, shows 16 an arrangement 1600 of a host 110 , a master node 102 and two slave nodes 104 and their associated peripheral devices 108 together with a flowchart of a method 1602 that by the host 110 the arrangement 1600 can be executed to selectively audio in the arrangement 1600 to route around. In the arrangement 1600 For example, a slave node 0 may be associated with a single speaker, while the slave node 1 may be associated with a speaker, a microphone, and a button acting as the conference circuit user interface element discussed above. The procedure 1602 can use a "host centric" approach to routing data in the array 1600 represent.

In 1604 can the host 110 provide music 0 to slave node 0. Music 0 represents any desired data stream being routed to slave node 0 during "nominal" operation. In some embodiments, the music may be video data, voice data, or any other suitable data. The host 110 can the music 0 in 1604 over the bus 106 the slave node 0 via the master node 102 using any of the bus protocols disclosed herein.

In 1606 can the host 110 provide music 1 to the slave node 1. The music 1 represents any desired data stream which is routed to the slave node 1 during "nominal" operation. In some embodiments, the music may be video data, voice data, or any other suitable data. The host 110 can the music 1 in 1606 over the bus 106 the slave node 1 via the master node 102 using any of the bus protocols disclosed herein.

In 1608 can the host 110 Receive button data from the slave node 1. The button data may indicate a state of the button (eg, whether the button was pressed by a user). The host 110 can over the bus 106 Button data from the slave node 1 in FIG 1608 over the master node 102 using any of the bus protocols disclosed herein.

In 1610 can the host 110 Receive microphone data from the slave node 1. The microphone data may be audio data detected by the microphone connected to the slave node 1 as peripheral device 108 is associated. The host 110 can input microphone data from the slave node 1 in FIG 1610 over the bus 106 over the master node 102 using any of the bus protocols disclosed herein.

In 1612 can the host 110 determine if the in 1608 Button information received indicates that the button was pressed by a user. If the host 110 in 1612 determines that the button was not pressed, the host can 110 to 1604 return and continue to provide 0 music 0 to the slave node.

If the host 110 in 1612 determines that the button was pressed, the host can 110 to 1614 progress and provide the microphone data from the slave node 1 to the slave node 0. The host 110 may provide the microphone data to the slave node 1 instead of the music 1, with the music 1 for the microphone data being interrupted. The slave node 1 may provide the microphone data to its associated speaker so as to provide the audio collected by the microphone associated with slave node 1 to the speaker associated with slave node 0. The host 110 can the microphone data over the bus 106 the slave node 1 in 1614 over the master node 102 using any of the bus protocols disclosed herein.

In 1616 can the host 110 stop providing music 1 to slave node 1 (to reset the speaker associated with slave node 1 while the microphone associated with slave node 1 sends its data to other devices on the bus) and can then to 1612 return to determine if the button is still pressed. In some embodiments, the host may 110 the volume of the music 1 in 1616 reduce instead of stopping their deployment. In some embodiments, the host may 110 the volume of the music 1 in 1616 mute instead of stopping their deployment.

17 is a flowchart of a method 1700 by the slave node 0 of the arrangement 1600 from 16 during the selective routing of audio around the device 1500 can be performed, according to various embodiments. The procedure 1700 can use a "slave centric" approach to routing data in the array 1600 represent.

In 1702 can the slave node 0 music 0 from the host 110 receive. As above with respect to 1604 the music 0 represents any desired data stream being routed to the slave node 0 during "nominal" operation. In some embodiments, the music may be video data, voice data, or any other suitable data. The host 110 can be the slave node 0 in 1702 over the bus 106 the music 0 over the master node 102 using any of the bus protocols disclosed herein.

In 1704 For example, slave node 0 may provide music 0 to the speaker, which may be a peripheral device 108 is associated with the slave node 0. In response, the speaker may output the music 0 as an audible signal.

In 1706 For example, the slave node 0 may receive button data from the slave node 1. The button data may indicate a state of the button associated with the slave node 1 (eg, whether the button has been pressed by a user). In some embodiments, the slave node 0 may receive the button data directly over the bus 106 received from the slave node 1 (eg, without the data first the master node 102 have to go through). In some embodiments, the slave node 0 may receive the button data via the master node 102 and / or over the host 110 received from the slave node 1. In general, the slave node can be 0 in 1706 receive button data from slave node 1 using any of the bus protocols disclosed herein.

In 1708 For example, the slave node 0 can receive microphone data from the slave node 1. The microphone data may be audio data detected by the microphone as a peripheral device 108 is associated with the slave node 1. In some embodiments, the slave node 0 may receive the microphone data directly over the bus 106 received from the slave node 1 (eg, without the data first the master node 102 have to go through). In some embodiments, the slave node 0 may receive the microphone data via the master node 102 and / or over the host 110 received from the slave node 1. In general, the slave node can be 0 in 1708 using any of the bus protocols disclosed herein, receive microphone data from the slave node 1.

In 1710 slave node 0 can determine whether the in 1706 Button information received indicates that the button was pressed by a user. If the slave node 0 in 1710 determines that the button was not pressed, the slave node 0 can 1702 return and continue the music 0 from the host 110 receive.

If the slave node 0 in 1710 determines that the button has been pressed, the slave node 0 can 1712 progress and provide the microphone data to the speaker associated with the slave node 0. The slave node 0 can provide the microphone data to the speaker instead of the music 0 and interrupt the music for the microphone data. The slave node 0 can then 1710 return to determine if the button is still pressed.

Routing voice calls

In some embodiments, the system may 100 provide a digital audio network for routing incoming and outgoing voice calls from a single receiver (eg, re-routing calls between different locations in a vehicle). By effectively deploying the low-latency downstream and upstream channels, high-quality voice calls can be rerouted in a vehicle in many ways.

In some embodiments, a slave node 104 Peripheral device communications circuits (such as the I2S / TDM / PDM transceiver 127 , the I2C transceiver 129 of the node transceiver 120 or one or more GPIO pins with interrupt request capability) associated with a wireless transceiver as a peripheral device 108 coupled include. The wireless transceiver can receive voice calls and the slave node 104 can represent the voice calls representing data (eg upstream or downstream) on the bus 106 lay.

For example, shows 18 an embodiment of the system 100 in which a wireless transceiver in the peripheral device associated with the slave node 1 108 is included. The slave node 1 may receive voice call data from the wireless transceiver and may transmit it to other devices in the system 100 (upstream and / or downstream) according to any of the bus protocols disclosed herein. The slave node 1 may also receive data from any other devices in the system 100 and provide it to the wireless transceiver for inclusion in an outgoing voice transmission according to any of the bus protocols disclosed herein.

In another example shows 19 an embodiment of the system 100 in which a wireless transceiver 1902 (eg using any suitable communication protocol) with the host 110 is coupled. The host 110 can receive data from the wireless transceiver 1902 and receive them in accordance with any of the bus protocols disclosed herein to other devices in the system 100 provide. The host 110 can also get data from any of the other devices in the system 100 receive and, according to any of the bus protocols disclosed herein, for inclusion in an outgoing voice transmission to the wireless transceiver 1902 provide.

Communication receiver and transmitter

As discussed above with respect to wireless transceivers of voice calls, instead of or in addition to providing speakers and microphones as peripheral devices 108 for slave nodes 104 by bus 106 connected, a slave node 104 also as a peripheral device 108 associated with one or more communication transceivers. Examples of such transceivers would include Bluetooth modules, near-field transceivers, wireless Internet transceivers, Ethernet transceivers, Ethernet Audio Video Bridging (EAVB) transceivers, transceivers used to transmit data in Internet of Things (IoT) applications, etc . The system 100 can effectively provide a physical layer communication link containing the bus 106 extended to provide not only downstream and upstream audio communication, but also streaming communication. Audio, video and any suitable information may be transmitted synchronously using the bus (data being simultaneously transmitted with audio I2S / TDM, I2C, IRQ, etc. simultaneously as described above with respect to the I2S / TDM / PDM transceiver 127 and the I2C transceiver 129 discussed). This functionality may be particularly advantageous for delivering and receiving time-encoded media, or in applications where timing between different data streams is important. The above with reference to 18 and 19 Embodiments discussed may also apply to any suitable communication receiver and transmitter.

For example, in some embodiments, one may be with the slave node 104 Associated Bluetooth module communicate with a mobile device to send signals via Bluetooth to the bus 106 (eg to a slave node 104 or the master node 102 ), sending the signal to other devices in the system 100 (For example, an audio signal can be played through speakers connected to the slave nodes 104 are associated with the bus 106 are connected). More generally, the bus protocols disclosed herein may be used as a bridge to other communication systems and / or to bypass multiple communication systems.

Routing content

In some embodiments, the system may 100 provide a digital audio network, transferring audio content locally to any one or more of the slave nodes 104 allowed. For example, the system 100 be configured to selectively route audio to different parts of the digital audio network (eg, rear channels, front channels, a speaker at a particular seat of the vehicle, etc.). Examples of this functionality were discussed above with reference to 16 and 17 discussed. In addition to audio, such selective routing may be applied to any other type of streaming content.

In some embodiments, the system 100 enabled communication between nodes used to receive audio signals from many in the peripheral devices 108 Microphones collected to crosstalk and / or echo in the system 100 implemented digital distributed audio network to avoid. In particular, different slave nodes 104 on the bus 106 the on the bus 106 transmitted audio signals and can compensate for their audio output in response. As above with respect to 16 and 17 For example, control decisions about how to properly compensate for multiple audio sources can be made in a distributed fashion (eg, by processing devices 1302 that is in one or more of the slave nodes 104 contained) or in a centralized manner (eg by processing devices 1302 that is in the master node 102 or the host 110 are included).

beamforming

In some embodiments, the ability of the system 100 , synchronous audio content to multiple slave nodes 104 on the bus 106 to deliver and collect from this support beam-forming applications. Such applications may detect where a speaker is located and / or form a beam to ensure that output audio is focused on a particular area (but with reduced or no audibility out of range). Any suitable applications for focused sending or receiving of audio may be used by the system 100 also use effectively.

Connectivity for microphones

In some embodiments, one can use the system 100 Provide a digital microphone connection that is compatible with existing analog microphones, connectors, and preamplifiers and works using standard shielded 3-wire microphone cabling.

Previous attempts have been made to introduce digital microphones for professional audio and sound. In these experiments, the audio signal was converted directly from analog to digital in the capsule and then digitally transmitted. This approach requires custom microphones, dedicated digital cabling, and digital receivers, and thus was not compatible with the rest of the ecosystem of professional audio.

With the system 100 For example, one can provide a digital interconnect system by using an ADC using a standard positive XLR connector of a microphone (or other housing connected to a microphone) using the node transceiver 120 by bus 106 is connected. The ADC can be directly connected to the output of any existing analog dynamic, electret or condenser microphone and can be powered by standard 48V microphone phantom power. The ADC can convert the analog microphone signal into a digital signal, and this digital signal can be sent (via the Node Transceiver) 120 ) using standard microphone cabling over the bus 106 be transmitted. In most embodiments, for communication over the bus 106 the characteristic high frequency signals on a common set of conductors are combined with the lower frequency analog microphone signal without that they interfere so that both can be transmitted on the same cable and easily separated as desired. Because the bus 106 is formed of two-wire connections, a connection can be provided by standard microphone cabling, and because communication over the bus 106 typically performed at a much higher frequency than standard audio, transmissions can be over the bus 106 on the microphone cabling for backward / forward compatibility with the existing analog microphone signal.

At the receiving end of a microphone, a number of different connection arrangements can be used. In some embodiments, a connector may be the node transceiver 120 and a digital output that can be converted to a standard S / PDIF, AES / EBU, AES42 or other digital format for connection to an audio receiving device (eg, a mixer or an audio input device). In some embodiments, a connector may also include the node transceiver and a DAC, and may send an analog signal to the standard microphone input. Benefits of such an approach may include the use of a lower-noise digital connection instead of an analog connection. In some embodiments, a connector may be connected to an analog microphone input via the node transceiver 120 transmitted signal is out of the audio band and thus backward compatible with analog devices. In some embodiments, a connector may include a dual receiver connection for both the digital output and the analog signal, thereby allowing a user to select between the digital signal and the analog signal for various applications (eg, the analog signal for a secondary preamplifier and conversion ).

In some embodiments, the node transceiver could 120 and a DAC can be installed directly into an XLR connector or power supply box through 48V phantom power. The entire assembly could include a standard microphone cable, with the node transceiver 120 and converters are located in the microphone connectors.

These embodiments may be applied to multiple microphone settings and used to create a "digital snake". In such embodiments, multiple microphone signals (either analog or digital) may be combined and transmitted via a standard microphone cable over the bus 106 without the need for any large multi-conductor or specialized digital cabling. At the receiving end may be a node transceiver 120 Disconnect any audio input channel for connection to standard audio hardware as discussed above.

20 - 23 show exemplary arrangements of a microphone 2002 , a microphone cable 2010 and an audio receiving device 2020 that in the system 100 may be included, according to various embodiments. In each of these arrangements has a microphone 2002 a cable connector 2004 on. The microphone cable 2010 has a first connector 2006 for coupling with the cable connector 2004 and a second connector 2012 for coupling to the audio receiving device 2020 on. One or more conductors couple the first connector 2006 and the second connector 2012 to transfer data between them. The one or more conductors may be, for example, standard microphone cabling. The audio receiving device 2020 can be a cable connector 2018 for coupling with the second connector 2012 of the microphone cable 2010 exhibit. In some embodiments, the cable connector 2004 , the first connector 2006 , the second connector 2012 and the cable connector 2018 XLR connector or have any other suitable geometry.

20 shows an arrangement 2000 in which an ADC 2008 in or near the first connector 2006 is arranged and generates a digital output from the analog microphone signal, one in or near the second connector 2012 arranged node transceiver 120 is supplied. The output of the node transceiver 120 may include four wires that provide upstream signals for transmission on an upstream pair of the four wires and / or downstream signals for transmission on a downstream pair of the four wires. The digital edition of the ADC 2008 can be parallel to the output of the node transceiver 120 (eg on his own wire or his own wires) are provided. The cable connector 2018 the audio receiving device 2020 can be the four wires that the output of the node transceiver 120 transmit, receive and send these signals on these four wires to the bus 106 can route and route the wires that make up the digital output of the ADC 2008 transmit, receive and route this digital output to any suitable digital audio input.

21 shows an arrangement 2100 in which an ADC 2008 in or near the first connector 2006 is arranged and generates a digital output from the analog microphone signal. This digital edition becomes a node transceiver 120 supplied in or near the second connector 2012 is arranged. As above with respect to 20 The output of the node transceiver can be discussed 120 comprise four wires providing upstream signals for transmission on an upstream pair of the four wires and / or downstream signals for transmission on a downstream pair of the four wires. The digital edition of the ADC 2008 can parallel a DAC 2016 supplied in or near the second connector 2012 is arranged. The analog output of the DAC 2016 can be parallel to the output of the node transceiver 120 be fed (eg on his own wire or his own wires). The cable connector 2018 the audio receiving device 2020 can be the four wires that the output of the node transceiver 120 transmit, receive and send the signals on these four wires to the bus 106 can route and connect the wires, which is the analog output of the DAC 2016 transmit, receive and route this analog output to any suitable analog audio input.

22 shows an arrangement 2200 in which an ADC 2008 in or near the first connector 2006 is arranged and generates a digital output from the analog microphone signal to a node transceiver 120 which is also in or near the first connector 2006 is arranged. The output of the node transceiver 120 may include four wires that provide upstream signals for transmission on an upstream pair of the four wires and / or downstream signals for transmission on a downstream pair of the four wires. The analog output of the microphone 2002 can with the output of the node transceiver 120 combined (eg on a common set of at least four wires). The cable connector 2018 the audio receiving device 2020 can be the four wires that the output of the node transceiver 120 , combined with the analog output of the microphone 2002 , transmit, receive and these four wires to the bus 106 and route to any suitable analog audio input. As discussed above, since those over the bus 106 transmitted signals generally do not overlap in frequency with analog audio signals, transmit the signals on the same set of conductors, and extract the desired signals (eg, by filtering or by the inability of the final receiving device to detect signals in the other frequency band).

23 shows an arrangement 2300 in which an ADC 2008 in or near the first connector 2006 is arranged and generates a digital output from the analog microphone signal. This digital output becomes a node transceiver 120 supplied in or near the second connector 2012 is arranged. As above with respect to 20 The output of the node transceiver can be discussed 120 comprise four wires providing upstream signals for transmission on an upstream pair of the four wires and / or downstream signals for transmission on a downstream pair of the four wires. The digital edition of the ADC 2008 can in the second connector 2012 parallel to the output of the node transceiver 120 (eg on its own wire or wires), and the analog microphone signal from the microphone 2002 can in the second connector 2012 be fed in parallel to both (eg on his own wire or his own wires). The cable connector 2018 the audio receiving device 2020 can be the four wires that the output of the node transceiver 120 transmit, receive and send the signals on these four wires to the bus 106 route the wires that transmit the analog microphone signal and route that analog signal to any suitable analog audio input and the wires that control the digital output of the ADC 2008 transmit, receive and route this digital signal to any suitable digital audio input.

Even though 20 - 23 different components in different places in a microphone cable 2010 These arrangements are merely exemplary, and the components may be rearranged as appropriate. For example, in some embodiments, some or all of the components (eg, the ADC 2008 , the Node Transceiver 120 and / or the DAC 2016 ) in the cable connector 2004 or the cable connector 2018 be arranged. As discussed above, in some embodiments, the analog microphone signal conductor may be coupled to that through the node transceiver 120 generated traffic on the bus 106 and / or the digital representation of the analog microphone signal transmitted by the ADC 2008 is generated, share.

Radio receiver as a node on the bus

As discussed above with respect to wireless transceivers of voice calls, instead of or in addition to providing speakers and microphones as a peripheral device 108 for by bus 106 connected slave nodes 104 a slave node 104 also with one or more radio receivers as a peripheral device 108 such as FM receivers (frequency modulation), AM receivers (amplitude modulation), satellite radio receivers, television media receivers or other radio signal receivers. In a conventional vehicle environment, a receiver has an antenna, which is attached to a roof, rear window, rear spoiler or other part of the vehicle, with a long wire connecting the antenna again to a radio head unit in the front of the vehicle. With this conventional approach, electromagnetic interference can occur due to the long wire that requires other in-vehicle electronics to be carefully designed and controlled so as not to disturb the frequency of the long-wire signal.

To mitigate these problems and improve design flexibility and performance, in some embodiments of the system 100 a node transceiver 120 (eg in a slave node 104 includes) peripheral device communication circuitry in communication with an antenna coupled to a roof or other portion of a vehicle, and the peripheral device communications circuitry may communicate with the antenna via a wired connection. The node transceiver 120 may be near the antenna, and the data received by the antenna may be over the bus 106 to a head unit (eg a master node 102 or a host 110 , which is contained in a head unit) rather than a single long conductor coupling the antenna to the head unit. This can reduce or eliminate the problem of electromagnetic interference by digitally transmitting the received data in frequency bands that are not easily disturbed by other in-vehicle electronics.

24 shows an arrangement 2400 in which there is a slave node 104 near an antenna coupled to a roof of a vehicle 2404 is, according to various embodiments. The antenna 2404 (and any associated radio receiver circuits) may be a peripheral device 108 of the slave node 104 and may receive received radio data via any suitable peripheral device communication circuitry to the slave node 104 provide. The slave node 104 can receive the received radio data (eg in unprocessed or processed form) over the bus 106 a master node 102 in a head unit 2402 of the vehicle.

The peripheral device communication circuitry communicating with the antenna (eg, the I2S / TDM / PDM transceiver 127 , the I2C transceiver 129 and / or one or more GPIO pins with interrupt request capability of the node transceiver 120 ) can interface with existing I2S and / or I2C interfaces for a radio receiver associated with the antenna, and thus the node transceiver can 120 readily form an interface with a radio receiver. In some embodiments, the node transceiver may 120 also provide a sample rate converter (eg, built-in) to process the received radio signals (which are usually fixed at an appropriate carrier frequency) before the received radio signals (eg, at the super-frame rate corresponding audio sampling frequency) over the bus 106 be transmitted. The data received by the radio receiver can then be upstream or downstream to a slave node 104 on the bus 106 (eg to a speaker or other delivery to a user).

Transporting compressed video

As discussed above, in addition to or instead of transmitting audio over the bus 106 Video over the bus 106 be transmitted. In some embodiments, compressed video (or low quality video, such as a rear-facing camera or a rear-seat video monitor) may also be transmitted over the bus at a suitable data rate 106 be transmitted. For example, compressed video may be transmitted from a camera or compressed video may be transmitted for a video display.

UI Controls

In the system 106 For example, microphones and any suitable sensors may be used as peripheral devices 108 be included to provide user interfaces or to enhance audio applications. Applications of microphones and / or sensors in a vehicle environment would include, for example, hands-free interfaces (eg, voice commands), telematics, driver monitoring, emergency / breakdown assistance, and gesture recognition applications. For example, microphones may be embedded in a seat belt or any suitable location in a vehicle. The bus 106 may provide an efficient communication channel for transmitting the audio data collected by the microphones and any suitable sensors. In some embodiments, any suitable I2C devices, such as gesture recognition sensors, pushbuttons, memory devices, displays, etc., may also be included in the system 100 be included (because, for example, the peripheral devices 108 with the one in the node transceiver 120 contained I2C transceiver 129 to be able to communicate).

Backplane Connectivity

In some embodiments, the system may 100 for connecting different subsystems (which may be included in different boards or on the same board, for example) with low latency. In particular, one can use the system 100 chain multiple boards to create a much larger system. The system 100 can also use the boards with smaller devices over the same bus 106 connect. Conference room, entertainment systems, intercom systems, smart homes, surveillance systems and emergency systems can include the bus 106 leverage to connect the subsystems together.

In some embodiments, one can use the system 100 connect audiovisual equipment to a performance stage, recording studio or any other suitable entertainment environment. The wiring needed to connect audiovisual equipment may advantageously be relative to conventional thick cable techniques by using the two-wire bus 106 be reduced. The audiovisual devices may include speakers, mixing consoles, musical instruments, time encode devices, lighting devices, amplifiers, video displays, pyrotechnics, and any other suitable devices. For example, shows 25 an arrangement 2500 where several types of audiovisual equipment have a node transceiver 120 contained and thus as a slave node 104 act and on the bus 106 to be able to communicate. In particular, a master consultation 2502 the host 110 and the master node 102 include, and the node transceivers 120 can in a mixer 2504 , a musical instrument 2506 , Lighting equipment 2508 , an amplifier 2510 , a speaker 2512 and a pyrotechnics console 2514 be included or coupled with it. Each of these devices can be considered a peripheral device 108 and can be determined using any suitable peripheral device communication circuitry (eg, the I2S / TDM / PDM transceiver 127 , the I2C transceiver 129 and / or one or more GPIO pins with interrupt request capability) with its associated node transceiver 120 communicate. Data from these devices can be on the bus 106 through the node transceivers 120 according to any of the bus protocols disclosed herein are provided to other devices.

The system 100 can be used to connect devices in any suitable environment. For example, you can use the system 100 medical devices with many sensors or subsystems (eg for patient monitoring applications) in relation to 25 Connect the discussed way together. The use of the two-wire bus 106 can reduce the wiring connecting these sensors and systems relative to conventional approaches.

vibration measurement

In some embodiments, one can use the system 100 Connect microphones and other sensors designed to monitor many parts of a material, such as a carbon fiber material, when the material is stress tested or during use. For example, the materials may include sheets of material, objects, rails, bridges, vehicles, or buildings. These microphones and other sensors and / or devices that generate stimuli for component testing of materials or objects may also be made using the bus 106 in the system 100 according to any of the bus protocols disclosed herein.

control systems

In some embodiments, the system may 100 as discussed above, provide a concatenated low latency communication architecture. Due to the low latency and synchronicity of data transmission of the system 100 can the system 100 provide an effective communication channel for control systems, in particular control systems that can benefit from reduced wiring and / or control systems that are connected to the bus 106 supplied power can work. Control systems can use the system 100 Advantageously, use commands between nodes on the bus 106 or data related to the state of the nodes on the bus 106 are transmitted to perform control functions.

If the system 100 implemented in systems with fault tolerance requirements, the slave nodes 104 be connected on the bus in a ring configuration, at any of the slave nodes 104 as the last slave node 104 can be provided. Examples of ring configurations are described above with reference to FIG 12 discussed. If a bus link in the ring fails, the ring configuration may have a fault-tolerant configuration to maintain connectivity between nodes provide. The bus 106 can also leverage the node discovery mechanism discussed here to find the correct last slave node 104 in the ring to recover from the mistake.

Distributed processing over low-latency communication links

The system 100 can be used to distribute processing operations between different slave nodes 104 be used. As discussed above, this may be advantageous for control systems where it is desirable to perform local processing on the nodes while still having a low latency communication link connecting the nodes. For example, backup / security functions can be shared between multiple slave nodes 104 be distributed. A slave node 104 can implement a mechanism to prevent one or more of this slave node 104 associated peripheral devices 108 (eg, devices that monitor and control a robotic limb) exert too much force or react too early to locally detected problems. The system 100 can enable distributed local processing, which is the immediate need for information from the slave nodes 104 send, mitigate or avoid a centralized processor (with the potential to compromise the system).

In some embodiments, a slave node 104 the broadcast functionality of the system 100 use other sensors / servos / actuators acting as peripheral devices 108 for other slave nodes 104 act, listen and react accordingly, without relying on a central processor (eg in the host 110 ) to leave.

By effectively inserting the through the system 100 enabling distributed processing, artificial limbs and other robotic applications can be given a processing that is equivalent to muscle memory, using the slave nodes 104 their environments and their own state can process independently and respond to it, without passing through the master node 102 and / or the host 110 to be disturbed.

Artificial limbs

Various embodiments of the system 100 can be advantageously applied to the control systems commonly found in artificial / robotic links and in robotics in general. The sensors and actuators and such sensors and actuators using robotic systems may be referred to as peripheral devices 108 for slave nodes 104 on the bus 106 serve. In some embodiments, these sensors and actuators may also be through the bus 106 be energized as discussed above. Advantageously, wiring instead of a large bundle of wires can be reduced to a concatenated two-wire system, thereby providing advantages in terms of form factor of robotics.

An example is a robotic leg in which the knee joint requires information from one or more foot sensors and the ankle requires information from one or more knee sensors. Conventionally, a centralized processor would be connected to the sensors and actuators using many wires. Using the system 100 For example, the number of wires can be reduced from this conventional approach to allow for faster localized processing since information is globally distributed over the bus according to any of the bus protocol techniques disclosed herein 106 be distributed.

For example, shows 26 a robotic link 2600 with a knee joint 2602 , ankle center 2604 and an ankle 2606 , 26 also shows an arrangement 2608 of the system 100 with which there are sensors and actuators for the robotic link 2600 can be enabled data on the robotic link 2600 to convey. In particular, the arrangement 2608 a slave node 0 with a peripheral device 108 with a knee sensor, a slave node 1 with a peripheral device 108 with the knee actuator, a slave node 2 with a peripheral device 108 with an ankle center sensor, a slave node 3 with a peripheral device 108 with an ankle center actuator, a slave node 4 with a peripheral device 108 with a foot sensor and a slave node 5 with a peripheral device 108 with a foot actuator. Through any of the peripheral devices 108 contained data can be sent to the associated slave node 104 are transmitted and can then be transmitted upstream and / or downstream, so eventually one or more of the other slave nodes 104 to reach (eg for use in controlling any of the peripheral devices 108 included actuators).

The same advantages discussed above with respect to robotic members may also apply to any robotic systems that include many smaller subsystems of electronics (each performing some local processing for the subsystem). The use of the system 100 in robotics for connecting sensors and servos is not limited to the connection of sensors and actuators, but the system 100 can be used to connect any suitable electronic devices, such as memory, processors, speakers, microphones, lamps, radio receivers, etc. For example, the system may 100 be applied to a network of body sensors in a game application, exploration of body movement or control of other machinery through body movement.

Sensor or device networks

With the system 100 For example, any suitable control system may be implemented to reduce cabling while providing a low latency communication link. These control systems would be, for example, machinery (heavy industrial machinery on a large scale), production line equipment (with many controls and sensors), drones (autonomous flying robots), autonomous control systems, powered control systems, etc. In many of these control systems, devices such as sensors (or sensor blocks) can be used. , Controllers and / or actuators (eg, small actuators) work synchronously to provide their respective functions, and the system 100 can provide an effective low latency communication link between these devices without excessive amounts of wiring (and weight) while powering these devices. Sensor networks generally can also use the features of the system 100 Take advantage of it to reduce the wiring, and can also use the bus 106 as a power supply network for the sensors.

Distributed intelligence support

In some embodiments, the slave node 104 and the host 110 each include, receive and send mailboxes for communication therebetween. Some embodiments may use I2C for the mailbox communication; the I2C interface of a slave node 104 (eg by the I2C transceiver 129 managed) can be configured as an I2C slave, so that a processing device the slave node 104 can program via I2C and initiate reads and / or writes to the mailboxes.

In some embodiments, the node transceiver may 120 for a slave node 104 Registers include, receive and transmit as input and output "mailboxes" for communication between a processing device 1302 of the host 110 and a processing device 1302 of the slave node 104 (eg one from the node transceiver 120 separate processing device) can be used. The host 110 and the slave node 104 can be notified of data in their respective mailboxes by an interrupt that is triggered upon completion of data writing to the mailbox. The node transceiver 120 may be configured to interrupt an in the relevant slave mailbox upon completion of a data write to a relevant mailbox 104 contained processing device 1302 to create.

27 is a block diagram of an arrangement 2700 in which a slave node 0 is a node transceiver 120 with a reception mailbox 2710 and a send mailbox 2712 Includes, what with a receiving mailbox 2704 and a send mailbox 2708 of a host 110 (via a master node 102 ) can be communicated. In particular, the receiving mailbox can 2710 supplied data via a through the node transceiver 120 generated interrupt to the processing device 1302 of the slave node 0, and the processing device 1302 Slave node 0 can be the node transceiver 120 notify that data is transferring to the host 110 in the broadcast mailbox 2712 are located.

The node transceiver 120 may include a number of registers for controlling these mailboxes. In some embodiments, registers MBOX0CTL and MBOX1CTL may provide fields to release these mailboxes and to control direction, message length, and interrupt releases for the mailboxes.

Mailbox 0 can be configured as a default as a receiving mailbox (eg the receiving mailbox 2710 in which the host 110 writes and a processing device 1302 of the slave node 104 read). Mailbox 1 can be configured as a default as a send mailbox (eg the Send mailbox 2712 into a processing device 1302 of the slave node 104 writes and the host 110 read).

An MBxLEN field of the MBOXxCTL register can define the length of the associated mailbox. If this field is 0, MBOXxB0 may be the last byte of the mailbox. If this field is 1, MBOXxB1 may be the last byte of the mailbox. If this field is 2, MBOXxB2 may be the last byte of the mailbox. If this field is 3, MBOXxB3 may be the last byte of the mailbox.

For a released receive mailbox, if an MBxFIEN bit of the MBOXxCTL register is set, an interrupt may be issued to the processing device 1302 of the slave node 104 occur after the last byte of the associated mailbox is hosted by the host 110 is written and the node transceiver 120 determines that no new bus attempt was necessary. If an MBxEIEN field of the MBOXxCTL register is set, an interrupt may be issued to the host 110 occur after the last byte of the associated mailbox by the processing device 1302 of the slave node 104 is read.

For a shared send mailbox, if the MBxFIEN field is set, an interrupt may be issued to the host 110 occur after the last byte of the associated mailbox by the processing device 1302 of the slave node 104 is written. If the MBxEIEN field is set, an interrupt may be issued to the processing device 1302 of the slave node 104 occur after the last byte of the associated mailbox is hosted by the host 110 is read and the node transceiver 120 determines that no new bus attempt was necessary.

In some embodiments, registers MBOX0STAT and MBOX1STAT may provide status information for the mailboxes. When a mailbox is filled, an associated MBxFULL bit of the MBOXxSTAT register may go high and the MBxEMPTY bit may go low. When a mailbox is emptied, an associated MBxEMPTY bit of the MBOXxSTAT register may go high and the MBxFULL bit may go low. The MBxEIRQ and MBxFIRQ bits included in the MBOXxSTAT register may go high if the associated mailbox interrupts the host 110 or local processor (eg, the processing device 1302 of the slave node 104 ), and can go low if the interrupt is through the host 110 or local processor is processed.

In some embodiments, registers MBOX0Bn and MBOX1Bn may contain mailbox data. Each mailbox, in some examples, can hold up to 32 bits of data. An MBxLEN field in the MBOXxBn register can define the number of active bytes in the mailbox. In some embodiments, each mailbox may support 8, 16, 24, or 32-bit messages.

sensor support

For some vehicle applications, the system may 100 an arrangement of slave nodes 104 on the bus 106 for connecting two microphones located on the left and right sides of the passenger compartment, respectively, and an environment sensor connected to a slave node 104 on the bus 106 coupled and positioned between the microphones and near the windshield. The environmental sensor can measure temperature and humidity (eg, for anti-condensation and climate control functions) and / or ambient gases (eg, ammonia, carbon monoxide, nitrogen dioxide) for air diversion to improve passenger comfort. The microphones may be, for example, MEMS microphone arrays (microelectromechanical systems).

In some embodiments, the node transceiver includes 120 a slave node 104 Peripheral device communication circuitry (eg, the I2S / TDM / PDM transceiver 127 , the I2C transceiver 129 and / or one or more GPIO pins with interrupt request capability) in communication with an environmental sensor (such as a humidity sensor, temperature sensor, and / or gas sensor) in a vehicle. In some embodiments, the host may 110 generate a control instruction for an air conditioning system in the vehicle on the basis of data from an environmental sensor, via a slave node 104 , the bus 106 and the master node 102 to the host 110 be transmitted. For example, shows 28 an arrangement 2800 of the system 100 in which a slave node 0 (on the left side of the passenger compartment) is a peripheral device 108 with a microphone and a speaker, a slave node 1 (near a windshield 2802 ) a peripheral device 108 having a humidity and / or temperature sensor, a slave node 2 has a peripheral device 108 comprising a gas sensor and a slave node 3 (on the right side of the passenger compartment) comprises a peripheral device 108 with a microphone and a speaker.

When microphones are included in vehicles on the left and right sides of the passenger compartment (eg for noise reduction and / or beamforming), the wiring used to couple these microphones may be through inter-slave nodes 104 which are coupled to the peripheral devices that perform HVAC (Heating Ventilation and Air Conditioning) and / or air monitoring functions near the windshield area. In some scenarios, a peripheral device may be for a slave node 104 a humidity and / or temperature sensor that can provide humidity and / or temperature information that allows the measurement of the dew point on the windshield surface and prediction of windshield condensation so that the HVAC system in the vehicle can operate "just in time" To prevent fogging of the discs. Such a system can save both energy and safety during vehicle operation over "always-on" or manually-controlled HVAC systems by avoiding fogging of the windshield. An example of a humidity and / or temperature sensor that may be used in some embodiments is the HTU21D sensor manufactured by Measurement Specialties of Hampton, Virginia, USA. Similarly, data generated by a gas sensor detecting the presence of unwanted chemicals in the air of the vehicle passenger compartment may be used to initiate operation of the HVAC system in the vehicle to improve ventilation and reduce chemical concentration. An example of a gas sensor that may be used in some embodiments is the MiCS-6814 sensor manufactured by SGX Sensortech in Switzerland.

Integrated accelerometer

In some embodiments, a slave node 104 with a peripheral device 108 which are one in the same board as the node transceiver 120 (eg the upstream transceiver 122 and / or the downstream transceiver 124 integrated accelerometer (eg, a multi-axis accelerometer). Audio inputs and outputs, such as microphones and speakers, may also be coupled to the same board. One application for such an embodiment may be road noise cancellation, in which the vibration of the chassis is measured and the audio components are lifted away.

Test Device Support

In some embodiments, a node transceiver may 120 be configured in a "bus monitor mode" or "BMM" at which the node transceiver 120 Upstream and / or downstream activity on a segment of the bus 106 both master and slave node behavior (eg which signals come from and / or go to master and / or slave). In some embodiments, the upstream transceiver monitors 122 of the node transceiver 120 Downstream data is presented to a protocol analyzer (eg over an I2S bus using the I2S / TDM / PDM transceiver 127 ) too. A node transceiver operating in bus monitor mode 120 can be referred to here as "bus monitor" or "BM". In this mode, the downstream transceiver can 124 of the node transceiver 120 be locked. A bus monitor can not communicate with other slave nodes 104 but the pair of wires may be just upstream of a slave node to be monitored 104 tap and can through the master node 102 be discovered, although he does not have all the functionality of a node transceiver 120 in a typical slave node 104 features. The bus monitor can initially be configured by a processor that communicates with the bus monitor (eg via an I2C protocol).

Thus, in some embodiments, a node transceiver acting as a bus monitor 120 Peripheral device communication circuitry (eg, the I2S / TDM / PDM transceiver 127 , the I2C transceiver 129 and / or one or more GPIO pins with interrupt request capability) to one over the bus 106 signal received from an upstream device to a protocol analyzer. In some embodiments, the downstream transceiver may be 124 a node transceiver operating in bus monitor mode 120 be locked. The upstream transceiver 122 can be designed to receive, not send, data only.

29 is a block diagram of an arrangement 2900 of elements of the system 100 and a bus monitor according to various embodiments. In the arrangement 2900 can be a bus monitor device 2902 a bus monitor 2906 and one over I2C and / or I2S (eg, using the I2S / TDM / PDM transceiver 127 and / or the I2C transceiver 129 of the bus monitor) with the bus monitor 2906 in communication processing device 2908 include. The processing device 2908 may be the shape of any of the above with respect to 13 discussed processing devices 1302 accept. The BMM 2906 can the two wires of the bus 106 just tap upstream of the slave node 1, and between the BMM 2906 and the bus 106 can isolation circuits 2904 be arranged. The isolation circuits 2904 can use analog circuits to isolate the bus 106 from the burden of the BMM 2906 include.

In some embodiments, the bus monitor mode may be a node transceiver 120 allow us to act as a passive BM, which is also referred to here as a sniffer. A BM can use its I2S port to send traffic from the bus 106 to a protocol analyzer. A BM can be passive in the system 100 be as he controls the bus synchronization control frame 180 to configure its bus properties to match those of the slave node 104 The BM monitors but does not respond to synchronization control frames 180 ,

The upstream transceiver 122 can see both upstream and downstream data because the BM is not chained. In some embodiments, upon receiving downstream data via the upstream transceiver 122 a BM, a received synchronization control frame 180 and its corresponding downstream data slots 198 in a downstream frame buffer. In some embodiments, a BM may receive upstream data via the upstream transceiver 122 load a received sync response frame and its corresponding upstream data slots into an upstream frame buffer. The BM can provide both downstream and upstream data for deployment to a protocol analyzer (eg, the processing device 2908 ) to the I2S / TDM / PDM transceiver 127 respectively.

The node transceiver 120 may include one or more registers to support the BMM. In some embodiments, the node transceiver may 120 a BMMCFG register. The BMMCFG register may include a BMMEN bit (indicating whether the node transceiver 120 to work in the BMM or not), a BMMRXEN bit (to enable or disable the upstream transceiver 122 if the node transceiver is in the BMM) and a BMMNDSC node (to indicate if the system's startup and discovery processes 100 should occur before or after the BM is connected and released).

30 is a flowchart of a method 3000 for starting the operation of a BM according to various embodiments. The procedure 3000 can through the processing device 2908 in the bus monitor device 2902 be executed and may be as with respect to the BM 2906 be described executed.

In 3002 can the processing device 2908 BMM in the BM 2906 release. Before releasing the BMM, the BM 2906 as default to a default configuration for the node transceiver 120 come. Releasing the BMM in 3002 may include setting the BMMEN bit discussed above.

In 3004 can the processing device 2908 after connecting the BM to the route of the bus 106 upstream of a slave node to be monitored 104 (eg, the slave node 1 of 29 ) the upstream transceiver 122 in the BM 2906 release. Release the upstream transceiver 122 in 3004 may include setting the BMMRXEN bit discussed above.

In 3006 can the processing device 2908 the I2S / TDM / PDM transceiver 127 of the BM 2906 for transmission using over the I2C transceiver 129 Configure sent commands.

In 3008 can after the BM 2906 through the host 110 is discovered and the PLL 128 of the BM 2906 engages the processing device 2908 via the I2S / TDM / PDM transceiver 127 of the BM 2906 Data from the bus 106 receive. As already mentioned, the BM 2906 Control writes of the bus synchronization control frame 180 to configure its bus properties (for example, the values of DNSLOTS and UPSLOTS) to match those of the slave node 104 which is monitored (eg, the slave node 1 of 29 ) to match.

A BM can be the segment of the bus 106 to which it is connected, find out and can also configure the downstream slave node 104 if the BM is allowed to experience the bus 106 to monitor during the discovery. Some monitored parameters may apply to the entire bus 106 (eg all slave nodes 104 ), some for the immediately downstream slave node 104 and some for downstream slave nodes 104 be valid. The BM can monitor discovery, save the parameters from a later discovery, use known settings, or try different parameter variants until successful decoding has been achieved (eg, music data has been successfully decoded).

In some embodiments, the downstream ones may be on the bus 106 transmitted payloads are only examined when the host 110 Releases this functionality with a control statement using the master node 102 to a slave node 104 is forwarded, which should act as BM. In some such embodiments, if the BM does not respond appropriately through the master node 102 is configured, the BM only "sniff" synchronization control and response frame data, but not the payload in the data slots. This can provide some degree of content protection because the data is scrambled and a BM can only access the payload data if it is the host 110 allowed.

Communication from slave to slave

In general, slave nodes 104 on the DTXn pins, output downstream data from the master node 102 come. The transceiver may also selectively output upstream or downstream data from other slave nodes 104 without it being necessary for data slots to pass through the master node first 102 be routed. Analog can slave nodes 104 Generally, on the DRx pins, input data is received for the master node 102 are determined. The transceiver can also send upstream or downstream data directly to other slave nodes 104 without it being necessary for data slots to pass through the master node first 102 be routed.

In embodiments, this synchronous communication between multiple slave nodes 104 can use the slave nodes 104 selectively receive bus upstream data slots on the DTXn pins. The system may skip DRXn data channels based on a programmable OFFSET before the upstream slots through the slave node 104 be generated.

31 - 65 show various examples of slave-to-slave communication systems and techniques. Any of the embodiments illustrated in these figures or discussed below with respect thereto may be combined with any of the other embodiments disclosed herein. The use or representation of certain numbers of elements in these figures (eg 10 in 31 illustrated upstream data slots) are merely examples, and the systems and techniques may be applied to or integrate any desired and appropriate number of optional elements. In addition, for clarity, concrete names may be used herein for registers, variables, data slots, etc., but any data structures used as described herein may have any suitable names or other identifiers.

In some embodiments, registers or other data structures may be used to store data representing which upstream data slots a slave node 104 can use. For example, registers UPMASK0, UPMASK1, UPMASK2, and UPMASK3 may provide 1 bit for each possible upstream data slot. If any of these bits are set, the corresponding upstream data slot may be serviced by the slave node 104 (eg by the downstream transceiver 124 ) and placed in the TX frame buffer after any received downstream data slots. The UPSLOTS register may define the number of upstream data slots starting immediately after the SRF that are upstream through the slave node 104 (eg by the upstream transceiver 122 ).

In embodiments in which no slave to slave communication occurs, a slave node may 104 the UPSLOTS upstream data slots with the downstream transceiver 124 receive and (UPSLOTS + LUPSLOTS) upstream data slots with the upstream transceiver 122 send. In embodiments where slave to slave communication occurs, use of registers UPMASK0 through UPMASK3 may change the calculation used to calculate the number of received upstream data slots. In particular, a slave node 104 MAX (UPSLOTS, upmaskrx) upstream data slots with the downstream transceiver 124 receive and (UPSLOTS + LUPSLOTS) upstream data slots with the upstream transceiver 122 send, whereupmascrx can be calculated as follows:
if (RXUPSLOT31 == 1) upmaskrx = 32;
else if (RXUPSLOT30 == 1) upmaskrx = 31;
else if (RXUPSLOT29 == 1) upmaskrx = 30;
, , ,
else if (RXUPSLOT02 == 1) upmaskrx = 3;
else if (RXUPSLOT01 == 1) upmaskrx = 2;
else if (RXUPSLOT00 == 1) upmaskrx = 1;
else upmaskrx = 0.

Since it is possible for a slave node 104 Upstream data slots that are not forwarded can be the slave node 104 local upstream data slots on the upstream transceiver 122 while still holding upstream data slots on the downstream transceiver 124 receives.

A slave node 104 which generates upstream data slots typically starts with the first entry in the RX frame buffer. In some embodiments, when used, an UPOFFSET register may define an offset to be applied in the RX frame buffer before data is taken and sent upstream.

31 gives an example of how upstream data slots in a slave node 104 after programming the registers UPMASK0, ..., UPMASK3 and UPOFFSET for slave to slave communication, according to various embodiments. The transceiver of the A-side may be the upstream transceiver 122 and the B-side transceiver may be the downstream transceiver 124 be. In the example of 31 can be the slave node 104 10 upstream data slots (UP0 to UP9) provided upstream by the downstream slave node for the transceiver of the B side of the current slave node 104 , received. In this example, six slots (UP0, UP1, UP6-9) are used locally for the transmit data output. Two of these slots become the upstream slave node 104 with additional four slots not used by this node (UPSLOTS = 6). Four slots are taken out of the data frame and replaced here by four slots (LUPSLOTS = 4) of locally provided receive data. When data slots off the bus 106 can be replaced or not replaced with a different number of slots (exceeding or decreasing the initial number).

32 shows a UPMASK0 register which defines bits 7 through 0 of a 32-bit UPMASK field. As discussed above, in a slave node 104 the UPMASK field will define the upstream data slots that pass through the slave node 104 (the "local" slave node) by the downstream transceiver 124 from the bus 106 be received. These data slots can be transmitted over I2S / TDM and can follow any downstream slots that pass through the slave node 104 received (defined in LDNSLOTS). In some embodiments, changes to this register will only be effective after setting a CONTROL.NEWSTRCT bit of the master node 102 out. Table 1 gives bit descriptions for an exemplary UPMASK0 register. Each bit set in the RXUPSLOT registers may indicate upstream data through upstream slave nodes 104 be intercepted. Table 1.

33 shows a UPMASK1 register defining bits 15-8 of the 32-bit UPMASK field. As discussed above, in a slave node 104 the UPMASK field will define the upstream data slots that pass through the slave node 104 with the downstream transceiver 124 be received from the bus 6. These data slots may be transmitted over I2S / TDM and may be followed by any downstream slots provided by the upstream transceiver 122 of the slave node 104 received (defined in LDNSLOTS). In some embodiments, changes to this register will not be effective until after the CONTROL.NEWSTRCT bit of the master node 2 is set. Table 2 gives bit descriptions for an exemplary UPMASK1 register. Table 2.

34 Figure 11 shows a UPMASK2 register defining bits 23-16 of the 32-bit UPMASK field. As discussed above, in a slave node 104 the UPMASK field defines the upstream data slots that pass through the local node with the downstream transceiver 124 from the bus 106 be received. These data slots can be transmitted over I2S / TDM and can follow any downstream slots that pass through the slave node 104 received (defined in LDNSLOTS). In some embodiments, changes to this register will only be effective after setting the CONTROL.NEWSTRCT bit of the master node 102 out. Table 3 gives bit descriptions for an exemplary UPMASK2 register. Table 3.

35 Figure 11 shows a UPMASK3 register defining bits 31 through 24 of the 32-bit UPMASK field. As discussed above, in a slave node 104 the UPMASK field defines the upstream data slots that pass through the local node from the bus 106 be received. These data slots can be transmitted over I2S / TDM and can follow any downstream slots that pass through the slave node 104 received (defined in LDNSLOTS). In some embodiments, changes to this register will only be effective after setting the CONTROL.NEWSTRCT bit of the master node 102 out. Table 4 gives bit descriptions for an exemplary UPMASK3 register. Table 4.

36 shows an exemplary local upstream slot offset register (UPOFFSET). In a slave node 104 For example, the UPOFFSET register may define a number of data slots received over I2S / TDM / PDM which are skipped before data slots are upstream by the upstream transceiver 122 on the bus 106 be transmitted. Table 5 gives bit descriptions for an exemplary UPOFFSET register. In some embodiments, instead of an UPOFFSET register, a node may use an RX data mask to selectively decide which data channels of an I2S / TDM frame to provide. Table 5.

Analogous operations can occur for downstream communication. In particular, slave nodes 104 selectively receive bus downstream slots on the DTXn pins. The slave nodes 104 can from the DRXn pin with a programmable OFFSET downstream slots on the bus 106 produce. This operating mode can be slave node 104 thus allow both to receive and send downstream data.

In some embodiments, registers or other data structures may be used to store data, which upstream data slots a slave node 104 can use. For example, registers DNMASK0, DNMASK1, DNMASK2, and DNMASK3 may provide 1 bit for each possible downstream data slot. If the LDNSLOTS.DNMASKEN bit is set, these bits select which downstream slots are consumed by the local node and place them in the TX frame buffer. If the LDNSLOTS.DNMASKEN bit is not set, the LDNSLOTS register may define the number of downstream slots consumed by the local node. The DNSLOTS register may define the number of downstream data slots beginning immediately after the SCF that are downstream (eg, by the downstream transceiver) 124 ) through the slave node 104 be directed. A variable dnmaskrx can be defined as follows:
if (RXDNSLOT31 == 1) dnmaskrx = 32;
else if (RXDNSLOT30 == 1) dnmaskrx = 31;
else if (RXDNSLOT29 == 1) dnmaskrx = 30;
, , ,
else if (RXDNSLOT02 == 1) dnmaskrx = 3;
else if (RXDNSLOT01 == 1) dnmaskrx = 2;
else if (RXDNSLOT00 == 1) dnmaskrx = 1;
else dnmaskrx = 0.

In case dnmaskrx == 0 can be a slave node 104 (BCDNSLOTS + DNSLOTS + LDNSLOTS) Receive downstream data slots and send (BCDNSLOTS + DNSLOTS) downstream data slots. In the case dnmaskrx! = 0, a slave node 104 MAX (DNSLOTS, dnmaskrx) receive downstream data slots and send (DNSLOTS + LDNSLOTS) downstream data slots. Since it is possible for a slave node 104 Downstream data slots can be sent to the slave node 104 local downstream data slots on the downstream transceiver 124 while still holding upstream data slots on the upstream transceiver 122 receives. Note that setting the LDNSLOTS.DNMASKEN bit in a slave node 104 change the meaning of the LDNSLOTS register and cause the BCDNSLOTS register to be ignored.

In some embodiments, a DNOFFSET register may define an offset to apply in the RX frame buffer before data is taken and communicated with the downstream transceiver 124 be sent downstream. The value of the DNOFFSET register can only be used if the slave node 104 is designed to send downstream data (eg, if registers DNMASK0, ..., DNMASK3 are not all zero and LDNSLOTS is not null). In a slave node 104 The meaning of the LDNSLOTS register may change depending on the LDNSLOTS.DNMASKEN bit. If the LDNSLOTS.DNMASKEN bit = 0, the LDNSLOTS register may define the number of data slots that will be used during the downstream part of the superframe by the slave node 104 be recorded. These data slots can be through the slave node 104 consumed and not to the next slave node 104 be routed downstream. If the LDNSLOTS.DNMASKEN bit = 1, the LDNSLOTS register may define the number of data slots that pass through the slave node 104 be added during the downstream part of the superframe. These data slots can be added after the DNSLOTS data slots are routed downstream through the local node.

37 gives an example of how downstream data slots in a slave node 104 after programming the registers DNMASK0, ..., DNMASK3 and DNOFFSET for slave to slave communication, according to various embodiments. The transceiver of the A-side may be the upstream transceiver 122 and the B-side transceiver may be the downstream transceiver 124 be. In the example of 37 can be the slave node 104 Provide 10 downstream data slots because RXDNSLOT09 is set and the value of DNSLOTS is 6.

38 shows an example of a DNMASK0 register defining bits 7 through 0 of a 32-bit DNMASK field. As discussed above, in a slave node 104 if any bits are set in DNMASKEN, the DNMASK field will define the downstream data slots that are passed through the local node from the bus 106 be received. These data slots can be sent via I2S / TDM. If DNMASKEN is not set, the LDNSLOTS register can define the number of downstream data slots that pass through the local slave node 104 be taken. In some embodiments, changes to this register will not be effective until after the CONTROL.NEWSTRCT bit of the master node 102 is set. Table 6 gives bit descriptions for an exemplary DNMASK0 register. Table 6.

39 Figure 11 shows an exemplary DNMASK1 register defining bits 15 through 8 of the 32-bit DNMASK field. As discussed above, in a slave node 104 If any bits are set in DNMASKEN, the DNMASK field will define the downstream data slots that will be used by the upstream transceiver 122 of the local slave node 104 from the bus 106 be received. These data slots can be sent via I2S / TDM. If DNMASKEN is not set, the LDNSLOTS register can define the number of downstream data slots taken by the local node. In some embodiments, changes to this register will not be effective until after the CONTROL.NEWSTRCT bit of the master node 102 is set. Table 7 gives bit descriptions for an exemplary DNMASK1 register. Table 7.

40 Figure 11 shows an exemplary DNMASK2 register defining bits 23-16 of the 32-bit DNMASK field. As discussed above, in a slave node 104 If any bits are set in DNMASKEN, the DNMASK field will define the downstream data slots that will be used by the upstream transceiver 122 of the local slave node 104 from the bus 106 be received. These data slots can be sent via I2S / TDM. If DNMASKEN is not set, the LDNSLOTS register can define the number of downstream data slots taken by the local node. In some embodiments, changes to this register will not be effective until after the CONTROL.NEWSTRCT bit of the master node 102 is set. Table 8 gives bit descriptions for an exemplary DNMASK2 register. Table 8.

41 Figure 11 shows an exemplary DNMASK3 register defining bits 31 through 24 of the 32-bit DNMASK field. As discussed above, in a slave node 104 If any bits are set in DNMASKEN, the DNMASK field will define the downstream data slots that will be used by the upstream transceiver 122 of the local slave node 104 from the bus 106 be received. These data slots can be sent via I2S / TDM. If DNMASKEN is not set, the LDNSLOTS register can define the number of downstream data slots taken by the local node. In some embodiments, changes to this register will not be effective until after the CONTROL.NEWSTRCT bit of the master node 102 is set. Table 9 gives bit descriptions for an exemplary DNMASK3 register. Table 9.

42 shows an example of a downstream downstream slot offset register (DNOFFSET). In a slave node 104 For example, the DNOFFSET register may define a number of data slots received over I2S / TDM / PDM which are skipped before data slots through the slave node 104 downstream on the bus 106 be transmitted. The value in the DNOFFSET register can only be used if any of the bits in DNMASKEN are set. Table 10 gives bit descriptions for an exemplary DNOFFSET register. Table 10.

43 shows an example of a downstream downstream slot register (LDNSLOTS). In a slave node 104 The meaning of the LDNSLOTS register may change depending on whether DNMASKEN is set or not. If DNMASKEN is 0, the LDNSLOTS register can define the number of data slots that pass through the local slave node 104 during the downstream part of the superframe. These data slots are passed through the local slave node 104 consumed and not to the next slave node 104 directed downstream. If DNMASKEN is 1, the LDNSLOTS register can define the number of data slots that are passed through the local slave node 104 be added during the downstream part of the superframe. These data slots are added after DNSLOTS data slots downstream through the local slave node 104 be directed. In some embodiments, changes to this register will not be effective until after the CONTROL.NEWSTRCT bit of the master node 102 was set. The LDNSLOTS register can only be in slave nodes 104 to be relevant. Table 11 gives bit descriptions for an exemplary LDNSLOTS register. Table 11.

44 and 45 show various exemplary scenarios using any of the slave-to-slave communication techniques disclosed herein. 44 shows a first arrangement (left), in the upstream transmissions from a microphone in a third slave node 104 on the bus 106 the master node 102 and the host 110 before going downstream to having a first and second slave node 104 paired loudspeakers, and a second slave-to-slave arrangement (right) where upstream transmissions can be routed from the microphone directly upstream to the loudspeakers without the master node 102 and the host 110 to go through (eg a DSP). The arrangements of 44 there can be slave nodes 104 closer to the master node 102 directly allow data from slave nodes 104 Consume further from the master node 102 are removed without data through the master node 102 or the host 110 to route. This can reduce the time delay of the communication and save bus bandwidth.

45 shows a first arrangement (left), in the downstream transmissions from a microphone in a first slave node 104 on the bus 106 upstream through the master node 102 and the host 110 need to be routed before going downstream with a second and third slave node 104 paired loudspeakers, and a second slave-to-slave arrangement (right), in which Communication can be routed from the microphone directly upstream to the speakers, without the master node 102 and the host 110 to go through (eg a DSP). The arrangements of 45 there can be slave nodes 104 closer to the master node 102 directly allow data from slave nodes 104 Consume further from the master node 102 are removed without data through the master node 102 or the host 110 to route. This can reduce the time delay of the communication and save bus bandwidth.

46 - 55 show an example of slave to slave communication on a multi-node concatenated bus according to various embodiments discussed herein. In particular, show 46 - 55 each, how data is on a bus 106 in a particular example system 100 according to various embodiments disclosed herein, and also show the structure of between adjacent nodes on the bus 106 forwarded super frame. As discussed above, the length of a superframe may depend on the sampling rate; For example, in some embodiments, a superframe may have a length of 20.83 microseconds when the sampling rate is 48 kilohertz.

46 shows an exemplary system 100 with a host 110 that with a stereo tuner 111 is coupled. The host 110 is with a master node 102 coupled and the master node 102 is with a concatenation of four slave nodes 104 (identified as slave 0, slave 1, slave 2 and slave 3) coupled. Each of the slave nodes 104 in the system 100 from 46 is with one or more associated peripheral devices 108 coupled. In particular, as in 46 Slave 0 shown coupled to a microphone, slave 1 coupled to six speakers, slave 2 paired with a microphone and slave 3 paired with two microphones. For example, slave 1 may include an amplifier that drives its associated speakers. As mentioned above, the concrete number and type are slave nodes 104 and the specific number and type of peripheral devices 108 , in the 46 (and 47 - 55 ), by way of example only, and any suitable number and type may be used in accordance with the techniques disclosed herein.

46 also shows a scenario in which the master node 102 Data from the tuner 111 (eg, left and right audio data) and the master node 102 prepared to send a superframe downstream to slave 0. As in 46 As shown, the downstream starts from the master node 102 superframe sent to slave 0 with a SCF and is received from a downstream data slot for the left and right audio data respectively from the tuner 111 followed. The value of DNSLOTS in this scenario is for the master node 102 equal to 2.

47 shows a scenario in which slave 0 is a superframe from the master node 102 , as in 46 has shown and is preparing to send a superframe downstream to slave 1. As in 47 As shown, the superframe transmitted downstream from slave 0 to slave 1 starts with a SCF and is supplied from a downstream data slot for the left and right audio data respectively from the tuner 111 (received from the master node 102 ) and a downstream data slot for microphone data generated by the microphone associated with Slave 0. The value of DNSLOTS is equal to 2 for slave 0 (indicating that two downstream slots are occupied by data received from an upstream node), and the value of LDNSLOTS is equal to 1 for slave 0 (indicating that slave 0 adds a single downstream slot data). The value of DNMASK0 is 0 for slave 0 in this scenario (indicating that slave 0 is not one of the master nodes) 102 consume transmitted data).

48 shows a scenario in which slave 1 has received a superframe from slave 0, as in 47 and prepared to send a superframe downstream to slave 2. As in 48 Slave 1 will read all data from slave 0 (ie the left and right audio data from the tuner) 111 and the data from the microphone associated with slave 0) and will not return any data or add any other data to the superframe being sent from slave 1 to slave 2. In some embodiments, slave 1 uses all the data consumed by slave 0 by outputting this data to the speakers associated with slave 1. The superframe sent downstream from slave 1 to slave 2 thus starts with an SCF and is not followed by any additional data. The value of DNSLOTS is 0 for slave 1 (indicating that no downstream data slots are occupied by data received from an upstream node), and the value of LDNSLOTS is 0 for slave 1 (indicating that slave 1 will not add any downstream data slots). The value of DNMASK0 is equal to 7 for slave 1 in this scenario (indicating that slave 1 consumes the data received from slave 0 in the downstream slots associated with mask values 1, 2, and 4).

49 shows a scenario in which slave 2 has received a superframe from slave 1, as in 48 (ie, only the SCF) and prepared to send a superframe downstream to slave 3. As in 49 Slave 2 does not add any other data to the superframe sent from slave 2 to slave 3. The superframe sent downstream from slave 2 to slave 3 thus starts with an SCF and is not followed by any additional data. The value of DNSLOTS is 0 for slave 2 (indicating that no downstream data slots are occupied by data received from an upstream node), and the value of LDNSLOTS is 0 for slave 2 (indicating that slave 2 will not add any downstream data slots). The value of DNMASK0 is 0 for slave 2 in this scenario (indicating that slave 2 is not consuming data received from slave 1).

50 shows a scenario in which slave 3 has received a superframe from slave 2, as in FIG 49 represented (ie only the SCF). Slave 3 is the last slave node 104 on the bus 106 is, he does not have to carry out any downstream transmissions. The value of DNSLOTS is 0 for slave 3 (indicating that no downstream data slots are occupied by data received from an upstream node) and the value of LDNSLOTS is 0 for slave 3 (indicating that slave 3 does not add any downstream data slots). The value of DNMASK0 is 0 for slave 3 in this scenario (indicating that slave 3 is not consuming data received from slave 2).

51 shows a scenario in which slave 3 after receiving a superframe from slave 2 as above with respect to 50 discussed being prepared to send a superframe back upstream to Slave 2. As in 51 2, the superframe upstream sent by slave 3 to slave 2 begins with an SRF and is followed by an upstream data slot for each of the 2 microphones associated with slave 3. The value of UPSLOTS is 0 for slave 3 (indicating that no upstream slots are occupied by data received from a downstream node), and the value of LUPSLOTS is 2 for slave 3 (indicating that slave 3 adds two upstream slots data). The value of UPMASK0 is 0 for slave 3 in this scenario (indicating that slave 3 is not from any downstream slave nodes) 104 sent data consumed).

52 shows a scenario in which slave 2 has received a superframe from slave 3, as in 51 and prepared to send a superframe upstream to slave 1. As in 52 1, the superframe upstream sent by slave 2 to slave 1 begins with an SRF and is taken from the 2 upstream data slots of slave 3 and an additional upstream data slot occupied by data generated by the slave 2 associated microphone followed. The value of UPSLOTS is 2 for slave 2 (indicating that two upstream slots are occupied by data received from a downstream node) and the value of LUPSLOTS is 1 for slave 2 (indicating slave 2 an upstream slot adds data). The value of UPMASK0 is 0 for slave 2 in this scenario (indicating that slave 2 is not consuming any data coming from any downstream slave node 104 be sent).

53 shows a scenario in which slave 1 has received a superframe from slave 2, as in FIG 52 and prepare to send a superframe upstream to slave 0. As in 53 Slave 1 consumes the data from the microphones associated with slave 2 and slave 3 and places the data from the microphones associated with slave 3 back onto the bus 106 for transmission upstream to slave 0. In some embodiments, slave 1 uses all data consumed by slave 2 by outputting this data to the speakers associated with slave 1. As in 53 5, the superframe upstream sent by slave 1 to slave 0 begins with an SRF and is followed by an upstream data slot for the data generated by each of the 2 microphones associated with slave 3. Slave 1 does not put any additional data upstream on the bus 106 , The value of UPSLOTS is 2 for slave 1 (indicating that two upstream slots are occupied by data received from a downstream node), and the value of LUPSLOTS is 0 for slave 1 (indicating that slave 1 no upstream slots adds data). The value of UPMASK0 is equal to 7 for slave 1 in this scenario (indicating that slave 1 consumes the data received from slave 2 in the upstream slots associated with mask values 1, 2, and 4).

54 shows a scenario in which slave 0 has received a superframe from slave 1, as in FIG 53 presented, and prepared, a superframe upstream to the master node 102 to send. Slave 0 may not consume any of the data from slave 1, but can only route that data upstream. As in 54 As shown, the upstream begins by slave 0 to the master node 102 sent superframes with an SRF and is followed by an upstream data slot for the data, generated by each of the 2 microphones associated with slave 3. Slave 0 does not put any additional data upstream on the bus 106 , The value of UPSLOTS is equal to 2 for slave 0 (indicating that two upstream slots are occupied by data received from a downstream node), and the value of LUPSLOTS is 0 for slave 0 (indicating that slave 0 will not add any upstream slots data). The value of UPMASK0 is 0 for slave 0 in this scenario (indicating that slave 0 is not consuming any data received from slave 1). 55 is a summary of in 46 - 54 illustrated downstream and upstream communication.

56 - 65 show another example of slave to slave communication on a multi-node concatenated bus in accordance with various of the embodiments discussed above. In particular, show 56 - 65 each, how data is on a bus 106 in a certain exemplary system 100 according to various embodiments disclosed herein, and also show the structure of between adjacent nodes on the bus 106 forwarded super frame.

56 shows an exemplary system 100 with a host 110 that with a stereo tuner 111 is coupled. The host 110 is with a master node 102 coupled, and the master node 102 is with a concatenation of four slave nodes 104 (identified as slave 0, slave 1, slave 2 and slave 3) coupled. Each of the slave nodes 104 in the system 100 from 56 is with one or more associated peripheral devices 108 coupled. In particular, as in 56 Slave 0 is coupled to a microphone and a speaker, Slave 1 is mated to a microphone and two speakers (labeled 1 and 2), Slave 2 is mapped to two microphones (labeled 1 and 2) and two speakers (labeled 1 and 2) and slave 3 with a microphone and two speakers (labeled 1 and 2) coupled. For example, slaves 1, 2, and 3 may include amplifiers that drive their associated speakers. As mentioned above, the concrete number and type are slave nodes 104 and the specific number and type of peripheral devices 108 , in the 56 (and 57 - 65 ), by way of example only, and any suitable number and type may be used in accordance with the techniques disclosed herein.

56 also shows a scenario in which the master node 102 Data from the tuner 111 (eg, left and right audio data) and the master node 102 prepared to send a superframe downstream to slave 0. As in 56 As shown, the downstream starts from the master node 102 superframe sent to slave 0 with a SCF and is received from a downstream data slot for the left and right audio data respectively from the tuner 111 followed. The value of DNSLOTS in this scenario is for the master node 102 equal to 2.

57 shows a scenario in which slave 0 is a superframe from the master node 102 has received, as in 56 and prepared to send a superframe downstream to slave 1. As in 57 Slave 0 consumes the right audio data from the tuner 111 , In some embodiments, slave 0 uses all of the master node 102 consumed data by outputting this data to the speakers associated with slave 0. In addition, Slave 0 puts data from its microphone on the bus 106 , In particular, starts as in 57 shown, the superframe sent downstream from slave 0 to slave 1 with a SCF and is from a downstream data slot for the Left audio data from the tuner 111 (received from the master node 102 ) and a downstream data slot for the microphone data generated by the microphone associated with Slave 0. The value of DNSLOTS is 1 for slave 0 (indicating that a downstream slot is occupied by data received from an upstream node), and the value of LDNSLOTS is 1 for slave 0 (indicating that slave 0 adds a single downstream slot data). The value of DNMASK0 is equal to 2 for slave 0 in this scenario (indicating that slave 0 is the one from the master node 102 consumed data received in the downstream slot associated with the mask value 2). As indicated by the curved arrows in 57 and discussed below, the data generated by the microphone of slave 0 can be output to speaker 2 of slave 1 and speaker 2 of slave 2.

58 shows a scenario in which slave 1 has received a superframe from slave 0, as in 57 and prepared to send a superframe downstream to slave 2. As in 58 Slave 1 consumes some of the data from slave 0 (ie the data from the microphone associated with slave 0) and places the data from the slave 0 microphone and the slave 1 microphone data onto the bus 106 , In some embodiments, slave 1 uses the data consumed by slave 0 by outputting that data to the loudspeaker 2 associated with slave 1. The superframe transmitted downstream from slave 1 to slave 2 starts with an SCF and is driven by a downstream data slot for the left-hand slave. Audio data from the tuner 111 , a downstream data slot for the microphone data of slave 0 and a downstream data slot for data generated by the slave 1 associated microphone followed. The value of DNSLOTS is 2 for slave 1 (indicating that two downstream data slots are occupied by data received from an upstream node), and the value of LDNSLOTS is 1 for slave 1 (indicating that slave 1 adds a downstream data slot). The value of DNMASK0 is equal to 2 for slave 1 in this scenario (indicating that slave 1 consumes the data received from slave 0 in the downstream slot associated with mask value 2). As indicated by the curved arrows in 58 and discussed below, the data generated by the microphone of slave 1 can be output to speaker 1 from the slave 2.

59 shows a scenario in which slave 2 has received a superframe from slave 1, as in 58 and prepared to send a superframe downstream to slave 3. As in 59 Slave 2 consumes some of the data from slave 1 (ie the data from the microphones associated with slave 0 and 1) and places data from microphone 2 from slave 2 onto the bus 106 , In some embodiments, slave 2 uses the slave 0 microphone data consumed by slave 1 by outputting this data to the speaker 2 associated with slave 2, and slave 2 uses the slave 1 microphone data consumed by slave 1 by outputting this data to slave 2 associated loudspeaker 1. The superframe sent downstream from slave 2 to slave 3 starts with a SCF and is passed through a downstream data slot for the left audio data from the tuner 111 and a downstream data slot for data generated by the slave 2 associated microphone 2. The value of DNSLOTS is 1 for slave 2 (indicating that a downstream data slot is occupied by data received from an upstream node), and the value of LDNSLOTS is 1 for slave 2 (indicating that slave 2 adds a downstream data slot). The value of DNMASK0 is equal to 6 for slave 2 in this scenario (indicating that slave 2 consumes the data received from slave 1 in the downstream slots associated with mask values 2 and 4). As indicated by the curved arrow in 59 and discussed below, the data generated by the microphone 2 from slave 2 may be output to speaker 1 of slave 3.

60 shows a scenario in which slave 3 has received a superframe from slave 2, as in FIG 59 shown. Slave 3 is the last slave node 104 on the bus 106 is, he does not have to carry out any downstream transmissions. Slave 3 can consume the data from Microphone 2 from Slave 2 (and can output it, for example, to Speaker 1 of Slave 3) and can listen to the left audio data from the tuner 111 consume (and may output to, for example, speaker 2 of slave 3). The value of DNSLOTS is equal to 0 for slave 3 (indicating that no downstream data slots are occupied by data received from an upstream node), and the value of LDNSLOTS is 0 for slave 3 (indicating that slave 3 does not add any downstream data slots). The value of DNMASK0 is equal to 3 for slave 3 in this scenario (indicating that slave 3 consumes the data received from slave 2 in the downstream slots associated with mask values 1 and 2).

61 shows a scenario in which slave 3 after receiving a superframe from slave 2 as above with respect to 60 discussed being prepared to send a superframe back upstream to Slave 2. As in 61 2, the superframe upstream sent by slave 3 to slave 2 begins with an SRF and is followed by an upstream data slot for data generated by the microphone associated with slave 3. The value of UPSLOTS is 0 for slave 3 (indicating that no upstream slots are occupied by data received from a downstream node), and the value of LUPSLOTS is 1 for slave 3 (indicating that slave 3 adds an upstream slot data). The value of UPMASK0 is 0 for slave 3 in this scenario (indicating that slave 3 is not from any downstream slave nodes) 104 sent data consumed).

62 shows a scenario in which slave 2 has received a superframe from slave 3, as in 61 and prepared to send a superframe upstream to slave 1. As in 62 5, the superframe upstream to slave 1, sent upstream by slave 2, begins with an SRF and is taken up by the upstream data slot of slave 3 and two additional upstream data slots generated by data generated by the microphones associated with slave 2 be followed. The value of UPSLOTS is 1 for slave 2 (indicating that an upstream slot is occupied by data received from a downstream node), and the value of LUPSLOTS is 2 for slave 2 (indicating that slave 2 two upstream slots will add data). The value of UPMASK0 is 0 for slave 2 in this scenario (indicating that slave 2 is not any of any downstream slave nodes) 104 sent data consumed). As by the curved arrow in 62 and discussed below, the data generated by the microphone 2 from slave 2 can be output to speaker 1 of slave 1.

63 shows a scenario in which slave 1 has received a superframe from slave 2, as in FIG 62 and prepare to send a superframe upstream to slave 0. As in 63 Slave 1 consumes the data from the slave 2 associated microphone 2 and does not put this data back on the bus 106 for transmission upstream to slave 0. In some embodiments, slave 1 uses all data consumed by slave 2 by outputting this data to the speakers associated with slave 1 (eg, speaker 1). In addition, slave 1 can generate data generated by its own microphone on the bus 106 lay. As in 63 2, the superframe upstream sent by slave 1 to slave 0 begins with an SRF and is provided by an upstream data slot for the data generated by the slave 3 associated microphone, an upstream data slot for the data generated by slave 1 microphone 2 and followed by an upstream data slot for data generated by the microphone of slave 1. The value of UPSLOTS is equal to 2 for slave 1 (indicating that two upstream slots are occupied by data received from a downstream node), and the value of LUPSLOTS is 1 for slave 1 (indicating that slave 1 adds an upstream slot data). The value of UPMASK0 is equal to 4 for slave 1 in this scenario (indicating that slave 1 consumes the data received by slave 2 in the upstream slot associated with mask value 4).

64 shows a scenario in which slave 0 has received a superframe from slave 1, as in FIG 63 presented, and prepared, a superframe upstream to the master node 102 to send. Slave 0 may not be able to consume any of the data from slave 1, but can only pass that data upstream. Slave 0 can also send data generated by its own microphone to the bus 106 lay. As in 64 As shown, the slave 0 starts upstream to the master node 102 sent superframes with an SRF and is provided by an upstream data slot for the data generated by the slave 3 associated microphone, an upstream data slot for the data generated by microphone 1 of slave 2, an upstream data slot for the slave's microphone 1 data and an upstream data slot for the data generated by the microphone of slave 0 followed. The value of UPSLOTS is equal to 3 for slave 0 (indicating that three upstream slots are occupied by data received from a downstream node), and the value of LUPSLOTS is equal to 1 for slave 0 (indicating that slave 0 adds an upstream slot data). The value of UPMASK0 is 0 for slave 0 in this scenario (indicating that slave 0 does not consume data received from slave 1). 65 is a summary of in 56 - 65 illustrated downstream and upstream communication.

Any of the embodiments described herein may be combined in any desired combination with slave-to-slave communication functionality according to any of the embodiments disclosed herein.

The following paragraphs give examples of various embodiments disclosed herein.

Example A1 is a low-latency communication slave node transceiver comprising: upstream transceiver circuitry for receiving a first signal transmitted over a two-wire bus from an upstream device and for providing a second signal over the two-wire bus for the upstream -Contraption; Downstream transceiver circuitry for providing a third signal downstream over the two-wire bus toward a downstream device and for receiving a fourth signal over the two-wire bus from the downstream device; and clock circuits for generating a clock signal in the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of receiving and providing signals over the two-wire bus by the slave node transceiver is based on the clock signal.

Example A2 may include the subject matter of Example A1, and may further specify that the synchronization control frame is associated with downstream data in a superframe of the first signal, the downstream data includes a plurality of data slots, and data for a single peripheral device is in communication with the slave node Transceiver occupy two or more of the multiple data slots.

Example A3 may include the subject matter of Example A2 and may further specify that the data for the single peripheral device is audio data.

Example A4 may include the subject matter of any of Examples A1-A3, and may further specify: the first signal including a first synchronization control frame and associated first downstream data and a second synchronization control frame and associated second downstream data; the first downstream data comprises a data slot having a particular index and data for a first peripheral device in communication with the slave node transceiver; and the second downstream data comprises a data slot having the predetermined index and data for a second peripheral device different from the first peripheral device in communication with the slave node transceiver.

Example A5 may include the subject matter of example A4 and may further specify that the first and second peripheral devices are different microphones.

Example A6 may include the subject matter of any of Examples A1-A5, and may further specify: The second signal comprises a synchronization response frame, the synchronization response frame is associated with upstream data in a superframe of the second signal, the upstream data includes a plurality of data slots and data Origins in a single peripheral device in communication with the slave node transceiver occupy two or more of the multiple data slots.

Example A7 may include the subject matter of Example A6 and may further specify that the data originating in the single peripheral device is audio data.

Example A8 may include the subject matter of any of Examples A1-A7, and may further specify: the second signal includes a first synchronization response frame and associated first upstream data and a second synchronization response frame and associated second upstream data;
the first upstream data comprises a data slot having a particular index and data originating in a first peripheral device in communication with the slave node transceiver; and the second upstream data comprises a data slot having the predetermined index and data originating in a second peripheral device different from the first peripheral device in communication with the slave node transceiver.

Example A9 may include the subject matter of Example A8 and may further specify that the first and second peripheral devices are different microphones.

Example A10 may include the subject matter of any of Examples A1-A9 and may further include power supply circuitry for receiving a bias voltage over the two-wire bus from the upstream device and providing power from the bias voltage to an energy storage device coupled to the slave node transceiver.

Example A11 may include the subject matter of any of Examples A1-A10, and may further include peripheral device communication circuitry for communicating with at least one speaker and at least one microphone.

Example A12 may include the subject matter of Example A11, and may further specify that the peripheral device communication circuitry include an I2S inter-integrated circuit (TDM) transceiver, a TDM transceiver, a PDM transceiver, an I2C transmitter. Transmit receiver (Inter-Integrated Circuit) or a GPIO pin (General Purpose Input / Output) include.

Example A13 may include the subject matter of any of Examples A1-A12, and may further comprise peripheral device communication circuitry for communicating with a microphone and a conferencing user interface element, wherein a user actuates the conference circuit user interface element when the user inputs audio from another's microphone Two-wire bus coupled device, and wherein the second signal comprises data originating from the microphone when the conference call user interface element is actuated.

Example A14 may include the subject matter of any of Examples A1-A13, and may further include peripheral device communication circuitry for communicating with a wireless transceiver, wherein the wireless transceiver is to receive voice calls and wherein the upstream transceiver circuitry transmits data representing the voice calls to the second signal to record.

Example A15 may include the subject matter of any of Examples A1-A14, and may further specify that the upstream device is coupled to a wireless transceiver, where the wireless transceiver is to receive voice calls, and the upstream transceiver circuits include data representing voice calls in the first Signal should receive.

Example A16 may include the subject matter of any of Examples A1-A15, and may further specify that a host device is coupled to a master device of the two-wire bus, the host device is coupled to a wireless transceiver, the wireless transceiver is to receive voice calls, and the upstream transceiver circuits Data representing the voice calls should be received in the first signal.

Example A17 may include the subject matter of any of Examples A1-A16 and may further comprise peripheral device communication circuitry in communication with an antenna coupled to a roof or other portion of a vehicle, the peripheral device communication circuitry being connected via a wired connection to the antenna communicate.

 Example A18 may include the subject matter of Example A17 and may further specify that the upstream device is a master device located in the head unit of the vehicle.

Example A19 may include the subject matter of any of Examples A1-A18, and may further specify that the slave node transceiver is contained in a speaker, a mixer, a musical instrument, time encode devices, an amplifier, a video display, or a pyrotechnics console.

Example A20 may include the subject matter of any of Examples A1-A19 and may further include peripheral device communication circuitry in communication with a sensor or an actuator at a hinge of a robotic link.

Example A21 may include the subject matter of any of Examples A1-A20 and may further include a receive mailbox and a send mailbox, wherein the host device is to generate an interrupt for transmission to the downstream device when data is provided to the send mailbox and the downstream device To generate interrupt for transmission to the host device when data is to be provided to the receiving mailbox.

Example A22 may include the subject matter of any of Examples A1-A21 and may further include peripheral device communication circuitry in communication with a humidity or temperature sensor in a vehicle.

Example A23 may include the subject matter of any of Examples A1-A22, and may further include peripheral device communication circuitry in communication with a gas sensor in a vehicle.

Example A24 may include the subject matter of any of Examples A1-A23, and may further include peripheral device communication circuitry for providing the first signal or the second signal to a protocol analyzer, and wherein the downstream transceiver circuitry is disabled.

Example A25 may include the subject matter of any of Examples A1-A24, and may further specify that data is sent downstream in the synchronization control frame.

Example A26 may include the subject matter of any of Examples A1-A25, and may further specify that data is sent upstream in a synchronization response frame.

Example B1 is a master node transceiver for low-latency communication comprising: an I / C (Inter-Integrated Circuit Sound) receiver for receiving an I2S signal from a host device, the I2S signal providing timing information; Clock circuits for generating a clock signal based on the clock information; and downstream transceiver circuitry for routing a first signal downstream over a two-wire bus toward a downstream device and receiving a second signal over the two-wire bus from the downstream device, wherein a preamble of a synchronization control frame of the first signal is based on the clock signal and the downstream Device generates its own clock signal based on the preamble.

Example B2 may include the subject matter of Example B1 and may further specify: The synchronization control frame is associated with downstream data in a superframe of the first signal, the downstream data comprises a plurality of data slots, and data is for a single peripheral device coupled to the downstream device two or more of the multiple data slots.

Example B3 may include the subject matter of Example B2 and may further specify that the data for the single peripheral device is audio data.

Example B4 may include the subject matter of any of examples B1-B3, and may further specify: the first signal comprises a first synchronization control frame and associated first downstream data and a second synchronization control frame and associated second downstream data; the first downstream data comprises a data slot having a particular index and data for a first peripheral device coupled to the downstream device; and the second downstream data includes a data slot having the predetermined index and data for a second peripheral device other than the first peripheral device coupled to the downstream device.

Example B5 may include the subject matter of Example B4, and may further specify that the first and second peripheral devices are different microphones.

Example B6 may include the subject matter of any of Examples B1-B5, and may further specify that the second signal comprises a synchronization response frame, the synchronization response frame is associated with upstream data in a superframe of the second signal, the upstream data includes a plurality of data slots, and data, which come from a single peripheral device coupled to the downstream device, occupy two or more of the multiple data slots.

Example B7 may include the subject matter of Example B6, and may further specify that the data coming from the single peripheral device is audio data.

Example B8 may include the subject matter of any of examples B1-B7, and may further specify: the second signal comprises a first synchronization response frame and associated first upstream data and a second synchronization response frame and associated second upstream data; the first upstream data comprises a data slot having a particular index and data coming from a first peripheral device coupled to the downstream device; and the second upstream data comprises a data slot having the designated index and data coming from a second peripheral device different from the first peripheral device coupled to the downstream device.

Example B9 may include the subject matter of Example B8 and may further specify that the first and second peripheral devices are different microphones.

Example B10 may include the subject matter of any of Examples B1-B9, and may further specify that the first signal includes data for at least one of the speakers coupled to the downstream device and the second signal includes data that is from at least one coupled to the downstream device Microphone come.

Example B11 may include the subject matter of any of Examples B1-B10, and may further include peripheral device communication circuitry for communicating with a wireless transceiver, wherein the wireless transceiver is to receive voice calls, and wherein the downstream transceiver circuitry encodes data representing the voice calls into the first signal to record.

Example B12 may include the subject matter of any of examples B1-B11 and may further specify that the downstream device is coupled to a wireless transceiver that is to receive wireless transceiver voice calls and the downstream transceiver circuitry transmits data representative of the voice calls to the second Signal should receive.

Example C1 is a host device comprising: I2S transceiver circuits for directing an I2S signal to a master node transceiver, the master node transceiver being a master of a two-wire bus, the I2S signal timing information provides the master node transceiver based on the clock information to generate a clock signal, the Master node transceiver is to provide a first downstream signal over the two-wire bus toward a downstream device, a preamble of the synchronization control frame of the first signal is based on the clock signal, and the preamble-based downstream device is to generate its own clock signal; I2C transceiver circuits for receiving a first I2C signal from the master node transceiver and for directing a second I2C signal to the master node transceiver; and processing circuitry for generating data for the downstream device based on the first I2C signal, wherein the data for the downstream device is included in the second I2C signal and transmitted through the master node transceiver to the downstream via the two-wire bus. Device to be sent.

Example C2 may include the subject matter of example C1 and may further specify that the first signal includes data for at least one speaker coupled to the downstream device.

Example C3 may include the subject matter of any of Examples C1-C2, and may further specify the following: The I2S transceiver circuits are to receive audio from the two-wire bus and the master node transceiver from a microphone coupled to the downstream device; the I2C transceiver circuits are to receive an indication, via the two-wire bus and the master node transceiver, that a user has operated a conference circuit user interface element coupled to the downstream device; and the I2S transceiver circuits are to provide audio over the two-wire bus to another downstream device in response to the indication and via the two-wire bus and the master node transceiver.

Example C4 may include the subject matter of any of examples C1-C3, and may further specify that the downstream device is coupled to a wireless transceiver that is to receive wireless transceiver voice calls, and the I2C transceiver circuitry transmits data representing the voice calls over the master Node transceiver and receive the two-wire bus.

Example C5 may include the subject matter of any of Examples C1-C4 and may further specify that the downstream device is wired to an antenna coupled to a roof or other part of a vehicle and the master node transceiver is in a head unit of the vehicle located.

Example C6 may include the subject matter of any of Examples C1-C5, and may further specify that the host device includes a receive mailbox and a broadcast mailbox, and wherein the host device is to generate an interrupt for transmission to the downstream device when data is provided to the broadcast mailbox.

 Example C7 may include the subject matter of any of examples C1-C6, and may further specify that the downstream device is coupled to an environmental sensor in a vehicle and the processing circuitry is to generate a control instruction for an air conditioning system in the vehicle based on data from the sensor which are sent to the host device via the master node transceiver and the two-wire bus.

Example D1 is a microphone cable comprising: a first connector for coupling to a microphone; a second connector for coupling to an audio receiving device; a conductor for transferring data between the first connector and the second connector; and a slave node transceiver with upstream transceiver circuitry for receiving a first signal transmitted over a two-wire bus from an upstream device and passing a second signal over the two-wire bus to the upstream device, clock circuitry for generating a clock signal in the slave node A transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the reception and provision of signals over the two-wire bus by the node transceiver is based on the clock signal, and peripheral device communication circuits coupled to the conductor to interoperate between receive data transmitted to the first connector and the second connector, the data being included in the second signal.

Example D2 may include the subject matter of example D1 and may further specify that the slave node transceiver is included in the first connector.

Example D3 may include the subject matter of any of examples D1-D2, and may further specify that the slave node transceivers are in the second connector.

Example D4 may include the subject matter of any of examples D1-D3, and may further specify that the slave node transceiver is located between the first connector and the second connector.

Example D5 may include the subject matter of any of Examples D1-D4 and may further comprise an analog-to-digital converter (ADC) for converting an analog microphone input signal received at the first connector into a digital signal, wherein the data transmitted between the first connector of the second connector include the digital signal.

Example D6 may include the subject matter of Example D5 and may further specify that the second connector should provide the second signal and the digital signal of the audio receiving device.

 Example D7 may include the subject matter of any of Examples D5-D6, and may further specify that the second connector should provide the second signal and the analog microphone input signal to the audio receiving device.

Example D8 may include the subject matter of Example D7 and may further specify that providing the second signal and the analog microphone input signal comprises providing the sum of the second signal and the analog microphone input signal.

Example D9 may include the subject matter of any of Examples D7-D8, and may further specify that the second connector further provide the digital signal to the audio receiving device.

Example D10 may include the subject matter of any of Examples D5-D9, and may further include a digital-to-analog converter for converting the digital signal to an analog signal.

Example D11 may include the subject matter of example D10 and may further specify that the second connector of the audio receiving device is to provide the second signal and the analog signal.

Example E1 is a system having one or more of the slave node transceivers of any one of Examples A coupled over two-wire bus links to a master node transceiver of one of Examples B.

Example E2 may comprise the subject matter of Example E1 and may further comprise a host device of any of Examples C coupled to the master node transceiver.

Example E3 is a method according to any of the techniques disclosed herein.

Example E4 is an apparatus having means for carrying out any of the techniques disclosed herein.

Example E5 is one or more non-transitory computer readable media having instructions thereon that, in response to execution by one or more processing devices of a system, cause the system to execute any of the techniques disclosed herein.

Example F1 may include any of the embodiments of the slave-to-slave communication functionality disclosed herein.

Example F2 may include the subject matter of any of Examples A-E above and may further include any embodiments of the slave-to-slave communication functionality disclosed herein.

Example G1 is a low latency communication system comprising: a slave node transceiver with upstream transceiver circuitry for receiving a first signal transmitted over a two-wire bus from an upstream device and for passing a second signal over the two-wire bus to the upstream device; Downstream transceiver circuitry for routing a third signal downstream over the two-wire bus toward a downstream device and receiving a fourth signal over the two-wire bus from the downstream device and a peripheral device interface for receiving data from one communicatively with the one Peripheral device interface coupled peripheral device, wherein the downstream transceiver circuits are to receive the data in the third signal.

Example G2 may include the subject matter of Example G1 and may further specify that the data is audio data.

Example G3 may include the subject matter of any of Examples G1-2 and may further specify that the first signal includes data generated by a peripheral device communicatively coupled to the upstream device, the third signal provided downstream upon receipt of the first signal and the third signal comprises less than all of the data generated by the peripheral device communicatively coupled to the upstream device.

Example G4 may include the subject matter of Example G3 and may further specify that the upstream device is a host device.

Example G5 may include the subject matter of any of Examples G3-4, and may further specify that the upstream device is a master node.

Example G6 may include the subject matter of any of Examples G3-5, and may further specify that the upstream device is a slave node.

Example G7 may include the subject matter of any of Examples G3-6, and may further specify that the peripheral device interface of the peripheral device communicatively coupled to the peripheral device interface provides at least some of the data generated by the peripheral device communicatively coupled to the upstream device.

Example G8 may include the subject matter of any of Examples G3-7, and may further specify that an intermediate upstream device is located on the two-wire bus in a daisy chain between the slave node transceiver and the upstream device.

 Example G9 may include the subject matter of any of Examples G1-8, and may further specify that the fourth signal comprises data generated by a peripheral device communicatively coupled to the downstream device, the second signal provided upstream upon receipt of the fourth signal and the second signal comprises less than all of the data generated by the peripheral device communicatively coupled to the downstream device.

Example G10 may include the subject matter of example G9 and may further specify that the peripheral device interface of the peripheral device communicatively coupled to the peripheral device interface provides at least some of the data generated by the peripheral device communicatively coupled to the downstream device.

Example G11 may include the subject matter of any of Examples G9-G10 and may further specify that the peripheral device comprises a speaker.

Example G12 may include the subject matter of any of Examples G9-11, and may further specify that an intermediate downstream device is located on the two-wire bus in a daisy chain between the slave node transceiver and the downstream device.

Example G13 may include the subject matter of any of Examples G1-12 and may further include the upstream device and the downstream device.

Example G14 may include the subject matter of any of Examples G1-13 and may further specify that the slave node transceiver further comprises clock circuitry for generating a clock signal in the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of receiving and providing signals over the two-wire bus by the slave node transceiver is based on the clock signal.

Example G15 may include the subject matter of example G14 and may further specify that the second signal comprises a synchronization response frame and the synchronization response frame is associated with upstream data in a superframe of the second signal.

Example G16 may include the subject matter of any of Examples G1-15, and may further include the peripheral device.

Example H1 is a low latency communication system comprising: a master node transceiver; and a plurality of slave node transceivers communicatively coupled together and to the master node transceiver in a concatenated two-wire bus, wherein at least one of the slave node transceivers comprises: upstream transceiver circuitry for receiving one over a two-wire bus from an upstream Device on the first signal transmitted on the bus and for providing a second signal over the two-wire bus for the upstream device,
wherein the first signal comprises data generated by a peripheral device communicatively coupled to the upstream device, and downstream transceiver circuitry for providing a third signal downstream over the two-wire bus toward a downstream device on the bus and for receiving a fourth signal the two-wire bus from the downstream device, wherein the third signal is provided downstream upon receipt of the first signal and the third signal comprises less than all data generated by the peripheral device communicatively coupled to the upstream device.

Example H2 may include the subject matter of example H1 and may further include a host device communicatively coupled to the master node transceiver.

Example I1 is a method of slave to slave communication in a daisy-chained two-wire bus comprising:
Receiving data in a first slave device from a second slave device downstream of the first slave device via the bus; and providing less than all data from the second slave device through the first slave device to a third device upstream of the first slave device via the bus.

Example I2 may include the subject matter of Example I1, and may further specify that the data from the second slave device is data generated by a peripheral device communicating through an I2S transceiver (Inter-Integrated Circuit Sound), a TDM device. Transceiver (time division multiplex), a PDM transceiver (pulse density modulation), an I2C transceiver (Inter-Integrated Circuit) or a GPIO pin (General Purpose Input / Output) is coupled to the second slave node.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited non-patent literature

• IEEE 802.11 [0134]
• Standards IEEE 802.16 [0134]
• IEEE 802.16 [0134]
• IEEE 802.16 standards [0134]

Claims (20)

 Low latency communication system comprising: a slave node transceiver comprising: Upstream transceiver circuitry for receiving a first signal sent over a two-wire bus from an upstream device and for providing a second signal over the two-wire bus for the upstream device, Downstream transceiver circuitry for providing a third signal downstream over the two-wire bus toward a downstream device and for receiving a fourth signal over the two-wire bus from the downstream device and a peripheral device interface for receiving data from a peripheral device communicatively coupled to the peripheral device interface, wherein the downstream transceiver circuitry is to receive the data in the third signal. The low latency communication system of claim 1, wherein the data is audio data. The low latency communication system of claim 1 or 2, wherein the first signal comprises data generated by a peripheral device communicatively coupled to the upstream device, the third signal is provided downstream after the first signal is received, and the third signal is less than all comprising data generated by the peripheral device communicatively coupled to the upstream device. The low latency communication system of claim 3, wherein the upstream device is a host device. The low latency communication system of claim 3, wherein the upstream device is a master node. The low latency communication system of claim 3, wherein the upstream device is a slave node. The low latency communication system of any of claims 3 to 6, wherein the peripheral device interface of the peripheral device communicatively coupled to the peripheral device interface is to provide at least a portion of the data generated by the peripheral device communicatively coupled to the upstream device. A low-latency communication system according to any one of claims 3 to 7, wherein an upstream upstream device is arranged in a daisy-chain on the two-wire bus between the slave node transceiver and the upstream device. The low latency communication system of any one of the preceding claims, wherein the fourth signal comprises data generated by a peripheral device communicatively coupled to the downstream device, the second signal is provided prior to receiving the fourth signal upstream, and the second signal is less than all comprising data generated by the peripheral device communicatively coupled to the downstream device. The low latency communication system of claim 9, wherein the peripheral device interface of the peripheral device communicatively coupled to the peripheral device interface is to provide at least a portion of the data generated by the peripheral device communicatively coupled to the downstream device. The low latency communication system of claim 9 or 10, wherein the peripheral device comprises a speaker. A low-latency communication system according to any one of claims 9 to 11, wherein an intermediate downstream device is arranged in a daisy-chain on the two-wire bus between the slave node transceiver and the downstream device. A low latency communication system according to any one of the preceding claims, further comprising the upstream device and the downstream device. The low latency communication system of any one of the preceding claims, wherein the slave node transceiver further comprises: Clocking circuits for generating a clock signal in the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the reception and provision of signals over the two-wire bus by the slave node transceiver is based on the clock signal. The low latency communication system of claim 14, wherein the second signal comprises a synchronization response frame and the synchronization response frame is associated with upstream data in a superframe of the second signal. A low latency communication system according to any one of the preceding claims, further comprising the peripheral device. Low latency communication system comprising: a master node transceiver; and a plurality of slave node transceivers communicatively coupled together and to the master node transceiver in a concatenated two-wire bus, wherein at least one of the slave node transceivers comprises: Upstream transceiver circuitry for receiving a first signal transmitted over the two-wire bus from an upstream device on the bus and for providing a second signal over the two-wire bus for the upstream device, wherein the first signal comprises data generated by a peripheral device communicatively coupled to the upstream device, and Downstream transceiver circuitry for providing a third signal downstream over the two-wire bus toward a downstream device on the bus and for receiving a fourth signal over the two-wire bus from the downstream device, the third signal being provided downstream upon receipt of the first signal; the third signal comprises less than all data generated by the peripheral device communicatively coupled to the upstream device. The low latency communication system of claim 17, further comprising: a host device communicatively coupled to the master node transceiver. A method of slave-to-slave communication in a daisy-chained two-wire bus, comprising: Receiving data in a first slave device from a second slave device downstream of the first slave device via the bus; and Providing less than all data from the second slave device through the first slave device to a third device upstream of the first slave device via the bus. The method of claim 19, wherein the data from the second slave device is generated by a peripheral device having an IQS transceiver (Inter-Integrated Circuit Sound), a TDM transceiver (Time Division Multiplex), a PDM transceiver (Pulse Density Modulation), an I2C transceiver (Inter-Integrated Circuit) or GPIO pin (General Purpose Input / Output) is coupled to the second slave device.

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