DE102015225255A1 - Method and a circuit arrangement for determining the frequency stability of an integrated circuit clock signal - Google Patents

Abstract

The invention relates to a method for determining the frequency stability of a clock signal of an integrated circuit, wherein a demodulation of the clock signal is performed and at least two demodulation signals are generated, wherein the demodulation signals are each mixed with a reference signal and at least two mixing signals are generated, wherein from the mixing signals a phase angle between the reference signal and the demodulation signals is determined, wherein a temporal change of the phase angle is determined, and being deduced from this specific change in the phase angle with respect to the frequency stability of the clock signal.

Description

The present invention relates to a method and a circuit arrangement for determining the frequency stability of an integrated circuit clock signal.

State of the art

Integrated circuits are used in a variety of systems, for example in control units of motor vehicles. In an integrated circuit, a clock signal can be generated, which specifies the system clock for arithmetic operations of the entire system.

In order to be able to ensure effective operation and high computing power of the system, it is of great importance that the clock signal is generated with a frequency that is as stable or as constant as possible. High demands are thus placed on the clock signal with regard to frequency stability.

The frequency stability of digital clock signals is referred to in the time domain with the term "jitter" and in the frequency domain as so-called "phase noise". One way to jitter measurement is for example in the DE 101 03 879 B4 described.

Disclosure of the invention

According to the invention, a method and a circuit arrangement for determining the frequency stability of a clock signal of an integrated circuit with the features of the independent patent claims are proposed. Advantageous embodiments are the subject of the dependent claims and the following description.

The particular high-frequency clock signal is generated in the integrated circuit itself, for example by means of a so-called phase-locked loop (PLL), an electronic circuit which phase angle and frequency of a variable oscillator in particular influenced such that a phase deviation between the oscillator and a reference signal as constant as possible.

The circuit arrangement for determining the frequency stability of the clock signal (also referred to below as the frequency stability determination circuit) can be implemented, for example, as a component in the integrated circuit or else as an external circuit. At a (signal) input, the clock signal is present and is introduced into the frequency stability determination circuit.

A demodulation, in particular an angle demodulation, in particular a phase angle demodulation, of the clock signal is carried out. In the course of this at least two demodulation signals are generated. The circuit arrangement has a demodulator for this purpose.

In the course of such a demodulation, the clock signal is decomposed into components or into its baseband signals. In particular, the so-called IQ components of the clock signal can be determined as demodulation signals. In particular a so-called in-phase component or I-component is generated as a first demodulation signal, as a second demodulation signal in particular a so-called quadrature component or Q-component.

These demodulation signals are each mixed with a reference signal, in particular multiplicatively, and in the course of which at least two mixed signals are generated. The circuit arrangement has for this purpose in particular at least two mixers or mixing elements.

The reference signal may be generated by the integrated circuit or circuitry. In particular, the reference signal is derived from an independent input signal. For example, the reference signal can be generated by an external test device and fed to the integrated circuit or the circuit arrangement. In particular, the reference signal can first be sampled with the clock signal or the system clock in order to generate a harmonic reference signal. For this purpose, the circuit arrangement may comprise a reference encoder to which the clock signal and the reference signal are supplied as input signals. This harmonic reference signal can be mixed with the demodulation signals.

From the mixed signals, a phase angle or a phase position between the reference signal and the demodulation signals generated by the demodulator is determined. For this purpose, the mixed signals are supplied to a decoder which outputs a corresponding phase angle signal, that is to say in particular a time profile of the determined phase angle.

In particular, a two-dimensional representation of the phase in the form of a corresponding vector signal is made possible by the demodulation. The relative phase position of the clock signal relative to the reference clock can be directly derived by decoding the components generated in the course of demodulation.

In particular, the demodulation signals or a sum signal of these suitably orthogonal components of the clock signal describe a vector in an IQ plane. The angle between this vector and the abscissa of the IQ plane (in particular the I-axis) represents in particular the phase angle.

Frequency instability leads to a corresponding rotation of this vector in the IQ plane and thus to an incremental or decremental change of the phase angle. This temporal change of the phase angle provides, in particular in the low-frequency baseband, an accurate image of the frequency offset of the clock signal relative to the reference signal and can therefore be used expediently for monitoring the frequency stability. The temporal change of the phase angle is in particular a measure of the frequency stability of the clock signal. By suitable choice of the reference clock, the evaluation of the frequency deviation and the stability of the clock signal can thus be carried out based on the change in the phase position.

In the course of the method, therefore, the time change of the phase angle is determined and from this conclusions are drawn about the frequency stability of the clock signal. The phase angle signal provided by the decoder is supplied to a differentiator for this purpose. From this differentiating element, a phase angle change signal is generated, which is supplied to an evaluation circuit. The evaluation circuit generates an appropriate frequency stability signal based on the frequency stability of the clock signal and provides it at an output of the frequency stability determination circuit.

The invention provides a way to easily determine the frequency stability of the generated clock signal of an integrated circuit. Frequency instabilities or phase noise can be detected early with high accuracy. In particular, it is possible to carry out a purely digital analysis of the clock signal with respect, in particular, to high-frequency frequency and phase stability. In particular, no analog-to-digital conversions or digital-to-analog conversions have to be made. In particular, a continuous monitoring of a corresponding clock generator can be made possible, which generates the clock signal. It can be ensured that even short-term frequency deviation can be detected with high accuracy. Such frequency shelves may pose a potential risk to the proper functioning of the logic board or system. The ability to detect such frequency instabilities at an early stage can increase the functional safety of the corresponding system. Furthermore, the frequency stability determination circuit is formed largely independently of the integrated circuit, whereby the risk of mutual interference can be minimized ("freedom of interference").

The invention takes advantage of the fact that the digital clock signal can be represented by a suitable coding in the course of demodulation as mathematically accurate harmonic signal low word width, in particular by means of sine and / or cosine functions. By, in particular multiplicative, mixture of such harmonic signals, an error-free image of the frequency offset of high-frequency clocking signals in the (in particular low-frequency) baseband can be reproduced in the mathematical sense. The mixture converts the high-frequency characteristics into a frequency range that can be handled for analysis and diagnostic purposes.

The frequency stability signal as an output signal of the frequency stability determination circuit is generated in particular according to an output format which enables unambiguous detection of an insufficient frequency stability and thus a conclusion on possibly defective components of the integrated circuit. In particular, a "fail / pass" distinction is made possible by means of the frequency stability signal, that is, it can be recognized from the frequency stability signal whether the frequency stability of the clock signal is within a predetermined range or insufficient.

Conveniently, an output signal from the frequency stability determination circuit is output only if there is insufficient frequency stability or correspondingly high frequency instability. Such an output signal is referred to below as an instability signal.

According to an advantageous embodiment, an insufficient frequency stability is inferred if both positive and negative temporal changes of the phase angle are detected in a predetermined time interval. For this purpose, the evaluation circuit preferably has at least one comparator which generates an increase and / or decrease signal from the phase angle change signal.

In particular, the evaluation circuit comprises two comparators, whereby two different channels are provided. A first channel is expediently provided for a positive change of the phase angle and a second channel in particular for a negative change. Everyone each of the channels can have an output at which a corresponding increase or decrease signal is output in each case in the case of positive or negative phase angle change.

Expediently, these channels can each have toggle elements, in particular T flip-flops, which in particular represent pulses of the increase or decrease signals as edge changes and provide correspondingly at the respective output. Jitter or phase noise and thus insufficient frequency stability manifests itself in this case, in particular by temporary positive and negative phase angle change and, accordingly, by occurrence of edge changes at both outputs of the two channels.

In order to ensure the highest possible computing power of the integrated circuit or the logic module, it may be required in particular that the phase angle change of the clock signal relative to the reference signal represents a predetermined constant value, for example zero. Inadequate frequency stability can be defined in particular by limit values of the phase angle change.

For example, deliberate detuning of the reference signal may be used in the course of a calibration or test phase in order to determine limit values for frequency fluctuations, from which only positive or negative changes of the phase angle occur. These limits represent in particular a measure of the bandwidth of the frequency instability.

Preferably, an evaluation variable is determined from the determined temporal change of the phase angle. If this evaluation variable reaches a threshold value, preference is given to inferring insufficient frequency stability. The evaluation variable can advantageously be determined by summing or integrating the temporal change of the phase angle over a predetermined time interval. In this case, the evaluation variable represents an integral phase change. For this purpose, the evaluation circuit preferably comprises a corresponding counter, to which the increase and / or reduction signals generated by the comparators are supplied and which preferably generates a corresponding evaluation variable signal.

This evaluation variable signal is advantageously fed to at least one further comparator, which compares the evaluation variable signal with the threshold value. In particular, a corresponding instability signal is output if the evaluation variable or the evaluation variable signal reaches the threshold value. If, therefore, this instability signal is present at the output of the evaluation circuit, this advantageously means, in the course of the "fail / pass" distinction, that there is insufficient frequency stability, which may possibly indicate defective components of the integrated circuit.

Advantageously, a low-pass filtering of the mixed signals is carried out in order to eliminate the higher-frequency components of the mixed signals. Each mixer is followed in particular by a low-pass filter for this purpose in each case.

Preferably, a so-called quadrature demodulation of the clock signal is performed. In the course of this two demodulation signals are generated in particular, the in-phase component and the quadrature component, which in particular are perpendicular to each other or are shifted from each other by 90 °. Alternatively or additionally, a so-called three-phase demodulation of the clock signal can be performed. In the course of this, in particular, three demodulation signals are generated, which in particular are shifted relative to one another by 120 ° in each case.

According to an advantageous embodiment, a second reference signal is determined as a function of the reference signal. Preferably, for this purpose, the reference signal can be sampled by the inverted system clock or the inverted clock signal. The demodulation signals are preferably mixed both with the reference signal and with the second reference signal, in particular multiplicatively, and at least four mixed signals are generated. The phase angle is preferably determined from these at least four mixing signals. Conveniently, all of these mixed signals are supplied to the decoder. Thus, the decoding can be performed with at least four mixing signals, whereby the angular resolution can be improved.

Preferably, the phase angle in the course of a so-called PSK decoding ("phase-shift keying") is determined. Preferably, a QPSK demodulation ("quadrature phase-shift keying") is performed, in the course of which, in particular, two demodulation signals are used to determine the phase angle. The phase angle can be determined with a resolution of 90 °. Alternatively or additionally, preferably a π / 4-QPSK decoding can be carried out, in the course of which in particular four demodulation signals are used, whereby the phase angle can be determined with a resolution of 45 °. Advantageously, a π / 3-PSK decoding with three demodulation signals can be performed, resulting in a phase angle resolution of 60 °. Preferably, a π / 6-PSK decoding with six demodulation signals and a phase angle resolution of 30 ° conceivable.

The integrated circuit and / or the frequency stability determination circuit can advantageously be implemented in a control unit of a motor vehicle. For example, the method or the circuit arrangement for determining the frequency stability in the automotive sector can be used for digital transmission control, piezo injection, NO _x sensor evaluation or the like.

Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings.

The invention is illustrated schematically by means of embodiments in the drawing and will be described below with reference to the drawing.

Brief description of the drawings

1 to 3 each show schematically a preferred embodiment of a circuit arrangement according to the invention, each of which is adapted to perform a preferred embodiment of a method according to the invention.

4 schematically shows a part of a preferred embodiment of a circuit arrangement according to the invention, which is adapted to carry out a preferred embodiment of a method according to the invention.

Embodiment (s) of the invention

In the 1 to 3 is in each case a preferred embodiment of a circuit arrangement according to the invention 100 . 100 ' respectively. 100 '' shown schematically. The circuit arrangements 100 . 100 ' respectively. 100 '' are each adapted to perform a preferred embodiment of a method according to the invention.

Identical reference numerals in the 1 to 3 each designate identical or equivalent elements.

At an entrance 101 the circuit arrangement 100 . 100 ' respectively. 100 '' is a clock signal, which is generated by an integrated circuit, for example, from a clock system of the integrated circuit. For example, this integrated circuit can be implemented in a control unit of a motor vehicle.

At another entrance 102 the circuit arrangement 100 is a reference signal. The reference signal is also generated, for example, by the integrated circuit and, in particular, is derived from an input signal of the integrated circuit which is independent of the clock signal to be tested.

The clock signal becomes a demodulator 111 , supplied to a quadrature demodulator in this example. The clock signal is output in the quadrature demodulator 111 an in-phase component I _HF and a quadrature component Q _HF derived and generated as demodulation signals. The frequency f _{IQ of} these two demodulation signals is preferably defined as: f _IQ = 1 / 4f _clk with ω _c = 2πf _clk
where f _{clk is} the frequency of the clock signal. Thus, the set of values of the demodulation signals without quantization losses on {+1; 0; -1} limit. The demodulation signals are preferably represented as 2-bit signals by: I _HF = sin (ω _c 1 / 4t + 90 °) and Q _RF = sin (ω _c 1 / 4t)

That at the entrance 102 applied reference signal is in a sampling element 121 sampled, to which the reference signal and the clock signal are supplied as inputs. That of the sensing element 121 sampled reference signal is a coder 122 fed and preferably also from this to a 2-bit value set {+1; 0; -1} encoded. From the encoder 122 Thus, a harmonic reference signal S _{ref is} generated: S _ref = sin (ω _r t)
with the frequency ω _r and f _{r of} the reference signal (f _ref ☐ f _IQ ).

The demodulation signals I _HF and Q _HF are mixed or mixed multiplicatively with the harmonic reference signal S _ref . For this purpose, the demodulation signal I _HF and the harmonic reference signal S _ref a first mixer 131 fed. A second mixer 132 the harmonic reference signal S _ref and the demodulation signal Q _{HF are also} supplied.

From the first mixer 131 a first mixing signal I _{MX is} generated and from the second mixer 132 a second mixing signal Q _MX , wherein preferably I _MX = sin ([1 / 4ω _c - ω _r ] t + 90 °) + sin ([1 / 4ω _c + ω _r ] t + 90 °)
and Q _MX = sin ([1 / 4ω _c - ω _r ] t) + sin ([1 / 4ω _c + ω _r ] t)

In order to eliminate the higher frequency components of the mixed signals, the mixed signal I _MX is a first low-pass filter 141 supplied and the mixing signal Q _MX a second low-pass filter 142 , Preferably, for the low-pass filter 141 and 142 each uses a transfer function of the following form: H (z) = 1/2 [1 + z - 1 + z - 2 + z - 3]

With such a transfer function, the imaging property of the limited value ranges can be advantageously used since the products of a value sequence over four steps always contain two zero values due to the demodulation function. The sum over a value sequence of four steps is thus particularly representable in the form: S = [(+/- 1 * + / - 1) + 0 + (+/- 1 * + / - 1) + 0]

In particular, for the set of values of S, S = {+2; 0; -2}. With a scaling factor of 1/2, the value set of the output signals of the low-pass filters remains 141 and 142 on {+1; 0; -1} and minimizes the effort required for the operations.

The output signals of the low-pass filter 141 and 142 represent quadrature components in the low frequency "baseband". From the low pass filter 141 the signal I _{LF is} output and from the low pass filter 142 the signal Q _LF , where: I _LF = sin ([1 / 4ω _c - ω _r ] t + 90 °)
and Q _LF = sin ([1 / 4ω _c - ω _r ] t)

The sum signal of these two low-pass filtered mixed signals I _LF and Q _LF describes a vector in an IQ plane. An angle φ between this vector and the abscissa of the IQ plane describes the phase relationship between the reference signal and the demodulation signals I _HF and Q _HF .

This phase angle φ is in a decoder 151 determined from the mixed signals I _MX and Q _MX and the low-pass filtered mixed signals I _LF and Q _LF . The decoder 151 is in the example of 1 formed as a QPSK decoder. With such a QPSK decoder 151 the phase angle φ can be derived directly, in particular with a resolution of δφ = 90 °, relative to the harmonic reference signal S _ref .

This particular phase angle or a corresponding one of the decoder 151 generated phase angle signal is a differentiator 160 fed. This differentiator 160 determines a temporal change dφ / dt of the phase angle φ and generates a corresponding phase angle change signal.

Due to the limited word width of φ, the operation of the differentiator is 160 can be represented with little effort by a simple filter, for example with the following transfer function: H (z) = 1/2 (1 - z ^-1)

This temporal change dφ / dt of the phase angle φ represents a measure of the frequency stability of the clock signal. In order to infer the frequency stability of the clock signal, the time change of the phase angle or the phase angle change signal to an evaluation circuit 200 guided. If the frequency stability of the clock signal is insufficient, is at an output 300 the evaluation circuit 200 a corresponding instability signal is output. Structure and mode of operation of the evaluation circuit 200 be in relation to 4 explained in detail.

In 2 is an alternative preferred embodiment of the circuit arrangement 100 ' analogous to 1 shown. In the example of 2 In addition to the reference signal, a second reference signal is used. The second reference signal is generated by sampling the reference signal by the inverted clock signal.

For this purpose, that will be at the entrance 101 applied clock signal in an inverter 103 inverted and together with the one at the entrance 102 adjacent second reference signal to a second sensing element 123 fed. That of the sensing element 123 correspondingly sampled second reference signal is a second encoder 124 which supplies this signal in an analogous manner to the encoder 122 to a 2-bit set of values {+1; 0; -1} encoded. From the second encoder 124 a harmonic second reference signal S _{ref2 is} generated: S _ref2 = sin (ω _r t - 45 °)

This harmonic second reference signal S _ref2 is mixed with the demodulation signals I _HF and Q _HF , in particular multiplicatively, analogously to the signal S _ref . The demodulation signal I _HF and the signal S _ref2 become a third mixer 133 supplied, which generates the multiplicative mixing signal I _MX2 . A fourth mixer 133 be that _Demodulation signal Q _HF and the signal S _ref2 supplied, and a fourth multiplicative mixing signal Q _MX2 is generated.

These mixed signals I _MX2 and Q _MX2 become a third low-pass filter 143 or a fourth low-pass filter 144 which respectively generate a low-pass filtered mixed signal I _LF2 or Q _LF2 , wherein preferably: I _LF2 = sin ([1 / 4ω _c - ω _r ] t + 45 °)
and Q _LF = sin ([1 / 4ω _c - ω _r ] t - 45 °)

The four low pass filtered mixed signals I _{LF, LF} Q, I _{LF2 LF2} and Q are supplied to a decoder 152 supplied, which is formed in this example as a π / 4-QPSK decoder. With the π / 4 QPSK decoder, the phase angle φ can be determined in particular with a resolution of δφ = 45 °, relative to the harmonic reference signal S _ref .

In 3 is a further preferred embodiment of the circuit arrangement 100 '' shown. In the example of 3 becomes a demodulator designed as a 3-phase demodulator 112 used.

In the course of the corresponding demodulation are of the 3-phase demodulator 112 generates three demodulation signals P1 _HF , P2 _HF and P3 _HF , for which preferably: P1 _HF = sin (ω _c 1 / 6t); P2 _HF = sin (ω _c 1 / 6t + 120 °); P3 _HF = sin (ω _c 1 / 6t + 240 °)

In particular, the demodulation signals P1 _HF , P2 _HF and P3 _{HF are} also characterized by a distortion-free quantization in the limited value set {-1; 0; +1} can be displayed.

Furthermore, in addition to the sensing element 121 and the encoder 122 a low pass filter 125 be provided, which performs a low-pass filtering of the harmonic reference signal S _ref and a signal Sp _ref with the limited value set {-1; 0; +1} generated. Preferably, the low-pass filter is used 125 following transfer function used: H (z) = 1/2 (1 + z ^-1 )

For the signal Sp _ref advantageously applies: Sp _ref = sin (ω _r t)

The P1 _HF , P2 _HF and P3 _HF are each a mixer with the signal Sp _ref 131 . 132 respectively. 135 supplied to each generate a multiplicative mixing signal. These three mixed signals are each a low-pass filter 141 . 142 respectively. 145 which respectively generate a low-pass filtered mixed signal P1 _LF , P2 _LF or P3 _LF . For the low pass filter 141 . 142 and 145 Preferably, the following transfer function is used in each case: H (z) = 1/2 [1 + z - 1 + z - 2 + z - 3 + z - 4 + z - 5]

For the products of a value sequence over 6 Steps due to the demodulation function of the 3-phase demodulator 112 at least 2 Zero values, in particular results in a sum function over the individual terms in the form: S = [(+/- 1 * + / - 1) N + (+/- 1 * + / - 1) N + 0 + (+/- 1 * + / - 1) N + (+/- 1 * + / - 1) N + 0]

Since the signal Sp _ref in this example also contains zero values (N = {1, 0}), further terms of the sum function can become zero, and thus the following applies to the set of values: S = {+4; +3; +2; +1; 0; -1; -2; -3; -4}. Therefore, in this case, for the representation of the low-pass-filtered mixed signals P1, _LF , P2, _LF , P3, _{LF are} respectively particular 4 Bit required.

The decoding of the three-phase baseband signal or the low-pass filtered mixed signals P1 _LF , P2 _LF , P3 _LF takes place in this example a π / 3-PSK decoder 153 at an angular resolution of in particular δφ = 60 °.

It is also conceivable that even for a 3-phase demodulator 112 a second reference signal according to 2 is provided. Thus, there are six mixed signals, which in particular a π / 6-PSK decoder with a resolution of δφ = 30 ° are supplied.

In 4 is the evaluation circuit 200 from the 1 to 3 shown schematically according to a preferred embodiment of the invention.

That of the differentiator 160 generated phase angle change signal is located at an input 201 the evaluation circuit 200 at. The evaluation circuit 200 has two channels 200A and 200B on. A first channel 200A is provided to detect positive change of the phase angle φ, a second channel 200B is for negative phase angle changes.

A comparator 211 is in the first channel 200A provided a signal to a toggle element 221 when the phase angle change signal is positive (δφ / dt> 0). For a negative phase angle change signal (δφ / dt <0) is from a second comparator 212 a corresponding signal to a second toggle element 222 directed.

Through the toggle elements 221 respectively. 222 are each the corresponding of the comparators 211 respectively. 212 transmitted pulses shown as an edge change and with a frequency reduction of in particular [1/2] at a corresponding output 231 respectively. 231 of the respective channel 200A respectively. 200b provided.

The toggle elements 221 and 222 For example, each formed as a T-flip-flop, which can take one of two switching positions. Through the toggle elements 221 respectively. 222 become the ones of the comparators 211 respectively. 212 transmitted signals in each case in a state change (High -> Low or Low -> High) converted.

A positive change of the phase angle φ by one step thus leads in particular to a change of state at the output 231 , while a negative change in the phase angle φ a change in state at the output 232 entails.

Furthermore, there is a third channel 200C with the exit 300 be provided on which at insufficient frequency stability of the clock signal, the instability signal is output.

In this third channel is a counter 240 provided to which the signals of the comparators 211 and 212 be supplied. The counter 240 sums or integrates the change pulses of δφ / dt over a predetermined time interval T _MI and generates a weighting signal. Thus, an integral phase change φ _{int is determined} as the corresponding evaluation quantity.

For a defined frequency offset or frequency instability .DELTA.f a corresponding setpoint φ _is obtained in this time interval T _MI particular as follows: φ _is = Δf · T _MI · 360 ° / δφ

From this desired value φ _is , a maximum threshold value S _max and a minimum threshold value S _min can be derived for a maximum permissible and a minimum permissible frequency instability Δf. The threshold values S _max and S _min thus correspond to the maximum permissible phase deviation from the setpoint value φ _is .

The integral phase change φ _int or the corresponding evaluation variable signal is from the counter 240 two comparators 251 and 252 fed. The comparator 251 checks whether the evaluation _variable reaches the maximum threshold value S _max (φ _int > S _max ). The comparator 252 checks whether the evaluation variable reaches the minimum threshold value S _min (φ _int <S _min ).

When the integral phase change φ _{int reaches} the minimum threshold value S _min and / or the maximum threshold value S _max , it is counted by one element 260 the instability signal is output and at the output 300 provided.

QUOTES INCLUDE IN THE DESCRIPTION

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Cited patent literature

• DE 10103879 B4 [0004]

Claims (14)

Method for determining the frequency stability of a clock signal of an integrated circuit, wherein a demodulation of the clock signal is performed and at least two demodulation signals are generated, wherein the demodulation signals are each mixed with a reference signal and at least two mixed signals are generated, wherein a phase angle between the reference signal and the demodulation signals is determined from the mixed signals, wherein a temporal change of the phase angle is determined and from this particular time change of the phase angle is deduced the frequency stability of the clock signal. The method of claim 1, wherein inferences in an insufficient frequency stability, if in a predetermined time interval both positive and negative changes in the phase angle are determined. Method according to claim 1 or 2, wherein an evaluation variable is determined from the determined temporal change of the phase angle and wherein an insufficient frequency stability is deduced when the evaluation variable reaches a threshold value. The method of claim 3, wherein the evaluation quantity is determined by summing up the determined time change of the phase angle over a predetermined time interval. Method according to one of the preceding claims, wherein a second reference signal is determined as a function of the reference signal, the demodulation signals are each mixed with both the reference signal and the second reference signal and at least four mixed signals are generated and the phase angle is determined from the at least four mixing signals. The method of claim 5, wherein the second reference signal is determined by sampling the reference signal by an inverted clock signal. Method according to one of the preceding claims, wherein a low-pass filtering of the mixed signals is performed. Method according to one of the preceding claims, wherein a quadrature demodulation and / or a three-phase demodulation of the clock signal are performed. Method according to one of the preceding claims, wherein the phase angle in the course of a QPSK decoding and / or a π / 4-QPSK decoding and / or a π / 3-PSK decoding and / or π / 6-PSK decoding is determined , Circuit arrangement ( 100 ) for determining the frequency stability of an integrated circuit clock signal, comprising: a demodulator ( 111 . 112 ) for performing a demodulation of the clock signal and for generating at least two demodulation signals, at least one mixer ( 131 . 132 . 133 . 134 . 135 ) for mixing the from the demodulator ( 111 . 112 ) generated demodulation signals each with a reference signal and for generating at least two mixing signals, a decoder ( 151 . 152 . 153 ) for determining a phase angle between the reference signal and that of the demodulator ( 111 . 112 ) generated demodulation signals from the at least one mixer ( 131 . 132 . 133 . 134 . 135 ) generated mixed signals and for generating a phase angle signal, a differentiator ( 160 ) for determining a temporal change of the phase angle from that of the decoder ( 151 . 152 . 153 ) provided phase angle signal and for generating a phase angle change signal and an evaluation circuit ( 200 ) for evaluating the time change of the phase angle from that of the differentiating element ( 160 ) and generating a frequency stability signal based on the frequency stability of the clock signal. Circuit arrangement ( 100 ) according to claim 10, wherein the evaluation circuit ( 200 ): at least one comparator ( 211 . 212 ) for determining a positive and / or a negative temporal changes of the phase angle from that of the differentiating element ( 160 ) generated phase angle change signal and for generating an increase and / or decrease signal, a counter ( 240 ) for summing the time changes of the phase angle from the generated increase and / or decrease signal and for providing an evaluation quantity signal, at least one comparator ( 251 . 252 ) for comparing the evaluation quantity signal with a threshold value and for outputting an instability signal when the evaluation quantity signal reaches the threshold value. Circuit arrangement ( 100 ) according to claim 10 or 11, wherein the at least one mixer ( 131 . 132 . 133 . 134 . 135 ) at least one low-pass filter ( 141 . 142 . 143 . 144 . 145 ) is connected downstream. Circuit arrangement ( 100 ) according to one of claims 10 to 12, wherein the demodulator ( 111 . 112 ) as a quadrature demodulator ( 111 ) and / or as a three-phase demodulator ( 112 ) is trained. Circuit arrangement according to one of claims 10 to 13, wherein the decoder ( 151 . 152 153 ) as a QPSK decoder ( 151 ) and / or as a π / 4 QPSK decoder ( 152 ) and / or as a π / 3 PSK decoder ( 153 ) and / or is designed as a π / 6-PSK decoder.

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