DE102015223539B4 - Method and circuit arrangement for generating an analog signal, resolver with the circuit arrangement - Google Patents

Abstract

Method for generating an analog signal (AS) from two pulse-width-modulated signals (PS1, PS2), comprising the following steps: - gain amplifying the two pulse width modulated signals (PS1, PS2) by a variable gain (VF); Amplification factor (VF) amplified pulse width modulated signals (PS1 ', PS2') to respective intermediate analog signals (ZS1, ZS2), - comparing the two analog intermediate signals (ZS1, ZS2) each with a reference voltage (Uref), - increasing the amplification factor (VF) as long as the voltage level of one of the two analog intermediate signals (ZS1, ZS2) falls below the voltage level of the reference voltage (Uref), - forming the analog signal (AS) from the two analog intermediate signals (ZS1, ZS2) by adding the signal deflections of the two analog intermediate signals (ZS2) ZS1, ZS2).

Description

Technical area:

The invention relates to a method and a circuit arrangement for generating an analog signal, in particular a sine / cosine signal, for a resolver, from two pulse width modulated signals. Furthermore, the invention relates to a resolver with a said circuit arrangement.

State of the art:

Resolvers are used to determine a rotation angle, in particular an electrical machine. In this case, the ratio of two output amplitudes of an analog excitation signal and an analog sensor signal is evaluated as a function of their respective signal level profiles. The excitation signal should be constant or have a sine / cosine form.

The patent publication DE 10 2006 043 878 B4 describes a motor control circuit for controlling an electric motor based on an output signal from a sensor. The circuit includes a first pulse width modulation or PWM output circuit which generates a first PWM output based on data stored in a waveform table. The circuit further includes a feedback control unit that generates a control signal based on a sensor output output from the sensor. The circuit further includes a level adjusting unit that adjusts the first PWM output signal to control the amplitude of an energizing power supply to excite the sensor based on the control signal. The circuit further includes a filter that generates the excitation power supply based on the adjusted first PWM output signal.

The patent publication DE 10 2005 005 024 A1 describes a resolver arrangement comprising a carrier signal generator and two processing channels, each having an analog input connected to a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator having an output that provides a bitstream that represents an analog input signal received from a corresponding stator coil. Each channel also includes a first digital filter that receives the bitstream from the sigma-delta modulator and converts the bitstream into digital intermediate data words. In addition, each channel has a digital synchronous demodulator which demodulates the digital intermediate data words in synchronism with the carrier signal and provides demodulated data words. Finally, each channel has a second digital filter which averages the demodulated data words and provides digital output data words at the channel output, with the carrier signal being suppressed in the output data words.

The patent publication DE 10 2007 052 603 A1 describes a rotation angle detection device for detecting a rotation angle of a rotatable body on the basis of a resolver signal output from a resolver mounted on the rotatable body. The apparatus comprises a first function for detecting a specific timing of the resolver signal, a second function for measuring a time necessary for the resolver signal to go from the specific phase timing to a peak thereof, a third function for generating a sampling timing in accordance with Time measured by the second function, a fourth function for sample-holding the resolver signal at the sampling timing to hold a peak value of the resolver signal, and a fifth function for calculating the rotational angle of the rotatable body based on the peak value of the resolver signal; which is held by the fourth function.

Thus, the object of the present invention is to provide a possibility for generating a constant or sinusoidal / cosinusoidal exciter signal.

Description of the invention:

This object is solved by subject matters of the independent claims. Advantageous embodiments are the subject of the dependent claims.

According to a first aspect of the invention, a method for generating an analog signal, in particular a sine / cosine signal for a resolver, from two pulse width modulated signals is provided.

According to the method, the two pulse width modulated signals are amplified by a controllable gain signal amplitudes. The two amplification factor enhanced pulse width modulated signals are then converted to respective intermediate analog signals by low pass filtering. The two analog intermediate signals are then each compared with a reference voltage (with a predetermined constant voltage level). The amplification factor is increased as long as the voltage level of one of the two analog intermediate signals falls below the voltage level of the differential voltage. The analog signal mentioned at the beginning is made up of the two analog intermediate signals by adding the signal deflections of the two analog intermediate signals.

In this case, a signal deflection is a momentary removal of a point of a signal from its rest position. If the signal is a signal with a constant signal level, then the maximum signal deflection corresponds to the signal level of the signal. If the signal is a sine or cosine signal, the maximum signal deflection corresponds to the signal amplitude of the signal.

By adding the signal deflections of the two analog intermediate signals, the instantaneous distances of the individual points of the two intermediate signals are added to each other at respective times, whereby the analog signal at respective times signal deflections, which the respective sums of the instantaneous distances of the individual points of the two intermediate signals to the respective Correspond to times. If the two intermediate signals are, for example, two mutually identical or mutually inverse sinusoidal signals having the same signal amplitude, then the analog signal corresponds to a sinusoidal signal having twice the signal amplitude.

The invention is based on the basic idea that a resolver for measuring the angle of rotation generally requires a constant or a distortion-free sinusoidal / cosinusoidal excitation signal in order to be able to supply a measurement result which can be evaluated in a simple manner.

Since an electrical circuit for generating an exciter signal is usually exposed to thermal fluctuations or other internal and external influences, which often lead to changes in the signal amplitude of the generated exciter signal, it requires a solution to provide an exciter signal with a constant signal amplitude.

In the context of this invention, it has been recognized that the signal amplitudes of pulse-width-modulated signals can be regulated in a simple manner and without appreciable time delay, from which the exciter signal can then be obtained with a constant signal amplitude. It proved to be advantageous if the analog excitation signal is generated from two pulse width modulated signals. The signal amplitudes of the two pulse-width-modulated signals can be controlled by a signal amplitude amplification before the excitation signal is formed from the two pulse width modulated signals by a low-pass filtering and a subsequent addition of the signal deflections of the two low-pass filtered signals. For regulating the signal amplitudes of the two pulse width modulated signals, the signal amplitudes of the two low-pass filtered signals are compared with a predetermined reference voltage (with a constant voltage value). Depending on the comparison results between the reference voltage and the two low-pass filtered signals, a gain factor is controlled in order to then amplify the two pulse width modulated signals.

The formation of the excitation signal from two pulse width modulated signals has the advantage that the control of the amplification factor and thus the signal amplitude of the excitation signal in a closed loop is more reliable and with a shorter time delay than would have occurred with a single pulse width modulated signal. This is achieved in that the adaptation of the amplification factor and thus the excitation signal takes place as soon as the signal amplitude of one of the two low-pass filtered signals falls below the voltage level of the reference voltage. In the closed loop, the signal amplitudes of the pulse-width modulated signals are adjusted or amplified (if necessary. Also reduced) until the desired signal amplitude and thus the desired output voltage is reached in the exciter signal. Thus, the signal amplitude remains constant in the exciter signal even with amplitude fluctuations in the pulse width modulated signals and is at an amplitude value that does not deviate or not more than 10% or 5% of an intended amplitude value. The amplitude fluctuations due to the temperature-related or other internal and external influences are also compensated.

By choosing two pulse width modulated signals and the subsequent addition of the signal deflections of the two low-pass filtered signals can also be generated from pulse width modulated signals with a signal level example. Of 5 volts or 3.3 volts, an excitation signal with a signal amplitude of, for example. 10 volts. As a result, the method described above can also be realized with a circuit arrangement which can be operated with an operating voltage of 5 volts.

The method described above thus provides a possibility for generating a constant or sinusoidal / cosinusoidal excitation signal.

By the method described above eliminates an amplitude monitoring, which would otherwise be required to monitor the signal amplitude of the exciter signal.

The two pulse width modulated signals are preferably each with a operated by means of an operating voltage digital amplifier the voltage value of the operating voltage is strengthened, wherein the voltage value of the operating voltage is changed linearly to the amplification factor.

The adaptation of the signal amplitudes of the two pulse width modulated signals is thus effected by changing the operating voltage of the two operated with this operating voltage digital amplifier.

The amplification factor is preferably changed by means of a control amplifier whose control frequency is smaller by a factor of twenty, in particular by at least a factor of fifty, especially by at least a factor of one hundred, than the signal frequency of the two analog intermediate signals.

Preferably, the two pulse width modulated signals are executed inversely to each other.

According to a further aspect of the invention, a circuit arrangement for generating an analog signal, in particular a sine / cosine signal for a resolver, from two pulse width modulated signals is provided.

The circuit arrangement comprises a controllable signal amplifier unit, which is set up to amplify the two pulse width modulated signals by a controllable amplification factor.

The circuit arrangement further comprises a filter unit, which is connected downstream of the signal amplifier unit and is set up to convert the two pulse-width-modulated signals amplified by the signal amplifier unit by the amplification factor into an analog intermediate signal by low-pass filtering.

The circuit arrangement further comprises a comparator unit, which is connected downstream of the filter unit and is set up to compare the two analog intermediate signals each with a reference voltage with a predetermined, in particular constant, voltage value.

The circuit arrangement further comprises a control amplifier, which is connected downstream of the comparator unit and is arranged to increase the amplification factor as long as the voltage level (magnitude) of one of the two analog intermediate signals falls below the voltage level of the reference voltage.

The circuit arrangement is further configured to form the analogue signal from the two analogue intermediate signals by adding the signal deflections of the two analogue intermediate signals.

In this case, the signal amplifier unit comprises two digital amplifiers which can be operated with an operating voltage, in particular in the form of logic gates, which are set up in each case to amplify one of the two pulse-width-modulated signals by the voltage value of the operating voltage.

The variable gain amplifier is further configured to change the voltage value of the operating voltage linearly to the amplification factor.

Thus, the voltage levels of the two, amplified by the signal amplifier unit pulse width modulated signals correspond to the voltage value of the operating voltage.

In accordance with yet another aspect of the invention, a resolver, in particular for measuring a rotation angle of an electrical machine, is provided. In this case, the resolver comprises an excitation winding with a first and a second power connection, and a previously described circuit arrangement, wherein the circuit arrangement is electrically connected via a first and a second signal output to the first and the second power terminal of the field winding and via the first and the second signal output feeds the analog signal as an excitation signal in the field winding.

Advantageous embodiments of the method described above, as far as applicable to the above-described circuit arrangement or to the resolver mentioned above, are also to be regarded as advantageous embodiments of the circuit arrangement or of the resolver.

Description of the drawing:

In the following, an exemplary embodiment of the invention with reference to the accompanying drawings is explained in more detail. The sole figure in a schematic circuit topology shows a resolver RS (or part thereof) with a circuit arrangement SA according to an embodiment of the invention.

The resolver RS includes, among other things, a field winding EW as well as the circuit arrangement SA , which is the excitation winding EW upstream and is set up, the exciter winding EW a sine wave signal AS provide.

The circuit arrangement SA includes a first and a second signal input E1 . E2 about which the circuit arrangement SA in each case a first and a second pulse width modulated input signal PS1 . PS2 receives, from which the circuit arrangement SA the sinusoidal signal AS for the excitation winding EW generated. The circuit arrangement SA further includes first and second signal outputs A1 . A2 , between which the sine wave signal AS to the excitation winding EW is delivered.

The circuit arrangement SA comprises a controllable signal amplifier unit VE which, in turn, a first and a second mutually analog controllable digital signal amplifier DV1 . DV2 includes, which in each case one of the two signal inputs E1 . E2 are downstream and are set up, the respective via the signal inputs E1 . E2 obtained pulse width modulated signals PS1 . PS2 around a controllable gain factor VF to reinforce. Here are the two signal amplifiers DV1 . DV2 each as a by means of an operating voltage ub operable logic gates executed which the signal amplitudes of the respective pulse width modulated signals PS1 . PS2 to the voltage value of the operating voltage ub strengthen.

The circuit arrangement further comprises a filter unit FE , which in turn each have a first and a second low-pass filter designed substantially symmetrically with respect to one another TP1 . TP2 each comprising one of the two digital signal amplifiers DV1 . DV2 are arranged downstream and are arranged, carrier signal components (with a carrier frequency of, for example, 2 megahertz) of the respective by the respective digital signal amplifier DV1 . DV2 amplified by the gain factor VF pulse width modulated signals PS1 ' . PS2 ' to suppress by a low-pass filtering and thus useful signal components of the two signals PS1 ' . PS2 ' (with a modulation frequency of, for example, 10 kilohertz) as respective analogue intermediate signals ZS1 . ZS2 forward.

The circuit arrangement SA further includes (optionally) an analog amplifier AV , which of the filter unit FE is downstream and set up, the two analog intermediate signals ZS1 . ZS2 again to amplify a fixed gain factor and the two signal outputs A1 . A2 to the excitation winding EW forward. Here is the analog amplifier AV preferably as a FROM Amplifier trained, which does not have to be extra cooled due to its low power loss.

Alternatively, the analog amplifier AV as a differential amplifier, for example, a push-pull output, be designed and set up, the signal difference of the two analog intermediate signals ZS1 . ZS2 to amplify and thereby formed output as the analog signal AS over the two signal outputs A1 . A2 leave.

At the two signal outputs A1 . A2 become the two intermediate signals ZS1 . ZS2 by adding the signal deflections of the two intermediate signals ZS1 . ZS2 the analogue output signal AS then formed as the exciter signal across the two signal outputs A1 . A2 the excitation winding EW is supplied.

The circuit arrangement SA further comprises a comparator unit KE , which in turn a first and a second substantially analog comparator KP1 . KP2 includes. The first comparator KP1 is via its positive input with the first signal output A1 the circuit arrangement SA electrically connected. About the negative input is the first comparator KP1 with a third signal input E3 the circuit arrangement SA electrically connected to which a reference voltage Uref is applied with a predetermined constant voltage value. The second comparator KP2 is via its positive input with the second signal output A2 the circuit arrangement SA electrically connected. About the negative signal input is the second comparator KP2 also with the third signal input E3 the circuit arrangement SA electrically connected.

The circuit arrangement SA further comprises a variable gain amplifier RV , the comparator unit KE or the two comparators KP1 . KP2 is connected downstream and via a signal input to the outputs of the two comparators KP1 . KP2 electrically connected.

The circuit arrangement SA further includes a buffer stage PS , which input side with an output of the control amplifier RV and on the output side with the operating voltage connections of the two digital amplifiers DV1 . DV2 electrically connected. The buffer level PS forms from the output voltage of the control amplifier RV , which is not suitable as the operating voltage of the LV Driver for signal amplitude control to be used directly, a loadable and stable voltage and represents this as the stable operating voltage ub for the two digital amplifiers DV1 . DV2 ready.

After the circuit topology of the resolver RS , in particular the circuit arrangement SA , has been described in detail with reference to the figure, below, the operation of the resolver RS or the circuit arrangement SA described in more detail.

For generating the sine signal AS is at the two signal inputs E1 . E2 the circuit arrangement SA two mutually inverse pulse width modulated signals PS1 . PS2 applied, which are provided by a signal generator, not shown in the figure.

These two pulse width modulated signals PS1 . PS2 be from the respective digital signal amplifier DV1 . DV2 around the voltage value of the operating voltage ub the two digital signal amplifiers DV1 . DV2 Signal amplitudes amplified, wherein voltage value of the operating voltage ub the amplification factor VF which corresponds to the control amplifier RV is regulated in the manner to be described below.

The order of the gain factor VF Signal Amplitude Enhanced Pulse Width Modulated Signals PS1 ' . PS2 ' are then from the respective low-pass filters TP1 . TP2 to the respective analog intermediate signals ZS1 . ZS2 transformed.

The two intermediate signals ZS1 . ZS2 are then taken from the analog amplifier AV fed where the two intermediate signals ZS1 . ZS2 reinforced again to the two signal outputs A1 . A2 be delivered.

At the two signal outputs A1 . A2 is done by adding the signal deflections of the two intermediate signals ZS1 . ZS2 the analogue output signal AS formed and as the excitation signal via the two signal outputs A1 . A2 the excitation winding EW fed.

About the respective signal connections between the signal outputs A1 . A2 and the two comparators KP1 . KP2 become the two intermediate signals ZS1 . ZS2 each at the positive signal input of the first comparator KP1 or at the negative signal input of the second comparator KP2 where the signal amplitudes of the two intermediate signals ZS1 . ZS2 each with the voltage value at the negative signal input of the first comparator KP1 or at the positive signal input of the second comparator KP2 applied reference voltage Uref be compared.

As long as the signal amplitude of the corresponding intermediate signal ZS1 . ZS2 the voltage value of the reference voltage Uref is below, the affected comparator gives KP1 respectively. KP2 an output signal with a signal level "logic one" to the downstream variable gain amplifier RV from.

The control amplifier RV evaluates the output signals of the two comparators KP1 . KP2 off and generates an output signal called the operating voltage ub with a corresponding voltage value to the two digital amplifiers DV1 . DV2 is supplied.

The control amplifier works RV as a control loop, in the signal level of its output signal and thus the voltage value of the operating voltage ub recursively increases as long as the signal amplitude of at least one of the two intermediate signals ZS1 . ZS2 the voltage value of the reference voltage Uref below. As soon as the signal amplitudes of the two intermediate signals ZS1 . ZS2 the voltage value of the reference voltage Uref reach, the signal level of the output signal and thus the voltage value of the operating voltage ub not changed anymore. Exceed the signal amplitudes of the two intermediate signals ZS1 . ZS2 the voltage value of the reference voltage Uref , so the signal level of the output signal and thus the voltage value of the operating voltage ub recursively reduced.

With the recursively adapted operating voltage ub become the two pulse width modulated signals PS1 . PS2 around the voltage value of this operating voltage ub amplitude increased.

By the method described above, an amplitude control in the sine signal AS for the resolver RS performed without a memorized pulse width modulation in the two pulse width modulated input signals PS1 . PS2 to have to perform. The amplitude control with the sine signal AS essentially takes place solely by the amplitude adjustment in the two pulse width modulated input signals PS1 . PS2 by means of two digital amplifiers formed from inexpensive logic gates DV1 . DV2 ,

Claims (8)

Method for generating an analog signal (AS) from two pulse width modulated signals (PS1, PS2), comprising the following steps: Amplitude amplification of the two pulse width modulated signals (PS1, PS2) in each case by a controllable amplification factor (VF); Low pass filtering the two amplification factor (VF) amplified pulse width modulated signals (PS1 ', PS2') to respective intermediate analog signals (ZS1, ZS2); - Comparing the two analog intermediate signals (ZS1, ZS2) each with a reference voltage (Uref); - increasing the amplification factor (VF), as long as the voltage level of one of the two analog intermediate signals (ZS1, ZS2) falls below the voltage level of the reference voltage (Uref); - Forming the analog signal (AS) from the two analog intermediate signals (ZS1, ZS2) by adding the signal deflections of the two analog intermediate signals (ZS1, ZS2). Method according to Claim 1 , wherein the two pulse width modulated signals (PS1, PS2) in each case with a by means of an operating voltage (Ub) operated digital amplifier (DV1, DV2) amplified by the voltage value of the operating voltage (Ub) be, wherein the voltage value of the operating voltage (Ub) is changed linearly to the gain (VF). Method according to Claim 1 or 2 , wherein the amplification factor (VF) is changed by means of a control amplifier (RV), the control frequency of which is smaller by at least a factor of twenty than the signal frequency of the two analog intermediate signals. Method according to one of the preceding claims, wherein the two pulse width modulated signals (PS1, PS2) are inverse to each other. Circuit arrangement (SA) for generating an analog signal (AS) from two pulse width modulated signals (PS1, PS2), having the following features: - A controllable signal amplifier unit (VE), which is adapted to amplify the two pulse width modulated signals (PS1, PS2) by a controllable gain factor (VF); - A filter unit (FE), which is the signal amplifier unit (VE) connected downstream and is arranged, the two, amplified by the signal amplifier unit (DV1) by the gain factor (VF) pulse width modulated signals (PS1 ', PS2') each to an analog intermediate signal ( ZS1, ZS2); - A comparator unit (KE), which is the filter unit (FE) connected downstream and is adapted to compare the two analog intermediate signals (ZS1, ZS2) each with a predetermined reference voltage (Uref); - A control amplifier (RV), which is the comparator unit (KE) connected downstream and is adapted to increase the gain (VF), as long as the voltage level of one of the two analog intermediate signals (ZS1, ZS2) below the voltage level of the reference voltage (Uref); - Wherein the circuit arrangement (SA) is arranged to form from the two analog intermediate signals (ZS1, ZS2), the analog signal (AS) by adding the signal deflections of the two analog intermediate signals (ZS1, ZS2). Circuit arrangement (SA) according to Claim 5 in which - the signal amplifier unit (VE) comprises two operating amplifiers (Ub) operable digital amplifier (DV1, DV2), which are each set one of the two pulse width modulated signals (PS1, PS2) to amplify the voltage value of the operating voltage (Ub). Circuit arrangement (SA) according to Claim 6 , wherein the control amplifier (RV) is further adapted to change the voltage value of the operating voltage (Ub) linearly to the gain factor (VF). Resolver (RS), comprising: - a field winding (EW); a circuit arrangement (SA) according to one of Claims 5 to 7 ; - Wherein the circuit arrangement (SA) via a first (A1) and a second (A2) signal output to the exciter winding is electrically connected and via the first (A1) and the second (A2) signal output the analog signal (AS) in the exciter winding (EW) feeds.

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